7,11c7,11
< host_inst_rate 731783 # Simulator instruction rate (inst/s)
< host_op_rate 860761 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 39683148028 # Simulator tick rate (ticks/s)
< host_mem_usage 744736 # Number of bytes of host memory used
< host_seconds 1195.99 # Real time elapsed on the host
---
> host_inst_rate 734945 # Simulator instruction rate (inst/s)
> host_op_rate 864481 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 39854660745 # Simulator tick rate (ticks/s)
> host_mem_usage 745756 # Number of bytes of host memory used
> host_seconds 1190.84 # Real time elapsed on the host
649,652c649,652
< system.cpu0.dcache.demand_hits::cpu0.data 152875582 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 152875582 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 153075138 # number of overall hits
< system.cpu0.dcache.overall_hits::total 153075138 # number of overall hits
---
> system.cpu0.dcache.demand_hits::cpu0.data 153056972 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 153056972 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 153256528 # number of overall hits
> system.cpu0.dcache.overall_hits::total 153256528 # number of overall hits
665,668c665,668
< system.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses
< system.cpu0.dcache.overall_misses::total 4954267 # number of overall misses
---
> system.cpu0.dcache.demand_misses::cpu0.data 5084807 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 5084807 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 5704397 # number of overall misses
> system.cpu0.dcache.overall_misses::total 5704397 # number of overall misses
681,684c681,684
< system.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 128993802000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 128993802000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 128993802000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 128993802000 # number of overall miss cycles
697,700c697,700
< system.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 158141779 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 158141779 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 158960925 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 158960925 # number of overall (read+write) accesses
713,716c713,716
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032153 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.032153 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.035886 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.035886 # miss rate for overall accesses
729,732c729,732
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25368.475539 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 25368.475539 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.047795 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 22613.047795 # average overall miss latency
739,740d738
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
765,768c763,766
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses
---
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039170 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5039170 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5657616 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5657616 # number of overall MSHR misses
789,792c787,790
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 121748812000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 121748812000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136627701500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 136627701500 # number of overall MSHR miss cycles
795,798c793,794
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5439516500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5439516500 # number of overall MSHR uncacheable cycles
811,814c807,810
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.031865 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035591 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.035591 # mshr miss rate for overall accesses
829,832c825,828
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24160.489128 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24160.489128 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24149.341613 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24149.341613 # average overall mshr miss latency
835,839c831,832
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93183.891801 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93183.891801 # average overall mshr uncacheable latency
898,899d890
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
938d928
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1152,1153d1141
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1236,1237d1223
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5090437000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5090437000 # number of WriteReq MSHR uncacheable cycles
1239,1240c1225,1226
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10293852000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15924623500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5203415000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10834186500 # number of overall MSHR uncacheable cycles
1304,1305d1289
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency
1307,1309c1291,1292
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89139.257204 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106741.805338 # average overall mshr uncacheable latency
1637,1640c1620,1623
< system.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits
< system.cpu1.dcache.overall_hits::total 142761779 # number of overall hits
---
> system.cpu1.dcache.demand_hits::cpu1.data 142736138 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 142736138 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 142907237 # number of overall hits
> system.cpu1.dcache.overall_hits::total 142907237 # number of overall hits
1653,1656c1636,1639
< system.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 4814576 # number of overall misses
< system.cpu1.dcache.overall_misses::total 4814576 # number of overall misses
---
> system.cpu1.dcache.demand_misses::cpu1.data 4671770 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 4671770 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 5298071 # number of overall misses
> system.cpu1.dcache.overall_misses::total 5298071 # number of overall misses
1669,1672c1652,1655
< system.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 93474799500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 93474799500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 93474799500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 93474799500 # number of overall miss cycles
1685,1688c1668,1671
< system.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses
---
> system.cpu1.dcache.demand_accesses::cpu1.data 147407908 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 147407908 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 148205308 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 148205308 # number of overall (read+write) accesses
1701,1704c1684,1687
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses
---
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031693 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031693 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035748 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.035748 # miss rate for overall accesses
1717,1720c1700,1703
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20008.433527 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20008.433527 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17643.176073 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17643.176073 # average overall miss latency
1727,1728d1709
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1753,1756c1734,1737
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses
---
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4654676 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4654676 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5280977 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5280977 # number of overall MSHR misses
1777,1780c1758,1761
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 87347321500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 87347321500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101627300000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 101627300000 # number of overall MSHR miss cycles
1783,1786c1764,1765
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1460511000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1460511000 # number of overall MSHR uncacheable cycles
1799,1802c1778,1781
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses
---
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031577 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031577 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
1817,1820c1796,1799
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18765.499790 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18765.499790 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19244.033822 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19244.033822 # average overall mshr miss latency
1823,1827c1802,1803
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82032.745450 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82032.745450 # average overall mshr uncacheable latency
1885,1886d1860
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1925d1898
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2135,2136d2107
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2221,2222d2191
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1502902000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1502902000 # number of WriteReq MSHR uncacheable cycles
2224,2225c2193,2194
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2893353500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1390451500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1404390000 # number of overall MSHR uncacheable cycles
2289,2290d2257
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency
2292,2294c2259,2260
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78097.702763 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78396.226415 # average overall mshr uncacheable latency
2454,2455c2420,2421
< system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8919 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115607 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115647 # number of demand (read+write) misses
2457,2458c2423,2424
< system.iocache.overall_misses::realview.ide 8879 # number of overall misses
< system.iocache.overall_misses::total 8919 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115607 # number of overall misses
> system.iocache.overall_misses::total 115647 # number of overall misses
2467,2468c2433,2434
< system.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15227361857 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15232928857 # number of demand (read+write) miss cycles
2470,2471c2436,2437
< system.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15227361857 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15232928857 # number of overall miss cycles
2480,2481c2446,2447
< system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115607 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115647 # number of demand (read+write) accesses
2483,2484c2449,2450
< system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115607 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115647 # number of overall (read+write) accesses
2506,2507c2472,2473
< system.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131719.187329 # average overall miss latency
2509,2510c2475,2476
< system.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131719.187329 # average overall miss latency
2517,2518d2482
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2529,2530c2493,2494
< system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115607 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115647 # number of demand (read+write) MSHR misses
2532,2533c2496,2497
< system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115607 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115647 # number of overall MSHR misses
2542,2543c2506,2507
< system.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9440544593 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9444111593 # number of demand (read+write) MSHR miss cycles
2545,2546c2509,2510
< system.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9440544593 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9444111593 # number of overall MSHR miss cycles
2568,2569c2532,2533
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency
2571,2573c2535,2536
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency
2900,2901d2862
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
3029,3031d2989
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4598373544 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1348007106 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5946380650 # number of WriteReq MSHR uncacheable cycles
3033c2991
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9271594067 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4673220523 # number of overall MSHR uncacheable cycles
3035,3036c2993,2994
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2581608624 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 16719680691 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1233601518 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10773300041 # number of overall MSHR uncacheable cycles
3134,3136d3091
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency
3138c3093
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80056.540977 # average overall mshr uncacheable latency
3140,3142c3095,3096
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69295.670037 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 90220.331804 # average overall mshr uncacheable latency
< host_inst_rate 731783 # Simulator instruction rate (inst/s)
< host_op_rate 860761 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 39683148028 # Simulator tick rate (ticks/s)
< host_mem_usage 744736 # Number of bytes of host memory used
< host_seconds 1195.99 # Real time elapsed on the host
---
> host_inst_rate 734945 # Simulator instruction rate (inst/s)
> host_op_rate 864481 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 39854660745 # Simulator tick rate (ticks/s)
> host_mem_usage 745756 # Number of bytes of host memory used
> host_seconds 1190.84 # Real time elapsed on the host
649,652c649,652
< system.cpu0.dcache.demand_hits::cpu0.data 152875582 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 152875582 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 153075138 # number of overall hits
< system.cpu0.dcache.overall_hits::total 153075138 # number of overall hits
---
> system.cpu0.dcache.demand_hits::cpu0.data 153056972 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 153056972 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 153256528 # number of overall hits
> system.cpu0.dcache.overall_hits::total 153256528 # number of overall hits
665,668c665,668
< system.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses
< system.cpu0.dcache.overall_misses::total 4954267 # number of overall misses
---
> system.cpu0.dcache.demand_misses::cpu0.data 5084807 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 5084807 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 5704397 # number of overall misses
> system.cpu0.dcache.overall_misses::total 5704397 # number of overall misses
681,684c681,684
< system.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 128993802000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 128993802000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 128993802000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 128993802000 # number of overall miss cycles
697,700c697,700
< system.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 158141779 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 158141779 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 158960925 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 158960925 # number of overall (read+write) accesses
713,716c713,716
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032153 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.032153 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.035886 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.035886 # miss rate for overall accesses
729,732c729,732
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25368.475539 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 25368.475539 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.047795 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 22613.047795 # average overall miss latency
739,740d738
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
765,768c763,766
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses
---
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039170 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5039170 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5657616 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5657616 # number of overall MSHR misses
789,792c787,790
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 121748812000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 121748812000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136627701500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 136627701500 # number of overall MSHR miss cycles
795,798c793,794
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5439516500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5439516500 # number of overall MSHR uncacheable cycles
811,814c807,810
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.031865 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035591 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.035591 # mshr miss rate for overall accesses
829,832c825,828
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24160.489128 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24160.489128 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24149.341613 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24149.341613 # average overall mshr miss latency
835,839c831,832
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93183.891801 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93183.891801 # average overall mshr uncacheable latency
898,899d890
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
938d928
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1152,1153d1141
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1236,1237d1223
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5090437000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5090437000 # number of WriteReq MSHR uncacheable cycles
1239,1240c1225,1226
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10293852000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15924623500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5203415000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10834186500 # number of overall MSHR uncacheable cycles
1304,1305d1289
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency
1307,1309c1291,1292
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89139.257204 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 106741.805338 # average overall mshr uncacheable latency
1637,1640c1620,1623
< system.cpu1.dcache.demand_hits::cpu1.data 142590680 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 142590680 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 142761779 # number of overall hits
< system.cpu1.dcache.overall_hits::total 142761779 # number of overall hits
---
> system.cpu1.dcache.demand_hits::cpu1.data 142736138 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 142736138 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 142907237 # number of overall hits
> system.cpu1.dcache.overall_hits::total 142907237 # number of overall hits
1653,1656c1636,1639
< system.cpu1.dcache.demand_misses::cpu1.data 4188275 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 4188275 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 4814576 # number of overall misses
< system.cpu1.dcache.overall_misses::total 4814576 # number of overall misses
---
> system.cpu1.dcache.demand_misses::cpu1.data 4671770 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 4671770 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 5298071 # number of overall misses
> system.cpu1.dcache.overall_misses::total 5298071 # number of overall misses
1669,1672c1652,1655
< system.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 93474799500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 93474799500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 93474799500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 93474799500 # number of overall miss cycles
1685,1688c1668,1671
< system.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses
---
> system.cpu1.dcache.demand_accesses::cpu1.data 147407908 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 147407908 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 148205308 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 148205308 # number of overall (read+write) accesses
1701,1704c1684,1687
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses
---
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031693 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031693 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035748 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.035748 # miss rate for overall accesses
1717,1720c1700,1703
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20008.433527 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20008.433527 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17643.176073 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17643.176073 # average overall miss latency
1727,1728d1709
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1753,1756c1734,1737
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses
---
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4654676 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4654676 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5280977 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5280977 # number of overall MSHR misses
1777,1780c1758,1761
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 87347321500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 87347321500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101627300000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 101627300000 # number of overall MSHR miss cycles
1783,1786c1764,1765
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1460511000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1460511000 # number of overall MSHR uncacheable cycles
1799,1802c1778,1781
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses
---
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031577 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031577 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
1817,1820c1796,1799
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18765.499790 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18765.499790 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19244.033822 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19244.033822 # average overall mshr miss latency
1823,1827c1802,1803
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82032.745450 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82032.745450 # average overall mshr uncacheable latency
1885,1886d1860
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1925d1898
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2135,2136d2107
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2221,2222d2191
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1502902000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1502902000 # number of WriteReq MSHR uncacheable cycles
2224,2225c2193,2194
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2893353500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1390451500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1404390000 # number of overall MSHR uncacheable cycles
2289,2290d2257
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency
2292,2294c2259,2260
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78097.702763 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78396.226415 # average overall mshr uncacheable latency
2454,2455c2420,2421
< system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8919 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115607 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115647 # number of demand (read+write) misses
2457,2458c2423,2424
< system.iocache.overall_misses::realview.ide 8879 # number of overall misses
< system.iocache.overall_misses::total 8919 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115607 # number of overall misses
> system.iocache.overall_misses::total 115647 # number of overall misses
2467,2468c2433,2434
< system.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15227361857 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15232928857 # number of demand (read+write) miss cycles
2470,2471c2436,2437
< system.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15227361857 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15232928857 # number of overall miss cycles
2480,2481c2446,2447
< system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115607 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115647 # number of demand (read+write) accesses
2483,2484c2449,2450
< system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115607 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115647 # number of overall (read+write) accesses
2506,2507c2472,2473
< system.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131719.187329 # average overall miss latency
2509,2510c2475,2476
< system.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 131716.607619 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131719.187329 # average overall miss latency
2517,2518d2482
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2529,2530c2493,2494
< system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115607 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115647 # number of demand (read+write) MSHR misses
2532,2533c2496,2497
< system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115607 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115647 # number of overall MSHR misses
2542,2543c2506,2507
< system.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9440544593 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9444111593 # number of demand (read+write) MSHR miss cycles
2545,2546c2509,2510
< system.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9440544593 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9444111593 # number of overall MSHR miss cycles
2568,2569c2532,2533
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency
2571,2573c2535,2536
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81660.665816 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81663.264875 # average overall mshr miss latency
2900,2901d2862
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
3029,3031d2989
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4598373544 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1348007106 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5946380650 # number of WriteReq MSHR uncacheable cycles
3033c2991
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9271594067 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4673220523 # number of overall MSHR uncacheable cycles
3035,3036c2993,2994
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2581608624 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 16719680691 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1233601518 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10773300041 # number of overall MSHR uncacheable cycles
3134,3136d3091
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency
3138c3093
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80056.540977 # average overall mshr uncacheable latency
3140,3142c3095,3096
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69295.670037 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 90220.331804 # average overall mshr uncacheable latency