3,5c3,5
< sim_seconds 47.593744 # Number of seconds simulated
< sim_ticks 47593744171500 # Number of ticks simulated
< final_tick 47593744171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.602418 # Number of seconds simulated
> sim_ticks 47602418253500 # Number of ticks simulated
> final_tick 47602418253500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 618435 # Simulator instruction rate (inst/s)
< host_op_rate 727668 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34163076444 # Simulator tick rate (ticks/s)
< host_mem_usage 740160 # Number of bytes of host memory used
< host_seconds 1393.13 # Real time elapsed on the host
< sim_insts 861562684 # Number of instructions simulated
< sim_ops 1013739401 # Number of ops (including micro ops) simulated
---
> host_inst_rate 704375 # Simulator instruction rate (inst/s)
> host_op_rate 828740 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38464814262 # Simulator tick rate (ticks/s)
> host_mem_usage 746580 # Number of bytes of host memory used
> host_seconds 1237.56 # Real time elapsed on the host
> sim_insts 871704321 # Number of instructions simulated
> sim_ops 1025613965 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 69440 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 68224 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 3088500 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 37423496 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 12959872 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 98944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 107776 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2567544 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 15084176 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 9154944 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory
< system.physmem.bytes_read::total 81051908 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 3088500 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2567544 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5656044 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 68863296 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 106624 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 114944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 3306740 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 39207752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 13461760 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 71360 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 71552 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 2461816 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 13970768 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 8718016 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 430784 # Number of bytes read from this memory
> system.physmem.bytes_read::total 81922116 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 3306740 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 2461816 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 5768556 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 69209472 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 68883880 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 1085 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 1066 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 88665 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 584755 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 202498 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1546 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1684 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 40206 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 235703 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 143046 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1306957 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1075989 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 69230056 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 1666 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 1796 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 92075 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 612634 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 210340 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 1115 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1118 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 38554 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 218306 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 136219 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6731 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1320554 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1081398 # Number of write requests responded to by this memory
50,66c50,66
< system.physmem.num_writes::total 1078563 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 1459 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 1433 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 64893 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 786311 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 272302 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2079 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 2264 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 53947 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 316936 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 192356 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9014 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1702995 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 64893 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 53947 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 118840 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1446898 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1083972 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 2240 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 2415 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 69466 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 823650 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 282796 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 1499 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 1503 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 51716 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 293489 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 183142 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9050 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1720965 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 69466 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 51716 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 121182 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1453907 # Write bandwidth from this memory (bytes/s)
69,126c69,126
< system.physmem.bw_write::total 1447331 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1446898 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 1459 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 1433 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 64893 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 786744 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 272302 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2079 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 2264 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 53947 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 316936 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 192356 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9014 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3150326 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1306957 # Number of read requests accepted
< system.physmem.writeReqs 1078563 # Number of write requests accepted
< system.physmem.readBursts 1306957 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1078563 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 83609728 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue
< system.physmem.bytesWritten 68881216 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 81051908 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 68883880 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 450744 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 74137 # Per bank write bursts
< system.physmem.perBankRdBursts::1 79440 # Per bank write bursts
< system.physmem.perBankRdBursts::2 74164 # Per bank write bursts
< system.physmem.perBankRdBursts::3 81483 # Per bank write bursts
< system.physmem.perBankRdBursts::4 82988 # Per bank write bursts
< system.physmem.perBankRdBursts::5 89928 # Per bank write bursts
< system.physmem.perBankRdBursts::6 78492 # Per bank write bursts
< system.physmem.perBankRdBursts::7 81076 # Per bank write bursts
< system.physmem.perBankRdBursts::8 74414 # Per bank write bursts
< system.physmem.perBankRdBursts::9 117966 # Per bank write bursts
< system.physmem.perBankRdBursts::10 72212 # Per bank write bursts
< system.physmem.perBankRdBursts::11 83486 # Per bank write bursts
< system.physmem.perBankRdBursts::12 77461 # Per bank write bursts
< system.physmem.perBankRdBursts::13 81836 # Per bank write bursts
< system.physmem.perBankRdBursts::14 80080 # Per bank write bursts
< system.physmem.perBankRdBursts::15 77239 # Per bank write bursts
< system.physmem.perBankWrBursts::0 62409 # Per bank write bursts
< system.physmem.perBankWrBursts::1 67459 # Per bank write bursts
< system.physmem.perBankWrBursts::2 64157 # Per bank write bursts
< system.physmem.perBankWrBursts::3 68996 # Per bank write bursts
< system.physmem.perBankWrBursts::4 69521 # Per bank write bursts
< system.physmem.perBankWrBursts::5 74527 # Per bank write bursts
< system.physmem.perBankWrBursts::6 66146 # Per bank write bursts
< system.physmem.perBankWrBursts::7 68657 # Per bank write bursts
< system.physmem.perBankWrBursts::8 63193 # Per bank write bursts
< system.physmem.perBankWrBursts::9 66730 # Per bank write bursts
< system.physmem.perBankWrBursts::10 63431 # Per bank write bursts
< system.physmem.perBankWrBursts::11 70210 # Per bank write bursts
< system.physmem.perBankWrBursts::12 65844 # Per bank write bursts
< system.physmem.perBankWrBursts::13 70148 # Per bank write bursts
< system.physmem.perBankWrBursts::14 68557 # Per bank write bursts
< system.physmem.perBankWrBursts::15 66284 # Per bank write bursts
---
> system.physmem.bw_write::total 1454339 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1453907 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2240 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 2415 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 69466 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 824083 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 282796 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 1499 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 1503 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 51716 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 293489 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 183142 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9050 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3175304 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1320554 # Number of read requests accepted
> system.physmem.writeReqs 1083972 # Number of write requests accepted
> system.physmem.readBursts 1320554 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1083972 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 84482048 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 33408 # Total number of bytes read from write queue
> system.physmem.bytesWritten 69229248 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 81922116 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 69230056 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 522 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 79060 # Per bank write bursts
> system.physmem.perBankRdBursts::1 84693 # Per bank write bursts
> system.physmem.perBankRdBursts::2 79264 # Per bank write bursts
> system.physmem.perBankRdBursts::3 82906 # Per bank write bursts
> system.physmem.perBankRdBursts::4 76161 # Per bank write bursts
> system.physmem.perBankRdBursts::5 86285 # Per bank write bursts
> system.physmem.perBankRdBursts::6 80943 # Per bank write bursts
> system.physmem.perBankRdBursts::7 81570 # Per bank write bursts
> system.physmem.perBankRdBursts::8 74520 # Per bank write bursts
> system.physmem.perBankRdBursts::9 121634 # Per bank write bursts
> system.physmem.perBankRdBursts::10 72298 # Per bank write bursts
> system.physmem.perBankRdBursts::11 79752 # Per bank write bursts
> system.physmem.perBankRdBursts::12 77563 # Per bank write bursts
> system.physmem.perBankRdBursts::13 85585 # Per bank write bursts
> system.physmem.perBankRdBursts::14 78768 # Per bank write bursts
> system.physmem.perBankRdBursts::15 79030 # Per bank write bursts
> system.physmem.perBankWrBursts::0 65472 # Per bank write bursts
> system.physmem.perBankWrBursts::1 70626 # Per bank write bursts
> system.physmem.perBankWrBursts::2 66791 # Per bank write bursts
> system.physmem.perBankWrBursts::3 69615 # Per bank write bursts
> system.physmem.perBankWrBursts::4 63756 # Per bank write bursts
> system.physmem.perBankWrBursts::5 71331 # Per bank write bursts
> system.physmem.perBankWrBursts::6 67500 # Per bank write bursts
> system.physmem.perBankWrBursts::7 68943 # Per bank write bursts
> system.physmem.perBankWrBursts::8 63410 # Per bank write bursts
> system.physmem.perBankWrBursts::9 68673 # Per bank write bursts
> system.physmem.perBankWrBursts::10 63007 # Per bank write bursts
> system.physmem.perBankWrBursts::11 67951 # Per bank write bursts
> system.physmem.perBankWrBursts::12 66506 # Per bank write bursts
> system.physmem.perBankWrBursts::13 73077 # Per bank write bursts
> system.physmem.perBankWrBursts::14 66769 # Per bank write bursts
> system.physmem.perBankWrBursts::15 68280 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 30 # Number of times write queue was full causing retry
< system.physmem.totGap 47593740806000 # Total gap between requests
---
> system.physmem.numWrRetry 42 # Number of times write queue was full causing retry
> system.physmem.totGap 47602414888000 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1263732 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1277329 # Read request sizes (log2)
143,164c143,164
< system.physmem.writePktSize::6 1075989 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1091015 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 68737 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 30330 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 25975 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 22184 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 19490 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 16927 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 14904 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 11891 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1868 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 888 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 551 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 438 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 304 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 237 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 204 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 147 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1081398 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1104957 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 68933 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 30329 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 25891 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 22057 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 19390 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 16894 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 14853 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 11934 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 867 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 435 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 305 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 221 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 191 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 130 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
191,257c191,257
< system.physmem.wrQLenPdf::15 18318 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 20896 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 46603 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 53376 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 57792 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 60877 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 64132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 65344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 67196 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 67473 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 69715 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 73497 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 68447 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 68375 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 71528 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 66722 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 63618 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 62101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1601 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 781 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 693 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 586 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 317 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 356 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 373 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 363 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 225 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 274 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 301 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 840117 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 181.511175 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 111.812729 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 240.875315 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 520248 61.93% 61.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 156423 18.62% 80.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 51977 6.19% 86.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 27385 3.26% 89.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 18542 2.21% 92.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 11713 1.39% 93.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 8913 1.06% 94.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 8910 1.06% 95.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 36006 4.29% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 840117 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 60330 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 21.654169 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 330.190002 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 60327 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 18639 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 22143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 48134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 53739 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 58424 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 60173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 62461 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 64493 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 65899 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 66079 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 68869 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 71761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 68201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 69441 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 73837 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 67956 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 64592 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 63507 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 2802 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 964 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 646 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 634 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 464 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 357 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 329 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 297 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 285 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 850234 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 180.786598 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 111.487051 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 240.213026 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 527654 62.06% 62.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 158419 18.63% 80.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 52205 6.14% 86.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 27644 3.25% 90.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 18445 2.17% 92.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 11596 1.36% 93.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 9081 1.07% 94.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 9121 1.07% 95.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 36069 4.24% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 850234 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 60429 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 21.843949 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 329.896328 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 60426 100.00% 100.00% # Reads before turning the bus around for writes
261,302c261,306
< system.physmem.rdPerTurnAround::total 60330 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 60330 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.839698 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.269040 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 7.176072 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 56620 93.85% 93.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 1546 2.56% 96.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 276 0.46% 96.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 296 0.49% 97.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 110 0.18% 97.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 266 0.44% 97.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 180 0.30% 98.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 98 0.16% 98.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 97 0.16% 98.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 84 0.14% 98.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 48 0.08% 98.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 66 0.11% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 398 0.66% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 43 0.07% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 35 0.06% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 96 0.16% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 19 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 60330 # Writes before turning the bus around for reads
< system.physmem.totQLat 28430560155 # Total ticks spent queuing
< system.physmem.totMemAccLat 52925597655 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 6532010000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 21762.49 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 60429 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 60429 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.900462 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.285869 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 7.671229 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 56824 94.03% 94.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 1552 2.57% 96.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 279 0.46% 97.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 180 0.30% 97.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 145 0.24% 97.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 117 0.19% 97.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 182 0.30% 98.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 82 0.14% 98.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 275 0.46% 98.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 67 0.11% 98.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 37 0.06% 98.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 44 0.07% 98.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 253 0.42% 99.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 30 0.05% 99.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 37 0.06% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 152 0.25% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 3 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 60429 # Writes before turning the bus around for reads
> system.physmem.totQLat 28489428593 # Total ticks spent queuing
> system.physmem.totMemAccLat 53240028593 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 6600160000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 21582.38 # Average queueing delay per DRAM burst
304,305c308,309
< system.physmem.avgMemAccLat 40512.49 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.76 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 40332.38 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s
307c311
< system.physmem.avgRdBWSys 1.70 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s
313,331c317,335
< system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing
< system.physmem.readRowHits 1047491 # Number of row buffer hits during reads
< system.physmem.writeRowHits 495062 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 46.00 # Row buffer hit rate for writes
< system.physmem.avgGap 19951096.95 # Average gap between requests
< system.physmem.pageHitRate 64.74 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3221134560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1757563500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 5005283400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3511330560 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1216360497735 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27489261984750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31827709611225 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.737288 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45730304477620 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1589259620000 # Time in different power states
---
> system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing
> system.physmem.readRowHits 1056858 # Number of row buffer hits during reads
> system.physmem.writeRowHits 494645 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 45.73 # Row buffer hit rate for writes
> system.physmem.avgGap 19797005.68 # Average gap between requests
> system.physmem.pageHitRate 64.60 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3250149840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1773395250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 5076832800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3525340320 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1224482966955 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27487341349500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31834608387225 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.760359 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45727050942416 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1589549260000 # Time in different power states
333c337
< system.physmem_0.memoryStateTime::ACT 274179379380 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 285815210084 # Time in different power states
335,345c339,349
< system.physmem_1.actEnergy 3130149960 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1707919125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 5184613200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3462892560 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1215861151230 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27489700008000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31827638550795 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.735795 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45731003279682 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1589259620000 # Time in different power states
---
> system.physmem_1.actEnergy 3177619200 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1733820000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 5219370000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3484121040 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1221031665405 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27490368798750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31834173746955 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.751229 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45732072121963 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1589549260000 # Time in different power states
347c351
< system.physmem_1.memoryStateTime::ACT 273478576568 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 280793976787 # Time in different power states
378,380c382,384
< system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
< system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
< system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
---
> system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
> system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
> system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
411,419c415,423
< system.cpu0.dtb.walker.walks 93408 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 93408 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7983 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 70276 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 93401 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 0.278370 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 85.074143 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-2047 93400 100.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu0.dtb.walker.walks 112758 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 112758 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10038 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 87373 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 112734 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 0.230631 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 77.436531 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-2047 112733 100.00% 100.00% # Table walker wait (enqueue to first request) latency
421,445c425,451
< system.cpu0.dtb.walker.walkWaitTime::total 93401 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 78266 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 22499.341988 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 20923.382111 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 16650.912887 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 77590 99.14% 99.14% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 164 0.21% 99.35% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 417 0.53% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 25 0.03% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.04% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 78266 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 5219685476 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.596746 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.490551 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 2104860204 40.33% 40.33% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::1 3114825272 59.67% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 5219685476 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 70276 89.80% 89.80% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 7983 10.20% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 78259 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 93408 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkWaitTime::total 112734 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 97435 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 23281.346539 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 21381.718359 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 19258.937396 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 96246 98.78% 98.78% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 178 0.18% 98.96% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 868 0.89% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 97435 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 8883013024 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.766632 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.422974 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 2073007704 23.34% 23.34% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::1 6810005320 76.66% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 8883013024 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 87373 89.70% 89.70% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 10038 10.30% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 97411 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112758 # Table walker requests started/completed, data/inst
447,448c453,454
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 93408 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78259 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112758 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97411 # Table walker requests started/completed, data/inst
450,451c456,457
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78259 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 171667 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97411 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 210169 # Table walker requests started/completed, data/inst
454,457c460,463
< system.cpu0.dtb.read_hits 80327529 # DTB read hits
< system.cpu0.dtb.read_misses 69973 # DTB read misses
< system.cpu0.dtb.write_hits 72902451 # DTB write hits
< system.cpu0.dtb.write_misses 23435 # DTB write misses
---
> system.cpu0.dtb.read_hits 88968055 # DTB read hits
> system.cpu0.dtb.read_misses 85634 # DTB read misses
> system.cpu0.dtb.write_hits 80360369 # DTB write hits
> system.cpu0.dtb.write_misses 27124 # DTB write misses
460,462c466,468
< system.cpu0.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 34709 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 39097 # Number of entries that have been flushed from TLB
464c470
< system.cpu0.dtb.prefetch_faults 4393 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 3879 # Number of TLB faults due to prefetch
466,468c472,474
< system.cpu0.dtb.perms_faults 8867 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 80397502 # DTB read accesses
< system.cpu0.dtb.write_accesses 72925886 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 10141 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 89053689 # DTB read accesses
> system.cpu0.dtb.write_accesses 80387493 # DTB write accesses
470,472c476,478
< system.cpu0.dtb.hits 153229980 # DTB hits
< system.cpu0.dtb.misses 93408 # DTB misses
< system.cpu0.dtb.accesses 153323388 # DTB accesses
---
> system.cpu0.dtb.hits 169328424 # DTB hits
> system.cpu0.dtb.misses 112758 # DTB misses
> system.cpu0.dtb.accesses 169441182 # DTB accesses
502,523c508,529
< system.cpu0.itb.walker.walks 52417 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 52417 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 598 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46386 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 52417 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 52417 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 52417 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 46984 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 25232.568534 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 22985.913240 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 21269.412068 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-65535 46328 98.60% 98.60% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.09% 98.69% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-196607 530 1.13% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-262143 16 0.03% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-327679 24 0.05% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.04% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-458751 22 0.05% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 46984 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 62308 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 62308 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 814 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55869 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 62308 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 62308 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 62308 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 56683 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 26679.454157 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23625.111342 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 26536.909948 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 55487 97.89% 97.89% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.07% 97.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 988 1.74% 99.71% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.75% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 65 0.11% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 49 0.09% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 56683 # Table walker service (enqueue to completion) latency
527,529c533,535
< system.cpu0.itb.walker.walkPageSizes::4K 46386 98.73% 98.73% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 598 1.27% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 46984 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 55869 98.56% 98.56% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 814 1.44% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 56683 # Table walker page sizes translated
531,532c537,538
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52417 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52417 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62308 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62308 # Table walker requests started/completed, data/inst
534,538c540,544
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 46984 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 46984 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 99401 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 426699171 # ITB inst hits
< system.cpu0.itb.inst_misses 52417 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56683 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56683 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 118991 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 472241024 # ITB inst hits
> system.cpu0.itb.inst_misses 62308 # ITB inst misses
545,547c551,553
< system.cpu0.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 24801 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 28001 # Number of entries that have been flushed from TLB
554,558c560,564
< system.cpu0.itb.inst_accesses 426751588 # ITB inst accesses
< system.cpu0.itb.hits 426699171 # DTB hits
< system.cpu0.itb.misses 52417 # DTB misses
< system.cpu0.itb.accesses 426751588 # DTB accesses
< system.cpu0.numCycles 95186924479 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 472303332 # ITB inst accesses
> system.cpu0.itb.hits 472241024 # DTB hits
> system.cpu0.itb.misses 62308 # DTB misses
> system.cpu0.itb.accesses 472303332 # DTB accesses
> system.cpu0.numCycles 95204836507 # number of cpu cycles simulated
562,584c568,590
< system.cpu0.kern.inst.quiesce 4674 # number of quiesce instructions executed
< system.cpu0.committedInsts 426454163 # Number of instructions committed
< system.cpu0.committedOps 501120280 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 460758133 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 395268 # Number of float alu accesses
< system.cpu0.num_func_calls 25675920 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 64224693 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 460758133 # number of integer instructions
< system.cpu0.num_fp_insts 395268 # number of float instructions
< system.cpu0.num_int_register_reads 666544840 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 365452769 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 661868 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 282064 # number of times the floating registers were written
< system.cpu0.num_cc_register_reads 110079606 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 109774743 # number of times the CC registers were written
< system.cpu0.num_mem_refs 153223313 # number of memory refs
< system.cpu0.num_load_insts 80324545 # Number of load instructions
< system.cpu0.num_store_insts 72898768 # Number of store instructions
< system.cpu0.num_idle_cycles 94023627088.560516 # Number of idle cycles
< system.cpu0.num_busy_cycles 1163297390.439485 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.012221 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.987779 # Percentage of idle cycles
< system.cpu0.Branches 94888903 # Number of branches fetched
---
> system.cpu0.kern.inst.quiesce 5131 # number of quiesce instructions executed
> system.cpu0.committedInsts 471986732 # Number of instructions committed
> system.cpu0.committedOps 554132163 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 509304939 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 463756 # Number of float alu accesses
> system.cpu0.num_func_calls 28209702 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 71348449 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 509304939 # number of integer instructions
> system.cpu0.num_fp_insts 463756 # number of float instructions
> system.cpu0.num_int_register_reads 736700300 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 403898232 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 771652 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 344244 # number of times the floating registers were written
> system.cpu0.num_cc_register_reads 122509563 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 122079243 # number of times the CC registers were written
> system.cpu0.num_mem_refs 169317654 # number of memory refs
> system.cpu0.num_load_insts 88962856 # Number of load instructions
> system.cpu0.num_store_insts 80354798 # Number of store instructions
> system.cpu0.num_idle_cycles 93934250531.242035 # Number of idle cycles
> system.cpu0.num_busy_cycles 1270585975.757973 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.013346 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.986654 # Percentage of idle cycles
> system.cpu0.Branches 105166310 # Number of branches fetched
586,616c592,622
< system.cpu0.op_class::IntAlu 346960051 69.20% 69.20% # Class of executed instruction
< system.cpu0.op_class::IntMult 1125201 0.22% 69.42% # Class of executed instruction
< system.cpu0.op_class::IntDiv 62694 0.01% 69.43% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 37154 0.01% 69.44% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction
< system.cpu0.op_class::MemRead 80324545 16.02% 85.46% # Class of executed instruction
< system.cpu0.op_class::MemWrite 72898768 14.54% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 383762588 69.22% 69.22% # Class of executed instruction
> system.cpu0.op_class::IntMult 1237276 0.22% 69.44% # Class of executed instruction
> system.cpu0.op_class::IntDiv 66509 0.01% 69.45% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 45552 0.01% 69.46% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction
> system.cpu0.op_class::MemRead 88962856 16.05% 85.51% # Class of executed instruction
> system.cpu0.op_class::MemWrite 80354798 14.49% 100.00% # Class of executed instruction
619,624c625,630
< system.cpu0.op_class::total 501408413 # Class of executed instruction
< system.cpu0.dcache.tags.replacements 5237512 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 505.877232 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 147745204 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5237891 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 28.207002 # Average number of references to valid blocks.
---
> system.cpu0.op_class::total 554429579 # Class of executed instruction
> system.cpu0.dcache.tags.replacements 5824476 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 506.611071 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 163267162 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5824987 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 28.028760 # Average number of references to valid blocks.
626,724c632,731
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.877232 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988041 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.988041 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 379 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 370 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.740234 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 311719457 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 311719457 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 74802484 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 74802484 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 68840975 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 68840975 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186514 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 186514 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 133741 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 133741 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1712983 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1712983 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1673957 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1673957 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 143643459 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 143643459 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 143829973 # number of overall hits
< system.cpu0.dcache.overall_hits::total 143829973 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 2859232 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 2859232 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1316810 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1316810 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 596453 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 596453 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 721743 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 721743 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153137 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 153137 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190741 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 190741 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 4176042 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 4176042 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 4772495 # number of overall misses
< system.cpu0.dcache.overall_misses::total 4772495 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45650819500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 45650819500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34330450500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 34330450500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65187396500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 65187396500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2390631500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2390631500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5489081000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 5489081000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7149000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7149000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 79981270000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 79981270000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 79981270000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 79981270000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 77661716 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 77661716 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 70157785 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 70157785 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 782967 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 782967 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 855484 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 855484 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1866120 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 1866120 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1864698 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 1864698 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 147819501 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 147819501 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 148602468 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 148602468 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036816 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.036816 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018769 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.018769 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761786 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.761786 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843666 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843666 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082062 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082062 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102291 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102291 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028251 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.028251 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032116 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.032116 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15966.112404 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 15966.112404 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26070.921773 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 26070.921773 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90319.402474 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90319.402474 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15611.063949 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15611.063949 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28777.667098 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28777.667098 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.611071 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989475 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.989475 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 344508686 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 344508686 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 82887500 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 82887500 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 75943802 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 75943802 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196404 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 196404 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 140054 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 140054 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847526 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1847526 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1825483 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1825483 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 158831302 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 158831302 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 159027706 # number of overall hits
> system.cpu0.dcache.overall_hits::total 159027706 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 3189198 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 3189198 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1439126 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1439126 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657536 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 657536 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792800 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 792800 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174919 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 174919 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195568 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 195568 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 4628324 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 4628324 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 5285860 # number of overall misses
> system.cpu0.dcache.overall_misses::total 5285860 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52614413500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 52614413500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36171191500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 36171191500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 66218479500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 66218479500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2808474500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2808474500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5670137000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 5670137000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6661000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6661000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 88785605000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 88785605000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 88785605000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 88785605000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 86076698 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 86076698 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 77382928 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 77382928 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853940 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 853940 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 932854 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 932854 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2022445 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2022445 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2021051 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2021051 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 163459626 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 163459626 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 164313566 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 164313566 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037051 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.037051 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018597 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.018597 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770003 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770003 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.849865 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.849865 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086489 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086489 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096765 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096765 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028315 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.028315 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032169 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.032169 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16497.694248 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 16497.694248 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25134.138012 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 25134.138012 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83524.822780 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83524.822780 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16055.857283 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16055.857283 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28993.173730 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28993.173730 # average StoreCondReq miss latency
727,730c734,737
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19152.410345 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19152.410345 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16758.795976 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 16758.795976 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19183.100621 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19183.100621 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16796.813574 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 16796.813574 # average overall miss latency
739,824c746,831
< system.cpu0.dcache.writebacks::writebacks 5237512 # number of writebacks
< system.cpu0.dcache.writebacks::total 5237512 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25341 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 25341 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21295 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 21295 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39838 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39838 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 46636 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 46636 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 46636 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 46636 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2833891 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 2833891 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1295515 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1295515 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595169 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 595169 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 721743 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 721743 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113299 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113299 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190741 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 190741 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4129406 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4129406 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 4724575 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 4724575 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16746 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17968 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34714 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41050881000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41050881000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32444395000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32444395000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14818032000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14818032000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64465653500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64465653500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564895500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564895500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5298419000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5298419000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7070000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7070000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73495276000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 73495276000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 88313308000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 88313308000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897717500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897717500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3102799000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3102799000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6000516500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6000516500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036490 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036490 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018466 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760146 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760146 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.843666 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.843666 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060714 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060714 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102291 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102291 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027935 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031793 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031793 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14485.695110 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14485.695110 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25043.627438 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25043.627438 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24897.183825 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24897.183825 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89319.402474 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89319.402474 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13812.085720 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.085720 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27778.081273 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27778.081273 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 5824476 # number of writebacks
> system.cpu0.dcache.writebacks::total 5824476 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27468 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 27468 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21247 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 21247 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43989 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43989 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 48715 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 48715 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 48715 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 48715 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3161730 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3161730 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417879 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1417879 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656252 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 656252 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792800 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 792800 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 130930 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 130930 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195568 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 195568 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579609 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4579609 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5235861 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5235861 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14992 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15725 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30717 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47545298500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47545298500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34168378500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34168378500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16138287000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16138287000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 65425679500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65425679500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1807284000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1807284000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5474645000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5474645000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6585000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6585000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 81713677000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 81713677000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97851964000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 97851964000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2585195500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2585195500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2654242000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654242000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5239437500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5239437500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036732 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018323 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018323 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768499 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768499 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.849865 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.849865 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064738 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064738 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096765 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096765 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028017 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.028017 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.031865 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15037.747847 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15037.747847 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24098.232994 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24098.232994 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24591.600483 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24591.600483 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82524.822780 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82524.822780 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13803.436951 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13803.436951 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27993.562341 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27993.562341 # average StoreCondReq mshr miss latency
827,836c834,843
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17798.026157 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17798.026157 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18692.328516 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18692.328516 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173039.382539 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173039.382539 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172684.717275 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172684.717275 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172855.807455 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172855.807455 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17842.937465 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17842.937465 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18688.800944 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18688.800944 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172438.333778 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172438.333778 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168791.224165 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168791.224165 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170571.263470 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170571.263470 # average overall mshr uncacheable latency
838,842c845,849
< system.cpu0.icache.tags.replacements 4772370 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.827216 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 421926289 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 4772882 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 88.400738 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 5187208 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 467053304 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 5187720 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 90.030554 # Average number of references to valid blocks.
844c851
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827216 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor
848,849c855,858
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 395 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
851,888c860,897
< system.cpu0.icache.tags.tag_accesses 858171224 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 858171224 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 421926289 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 421926289 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 421926289 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 421926289 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 421926289 # number of overall hits
< system.cpu0.icache.overall_hits::total 421926289 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 4772882 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 4772882 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 4772882 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 4772882 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 4772882 # number of overall misses
< system.cpu0.icache.overall_misses::total 4772882 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52975952000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 52975952000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 52975952000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 52975952000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 52975952000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 52975952000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 426699171 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 426699171 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 426699171 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 426699171 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 426699171 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 426699171 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011186 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.011186 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011186 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.011186 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011186 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.011186 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11099.363445 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 11099.363445 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 11099.363445 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 11099.363445 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 949669768 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 949669768 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 467053304 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 467053304 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 467053304 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 467053304 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 467053304 # number of overall hits
> system.cpu0.icache.overall_hits::total 467053304 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 5187720 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 5187720 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 5187720 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 5187720 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 5187720 # number of overall misses
> system.cpu0.icache.overall_misses::total 5187720 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57877602000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 57877602000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 57877602000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 57877602000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 57877602000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 57877602000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 472241024 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 472241024 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 472241024 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 472241024 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 472241024 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 472241024 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010985 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.010985 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010985 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.010985 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010985 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.010985 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11156.654947 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11156.654947 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11156.654947 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11156.654947 # average overall miss latency
897,904c906,913
< system.cpu0.icache.writebacks::writebacks 4772370 # number of writebacks
< system.cpu0.icache.writebacks::total 4772370 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4772882 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 4772882 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 4772882 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 4772882 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 4772882 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 4772882 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 5187208 # number of writebacks
> system.cpu0.icache.writebacks::total 5187208 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5187720 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 5187720 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 5187720 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 5187720 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 5187720 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 5187720 # number of overall MSHR misses
909,914c918,923
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 50589511000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 50589511000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 50589511000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 50589511000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 50589511000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 50589511000 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 55283742000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 55283742000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 55283742000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 55283742000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 55283742000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 55283742000 # number of overall MSHR miss cycles
919,930c928,939
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011186 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.011186 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.011186 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.363445 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010985 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.010985 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.010985 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10656.654947 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency
936,938c945,947
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230591 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 7230639 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 7982984 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 7983049 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue
941,946c950,955
< system.cpu0.l2cache.prefetcher.pfSpanPage 940745 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2188465 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16163.582102 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 14109503 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2203636 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.402828 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1030695 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2438237 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16163.287998 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 15536795 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2453930 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.331393 # Average number of references to valid blocks.
948,1089c957,1102
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15163.258465 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.967950 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 74.840251 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 875.515436 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.925492 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003050 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004568 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053437 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.986547 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1542 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13561 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 58 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 726 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 758 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 590 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6261 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6710 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.094116 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.827698 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 339677714 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 339677714 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 214201 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 132495 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 346696 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 3462500 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 3462500 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 6546722 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 6546722 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 323 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 323 # number of UpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 835467 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 835467 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4337083 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 4337083 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2670834 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2670834 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164201 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 164201 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 214201 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 132495 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 4337083 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3506301 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 8190080 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 214201 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 132495 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 4337083 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3506301 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 8190080 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9167 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7221 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 16388 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 234409 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 234409 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190710 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 190710 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 31 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 31 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 244449 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 244449 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 435799 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 435799 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 871525 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 871525 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 555346 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 555346 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9167 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7221 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 435799 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1115974 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1568161 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9167 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7221 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 435799 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1115974 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1568161 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 351604000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 298997000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 650601000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3324963500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 3324963500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1970779500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1970779500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6951500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6951500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15779075998 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 15779075998 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17377629000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17377629000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34720917000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 34720917000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62263259000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 62263259000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 351604000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 298997000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17377629000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 50499992998 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 68528222998 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 351604000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 298997000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17377629000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 50499992998 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 68528222998 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 223368 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 139716 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 363084 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3462500 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 3462500 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 6546722 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 6546722 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 234732 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 234732 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190710 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 190710 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 31 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 31 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1079916 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1079916 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4772882 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 4772882 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3542359 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 3542359 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 719547 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 719547 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 223368 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 139716 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 4772882 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 4622275 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 9758241 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 223368 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 139716 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 4772882 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 4622275 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 9758241 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051683 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.045136 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998624 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998624 # miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15209.476134 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.686152 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 84.208097 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 811.917616 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.928313 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003521 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005140 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049556 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.986529 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1345 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14277 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 148 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 373 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 28 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 836 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4477 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6612 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2188 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082092 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871399 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 373900742 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 373900742 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267168 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160390 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 427558 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 3842470 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 3842470 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 7168468 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 7168468 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 471 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 471 # number of UpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 929656 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 929656 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695648 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 4695648 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2994194 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2994194 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216752 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 216752 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267168 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 160390 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 4695648 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3923850 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 9047056 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267168 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 160390 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 4695648 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3923850 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 9047056 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10276 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8531 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 18807 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 247276 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 247276 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195553 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 195553 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 15 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 259410 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 259410 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 492072 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 492072 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 954718 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 954718 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 574037 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 574037 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10276 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8531 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 492072 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1214128 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 1725007 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10276 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8531 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 492072 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1214128 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 1725007 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 446033500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 421456000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 867489500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3471551500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 3471551500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2028869500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2028869500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6470500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6470500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16372128999 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 16372128999 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 19305851000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 19305851000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40062303500 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40062303500 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62780545000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 62780545000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 446033500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 421456000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19305851000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 56434432499 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 76607772999 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 446033500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 421456000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19305851000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 56434432499 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 76607772999 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277444 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 168921 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 446365 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3842470 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 3842470 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 7168468 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 7168468 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 247747 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 247747 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195553 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 195553 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 15 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1189066 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1189066 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5187720 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 5187720 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3948912 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 3948912 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790789 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 790789 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277444 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 168921 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 5187720 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5137978 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 10772063 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277444 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 168921 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 5187720 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5137978 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 10772063 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037038 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050503 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.042134 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998099 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998099 # miss rate for UpgradeReq accesses
1094,1138c1107,1151
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.226359 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.226359 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091307 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091307 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.246030 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.246030 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771799 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771799 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051683 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091307 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241434 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.160701 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051683 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091307 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241434 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.160701 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41406.591885 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39699.841347 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14184.453242 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14184.453242 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10333.907504 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10333.907504 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 224241.935484 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 224241.935484 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64549.562477 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64549.562477 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39875.330141 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39875.330141 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39839.266802 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39839.266802 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 112116.156414 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 112116.156414 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41406.591885 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39875.330141 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45251.944040 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 43699.736824 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41406.591885 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39875.330141 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45251.944040 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 43699.736824 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.218163 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.218163 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.094853 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.094853 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.241767 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.241767 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.725904 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.725904 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037038 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050503 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.094853 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236305 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.160137 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037038 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050503 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.094853 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236305 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.160137 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43405.362009 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49402.883601 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46125.883979 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14039.176871 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14039.176871 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10375.036435 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10375.036435 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 431366.666667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 431366.666667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63112.944755 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63112.944755 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39233.793022 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39233.793022 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41962.447026 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41962.447026 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 109366.722006 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 109366.722006 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43405.362009 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49402.883601 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39233.793022 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46481.452120 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 44410.122973 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43405.362009 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49402.883601 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39233.793022 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46481.452120 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 44410.122973 # average overall miss latency
1147,1186c1160,1199
< system.cpu0.l2cache.writebacks::writebacks 1408018 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1408018 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5268 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 5268 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 532 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 532 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5800 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 5800 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5800 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 5800 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9167 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7221 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 16388 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 673244 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 673244 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 234409 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 234409 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190710 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190710 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 31 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 31 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 239181 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 239181 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 435799 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 435799 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 870993 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 870993 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 555346 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 555346 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9167 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7221 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 435799 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1110174 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1562361 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9167 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7221 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 435799 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1110174 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 673244 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2235605 # number of overall MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 1553882 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1553882 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5243 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5243 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 604 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 604 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5847 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 5847 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5847 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 5847 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10276 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8531 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 18807 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 729213 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 729213 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 247276 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 247276 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195553 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195553 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 15 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 254167 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 254167 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 492072 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 492072 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 954114 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 954114 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 574037 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 574037 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10276 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8531 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 492072 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1208281 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 1719160 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10276 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8531 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 492072 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1208281 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 729213 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2448373 # number of overall MSHR misses
1188,1191c1201,1204
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59871 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17968 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 58117 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15725 # number of WriteReq MSHR uncacheable
1193,1224c1206,1237
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77839 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 255671000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 552273000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37620512818 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37620512818 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7511827000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7511827000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3867075000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3867075000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6477500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6477500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13744375998 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13744375998 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14762835000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14762835000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29450022000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29450022000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 58931183000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 58931183000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 255671000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14762835000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43194397998 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 58509505998 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 255671000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14762835000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43194397998 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37620512818 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 96130018816 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 73842 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 384377500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 370270000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 754647500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39166505132 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 39166505132 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7760971000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7760971000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4006997499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4006997499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6014500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6014500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14251828999 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14251828999 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16353419000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16353419000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34284773000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34284773000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 59336323000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 59336323000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 384377500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 370270000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16353419000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 48536601999 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 65644668499 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 384377500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 370270000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16353419000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 48536601999 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39166505132 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 104811173631 # number of overall MSHR miss cycles
1226,1229c1239,1242
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2763179500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8393951000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2967633500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2967633500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2464927000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8095698500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2535920000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2535920000 # number of WriteReq MSHR uncacheable cycles
1231,1235c1244,1248
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5730813000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11361584500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045136 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5000847000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10631618500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037038 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050503 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadReq accesses
1238,1239c1251,1252
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998624 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998624 # mshr miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998099 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998099 # mshr miss rate for UpgradeReq accesses
1244,1260c1257,1273
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221481 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221481 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091307 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245879 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245879 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771799 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771799 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160107 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213753 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213753 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.094853 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094853 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241614 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241614 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.725904 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.725904 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037038 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050503 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.094853 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235167 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159594 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037038 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050503 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.094853 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235167 # mshr miss rate for overall accesses
1262,1292c1275,1305
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229099 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33699.841347 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55879.462450 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32045.813087 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32045.813087 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20277.253421 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20277.253421 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 208951.612903 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 208951.612903 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57464.330352 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57464.330352 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33875.330141 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33812.007674 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33812.007674 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 106116.156414 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 106116.156414 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37449.415339 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42999.554401 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227289 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40125.883979 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53710.651253 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31385.864378 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31385.864378 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20490.595895 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20490.595895 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400966.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400966.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56072.696294 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56072.696294 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33233.793022 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35933.623236 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35933.623236 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 103366.722006 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 103366.722006 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38184.153016 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42808.499208 # average overall mshr miss latency
1294,1297c1307,1310
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165005.344560 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 140200.614655 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165162.149377 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165162.149377 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164416.155283 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139300.006883 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161266.772655 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161266.772655 # average WriteReq mshr uncacheable latency
1299,1300c1312,1313
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165086.506885 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145962.621565 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 162803.887098 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143977.932613 # average overall mshr uncacheable latency
1302,1340c1315,1353
< system.cpu0.toL2Bus.snoop_filter.tot_requests 20776945 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 10662406 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 659 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 1726264 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1726085 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 488069 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 8911186 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 17968 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 17968 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 4874700 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 6546722 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 2139143 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 829102 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 434919 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350602 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 501065 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1159158 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1092705 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4772882 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4419934 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 726049 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 719547 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14404114 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17037537 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296236 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 495044 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 32232931 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 611051348 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 638823901 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1117728 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1786944 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1252779921 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 5965413 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 16750116 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.116655 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.321042 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 22819923 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11703604 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879398 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879148 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 250 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 571604 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 9815849 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 15726 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 15725 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 5399709 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 7169213 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 2378526 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 893354 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 436778 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 349583 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 518285 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1259427 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1201684 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5187720 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4806547 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 796318 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 790789 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15648898 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18825417 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 354875 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 604975 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 35434165 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 664167892 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 709387519 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1351368 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2219552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1377126331 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 6368237 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 18252902 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.116630 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.321021 # Request fanout histogram
1342,1344c1355,1357
< system.cpu0.toL2Bus.snoop_fanout::0 14796306 88.34% 88.34% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 1953631 11.66% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 16124321 88.34% 88.34% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 2128331 11.66% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 250 0.00% 100.00% # Request fanout histogram
1348,1349c1361,1362
< system.cpu0.toL2Bus.snoop_fanout::total 16750116 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 20546913496 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 18252902 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 22598952997 # Layer occupancy (ticks)
1351c1364
< system.cpu0.toL2Bus.snoopLayer0.occupancy 219185391 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 218107077 # Layer occupancy (ticks)
1353c1366
< system.cpu0.toL2Bus.respLayer0.occupancy 7202448000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 7824705000 # Layer occupancy (ticks)
1355c1368
< system.cpu0.toL2Bus.respLayer1.occupancy 7531952589 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 8347252415 # Layer occupancy (ticks)
1357c1370
< system.cpu0.toL2Bus.respLayer2.occupancy 156520499 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 185954998 # Layer occupancy (ticks)
1359c1372
< system.cpu0.toL2Bus.respLayer3.occupancy 271676000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 327531000 # Layer occupancy (ticks)
1390,1412c1403,1425
< system.cpu1.dtb.walker.walks 101882 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 101882 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8030 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79527 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 101873 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 0.078529 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 25.064580 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-511 101872 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 101873 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 87566 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 23519.505287 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 21365.105207 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 20825.826742 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 86337 98.60% 98.60% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 178 0.20% 98.80% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 904 1.03% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 19 0.02% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walks 91986 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 91986 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7535 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69987 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 91981 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 0.271795 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 82.431072 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-2047 91980 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 91981 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 77527 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 23020.089775 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 21173.462910 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 18225.313395 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 76677 98.90% 98.90% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.21% 99.12% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 586 0.76% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 21 0.03% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.03% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
1414,1425c1427,1438
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 87566 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 239339024 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 9.661342 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 -2072997220 -866.13% -866.13% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 2312336244 966.13% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 239339024 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 79528 90.83% 90.83% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 8030 9.17% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 87558 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101882 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 77527 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples -5562525576 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.783829 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.411632 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 -1202455220 21.62% 21.62% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 -4360070356 78.38% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total -5562525576 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 69988 90.28% 90.28% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 7535 9.72% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 77523 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 91986 # Table walker requests started/completed, data/inst
1427,1428c1440,1441
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101882 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87558 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 91986 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77523 # Table walker requests started/completed, data/inst
1430,1431c1443,1444
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87558 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 189440 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77523 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 169509 # Table walker requests started/completed, data/inst
1434,1437c1447,1450
< system.cpu1.dtb.read_hits 82176038 # DTB read hits
< system.cpu1.dtb.read_misses 74927 # DTB read misses
< system.cpu1.dtb.write_hits 74775352 # DTB write hits
< system.cpu1.dtb.write_misses 26955 # DTB write misses
---
> system.cpu1.dtb.read_hits 75524944 # DTB read hits
> system.cpu1.dtb.read_misses 67300 # DTB read misses
> system.cpu1.dtb.write_hits 69031204 # DTB write hits
> system.cpu1.dtb.write_misses 24686 # DTB write misses
1440,1442c1453,1455
< system.cpu1.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 37701 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 34037 # Number of entries that have been flushed from TLB
1444c1457
< system.cpu1.dtb.prefetch_faults 4186 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 4586 # Number of TLB faults due to prefetch
1446,1448c1459,1461
< system.cpu1.dtb.perms_faults 10277 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 82250965 # DTB read accesses
< system.cpu1.dtb.write_accesses 74802307 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 9261 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 75592244 # DTB read accesses
> system.cpu1.dtb.write_accesses 69055890 # DTB write accesses
1450,1452c1463,1465
< system.cpu1.dtb.hits 156951390 # DTB hits
< system.cpu1.dtb.misses 101882 # DTB misses
< system.cpu1.dtb.accesses 157053272 # DTB accesses
---
> system.cpu1.dtb.hits 144556148 # DTB hits
> system.cpu1.dtb.misses 91986 # DTB misses
> system.cpu1.dtb.accesses 144648134 # DTB accesses
1482,1509c1495,1523
< system.cpu1.itb.walker.walks 63786 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 63786 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 574 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58046 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 63786 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 63786 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 63786 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 58620 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 26694.208461 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 23680.273613 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 26398.773524 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 57379 97.88% 97.88% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 45 0.08% 97.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 1025 1.75% 99.71% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 33 0.06% 99.76% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 49 0.08% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 58620 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 58046 99.02% 99.02% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 574 0.98% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 58620 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 54155 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 54155 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 390 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48650 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 54155 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 54155 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 54155 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 49040 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 26306.504894 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 23642.829205 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 24027.787857 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 48185 98.26% 98.26% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 51 0.10% 98.36% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 689 1.40% 99.77% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.04% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 49040 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples -2103778220 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 -2103778220 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total -2103778220 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 48650 99.20% 99.20% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 390 0.80% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 49040 # Table walker page sizes translated
1511,1512c1525,1526
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63786 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63786 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54155 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54155 # Table walker requests started/completed, data/inst
1514,1518c1528,1532
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58620 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58620 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 122406 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 435405767 # ITB inst hits
< system.cpu1.itb.inst_misses 63786 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49040 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49040 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 103195 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 400011912 # ITB inst hits
> system.cpu1.itb.inst_misses 54155 # ITB inst misses
1525,1527c1539,1541
< system.cpu1.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 26334 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 23432 # Number of entries that have been flushed from TLB
1534,1538c1548,1552
< system.cpu1.itb.inst_accesses 435469553 # ITB inst accesses
< system.cpu1.itb.hits 435405767 # DTB hits
< system.cpu1.itb.misses 63786 # DTB misses
< system.cpu1.itb.accesses 435469553 # DTB accesses
< system.cpu1.numCycles 95187488343 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 400066067 # ITB inst accesses
> system.cpu1.itb.hits 400011912 # DTB hits
> system.cpu1.itb.misses 54155 # DTB misses
> system.cpu1.itb.accesses 400066067 # DTB accesses
> system.cpu1.numCycles 95204836507 # number of cpu cycles simulated
1542,1564c1556,1578
< system.cpu1.kern.inst.quiesce 14345 # number of quiesce instructions executed
< system.cpu1.committedInsts 435108521 # Number of instructions committed
< system.cpu1.committedOps 512619121 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 471360298 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 517037 # Number of float alu accesses
< system.cpu1.num_func_calls 26310177 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 66181606 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 471360298 # number of integer instructions
< system.cpu1.num_fp_insts 517037 # number of float instructions
< system.cpu1.num_int_register_reads 683625420 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 373659475 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 819092 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 470852 # number of times the floating registers were written
< system.cpu1.num_cc_register_reads 112718016 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 112414585 # number of times the CC registers were written
< system.cpu1.num_mem_refs 156939308 # number of memory refs
< system.cpu1.num_load_insts 82171340 # Number of load instructions
< system.cpu1.num_store_insts 74767968 # Number of store instructions
< system.cpu1.num_idle_cycles 94109373851.176025 # Number of idle cycles
< system.cpu1.num_busy_cycles 1078114491.823977 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.011326 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.988674 # Percentage of idle cycles
< system.cpu1.Branches 97258514 # Number of branches fetched
---
> system.cpu1.kern.inst.quiesce 14080 # number of quiesce instructions executed
> system.cpu1.committedInsts 399717589 # Number of instructions committed
> system.cpu1.committedOps 471481802 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 433690793 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 447669 # Number of float alu accesses
> system.cpu1.num_func_calls 24290810 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 60559296 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 433690793 # number of integer instructions
> system.cpu1.num_fp_insts 447669 # number of float instructions
> system.cpu1.num_int_register_reads 628918503 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 343906147 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 709471 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 405960 # number of times the floating registers were written
> system.cpu1.num_cc_register_reads 102969972 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 102767338 # number of times the CC registers were written
> system.cpu1.num_mem_refs 144547138 # number of memory refs
> system.cpu1.num_load_insts 75521772 # Number of load instructions
> system.cpu1.num_store_insts 69025366 # Number of store instructions
> system.cpu1.num_idle_cycles 94207572529.552017 # Number of idle cycles
> system.cpu1.num_busy_cycles 997263977.447979 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.010475 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.989525 # Percentage of idle cycles
> system.cpu1.Branches 89155171 # Number of branches fetched
1566,1596c1580,1610
< system.cpu1.op_class::IntAlu 354775953 69.17% 69.17% # Class of executed instruction
< system.cpu1.op_class::IntMult 1066461 0.21% 69.38% # Class of executed instruction
< system.cpu1.op_class::IntDiv 59336 0.01% 69.39% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.39% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 75375 0.01% 69.40% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 69.40% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.40% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.40% # Class of executed instruction
< system.cpu1.op_class::MemRead 82171340 16.02% 85.42% # Class of executed instruction
< system.cpu1.op_class::MemWrite 74767968 14.58% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 326125112 69.13% 69.13% # Class of executed instruction
> system.cpu1.op_class::IntMult 978063 0.21% 69.33% # Class of executed instruction
> system.cpu1.op_class::IntDiv 57214 0.01% 69.35% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 68664 0.01% 69.36% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction
> system.cpu1.op_class::MemRead 75521772 16.01% 85.37% # Class of executed instruction
> system.cpu1.op_class::MemWrite 69025366 14.63% 100.00% # Class of executed instruction
1599,1705c1613,1719
< system.cpu1.op_class::total 512916476 # Class of executed instruction
< system.cpu1.dcache.tags.replacements 5113111 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 443.711015 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 151630595 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5113623 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 29.652283 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.711015 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.866623 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.866623 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 319002554 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 319002554 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 76632055 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 76632055 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 70902064 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 70902064 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183506 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 183506 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 192465 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 192465 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1673719 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1673719 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1647145 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1647145 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 147534119 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 147534119 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 147717625 # number of overall hits
< system.cpu1.dcache.overall_hits::total 147717625 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 2895739 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 2895739 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1291835 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1291835 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 599128 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 599128 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 515597 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 515597 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170116 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 170116 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195350 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 195350 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 4187574 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 4187574 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 4786702 # number of overall misses
< system.cpu1.dcache.overall_misses::total 4786702 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44430252500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 44430252500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 29275459500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 29275459500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21176769000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 21176769000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2717509500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2717509500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5539928000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 5539928000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5730000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5730000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 73705712000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 73705712000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 73705712000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 73705712000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 79527794 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 79527794 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 72193899 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 72193899 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 782634 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 782634 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 708062 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 708062 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843835 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1843835 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1842495 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1842495 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 151721693 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 151721693 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 152504327 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 152504327 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036412 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.036412 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017894 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.017894 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765528 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765528 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728181 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.728181 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092262 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092262 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106025 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106025 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027600 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.027600 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031387 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.031387 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.320824 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.320824 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22661.918511 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 22661.918511 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41072.327806 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41072.327806 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.449787 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.449787 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28358.986435 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28358.986435 # average StoreCondReq miss latency
---
> system.cpu1.op_class::total 471776234 # Class of executed instruction
> system.cpu1.dcache.tags.replacements 4623789 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 430.899907 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 139725575 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 4624300 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 30.215508 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8408408114000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.899907 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841601 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.841601 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 293714645 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 293714645 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 70428619 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 70428619 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 65452147 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 65452147 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175356 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 175356 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 181976 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 181976 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1569435 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1569435 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1531483 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1531483 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 135880766 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 135880766 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 136056122 # number of overall hits
> system.cpu1.dcache.overall_hits::total 136056122 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 2625513 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 2625513 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1190956 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1190956 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 551150 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 551150 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454381 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 454381 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150766 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 150766 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187526 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 187526 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 3816469 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 3816469 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 4367619 # number of overall misses
> system.cpu1.dcache.overall_misses::total 4367619 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39306904500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 39306904500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28030249500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 28030249500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20535959500 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 20535959500 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2343079000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2343079000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5222807000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 5222807000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5948500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5948500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 67337154000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 67337154000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 67337154000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 67337154000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 73054132 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 73054132 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 66643103 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 66643103 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 726506 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 726506 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 636357 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 636357 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1720201 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1720201 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1719009 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1719009 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 139697235 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 139697235 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 140423741 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 140423741 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035939 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035939 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017871 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.017871 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.758631 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.758631 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.714035 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.714035 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087644 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087644 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109090 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109090 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027320 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.027320 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031103 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.031103 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.133070 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14971.133070 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23535.923661 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 23535.923661 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45195.462618 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45195.462618 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15541.163127 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15541.163127 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27851.108646 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27851.108646 # average StoreCondReq miss latency
1708,1711c1722,1725
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17601.053020 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17601.053020 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15398.015586 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15398.015586 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17643.836227 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17643.836227 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15417.359893 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 15417.359893 # average overall miss latency
1720,1805c1734,1819
< system.cpu1.dcache.writebacks::writebacks 5113111 # number of writebacks
< system.cpu1.dcache.writebacks::total 5113111 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16657 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 16657 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46028 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46028 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 17059 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 17059 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 17059 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 17059 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879082 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2879082 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1291433 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1291433 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599128 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 599128 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 515597 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 515597 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 124088 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 124088 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195350 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 195350 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4170515 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4170515 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4769643 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4769643 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21793 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42209 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40268780500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40268780500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27960090500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27960090500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13604579000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13604579000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20661172000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20661172000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751690500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751690500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344637000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344637000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5671000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5671000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68228871000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 68228871000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81833450000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 81833450000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4030825000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4030825000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3797015500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3797015500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7827840500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7827840500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036202 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036202 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017888 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765528 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765528 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728181 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728181 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067299 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067299 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106025 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106025 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027488 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.027488 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031275 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.031275 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.673704 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.673704 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21650.438312 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21650.438312 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22707.299609 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22707.299609 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40072.327806 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40072.327806 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14116.518116 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14116.518116 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27359.288457 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27359.288457 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 4623789 # number of writebacks
> system.cpu1.dcache.writebacks::total 4623789 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13826 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 13826 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 458 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 458 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43478 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43478 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 14284 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 14284 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 14284 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 14284 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2611687 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 2611687 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1190498 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1190498 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 551150 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 551150 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454381 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 454381 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 107288 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 107288 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187526 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 187526 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 3802185 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 3802185 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 4353335 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 4353335 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 24123 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 24123 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 23288 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 23288 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 47411 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 47411 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35578565500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35578565500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26805763500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26805763500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12511151000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12511151000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20081578500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20081578500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1492978000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1492978000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035346000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035346000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5883500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5883500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62384329000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 62384329000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74895480000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 74895480000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4378993500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4378993500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4297960500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4297960500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8676954000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8676954000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035750 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035750 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017864 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017864 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758631 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.758631 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714035 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.714035 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062369 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062369 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109090 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109090 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027217 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027217 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031001 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.031001 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13622.829037 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13622.829037 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22516.428839 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22516.428839 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22700.083462 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22700.083462 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44195.462618 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44195.462618 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13915.610320 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13915.610320 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26851.455265 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26851.455265 # average StoreCondReq mshr miss latency
1808,1817c1822,1831
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16359.819111 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16359.819111 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17157.143627 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17157.143627 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184959.620061 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184959.620061 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185982.342281 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185982.342281 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185454.298846 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 185454.298846 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16407.494375 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16407.494375 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17204.161867 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17204.161867 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181527.732869 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181527.732869 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 184556.874785 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184556.874785 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 183015.629284 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 183015.629284 # average overall mshr uncacheable latency
1819,1827c1833,1841
< system.cpu1.icache.tags.replacements 5153049 # number of replacements
< system.cpu1.icache.tags.tagsinuse 495.966911 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 430252201 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5153561 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 83.486390 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.966911 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968685 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.968685 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 4822868 # number of replacements
> system.cpu1.icache.tags.tagsinuse 495.969838 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 395188527 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 4823380 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 81.931867 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8408376446000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.969838 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968691 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.968691 # Average percentage of cache occupancy
1829,1832c1843,1845
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
1834,1871c1847,1884
< system.cpu1.icache.tags.tag_accesses 875965100 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 875965100 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 430252201 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 430252201 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 430252201 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 430252201 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 430252201 # number of overall hits
< system.cpu1.icache.overall_hits::total 430252201 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 5153566 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 5153566 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 5153566 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 5153566 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 5153566 # number of overall misses
< system.cpu1.icache.overall_misses::total 5153566 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 55699016000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 55699016000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 55699016000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 55699016000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 55699016000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 55699016000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 435405767 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 435405767 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 435405767 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 435405767 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 435405767 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 435405767 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011836 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.011836 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011836 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.011836 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011836 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.011836 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10807.859257 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10807.859257 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10807.859257 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10807.859257 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 804847209 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 804847209 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 395188527 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 395188527 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 395188527 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 395188527 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 395188527 # number of overall hits
> system.cpu1.icache.overall_hits::total 395188527 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 4823385 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 4823385 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 4823385 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 4823385 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 4823385 # number of overall misses
> system.cpu1.icache.overall_misses::total 4823385 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52228876500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 52228876500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 52228876500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 52228876500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 52228876500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 52228876500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 400011912 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 400011912 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 400011912 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 400011912 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 400011912 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 400011912 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012058 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.012058 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012058 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.012058 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012058 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.012058 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10828.261999 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10828.261999 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10828.261999 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10828.261999 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10828.261999 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10828.261999 # average overall miss latency
1880,1887c1893,1900
< system.cpu1.icache.writebacks::writebacks 5153049 # number of writebacks
< system.cpu1.icache.writebacks::total 5153049 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5153566 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5153566 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5153566 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5153566 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5153566 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5153566 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 4822868 # number of writebacks
> system.cpu1.icache.writebacks::total 4822868 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4823385 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 4823385 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 4823385 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 4823385 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 4823385 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 4823385 # number of overall MSHR misses
1892,1917c1905,1930
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 53122233000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 53122233000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 53122233000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 53122233000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 53122233000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 53122233000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011836 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.011836 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.011836 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10307.859257 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49817184000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 49817184000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49817184000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 49817184000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49817184000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 49817184000 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14655500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14655500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14655500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 14655500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012058 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012058 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012058 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.012058 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012058 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.012058 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10328.261999 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10328.261999 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10328.261999 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133231.818182 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133231.818182 # average overall mshr uncacheable latency
1919,1921c1932,1934
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 6859303 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 6859383 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 6259356 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 6259387 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 27 # number of redundant prefetches already in prefetch queue
1924,1986c1937,1999
< system.cpu1.l2cache.prefetcher.pfSpanPage 859985 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 1911702 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13239.490812 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 15125743 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 1927829 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 7.845998 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 10087167671000 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12280.954827 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.921711 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.687685 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 831.926589 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.749570 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003230 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004498 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050777 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.808074 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1375 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14698 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 718 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 459 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1004 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4268 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6358 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2989 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.083923 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897095 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 347994589 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 347994589 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 237538 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166264 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 403802 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3233759 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3233759 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 7031230 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 7031230 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 362 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 362 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 841313 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 841313 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4702873 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 4702873 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2730195 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2730195 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 242884 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 242884 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 237538 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 166264 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 4702873 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3571508 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 8678183 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 237538 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 166264 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 4702873 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3571508 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 8678183 # number of overall hits
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 793397 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 1777622 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13086.026545 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 13889107 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 1793675 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 7.743380 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 10216605092500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 11949.147964 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 18.692431 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.350132 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1106.836018 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.729318 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001141 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000693 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.067556 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.798708 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1073 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14890 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 279 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 80 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 993 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4499 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8129 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.065491 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908813 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 320280578 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 320280578 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 210783 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138334 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 349117 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 2929003 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 2929003 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 6516555 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 6516555 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 209 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 209 # number of UpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 752189 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 752189 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4404363 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 4404363 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2449744 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2449744 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191107 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 191107 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 210783 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138334 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 4404363 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3201933 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 7955413 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 210783 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138334 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 4404363 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3201933 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 7955413 # number of overall hits
1988,2003c2001,2016
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8172 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 17830 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 204136 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 204136 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195335 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 195335 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 248244 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 248244 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 450693 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 450693 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 872103 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 872103 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 270299 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 270299 # number of InvalidateReq misses
---
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8230 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 17888 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 199042 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 199042 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187508 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 187508 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 18 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 18 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 241510 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 241510 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 419022 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 419022 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 820381 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 820381 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261023 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 261023 # number of InvalidateReq misses
2005,2008c2018,2021
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8172 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 450693 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1120347 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1588870 # number of demand (read+write) misses
---
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8230 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 419022 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1061891 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1498801 # number of demand (read+write) misses
2010,2076c2023,2089
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8172 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 450693 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1120347 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1588870 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 420391500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 400950500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 821342000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3230006000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 3230006000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1996070000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1996070000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5582500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5582500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12845706999 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 12845706999 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17128169000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17128169000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32431804500 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32431804500 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18248876500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 18248876500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 420391500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 400950500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17128169000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 45277511499 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 63227022499 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 420391500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 400950500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17128169000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 45277511499 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 63227022499 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 247196 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174436 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 421632 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3233759 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3233759 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 7031230 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 7031230 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 204498 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 204498 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195335 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 195335 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1089557 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1089557 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5153566 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 5153566 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3602298 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3602298 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 513183 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 513183 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 247196 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174436 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5153566 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4691855 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 10267053 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 247196 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174436 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5153566 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4691855 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 10267053 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046848 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.042288 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998230 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998230 # miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8230 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 419022 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1061891 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1498801 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 365970000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 332045500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 698015500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3049287500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 3049287500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1869580500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1869580500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5786000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5786000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12702911999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 12702911999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16109032000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16109032000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28713782500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28713782500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18098463500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 18098463500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 365970000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 332045500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16109032000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 41416694499 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 58223741999 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 365970000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 332045500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16109032000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 41416694499 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 58223741999 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 220441 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 146564 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 367005 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2929003 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 2929003 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 6516555 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 6516555 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 199251 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 199251 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187508 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 187508 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 18 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 18 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 993699 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 993699 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4823385 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 4823385 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3270125 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3270125 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 452130 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 452130 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 220441 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 146564 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 4823385 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4263824 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 9454214 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 220441 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 146564 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 4823385 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4263824 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 9454214 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.043812 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.056153 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.048740 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998951 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998951 # miss rate for UpgradeReq accesses
2081,2125c2094,2138
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227839 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.227839 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087453 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087453 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242096 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242096 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.526711 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.526711 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046848 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087453 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238786 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.154754 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046848 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087453 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238786 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.154754 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 49063.937837 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 46065.171060 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15822.814202 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15822.814202 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10218.701206 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10218.701206 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372166.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372166.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51746.293965 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51746.293965 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38004.071508 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38004.071508 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37188.043729 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37188.043729 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67513.666347 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67513.666347 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 49063.937837 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38004.071508 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40413.828483 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 39793.704015 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 49063.937837 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38004.071508 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40413.828483 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 39793.704015 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.243041 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.243041 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.086873 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.086873 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.250871 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.250871 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.577318 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.577318 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.043812 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.056153 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086873 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.249047 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.158533 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.043812 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.056153 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086873 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.249047 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.158533 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37892.938497 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40345.747266 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39021.438953 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15319.819435 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15319.819435 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9970.670585 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9970.670585 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 321444.444444 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 321444.444444 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52597.871720 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52597.871720 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38444.358530 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38444.358530 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.545478 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.545478 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69336.661903 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69336.661903 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37892.938497 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40345.747266 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38444.358530 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39002.773824 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 38846.879605 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37892.938497 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40345.747266 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38444.358530 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39002.773824 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 38846.879605 # average overall miss latency
2134,2143c2147,2158
< system.cpu1.l2cache.writebacks::writebacks 1066343 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1066343 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3931 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 3931 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 513 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 513 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4444 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 4444 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4444 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 4444 # number of overall MSHR hits
---
> system.cpu1.l2cache.writebacks::writebacks 999911 # number of writebacks
> system.cpu1.l2cache.writebacks::total 999911 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3856 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 3856 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 484 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 484 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4340 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 4340 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4340 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 4340 # number of overall MSHR hits
2145,2162c2160,2177
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8172 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 17830 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 644489 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 644489 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 204136 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 204136 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195335 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195335 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244313 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 244313 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 450693 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 450693 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 871590 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 871590 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 270299 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 270299 # number of InvalidateReq MSHR misses
---
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8230 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 17888 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 596510 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 596510 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 199042 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 199042 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 187508 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 187508 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 18 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 18 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237654 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 237654 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 419022 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 419022 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 819897 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 819897 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 261021 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 261021 # number of InvalidateReq MSHR misses
2164,2167c2179,2182
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8172 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 450693 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1115903 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1584426 # number of demand (read+write) MSHR misses
---
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8230 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 419022 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1057551 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1494461 # number of demand (read+write) MSHR misses
2169,2173c2184,2188
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8172 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 450693 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1115903 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 644489 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2228915 # number of overall MSHR misses
---
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8230 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 419022 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1057551 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 596510 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2090971 # number of overall MSHR misses
2175,2178c2190,2193
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21903 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 24123 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 24233 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 23288 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 23288 # number of WriteReq MSHR uncacheable
2180,2222c2195,2237
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 42319 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 351918500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 714362000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28219162309 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28219162309 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6506833500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6506833500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3878333500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3878333500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5228500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5228500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10923389999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10923389999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14424011000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14424011000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27157045000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27157045000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16627082500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16627082500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 351918500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14424011000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38080434999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 53218807999 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 351918500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14424011000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38080434999 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28219162309 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 81437970308 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13974500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3856157500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3870132000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3643453500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3643453500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13974500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7499611000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7513585500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042288 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 47411 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 47521 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 308022000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 282665500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 590687500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26979236218 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26979236218 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6259584005 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6259584005 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3627729000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3627729000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5396000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5396000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10808104999 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10808104999 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13594900000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13594900000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23755841000 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23755841000 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16532269500 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16532269500 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 308022000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 282665500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13594900000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34563945999 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 48749533499 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 308022000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 282665500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13594900000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34563945999 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26979236218 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 75728769717 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13830500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4185464000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4199294500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 4122722000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 4122722000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13830500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8308186000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8322016500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048740 # mshr miss rate for ReadReq accesses
2225,2226c2240,2241
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998230 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998230 # mshr miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998951 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998951 # mshr miss rate for UpgradeReq accesses
2231,2247c2246,2262
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.224231 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.224231 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087453 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.241954 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241954 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.526711 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.526711 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154321 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239161 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239161 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086873 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.250723 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250723 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.577314 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.577314 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248029 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158074 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248029 # mshr miss rate for overall accesses
2249,2287c2264,2302
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.217094 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 40065.171060 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43785.328080 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31874.992652 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31874.992652 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19854.780249 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19854.780249 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 348566.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 348566.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44710.637580 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44710.637580 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32004.071508 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31158.050230 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31158.050230 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61513.666347 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61513.666347 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33588.698998 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36537.046190 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176944.775845 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176694.151486 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178460.692594 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178460.692594 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 177678.007060 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 177546.385784 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.221168 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33021.438953 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45228.472646 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31448.558621 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31448.558621 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19347.062525 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19347.062525 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 299777.777778 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 299777.777778 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45478.321421 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45478.321421 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32444.358530 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28974.177244 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28974.177244 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63336.932661 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63336.932661 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32620.144319 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36217.034917 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173505.119595 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173288.263938 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177032.033665 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 177032.033665 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 175237.518719 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 175122.924602 # average overall mshr uncacheable latency
2289,2305c2304,2320
< system.cpu1.toL2Bus.snoop_filter.tot_requests 21257827 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10899393 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 1702072 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1701871 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 509534 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 9349922 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 20416 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 20416 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4305236 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 7031230 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 2216107 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 785182 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 389899 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353464 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 462412 # Transaction distribution
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 19593534 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10054336 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1096 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 1611494 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1611307 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 454071 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 8632529 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 23288 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 23288 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 3935373 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 6517651 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 2069350 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 732453 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 387389 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344195 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 449127 # Transaction distribution
2307,2327c2322,2342
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1157273 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1096575 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5153566 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4436249 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 522065 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 513183 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15459725 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16561050 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365076 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544187 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 32930038 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 659580536 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 633491086 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395488 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1977568 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1296444678 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 5547167 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 16615326 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.116559 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.320932 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1061448 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1001075 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4823385 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4143057 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 462376 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 452130 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14469858 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15078885 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 308515 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 488328 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 30345586 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617360632 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 574871104 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1172512 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1763528 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1195167776 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5321649 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 15507476 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.118236 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.322925 # Request fanout histogram
2329,2331c2344,2346
< system.cpu1.toL2Bus.snoop_fanout::0 14678862 88.35% 88.35% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 1936263 11.65% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 201 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 13674115 88.18% 88.18% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 1833174 11.82% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram
2335,2336c2350,2351
< system.cpu1.toL2Bus.snoop_fanout::total 16615326 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 21053645498 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 15507476 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 19383363503 # Layer occupancy (ticks)
2338c2353
< system.cpu1.toL2Bus.snoopLayer0.occupancy 168856163 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 170060906 # Layer occupancy (ticks)
2340c2355
< system.cpu1.toL2Bus.respLayer0.occupancy 7730459000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 7235187500 # Layer occupancy (ticks)
2342c2357
< system.cpu1.toL2Bus.respLayer1.occupancy 7526670911 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 6851260042 # Layer occupancy (ticks)
2344c2359
< system.cpu1.toL2Bus.respLayer2.occupancy 190640499 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 161951000 # Layer occupancy (ticks)
2346c2361
< system.cpu1.toL2Bus.respLayer3.occupancy 296991000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 267887000 # Layer occupancy (ticks)
2348,2352c2363,2367
< system.iobus.trans_dist::ReadReq 40402 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40402 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136652 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136652 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47834 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40445 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40445 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136989 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136989 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47854 # Packet count per connected master and slave (bytes)
2363c2378
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
2365,2367c2380,2382
< system.iobus.pkt_count_system.bridge.master::total 122768 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231260 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231260 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122996 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231792 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231792 # Packet count per connected master and slave (bytes)
2370,2371c2385,2386
< system.iobus.pkt_count::total 354108 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47854 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354868 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47874 # Cumulative packet size per connected master and slave (bytes)
2382c2397
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
2384,2386c2399,2401
< system.iobus.pkt_size_system.bridge.master::total 155875 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339056 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7339056 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 156011 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355520 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7355520 # Cumulative packet size per connected master and slave (bytes)
2389,2390c2404,2405
< system.iobus.pkt_size::total 7497017 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 37033500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7513617 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 37057000 # Layer occupancy (ticks)
2394c2409
< system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks)
2398c2413
< system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
2412c2427
< system.iobus.reqLayer23.occupancy 26450500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 26714502 # Layer occupancy (ticks)
2414c2429
< system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks)
2416c2431
< system.iobus.reqLayer25.occupancy 565570401 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 568759261 # Layer occupancy (ticks)
2418c2433
< system.iobus.respLayer0.occupancy 92847000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92994000 # Layer occupancy (ticks)
2420c2435
< system.iobus.respLayer3.occupancy 147956000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148232000 # Layer occupancy (ticks)
2424,2434c2439,2449
< system.iocache.tags.replacements 115605 # number of replacements
< system.iocache.tags.tagsinuse 11.294118 # Cycle average of tags in use
< system.iocache.tags.total_refs 10 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 115621 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0.000086 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 9206098021000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.822126 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 7.471992 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.238883 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.705882 # Average percentage of cache occupancy
---
> system.iocache.tags.replacements 115885 # number of replacements
> system.iocache.tags.tagsinuse 11.295009 # Cycle average of tags in use
> system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 115901 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 9206049239000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.821414 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.473594 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.467100 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.705938 # Average percentage of cache occupancy
2438,2441c2453,2454
< system.iocache.tags.tag_accesses 1041013 # Number of tag accesses
< system.iocache.tags.data_accesses 1041013 # Number of data accesses
< system.iocache.WriteLineReq_hits::realview.ide 5 # number of WriteLineReq hits
< system.iocache.WriteLineReq_hits::total 5 # number of WriteLineReq hits
---
> system.iocache.tags.tag_accesses 1043421 # Number of tag accesses
> system.iocache.tags.data_accesses 1043421 # Number of data accesses
2443,2444c2456,2457
< system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses
2447,2448c2460,2461
< system.iocache.WriteLineReq_misses::realview.ide 106723 # number of WriteLineReq misses
< system.iocache.WriteLineReq_misses::total 106723 # number of WriteLineReq misses
---
> system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
> system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2450,2451c2463,2464
< system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8942 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8952 # number of demand (read+write) misses
2453,2457c2466,2470
< system.iocache.overall_misses::realview.ide 8902 # number of overall misses
< system.iocache.overall_misses::total 8942 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1679170514 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1684370014 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 8912 # number of overall misses
> system.iocache.overall_misses::total 8952 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5263500 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1680350485 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1685613985 # number of ReadReq miss cycles
2460,2467c2473,2480
< system.iocache.WriteLineReq_miss_latency::realview.ide 13974494387 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13974494387 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 1679170514 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1684739014 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 1679170514 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1684739014 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13574924276 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13574924276 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5632500 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 1680350485 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1685982985 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5632500 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 1680350485 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1685982985 # number of overall miss cycles
2469,2470c2482,2483
< system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses)
2473,2474c2486,2487
< system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
< system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
---
> system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
> system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2476,2477c2489,2490
< system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses
2479,2480c2492,2493
< system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses
2486,2487c2499,2500
< system.iocache.WriteLineReq_miss_rate::realview.ide 0.999953 # miss rate for WriteLineReq accesses
< system.iocache.WriteLineReq_miss_rate::total 0.999953 # miss rate for WriteLineReq accesses
---
> system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
> system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2494,2496c2507,2509
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 188628.455853 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 188429.356080 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142256.756757 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 188549.201638 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 188357.803665 # average ReadReq miss latency
2499,2507c2512,2520
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130941.731276 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130941.731276 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 188407.404831 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 188407.404831 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 35755 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126887.424998 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 126887.424998 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 188335.900916 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 188335.900916 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 33982 # number of cycles access was blocked
2509c2522
< system.iocache.blocked::no_mshrs 3742 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3504 # number of cycles access was blocked
2511c2524
< system.iocache.avg_blocked_cycles::no_mshrs 9.555051 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.698059 # average number of cycles each access was blocked
2515,2516c2528,2529
< system.iocache.writebacks::writebacks 106695 # number of writebacks
< system.iocache.writebacks::total 106695 # number of writebacks
---
> system.iocache.writebacks::writebacks 106958 # number of writebacks
> system.iocache.writebacks::total 106958 # number of writebacks
2518,2519c2531,2532
< system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses
2522,2523c2535,2536
< system.iocache.WriteLineReq_mshr_misses::realview.ide 106723 # number of WriteLineReq MSHR misses
< system.iocache.WriteLineReq_mshr_misses::total 106723 # number of WriteLineReq MSHR misses
---
> system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
> system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2525,2526c2538,2539
< system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses
2528,2532c2541,2545
< system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234070514 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1237420014 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3413500 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234750485 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1238163985 # number of ReadReq MSHR miss cycles
2535,2542c2548,2555
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638344387 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 8638344387 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 1234070514 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1237639014 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 1234070514 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1237639014 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8219197460 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8219197460 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3632500 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 1234750485 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1238382985 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3632500 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 1234750485 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1238382985 # number of overall MSHR miss cycles
2548,2549c2561,2562
< system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999953 # mshr miss rate for WriteLineReq accesses
< system.iocache.WriteLineReq_mshr_miss_rate::total 0.999953 # mshr miss rate for WriteLineReq accesses
---
> system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
> system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2556,2558c2569,2571
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138628.455853 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 138429.356080 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92256.756757 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138549.201638 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 138357.803665 # average ReadReq mshr miss latency
2561,2568c2574,2581
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80941.731276 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80941.731276 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76826.417595 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76826.417595 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency
2570,2574c2583,2587
< system.l2c.tags.replacements 1201728 # number of replacements
< system.l2c.tags.tagsinuse 62776.329461 # Cycle average of tags in use
< system.l2c.tags.total_refs 5149298 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1259663 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.087838 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 1212335 # number of replacements
> system.l2c.tags.tagsinuse 62688.740428 # Cycle average of tags in use
> system.l2c.tags.total_refs 5318857 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1271612 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 4.182767 # Average number of references to valid blocks.
2576,2872c2589,2887
< system.l2c.tags.occ_blocks::writebacks 23700.762045 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 102.528322 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 175.969290 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4011.755779 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 5217.555279 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7227.978697 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.263944 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 281.111554 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3722.000784 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 8039.407020 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10130.996747 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.361645 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001564 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.002685 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.061215 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.079614 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110290 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002537 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.004289 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.056793 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.122672 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.154587 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.957891 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 9737 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 265 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 47933 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 277 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 9401 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 264 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5230 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 40901 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.148575 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.004044 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.731400 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 66235328 # Number of tag accesses
< system.l2c.tags.data_accesses 66235328 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 2474359 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2474359 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 150616 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 127305 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 277921 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 34718 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 37539 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 72257 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 146279 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 167990 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 314269 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4627 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3559 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 390104 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 513889 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 259608 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5392 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4493 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 410490 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 516454 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 291033 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2399649 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 4627 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 3559 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 390104 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 660168 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 259608 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 5392 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4493 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 410490 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 684444 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 291033 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2713918 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 4627 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 3559 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 390104 # number of overall hits
< system.l2c.overall_hits::cpu0.data 660168 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 259608 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 5392 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4493 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 410490 # number of overall hits
< system.l2c.overall_hits::cpu1.data 684444 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 291033 # number of overall hits
< system.l2c.overall_hits::total 2713918 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 62469 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 57486 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 119955 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 13684 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 12909 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 26593 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 477377 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 148178 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 625555 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1066 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 45695 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 111052 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1684 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 40203 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 92070 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 640180 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 1085 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1066 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 45695 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 588429 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1546 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1684 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 40203 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 240248 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1265735 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 1085 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1066 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 45695 # number of overall misses
< system.l2c.overall_misses::cpu0.data 588429 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 202654 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1546 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1684 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 40203 # number of overall misses
< system.l2c.overall_misses::cpu1.data 240248 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 143125 # number of overall misses
< system.l2c.overall_misses::total 1265735 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 928670500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1025251000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 1953921500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 178207000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182538500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 360745500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 63116930500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 19400961500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 82517892000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 153728000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 149604000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6143069000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 15249907500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 212651500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 233752000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5417778000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 12722216500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 96202750409 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 153728000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 149604000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 6143069000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 78366838000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 212651500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 233752000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 5417778000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 32123178000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 178720642409 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 153728000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 149604000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 6143069000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 78366838000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 212651500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 233752000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 5417778000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 32123178000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 178720642409 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2474359 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2474359 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 213085 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 184791 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 397876 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 48402 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 50448 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 98850 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 623656 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 316168 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 939824 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5712 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4625 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 435799 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 624941 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 462262 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6938 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6177 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 450693 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 608524 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 434158 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3039829 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 5712 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 4625 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 435799 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1248597 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462262 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 6938 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6177 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 450693 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 924692 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 434158 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 3979653 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 5712 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 4625 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 435799 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1248597 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462262 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 6938 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6177 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 450693 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 924692 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 434158 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 3979653 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.293165 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311087 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.301488 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.282716 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.255887 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.269024 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.765449 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.468669 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.665609 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.230486 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104853 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.177700 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.272624 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089203 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.151301 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.210597 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.230486 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.104853 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.471272 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.272624 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.089203 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.259814 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.318052 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.230486 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.104853 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.471272 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.272624 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.089203 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.259814 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.318052 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14866.101586 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17834.794559 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 16288.787462 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13023.019585 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14140.405918 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 13565.430752 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132216.111166 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130930.107708 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 131911.489797 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140341.463415 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134436.349710 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137322.222923 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138807.600950 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134760.540258 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138179.825133 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 150274.532802 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140341.463415 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 134436.349710 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 133179.768502 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138807.600950 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 134760.540258 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 133708.409643 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 141199.099661 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140341.463415 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 134436.349710 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 133179.768502 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138807.600950 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 134760.540258 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 133708.409643 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 141199.099661 # average overall miss latency
---
> system.l2c.tags.occ_blocks::writebacks 22897.710256 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 262.803618 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 467.362186 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4684.066084 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 11639.690690 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16421.765271 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.113156 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 2.385766 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 2988.095077 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 1979.468778 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1337.279546 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.349391 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004010 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.007131 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.071473 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.177608 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.250576 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000124 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.000036 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.045595 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.030204 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.020405 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.956554 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 10727 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 48317 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 79 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 232 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 1534 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 8882 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1867 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 10232 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 35894 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.163681 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.737259 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 68046834 # Number of tag accesses
> system.l2c.tags.data_accesses 68046834 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 2553793 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 2553793 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 170923 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 116715 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 287638 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 41425 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 35212 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 76637 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 168896 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 169545 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 338441 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5417 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4358 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 442976 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 579881 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 303485 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5587 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4895 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 380461 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 481285 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 259287 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2467632 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 5417 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 442976 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 748777 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 303485 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5587 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 4895 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 380461 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 650830 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 259287 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2806073 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 5417 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 442976 # number of overall hits
> system.l2c.overall_hits::cpu0.data 748777 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 303485 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5587 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 4895 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 380461 # number of overall hits
> system.l2c.overall_hits::cpu1.data 650830 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 259287 # number of overall hits
> system.l2c.overall_hits::total 2806073 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 65926 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 56137 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 122063 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 14762 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 11662 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 26424 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 479802 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 149602 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 629404 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1666 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1796 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 49096 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 137247 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 210371 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1115 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1118 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 38561 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 72759 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 136420 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 650149 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 1666 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 1796 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 49096 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 617049 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 210371 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 1115 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1118 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 38561 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 222361 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 136420 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1279553 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 1666 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 1796 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 49096 # number of overall misses
> system.l2c.overall_misses::cpu0.data 617049 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 210371 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 1115 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1118 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 38561 # number of overall misses
> system.l2c.overall_misses::cpu1.data 222361 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 136420 # number of overall misses
> system.l2c.overall_misses::total 1279553 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 951839000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 920304000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 1872143000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 185965000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 175745500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 361710500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 63393976500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 19575358000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 82969334500 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 226854500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248582500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6606900000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 18800983000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33843632698 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 154867000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 158576000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5179317500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 10092238000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22255519844 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 97567471042 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 226854500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 248582500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 6606900000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 82194959500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33843632698 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 154867000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 158576000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 5179317500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 29667596000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22255519844 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 180536805542 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 226854500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 248582500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 6606900000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 82194959500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33843632698 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 154867000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 158576000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 5179317500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 29667596000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22255519844 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 180536805542 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 2553793 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 2553793 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 236849 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 172852 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 409701 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 56187 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 46874 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 103061 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 648698 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 319147 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 967845 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7083 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6154 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 492072 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 717128 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 513856 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6702 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6013 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 419022 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 554044 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 395707 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3117781 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 7083 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 6154 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 492072 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1365826 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 513856 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 6702 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 6013 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 419022 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 873191 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 395707 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4085626 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 7083 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 6154 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 492072 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1365826 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 513856 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 6702 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 6013 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 419022 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 873191 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 395707 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4085626 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.278346 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.324769 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.297932 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.262730 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.248795 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.256392 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.739638 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.468756 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.650315 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.235211 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.291843 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.099774 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.191384 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.409397 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.166368 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.185930 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.092026 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.131324 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.344750 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.208529 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.235211 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.291843 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.099774 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.451777 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.409397 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.166368 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.185930 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.092026 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.254653 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.344750 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.313184 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.235211 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.291843 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.099774 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.451777 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.409397 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.166368 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.185930 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.092026 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.254653 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.344750 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.313184 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14437.991081 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16393.893511 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 15337.514234 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12597.547758 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15069.927971 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 13688.711020 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132125.286055 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130849.574204 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 131822.064207 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136167.166867 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138408.964365 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134571.044484 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136986.476936 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 138894.170404 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141838.998211 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134314.916626 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138707.761239 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 150069.401079 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136167.166867 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138408.964365 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 134571.044484 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 133206.535462 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138894.170404 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141838.998211 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 134314.916626 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 133420.860673 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 141093.651878 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136167.166867 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138408.964365 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 134571.044484 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 133206.535462 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138894.170404 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141838.998211 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 134314.916626 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 133420.860673 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 141093.651878 # average overall miss latency
2881,2941c2896,2956
< system.l2c.writebacks::writebacks 969294 # number of writebacks
< system.l2c.writebacks::total 969294 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 118 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 27 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 91 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 259 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 118 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 27 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 91 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 118 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 27 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 91 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 259 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 39496 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 39496 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 62469 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 57486 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 119955 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13684 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12909 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 26593 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 477377 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 148178 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 625555 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1066 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45577 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 111025 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1684 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 40112 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 92047 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 639921 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 1085 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 1066 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 45577 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 588402 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1546 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1684 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 40112 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 240225 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1265476 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 1085 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 1066 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 45577 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 588402 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1546 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1684 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 40112 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 240225 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1265476 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 974440 # number of writebacks
> system.l2c.writebacks::total 974440 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 109 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 16 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 101 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 247 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 109 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 16 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 101 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 247 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 109 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 16 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 101 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 247 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 38798 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 38798 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 65926 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 56137 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 122063 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 14762 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11662 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 26424 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 479802 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 149602 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 629404 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1666 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1796 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48987 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 137231 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 210371 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1115 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1118 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 38460 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 72738 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 136420 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 649902 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 1666 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 1796 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 48987 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 617033 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 210371 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 1115 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1118 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 38460 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 222340 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 136420 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1279306 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 1666 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 1796 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 48987 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 617033 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 210371 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 1115 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1118 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 38460 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 222340 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 136420 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1279306 # number of overall MSHR misses
2943c2958
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable
2945,2949c2960,2964
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21791 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 81772 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38384 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 24121 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 82348 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 23288 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 39013 # number of WriteReq MSHR uncacheable
2951c2966
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses
2953,2996c2968,3011
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 42207 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 120156 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4603464500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4224060500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 8827525000 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1048639500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 988070500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 2036710000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 58343160500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17919181500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 76262342000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 138944000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5673195000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14136518000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 216912000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5007052000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11798625000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 89773569409 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 138944000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 5673195000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 72479678500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 216912000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 5007052000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 29717806500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 166035911409 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 138944000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 5673195000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 72479678500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 216912000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 5007052000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 29717806500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 166035911409 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 47409 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 121361 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4679642000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3966885500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 8646527500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1090611500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 859764000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1950375500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 58595767959 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18079108058 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 76674876017 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 210193003 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 230621502 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6104112113 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17426442010 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 31739278014 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 143716501 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 147393505 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4783143154 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9361991430 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20890811537 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 91037702769 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 210193003 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 230621502 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 6104112113 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 76022209969 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 31739278014 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 143716501 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 147393505 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 4783143154 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 27441099488 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20890811537 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 167712578786 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 210193003 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 230621502 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 6104112113 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 76022209969 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31739278014 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 143716501 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 147393505 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 4783143154 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 27441099488 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20890811537 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 167712578786 # number of overall MSHR miss cycles
2998,3004c3013,3019
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2461668000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11994000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3463851500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 10792034500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2661815500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3296062500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5957878000 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2194977011 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11849500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3751197013 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 10812544524 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2268278521 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3726528606 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5994807127 # number of WriteReq MSHR uncacheable cycles
3006,3009c3021,3024
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5123483500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11994000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6759914000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 16749912500 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4463255532 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11849500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7477725619 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 16807351651 # number of overall MSHR uncacheable cycles
3012,3095c3027,3110
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.293165 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.311087 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.301488 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.282716 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.255887 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.269024 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.765449 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468669 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.665609 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.177657 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151263 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210512 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.317987 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.317987 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73691.983224 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73479.812476 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73590.304698 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76632.527039 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76541.211558 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76588.199902 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122216.111166 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120930.107708 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 121911.489797 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127327.340689 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128180.440427 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140288.519066 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.278346 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324769 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.297932 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.262730 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.248795 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.256392 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739638 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468756 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.650315 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.191362 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.131286 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.208450 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.451765 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.254629 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.313124 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.451765 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.254629 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.313124 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70983.253951 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70664.365748 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70836.596675 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73879.657228 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73723.546561 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73810.759158 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122124.893100 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120848.037179 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 121821.399319 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.191240 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128708.397674 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140079.123882 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123206.068345 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123419.535342 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 131096.531077 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123206.068345 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123419.535342 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 131096.531077 # average overall mshr miss latency
3097,3103c3112,3118
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 147000.358295 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158957.895461 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131977.137651 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148142.002449 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161445.067594 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155217.746978 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146409.886006 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155515.816633 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131303.061689 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144246.646804 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160019.263397 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153661.782662 # average WriteReq mshr uncacheable latency
3105,3108c3120,3123
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147591.274414 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160160.968560 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 139401.382370 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145302.455709 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157727.976102 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 138490.550103 # average overall mshr uncacheable latency
3110,3124c3125,3138
< system.membus.trans_dist::ReadReq 81772 # Transaction distribution
< system.membus.trans_dist::ReadResp 730632 # Transaction distribution
< system.membus.trans_dist::WriteReq 38384 # Transaction distribution
< system.membus.trans_dist::WriteResp 38384 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1075989 # Transaction distribution
< system.membus.trans_dist::CleanEvict 189758 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 405662 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 313696 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 154281 # Transaction distribution
< system.membus.trans_dist::ReadExReq 640388 # Transaction distribution
< system.membus.trans_dist::ReadExResp 617827 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 648860 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 106721 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 106721 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122768 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 82348 # Transaction distribution
> system.membus.trans_dist::ReadResp 741199 # Transaction distribution
> system.membus.trans_dist::WriteReq 39013 # Transaction distribution
> system.membus.trans_dist::WriteResp 39013 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1081398 # Transaction distribution
> system.membus.trans_dist::CleanEvict 196468 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 401198 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 306316 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
> system.membus.trans_dist::ReadExReq 643986 # Transaction distribution
> system.membus.trans_dist::ReadExResp 621414 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 658851 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122996 # Packet count per connected master and slave (bytes)
3126,3132c3140,3146
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25854 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4655021 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4803735 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342369 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 342369 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5146104 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155875 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28036 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4525576 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4676700 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238552 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 238552 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4915252 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156011 # Cumulative packet size per connected master and slave (bytes)
3134,3141c3148,3155
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51708 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142678316 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 142886103 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257472 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7257472 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 150143575 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 590609 # Total snoops (count)
< system.membus.snoop_fanout::samples 3503595 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56072 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143876076 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 144088363 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276096 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7276096 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 151364459 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 576558 # Total snoops (count)
> system.membus.snoop_fanout::samples 3516604 # Request fanout histogram
3146c3160
< system.membus.snoop_fanout::1 3503595 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3516604 100.00% 100.00% # Request fanout histogram
3151,3152c3165,3166
< system.membus.snoop_fanout::total 3503595 # Request fanout histogram
< system.membus.reqLayer0.occupancy 101306500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3516604 # Request fanout histogram
> system.membus.reqLayer0.occupancy 101595998 # Layer occupancy (ticks)
3156c3170
< system.membus.reqLayer2.occupancy 21492499 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 23093498 # Layer occupancy (ticks)
3158c3172
< system.membus.reqLayer5.occupancy 7402591959 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 7460114319 # Layer occupancy (ticks)
3160c3174
< system.membus.respLayer2.occupancy 7154332547 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 6921315949 # Layer occupancy (ticks)
3162c3176
< system.membus.respLayer3.occupancy 228436684 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 45614101 # Layer occupancy (ticks)
3216,3246c3230,3260
< system.toL2Bus.snoop_filter.tot_requests 10356989 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 5641244 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 1705825 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 115755 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 104698 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 11057 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 81774 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 3879147 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38384 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38384 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 3550378 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1245199 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 675855 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 385953 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1061806 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1071844 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1071844 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 3804622 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 106721 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7596632 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6529428 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 14126060 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 228502049 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185064310 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 413566359 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 2887820 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 7482662 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.359179 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.482830 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 10579543 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 5766836 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 1724769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 116961 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 105875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 11086 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 82350 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 3947474 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 39013 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 39013 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 3635231 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 2252852 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 680846 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 382953 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1063799 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 141 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 1092357 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 1092357 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 3872368 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8825237 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6597118 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 15422355 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252378371 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 173059496 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 425437867 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 2867232 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 7585274 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.353752 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.481180 # Request fanout histogram
3248,3250c3262,3264
< system.toL2Bus.snoop_fanout::0 4806103 64.23% 64.23% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 2665502 35.62% 99.85% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 11057 0.15% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 4913057 64.77% 64.77% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 2661131 35.08% 99.85% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 11086 0.15% 100.00% # Request fanout histogram
3254,3255c3268,3269
< system.toL2Bus.snoop_fanout::total 7482662 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 8118734038 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 7585274 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 8312830316 # Layer occupancy (ticks)
3257c3271
< system.toL2Bus.snoopLayer0.occupancy 2606433 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2630923 # Layer occupancy (ticks)
3259c3273
< system.toL2Bus.respLayer0.occupancy 4223747952 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4557123754 # Layer occupancy (ticks)
3261c3275
< system.toL2Bus.respLayer1.occupancy 3725557524 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3526163360 # Layer occupancy (ticks)