3,5c3,5
< sim_seconds 47.456680 # Number of seconds simulated
< sim_ticks 47456679626500 # Number of ticks simulated
< final_tick 47456679626500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.474700 # Number of seconds simulated
> sim_ticks 47474700369500 # Number of ticks simulated
> final_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 503190 # Simulator instruction rate (inst/s)
< host_op_rate 591944 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27602071667 # Simulator tick rate (ticks/s)
< host_mem_usage 755208 # Number of bytes of host memory used
< host_seconds 1719.32 # Real time elapsed on the host
< sim_insts 865142471 # Number of instructions simulated
< sim_ops 1017738631 # Number of ops (including micro ops) simulated
---
> host_inst_rate 631720 # Simulator instruction rate (inst/s)
> host_op_rate 743100 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 34016391858 # Simulator tick rate (ticks/s)
> host_mem_usage 766400 # Number of bytes of host memory used
> host_seconds 1395.64 # Real time elapsed on the host
> sim_insts 881655060 # Number of instructions simulated
> sim_ops 1037101350 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 51904 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 48448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 2877620 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 38342664 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 11776896 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 153536 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 163840 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2826616 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 16120336 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 11259712 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory
< system.physmem.bytes_read::total 84057220 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 2877620 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2826616 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5704236 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 70891776 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 127360 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 143744 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 3459124 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 40376840 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 12078528 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 91584 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 86464 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 2488056 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 17058000 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 14991744 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 410816 # Number of bytes read from this memory
> system.physmem.bytes_read::total 91312260 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 3459124 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 2488056 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 5947180 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 77042688 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 70912360 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 811 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 757 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 85370 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 599117 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 184014 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 2399 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 2560 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 44254 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 251893 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 175933 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1353915 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1107684 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 77063272 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 1990 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 2246 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 94456 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 630901 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 188727 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 1431 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1351 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 38964 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 266544 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 234246 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6419 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1467275 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1203792 # Number of write requests responded to by this memory
50,67c50,67
< system.physmem.num_writes::total 1110258 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 1094 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 1021 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 60637 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 807951 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 248161 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 3235 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 3452 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 59562 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 339685 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 237263 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9180 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1771241 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 60637 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 59562 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 120199 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1493821 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1206366 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 2683 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 3028 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 72862 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 850492 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 254420 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 1929 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 1821 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 52408 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 359307 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 315784 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8653 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1923388 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 72862 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 52408 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 125271 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1622816 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
69,92c69,92
< system.physmem.bw_write::total 1494255 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1493821 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 1094 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 1021 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 60637 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 808384 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 248161 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 3235 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 3452 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 59562 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 339685 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 237263 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9180 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3265496 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1353915 # Number of read requests accepted
< system.physmem.writeReqs 1110258 # Number of write requests accepted
< system.physmem.readBursts 1353915 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1110258 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 86619200 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue
< system.physmem.bytesWritten 70911104 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 84057220 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 70912360 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1623249 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1622816 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2683 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 3028 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 72862 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 850925 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 254420 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 1929 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 1821 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 52408 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 359307 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 315784 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8653 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3546637 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1467275 # Number of read requests accepted
> system.physmem.writeReqs 1206366 # Number of write requests accepted
> system.physmem.readBursts 1467275 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1206366 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 93873920 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 31680 # Total number of bytes read from write queue
> system.physmem.bytesWritten 77062336 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 91312260 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 77063272 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 495 # Number of DRAM read bursts serviced by the write queue
94,126c94,126
< system.physmem.neitherReadNorWriteReqs 220771 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 83838 # Per bank write bursts
< system.physmem.perBankRdBursts::1 89540 # Per bank write bursts
< system.physmem.perBankRdBursts::2 77326 # Per bank write bursts
< system.physmem.perBankRdBursts::3 81695 # Per bank write bursts
< system.physmem.perBankRdBursts::4 84097 # Per bank write bursts
< system.physmem.perBankRdBursts::5 94926 # Per bank write bursts
< system.physmem.perBankRdBursts::6 83322 # Per bank write bursts
< system.physmem.perBankRdBursts::7 86179 # Per bank write bursts
< system.physmem.perBankRdBursts::8 76741 # Per bank write bursts
< system.physmem.perBankRdBursts::9 125350 # Per bank write bursts
< system.physmem.perBankRdBursts::10 75788 # Per bank write bursts
< system.physmem.perBankRdBursts::11 81366 # Per bank write bursts
< system.physmem.perBankRdBursts::12 76482 # Per bank write bursts
< system.physmem.perBankRdBursts::13 81797 # Per bank write bursts
< system.physmem.perBankRdBursts::14 77630 # Per bank write bursts
< system.physmem.perBankRdBursts::15 77348 # Per bank write bursts
< system.physmem.perBankWrBursts::0 68540 # Per bank write bursts
< system.physmem.perBankWrBursts::1 72321 # Per bank write bursts
< system.physmem.perBankWrBursts::2 65671 # Per bank write bursts
< system.physmem.perBankWrBursts::3 69464 # Per bank write bursts
< system.physmem.perBankWrBursts::4 70371 # Per bank write bursts
< system.physmem.perBankWrBursts::5 77894 # Per bank write bursts
< system.physmem.perBankWrBursts::6 70312 # Per bank write bursts
< system.physmem.perBankWrBursts::7 72647 # Per bank write bursts
< system.physmem.perBankWrBursts::8 65746 # Per bank write bursts
< system.physmem.perBankWrBursts::9 72323 # Per bank write bursts
< system.physmem.perBankWrBursts::10 65450 # Per bank write bursts
< system.physmem.perBankWrBursts::11 68291 # Per bank write bursts
< system.physmem.perBankWrBursts::12 65769 # Per bank write bursts
< system.physmem.perBankWrBursts::13 69040 # Per bank write bursts
< system.physmem.perBankWrBursts::14 66651 # Per bank write bursts
< system.physmem.perBankWrBursts::15 67496 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 220616 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 87562 # Per bank write bursts
> system.physmem.perBankRdBursts::1 88840 # Per bank write bursts
> system.physmem.perBankRdBursts::2 82797 # Per bank write bursts
> system.physmem.perBankRdBursts::3 92927 # Per bank write bursts
> system.physmem.perBankRdBursts::4 90148 # Per bank write bursts
> system.physmem.perBankRdBursts::5 93986 # Per bank write bursts
> system.physmem.perBankRdBursts::6 87799 # Per bank write bursts
> system.physmem.perBankRdBursts::7 94269 # Per bank write bursts
> system.physmem.perBankRdBursts::8 90753 # Per bank write bursts
> system.physmem.perBankRdBursts::9 132105 # Per bank write bursts
> system.physmem.perBankRdBursts::10 81290 # Per bank write bursts
> system.physmem.perBankRdBursts::11 92144 # Per bank write bursts
> system.physmem.perBankRdBursts::12 81361 # Per bank write bursts
> system.physmem.perBankRdBursts::13 87555 # Per bank write bursts
> system.physmem.perBankRdBursts::14 92182 # Per bank write bursts
> system.physmem.perBankRdBursts::15 91062 # Per bank write bursts
> system.physmem.perBankWrBursts::0 71771 # Per bank write bursts
> system.physmem.perBankWrBursts::1 74672 # Per bank write bursts
> system.physmem.perBankWrBursts::2 72652 # Per bank write bursts
> system.physmem.perBankWrBursts::3 78055 # Per bank write bursts
> system.physmem.perBankWrBursts::4 74620 # Per bank write bursts
> system.physmem.perBankWrBursts::5 78875 # Per bank write bursts
> system.physmem.perBankWrBursts::6 73591 # Per bank write bursts
> system.physmem.perBankWrBursts::7 76891 # Per bank write bursts
> system.physmem.perBankWrBursts::8 77107 # Per bank write bursts
> system.physmem.perBankWrBursts::9 78277 # Per bank write bursts
> system.physmem.perBankWrBursts::10 71128 # Per bank write bursts
> system.physmem.perBankWrBursts::11 78119 # Per bank write bursts
> system.physmem.perBankWrBursts::12 70456 # Per bank write bursts
> system.physmem.perBankWrBursts::13 74533 # Per bank write bursts
> system.physmem.perBankWrBursts::14 76600 # Per bank write bursts
> system.physmem.perBankWrBursts::15 76752 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 71 # Number of times write queue was full causing retry
< system.physmem.totGap 47456676566000 # Total gap between requests
---
> system.physmem.numWrRetry 39 # Number of times write queue was full causing retry
> system.physmem.totGap 47474697259000 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1310690 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1424050 # Read request sizes (log2)
143,160c143,160
< system.physmem.writePktSize::6 1107684 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1123748 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 74620 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 32556 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 27437 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 23297 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 20472 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 17890 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 14951 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 12831 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2528 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 983 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 550 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 416 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 288 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 209 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 175 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 158 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1203792 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1195881 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 91231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 37643 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 32050 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 26760 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 23675 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 20974 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 18326 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 14619 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2367 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 941 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 584 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 447 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 348 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 253 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 224 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see
162,167c162,167
< system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
191,257c191,257
< system.physmem.wrQLenPdf::15 16504 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 19352 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 48877 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 56560 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 60723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 62814 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 63983 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 67411 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 68337 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 71503 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 71245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 72329 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 70408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 71228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 74472 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 69249 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 66307 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 64601 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1352 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1011 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 616 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 534 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 469 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 470 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 437 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 403 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 372 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 308 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 386 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 390 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 285 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 247 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 283 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 156 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 238 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 850568 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 185.205557 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 113.971853 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 243.835447 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 513606 60.38% 60.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 167161 19.65% 80.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 54824 6.45% 86.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 28166 3.31% 89.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 18449 2.17% 91.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 11525 1.35% 93.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 9338 1.10% 94.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 9545 1.12% 95.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 37954 4.46% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 850568 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 62842 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 21.536775 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 323.180031 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 62840 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 18047 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 20216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 49731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 58137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 63836 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 67727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 72112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 73557 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 75338 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 76158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 77610 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 81366 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 78544 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 78356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 81800 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 76571 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 72953 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 70532 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1899 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1287 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 892 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 591 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 574 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 376 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 359 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 330 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 302 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 940579 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 181.734800 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 113.091903 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 237.596263 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 569137 60.51% 60.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 185879 19.76% 80.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 61156 6.50% 86.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 31438 3.34% 90.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 21576 2.29% 92.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 13250 1.41% 93.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 9973 1.06% 94.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 9805 1.04% 95.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 38365 4.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 940579 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 68336 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 21.464104 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 309.922160 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 68334 100.00% 100.00% # Reads before turning the bus around for writes
260,291c260,289
< system.physmem.rdPerTurnAround::total 62842 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 62842 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.631298 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.120021 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 6.777595 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 59398 94.52% 94.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 1045 1.66% 96.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 473 0.75% 96.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 210 0.33% 97.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 336 0.53% 97.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 469 0.75% 98.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 106 0.17% 98.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 34 0.05% 98.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 31 0.05% 98.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 28 0.04% 98.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 37 0.06% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 34 0.05% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 449 0.71% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 44 0.07% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 47 0.07% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 32 0.05% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 9 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 4 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 26 0.04% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 4 0.01% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 68336 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 68336 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.620273 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.104093 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 6.841865 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 64690 94.66% 94.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 1540 2.25% 96.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 239 0.35% 97.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 282 0.41% 97.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 82 0.12% 97.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 291 0.43% 98.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 162 0.24% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 86 0.13% 98.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 81 0.12% 98.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 117 0.17% 98.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 30 0.04% 98.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 46 0.07% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 391 0.57% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 42 0.06% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 42 0.06% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 142 0.21% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 21 0.03% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 7 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
293,297c291,294
< system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads
299,304c296,301
< system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 62842 # Writes before turning the bus around for reads
< system.physmem.totQLat 31787428314 # Total ticks spent queuing
< system.physmem.totMemAccLat 57164147064 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 6767125000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 23486.66 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 68336 # Writes before turning the bus around for reads
> system.physmem.totQLat 37142962355 # Total ticks spent queuing
> system.physmem.totMemAccLat 64645087355 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 7333900000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25322.79 # Average queueing delay per DRAM burst
306,310c303,307
< system.physmem.avgMemAccLat 42236.66 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.77 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44072.79 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.98 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s
313c310
< system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
---
> system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
315,333c312,330
< system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.28 # Average write queue length when enqueuing
< system.physmem.readRowHits 1086313 # Number of row buffer hits during reads
< system.physmem.writeRowHits 524528 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.26 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 47.34 # Row buffer hit rate for writes
< system.physmem.avgGap 19258662.67 # Average gap between requests
< system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3335290560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1819851000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 5311160400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3675585600 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1204726391325 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27417225862500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31735733267865 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.730691 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45610216470982 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1584682580000 # Time in different power states
---
> system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing
> system.physmem.readRowHits 1168360 # Number of row buffer hits during reads
> system.physmem.writeRowHits 561939 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 46.67 # Row buffer hit rate for writes
> system.physmem.avgGap 17756571.38 # Average gap between requests
> system.physmem.pageHitRate 64.78 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3585949920 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1956619500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 5602958400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3895302960 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1230768339570 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27405197149500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31751822762730 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.815694 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45589938065590 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1585284480000 # Time in different power states
335c332
< system.physmem_0.memoryStateTime::ACT 261780130518 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 299474968160 # Time in different power states
337,347c334,344
< system.physmem_1.actEnergy 3095003520 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1688742000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 5245507800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3504163680 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1191482148060 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27428843611500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31733498303040 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.683596 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45629577337540 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1584682580000 # Time in different power states
---
> system.physmem_1.actEnergy 3524827320 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1923268875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 5837886600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3907258560 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1224297828675 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27410873036250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31751180549160 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.802167 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45599398366763 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1585284480000 # Time in different power states
349c346
< system.physmem_1.memoryStateTime::ACT 242414504460 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 290016828237 # Time in different power states
413,450c410,442
< system.cpu0.dtb.walker.walks 105954 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 105954 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10115 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80576 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 105928 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 0.169927 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 55.305347 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-2047 105927 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 105928 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-32767 87482 96.43% 96.43% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2786 3.07% 99.51% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-98303 233 0.26% 99.76% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-131071 145 0.16% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-163839 15 0.02% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::163840-196607 6 0.01% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-229375 19 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-294911 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 9139568088 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 1.172115 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 -1573058396 -17.21% -17.21% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::1 10712626484 117.21% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 9139568088 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 80577 88.85% 88.85% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 10115 11.15% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 90692 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105954 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walks 101051 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 101051 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8300 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 78014 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 101044 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 101044 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 101044 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 86321 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 84871 98.32% 98.32% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 161 0.19% 98.51% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1103 1.28% 99.78% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 57 0.07% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 86321 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 1368339312 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean -0.519630 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 2079369704 151.96% 151.96% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::1 -711030392 -51.96% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 1368339312 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 78015 90.38% 90.38% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 8300 9.62% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 86315 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101051 # Table walker requests started/completed, data/inst
452,453c444,445
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105954 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90692 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101051 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 86315 # Table walker requests started/completed, data/inst
455,456c447,448
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90692 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 196646 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 86315 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 187366 # Table walker requests started/completed, data/inst
459,462c451,454
< system.cpu0.dtb.read_hits 80457124 # DTB read hits
< system.cpu0.dtb.read_misses 79863 # DTB read misses
< system.cpu0.dtb.write_hits 72637408 # DTB write hits
< system.cpu0.dtb.write_misses 26091 # DTB write misses
---
> system.cpu0.dtb.read_hits 83039604 # DTB read hits
> system.cpu0.dtb.read_misses 74585 # DTB read misses
> system.cpu0.dtb.write_hits 76137695 # DTB write hits
> system.cpu0.dtb.write_misses 26466 # DTB write misses
465,467c457,459
< system.cpu0.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 34410 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 37690 # Number of entries that have been flushed from TLB
469c461
< system.cpu0.dtb.prefetch_faults 3731 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 4076 # Number of TLB faults due to prefetch
471,473c463,465
< system.cpu0.dtb.perms_faults 8741 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 80536987 # DTB read accesses
< system.cpu0.dtb.write_accesses 72663499 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 10173 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 83114189 # DTB read accesses
> system.cpu0.dtb.write_accesses 76164161 # DTB write accesses
475,477c467,469
< system.cpu0.dtb.hits 153094532 # DTB hits
< system.cpu0.dtb.misses 105954 # DTB misses
< system.cpu0.dtb.accesses 153200486 # DTB accesses
---
> system.cpu0.dtb.hits 159177299 # DTB hits
> system.cpu0.dtb.misses 101051 # DTB misses
> system.cpu0.dtb.accesses 159278350 # DTB accesses
507,538c499,528
< system.cpu0.itb.walker.walks 53482 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 53482 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 578 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47523 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 53482 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 53482 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 53482 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 48101 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 21551.932392 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 45094 93.75% 93.75% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-65535 2542 5.28% 99.03% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-98303 133 0.28% 99.31% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::98304-131071 277 0.58% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-163839 5 0.01% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::163840-196607 6 0.01% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-229375 18 0.04% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::229376-262143 2 0.00% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 48101 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 47523 98.80% 98.80% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 578 1.20% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 48101 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walks 61250 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 61250 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 499 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55525 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 61250 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 61250 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 61250 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 56024 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 26762.682065 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 54387 97.08% 97.08% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.07% 97.15% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 1384 2.47% 99.62% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 41 0.07% 99.69% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 72 0.13% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 22 0.04% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 55 0.10% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 56024 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 1978837204 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 1978837204 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 1978837204 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 55525 99.11% 99.11% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 499 0.89% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 56024 # Table walker page sizes translated
540,541c530,531
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53482 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53482 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61250 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61250 # Table walker requests started/completed, data/inst
543,547c533,537
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48101 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48101 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 101583 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 428491503 # ITB inst hits
< system.cpu0.itb.inst_misses 53482 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56024 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56024 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 117274 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 441205116 # ITB inst hits
> system.cpu0.itb.inst_misses 61250 # ITB inst misses
554,556c544,546
< system.cpu0.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 24315 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 26202 # Number of entries that have been flushed from TLB
563,567c553,557
< system.cpu0.itb.inst_accesses 428544985 # ITB inst accesses
< system.cpu0.itb.hits 428491503 # DTB hits
< system.cpu0.itb.misses 53482 # DTB misses
< system.cpu0.itb.accesses 428544985 # DTB accesses
< system.cpu0.numCycles 94913359253 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 441266366 # ITB inst accesses
> system.cpu0.itb.hits 441205116 # DTB hits
> system.cpu0.itb.misses 61250 # DTB misses
> system.cpu0.itb.accesses 441266366 # DTB accesses
> system.cpu0.numCycles 94949400739 # number of cpu cycles simulated
570,591c560,581
< system.cpu0.committedInsts 428232691 # Number of instructions committed
< system.cpu0.committedOps 502476550 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 461534262 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 406829 # Number of float alu accesses
< system.cpu0.num_func_calls 25466680 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 64818437 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 461534262 # number of integer instructions
< system.cpu0.num_fp_insts 406829 # number of float instructions
< system.cpu0.num_int_register_reads 668961319 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 366250009 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 674435 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 305880 # number of times the floating registers were written
< system.cpu0.num_cc_register_reads 111832425 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 111484776 # number of times the CC registers were written
< system.cpu0.num_mem_refs 153083738 # number of memory refs
< system.cpu0.num_load_insts 80450777 # Number of load instructions
< system.cpu0.num_store_insts 72632961 # Number of store instructions
< system.cpu0.num_idle_cycles 93826651579.898026 # Number of idle cycles
< system.cpu0.num_busy_cycles 1086707673.101977 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.011449 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.988551 # Percentage of idle cycles
< system.cpu0.Branches 95423987 # Number of branches fetched
---
> system.cpu0.committedInsts 440958495 # Number of instructions committed
> system.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 531836 # Number of float alu accesses
> system.cpu0.num_func_calls 26928397 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 66358328 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 478066113 # number of integer instructions
> system.cpu0.num_fp_insts 531836 # number of float instructions
> system.cpu0.num_int_register_reads 691558601 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 378884875 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 853461 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 460304 # number of times the floating registers were written
> system.cpu0.num_cc_register_reads 113354931 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 113143261 # number of times the CC registers were written
> system.cpu0.num_mem_refs 159167445 # number of memory refs
> system.cpu0.num_load_insts 83034076 # Number of load instructions
> system.cpu0.num_store_insts 76133369 # Number of store instructions
> system.cpu0.num_idle_cycles 93735186324.296036 # Number of idle cycles
> system.cpu0.num_busy_cycles 1214214414.703974 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.012788 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.987212 # Percentage of idle cycles
> system.cpu0.Branches 98314010 # Number of branches fetched
593,623c583,613
< system.cpu0.op_class::IntAlu 348470598 69.31% 69.31% # Class of executed instruction
< system.cpu0.op_class::IntMult 1120076 0.22% 69.53% # Class of executed instruction
< system.cpu0.op_class::IntDiv 60052 0.01% 69.54% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 44021 0.01% 69.55% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
< system.cpu0.op_class::MemRead 80450777 16.00% 85.55% # Class of executed instruction
< system.cpu0.op_class::MemWrite 72632961 14.45% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 359396375 69.13% 69.13% # Class of executed instruction
> system.cpu0.op_class::IntMult 1169846 0.23% 69.36% # Class of executed instruction
> system.cpu0.op_class::IntDiv 59621 0.01% 69.37% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 75402 0.01% 69.38% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction
> system.cpu0.op_class::MemRead 83034076 15.97% 85.36% # Class of executed instruction
> system.cpu0.op_class::MemWrite 76133369 14.64% 100.00% # Class of executed instruction
626c616
< system.cpu0.op_class::total 502778486 # Class of executed instruction
---
> system.cpu0.op_class::total 519868732 # Class of executed instruction
628,637c618,627
< system.cpu0.kern.inst.quiesce 15090 # number of quiesce instructions executed
< system.cpu0.dcache.tags.replacements 5233253 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 480.798924 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 147607157 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5233765 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 28.202863 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 3987157000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.798924 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.939060 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.939060 # Average percentage of cache occupancy
---
> system.cpu0.kern.inst.quiesce 7168 # number of quiesce instructions executed
> system.cpu0.dcache.tags.replacements 5565465 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5565977 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 27.554484 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 6293402000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.695844 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983781 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.983781 # Average percentage of cache occupancy
639,641c629,631
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 429 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
643,734c633,724
< system.cpu0.dcache.tags.tag_accesses 311404737 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 311404737 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 74943991 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 74943991 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 68564818 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 68564818 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 176894 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 176894 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135340 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 135340 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1719391 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1719391 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1677698 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1677698 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 143508809 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 143508809 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 143685703 # number of overall hits
< system.cpu0.dcache.overall_hits::total 143685703 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 2840159 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 2840159 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1279764 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1279764 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601589 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 601589 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 758772 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 758772 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148889 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 148889 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188945 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 188945 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 4119923 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 4119923 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 4721512 # number of overall misses
< system.cpu0.dcache.overall_misses::total 4721512 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41012776500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 41012776500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24489617000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 24489617000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46337666000 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 46337666000 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2203666500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2203666500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4074419000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4074419000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2847000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2847000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 65502393500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 65502393500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 65502393500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 65502393500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 77784150 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 77784150 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 69844582 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 69844582 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 778483 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 778483 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894112 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 894112 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1868280 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 1868280 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1866643 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 1866643 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 147628732 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 147628732 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 148407215 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 148407215 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036513 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.036513 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018323 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.018323 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772771 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772771 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.848632 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.848632 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079693 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079693 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101222 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101222 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027907 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.027907 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14440.310032 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 14440.310032 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19136.041489 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 19136.041489 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61069.288271 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61069.288271 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14800.734104 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14800.734104 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21564.047739 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21564.047739 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 323920102 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 323920102 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 77284320 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 77284320 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 71935312 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 71935312 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 189585 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 189585 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125588 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 125588 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1730584 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1730584 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1699772 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1699772 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 149219632 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 149219632 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 149409217 # number of overall hits
> system.cpu0.dcache.overall_hits::total 149409217 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 3014242 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 3014242 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1370827 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1370827 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635540 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 635540 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 782263 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 782263 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168057 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 168057 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197269 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 197269 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 4385069 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 4385069 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 5020609 # number of overall misses
> system.cpu0.dcache.overall_misses::total 5020609 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52298763500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 52298763500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33070874000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 33070874000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65701301500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 65701301500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2847254500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2847254500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4866222000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4866222000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3481500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3481500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 85369637500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 85369637500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 85369637500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 85369637500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 80298562 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 80298562 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 73306139 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 73306139 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825125 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 825125 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 907851 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 907851 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1898641 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 1898641 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897041 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 1897041 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 153604701 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 153604701 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 154429826 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 154429826 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037538 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.037538 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018700 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.018700 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770235 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770235 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.861665 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.861665 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088514 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088514 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103988 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103988 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028548 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.028548 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032511 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.032511 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.552311 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 17350.552311 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 24124.761184 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 24124.761184 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83988.762731 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83988.762731 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16942.195208 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16942.195208 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24667.950869 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869 # average StoreCondReq miss latency
737,740c727,730
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15898.936339 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 15898.936339 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13873.181621 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13873.181621 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19468.254091 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 17003.841068 # average overall miss latency
749,834c739,824
< system.cpu0.dcache.writebacks::writebacks 3560219 # number of writebacks
< system.cpu0.dcache.writebacks::total 3560219 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30162 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 30162 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21215 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 21215 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39917 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39917 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 51377 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 51377 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 51377 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 51377 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2809997 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 2809997 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1258549 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1258549 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595949 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 595949 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 758772 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 758772 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108972 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108972 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188945 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 188945 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4068546 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4068546 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 4664495 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 4664495 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 26231 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 51684 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36991828000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36991828000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22707525500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22707525500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12844611500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12844611500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45578894000 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45578894000 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1445565000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1445565000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3885534000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3885534000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2787000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2787000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 59699353500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 59699353500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 72543965000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 72543965000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4455810500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4455810500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4073355500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4073355500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8529166000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8529166000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036126 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018019 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765526 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765526 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.848632 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.848632 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058327 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058327 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101222 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101222 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027559 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027559 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031430 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031430 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 3771246 # number of writebacks
> system.cpu0.dcache.writebacks::total 3771246 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 38597 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 38597 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21414 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 21414 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46766 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46766 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 60011 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 60011 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 60011 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 60011 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2975645 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 2975645 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1349413 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1349413 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 629920 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 629920 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 782263 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 782263 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121291 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121291 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197269 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 197269 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4325058 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4325058 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 4954978 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 4954978 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17296 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35915 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46589316500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46589316500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30941514500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30941514500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17872150500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17872150500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64919038500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64919038500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795061500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795061500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4668993000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4668993000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77530831000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 77530831000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 95402981500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 95402981500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2879350000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2879350000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3091479000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3091479000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5970829000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5970829000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037057 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037057 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018408 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018408 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763424 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763424 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.861665 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.861665 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063883 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063883 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103988 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103988 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028157 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.028157 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032086 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.032086 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638 # average StoreCondReq mshr miss latency
837,846c827,836
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17925.963305 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17925.963305 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19253.966718 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19253.966718 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166474.907493 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166474.907493 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166038.938719 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166038.938719 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 166248.893220 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220 # average overall mshr uncacheable latency
848,856c838,846
< system.cpu0.icache.tags.replacements 4666970 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.880807 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 423824020 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 4667482 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 90.803568 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 42558943000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.880807 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999767 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999767 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 5319178 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.824621 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 435885421 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 5319690 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 81.938124 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 59948153000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.824621 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999657 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999657 # Average percentage of cache occupancy
858,860c848,850
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id
862,899c852,889
< system.cpu0.icache.tags.tag_accesses 861650489 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 861650489 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 423824020 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 423824020 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 423824020 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 423824020 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 423824020 # number of overall hits
< system.cpu0.icache.overall_hits::total 423824020 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 4667483 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 4667483 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 4667483 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 4667483 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 4667483 # number of overall misses
< system.cpu0.icache.overall_misses::total 4667483 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48694088500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 48694088500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 48694088500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 48694088500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 48694088500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 48694088500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 428491503 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 428491503 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 428491503 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 428491503 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 428491503 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 428491503 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010893 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.010893 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010893 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.010893 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010893 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.010893 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10432.622572 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10432.622572 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 887729927 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 887729927 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 435885421 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 435885421 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 435885421 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 435885421 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 435885421 # number of overall hits
> system.cpu0.icache.overall_hits::total 435885421 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 5319695 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 5319695 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 5319695 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 5319695 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 5319695 # number of overall misses
> system.cpu0.icache.overall_misses::total 5319695 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 59521353000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 59521353000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 59521353000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 59521353000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 59521353000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 59521353000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 441205116 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 441205116 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 441205116 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 441205116 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 441205116 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 441205116 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012057 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.012057 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012057 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.012057 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012057 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.012057 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11188.865715 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11188.865715 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11188.865715 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11188.865715 # average overall miss latency
908,913c898,903
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4667483 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 4667483 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 4667483 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 4667483 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 4667483 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 4667483 # number of overall MSHR misses
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5319695 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 5319695 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 5319695 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 5319695 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 5319695 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 5319695 # number of overall MSHR misses
918,943c908,933
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 46360347000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 46360347000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 46360347000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 46360347000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 46360347000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 46360347000 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3777715000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3777715000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 3777715000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010893 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.010893 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.010893 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.622572 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # average overall mshr uncacheable latency
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 56861505500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 56861505500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 56861505500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 56861505500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 56861505500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 56861505500 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5953877000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5953877000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 5953877000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012057 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.012057 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012057 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.012057 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10688.865715 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942 # average overall mshr uncacheable latency
945,947c935,937
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 7039817 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 7039817 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 7344223 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 7344239 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
950,1106c940,1096
< system.cpu0.l2cache.prefetcher.pfSpanPage 925071 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2212798 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16140.904175 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 16304400 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2228972 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 7.314762 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 38965596000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 7022.512638 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.899316 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.792978 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3705.081021 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4185.062005 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1103.556217 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.428620 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003833 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226140 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.255436 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.067356 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.985163 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1459 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 603 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 957 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4495 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089050 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 335472623 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 335472623 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224520 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122258 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 346778 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 3560218 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 3560218 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 92512 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 92512 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 28864 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 28864 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 829198 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 829198 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4185639 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 4185639 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2620915 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2620915 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 197417 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 197417 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 224520 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122258 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 4185639 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3450113 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 7982530 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 224520 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122258 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 4185639 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3450113 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 7982530 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8873 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6826 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 15699 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 123328 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 123328 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160077 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 160077 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 230435 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 230435 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 481844 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 481844 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 894003 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 894003 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 560192 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 560192 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8873 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6826 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 481844 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1124438 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1621981 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8873 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6826 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 481844 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1124438 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1621981 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 259670000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 210027000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 469697000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2651049500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 2651049500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3319563500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3319563500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2697000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2697000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11221935999 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 11221935999 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 14420808000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 14420808000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 28972230000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 28972230000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 43145750500 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 43145750500 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 259670000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 210027000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 14420808000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 40194165999 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 55084670999 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 259670000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 210027000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 14420808000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 40194165999 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 55084670999 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 233393 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 129084 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 362477 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 3560218 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 3560218 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 215840 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 215840 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188941 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 188941 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1059633 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1059633 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4667483 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 4667483 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3514918 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 3514918 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 757609 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 757609 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 233393 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 129084 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 4667483 # number of demand (read+write) accesses
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< system.cpu0.l2cache.demand_accesses::total 9604511 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 233393 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 129084 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 4667483 # number of overall (read+write) accesses
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< system.cpu0.l2cache.overall_accesses::total 9604511 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052880 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.043310 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.571386 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.571386 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.847233 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.847233 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 976449 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2329725 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16186.065873 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 18053337 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2345760 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 7.696157 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 55834398000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 6981.301122 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.056568 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 81.620115 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4075.206909 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4054.876060 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 929.005098 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.426105 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003910 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004982 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.248731 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.247490 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056702 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.987919 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1345 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14643 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 806 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4474 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5446 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3835 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082092 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.893738 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 367456425 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 367456425 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 210868 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 144785 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 355653 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 3771244 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 3771244 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 99488 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 99488 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31647 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 31647 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 896733 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 896733 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4806679 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 4806679 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2773726 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2773726 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 232290 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 232290 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 210868 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 144785 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 4806679 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3670459 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 8832791 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 210868 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 144785 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 4806679 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3670459 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 8832791 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10391 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9054 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 19445 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121662 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 121662 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 165610 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 165610 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 248725 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 248725 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 513016 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 513016 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 953130 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 953130 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 548738 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 548738 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10391 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9054 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 513016 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1201855 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 1734316 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10391 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9054 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 513016 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1201855 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 1734316 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 495108500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 493404500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 988513000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3820404000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 3820404000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3956624500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3956624500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3380498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3380498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16864079500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 16864079500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20224946500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20224946500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 42635415000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 42635415000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62221144000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 62221144000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 495108500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 493404500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20224946500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 59499494500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 80712954000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 495108500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 493404500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20224946500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 59499494500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 80712954000 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221259 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 153839 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 375098 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 3771244 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 3771244 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 221150 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 221150 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197257 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 197257 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1145458 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1145458 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5319695 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 5319695 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3726856 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 3726856 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 781028 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 781028 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221259 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 153839 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 5319695 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 4872314 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 10567107 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221259 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 153839 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 5319695 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 4872314 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 10567107 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058854 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.051840 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550133 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550133 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.839565 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.839565 # miss rate for SCUpgradeReq accesses
1109,1153c1099,1143
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217467 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217467 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.103234 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.103234 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.254345 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.254345 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.739421 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.739421 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052880 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.103234 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.245803 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.168877 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038017 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052880 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.103234 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.245803 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.168877 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 30768.678582 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29918.912033 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21495.925499 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21495.925499 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20737.292053 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20737.292053 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 674250 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 674250 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48698.921600 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48698.921600 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 29928.375159 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 29928.375159 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32407.307358 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32407.307358 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 77019.576324 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 77019.576324 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 30768.678582 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29928.375159 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35746.004670 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 33961.354047 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29265.186521 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 30768.678582 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29928.375159 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35746.004670 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 33961.354047 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217140 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217140 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.096437 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.096437 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255746 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255746 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.702584 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.702584 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058854 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.096437 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246670 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.164124 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.046963 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058854 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.096437 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246670 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.164124 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54495.747736 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50836.358961 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31401.785274 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31401.785274 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23891.217318 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23891.217318 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 281708.166667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 281708.166667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67802.108755 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67802.108755 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39423.617392 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39423.617392 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44732.004029 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44732.004029 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113389.530158 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113389.530158 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54495.747736 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39423.617392 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 49506.383466 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 46538.781860 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47647.820229 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54495.747736 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39423.617392 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 49506.383466 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 46538.781860 # average overall miss latency
1162,1203c1152,1193
< system.cpu0.l2cache.writebacks::writebacks 1248318 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1248318 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3799 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 3799 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 319 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 319 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 4118 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 4118 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 4118 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 4118 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8873 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6826 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 15699 # number of ReadReq MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 86363 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::total 86363 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 615430 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 615430 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 123328 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 123328 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160077 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160077 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 226636 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 226636 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 481844 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 481844 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 893684 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 893684 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 560192 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 560192 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8873 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6826 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 481844 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1120320 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1617863 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8873 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6826 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 481844 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1120320 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 615430 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2233293 # number of overall MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 1299353 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1299353 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 4520 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 4520 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 530 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 530 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5050 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 5050 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5050 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 5050 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10391 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9054 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 19445 # number of ReadReq MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 93813 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::total 93813 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 630880 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 630880 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121662 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121662 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 165610 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 165610 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 12 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 12 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 244205 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 244205 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 513016 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 513016 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 952600 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 952600 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 548738 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 548738 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10391 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9054 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 513016 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1196805 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 1729266 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10391 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9054 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 513016 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1196805 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 630880 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2360146 # number of overall MSHR misses
1205,1208c1195,1198
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 69356 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 60421 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18619 # number of WriteReq MSHR uncacheable
1210,1252c1200,1242
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 94809 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 169071000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 375503000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25855371219 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 25855371219 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2504859500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2504859500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2454464000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2454464000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2337000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2337000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9468370499 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9468370499 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 11529744000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 11529744000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 23586536500 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 23586536500 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 39784598500 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 39784598500 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 169071000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11529744000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 33054906999 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 44960153999 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 206432000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 169071000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11529744000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 33054906999 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25855371219 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 70815525218 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4245962500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7700240000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3882458000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3882458000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3454277500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8128420500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11582698000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043310 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 79040 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 439080500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 871843000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35559655965 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35559655965 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4486256000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4486256000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3173949000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3173949000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3140498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3140498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14883734000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14883734000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17146850500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17146850500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36873595000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36873595000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 58928716000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 58928716000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 439080500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17146850500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51757329000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 69776022500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 432762500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 439080500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17146850500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51757329000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35559655965 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 105335678465 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630439500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2740982000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8371421500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2951836500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2951836500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630439500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5692818500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11323258000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.051840 # mshr miss rate for ReadReq accesses
1257,1260c1247,1250
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.571386 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.571386 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.847233 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.847233 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550133 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550133 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.839565 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839565 # mshr miss rate for SCUpgradeReq accesses
1263,1279c1253,1269
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213882 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213882 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103234 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254255 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254255 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.739421 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.739421 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244903 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.168448 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038017 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052880 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103234 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244903 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213194 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213194 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096437 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255604 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255604 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.702584 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.702584 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.245634 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163646 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.046963 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058854 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096437 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.245634 # mshr miss rate for overall accesses
1281,1319c1271,1309
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.232525 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23918.912033 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42011.879855 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20310.549916 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20310.549916 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15333.020984 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15333.020984 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 584250 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 584250 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41777.875090 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41777.875090 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.223348 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117 # average overall mshr uncacheable latency
1321,1352c1311,1348
< system.cpu0.toL2Bus.trans_dist::ReadReq 548810 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 8811478 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 25453 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 6868539 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 8637410 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 769123 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 445989 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 473125 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1446257 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1069406 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4667483 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5564741 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 864337 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 757609 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14087759 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16981197 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 288818 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 540500 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 31898274 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 298891412 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 527370978 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1032672 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1867144 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 829162206 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 9613339 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 30204161 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 1.324614 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.468231 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 22509328 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11536373 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 848 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 485130 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 485124 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 537841 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 9675681 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 18620 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 18619 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 5107009 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 8757288 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 798537 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 405076 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363715 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 481157 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 40 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1220841 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1155337 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5319695 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4658319 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 788798 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 781028 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16044388 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17944373 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 336960 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 515556 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 34841277 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 340632980 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 559762054 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1230712 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1770072 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 903395818 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 5410368 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 27976627 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.025738 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.158355 # Request fanout histogram
1354,1356c1350,1352
< system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 20399459 67.54% 67.54% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 9804702 32.46% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 27256564 97.43% 97.43% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 720057 2.57% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
1358c1354
< system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1360,1361c1356,1357
< system.cpu0.toL2Bus.snoop_fanout::total 30204161 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 14006094999 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 27976627 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 15196832497 # Layer occupancy (ticks)
1363c1359
< system.cpu0.toL2Bus.snoopLayer0.occupancy 188261483 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 183439903 # Layer occupancy (ticks)
1365c1361
< system.cpu0.toL2Bus.respLayer0.occupancy 7044349500 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 8022667500 # Layer occupancy (ticks)
1367c1363
< system.cpu0.toL2Bus.respLayer1.occupancy 7482254107 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 7935130422 # Layer occupancy (ticks)
1369c1365
< system.cpu0.toL2Bus.respLayer2.occupancy 159734000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 183121000 # Layer occupancy (ticks)
1371c1367
< system.cpu0.toL2Bus.respLayer3.occupancy 307107000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 294297000 # Layer occupancy (ticks)
1402,1425c1398,1422
< system.cpu1.dtb.walker.walks 101352 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 101352 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8872 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77968 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 101349 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 0.078935 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 25.129292 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-511 101348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 101349 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 86843 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 85298 98.22% 98.22% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1315 1.51% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 45 0.05% 99.79% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 84 0.10% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 70 0.08% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walks 111674 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 111674 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10360 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85053 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 111653 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 0.241821 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 61.696123 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-2047 111651 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 111653 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 95434 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 94629 99.16% 99.16% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 150 0.16% 99.31% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 551 0.58% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1427,1436c1424,1433
< system.cpu1.dtb.walker.walkCompletionTime::total 86843 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples -857364308 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean -0.833676 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 -1572128036 183.37% 183.37% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 714763728 -83.37% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total -857364308 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 77968 89.78% 89.78% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 8872 10.22% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 86840 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101352 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkCompletionTime::total 95434 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 10744163364 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 1.061708 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 -663005280 -6.17% -6.17% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 11407168644 106.17% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 10744163364 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 85053 89.14% 89.14% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 10360 10.86% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 95413 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 111674 # Table walker requests started/completed, data/inst
1438,1439c1435,1436
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101352 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86840 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 111674 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95413 # Table walker requests started/completed, data/inst
1441,1442c1438,1439
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86840 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 188192 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95413 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 207087 # Table walker requests started/completed, data/inst
1445,1448c1442,1445
< system.cpu1.dtb.read_hits 82714274 # DTB read hits
< system.cpu1.dtb.read_misses 74721 # DTB read misses
< system.cpu1.dtb.write_hits 75460503 # DTB write hits
< system.cpu1.dtb.write_misses 26631 # DTB write misses
---
> system.cpu1.dtb.read_hits 82869257 # DTB read hits
> system.cpu1.dtb.read_misses 83659 # DTB read misses
> system.cpu1.dtb.write_hits 74681159 # DTB write hits
> system.cpu1.dtb.write_misses 28015 # DTB write misses
1451,1453c1448,1450
< system.cpu1.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 38549 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 37721 # Number of entries that have been flushed from TLB
1455c1452
< system.cpu1.dtb.prefetch_faults 4418 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 4459 # Number of TLB faults due to prefetch
1457,1459c1454,1456
< system.cpu1.dtb.perms_faults 10567 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 82788995 # DTB read accesses
< system.cpu1.dtb.write_accesses 75487134 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 10437 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 82952916 # DTB read accesses
> system.cpu1.dtb.write_accesses 74709174 # DTB write accesses
1461,1463c1458,1460
< system.cpu1.dtb.hits 158174777 # DTB hits
< system.cpu1.dtb.misses 101352 # DTB misses
< system.cpu1.dtb.accesses 158276129 # DTB accesses
---
> system.cpu1.dtb.hits 157550416 # DTB hits
> system.cpu1.dtb.misses 111674 # DTB misses
> system.cpu1.dtb.accesses 157662090 # DTB accesses
1493,1526c1490,1516
< system.cpu1.itb.walker.walks 60693 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 60693 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 593 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54830 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 60693 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 60693 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 60693 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 55423 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 24648.566480 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-32767 49924 90.08% 90.08% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-65535 3716 6.70% 96.78% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-98303 553 1.00% 97.78% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::98304-131071 965 1.74% 99.52% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.06% 99.58% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.63% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-229375 86 0.16% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::229376-262143 15 0.03% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-294911 45 0.08% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::294912-327679 26 0.05% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::360448-393215 12 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 55423 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples -1656015036 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 -1656015036 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total -1656015036 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 54830 98.93% 98.93% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 593 1.07% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 55423 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 54727 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 54727 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 669 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48424 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 54727 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 54727 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 54727 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 49093 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 23909.080724 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 48315 98.42% 98.42% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 33 0.07% 98.48% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 627 1.28% 99.76% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 24 0.05% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 49093 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples -1309982220 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 -1309982220 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total -1309982220 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 48424 98.64% 98.64% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 669 1.36% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 49093 # Table walker page sizes translated
1528,1529c1518,1519
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60693 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60693 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54727 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54727 # Table walker requests started/completed, data/inst
1531,1535c1521,1525
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55423 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55423 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 116116 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 437193188 # ITB inst hits
< system.cpu1.itb.inst_misses 60693 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49093 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49093 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 103820 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 441006552 # ITB inst hits
> system.cpu1.itb.inst_misses 54727 # ITB inst misses
1542,1544c1532,1534
< system.cpu1.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 27130 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 26047 # Number of entries that have been flushed from TLB
1551,1555c1541,1545
< system.cpu1.itb.inst_accesses 437253881 # ITB inst accesses
< system.cpu1.itb.hits 437193188 # DTB hits
< system.cpu1.itb.misses 60693 # DTB misses
< system.cpu1.itb.accesses 437253881 # DTB accesses
< system.cpu1.numCycles 94913359253 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 441061279 # ITB inst accesses
> system.cpu1.itb.hits 441006552 # DTB hits
> system.cpu1.itb.misses 54727 # DTB misses
> system.cpu1.itb.accesses 441061279 # DTB accesses
> system.cpu1.numCycles 94949400719 # number of cpu cycles simulated
1558,1579c1548,1569
< system.cpu1.committedInsts 436909780 # Number of instructions committed
< system.cpu1.committedOps 515262081 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 474007520 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 488695 # Number of float alu accesses
< system.cpu1.num_func_calls 26553696 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 66234119 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 474007520 # number of integer instructions
< system.cpu1.num_fp_insts 488695 # number of float instructions
< system.cpu1.num_int_register_reads 687449190 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 375811208 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 781283 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 430208 # number of times the floating registers were written
< system.cpu1.num_cc_register_reads 112572477 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 112287439 # number of times the CC registers were written
< system.cpu1.num_mem_refs 158166235 # number of memory refs
< system.cpu1.num_load_insts 82712263 # Number of load instructions
< system.cpu1.num_store_insts 75453972 # Number of store instructions
< system.cpu1.num_idle_cycles 93876093406.586029 # Number of idle cycles
< system.cpu1.num_busy_cycles 1037265846.413978 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.010929 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.989071 # Percentage of idle cycles
< system.cpu1.Branches 97493416 # Number of branches fetched
---
> system.cpu1.committedInsts 440696565 # Number of instructions committed
> system.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 365483 # Number of float alu accesses
> system.cpu1.num_func_calls 25816030 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 67531060 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 474820793 # number of integer instructions
> system.cpu1.num_fp_insts 365483 # number of float instructions
> system.cpu1.num_int_register_reads 694878928 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 377300064 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 605102 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 276864 # number of times the floating registers were written
> system.cpu1.num_cc_register_reads 116712375 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 116303175 # number of times the CC registers were written
> system.cpu1.num_mem_refs 157542729 # number of memory refs
> system.cpu1.num_load_insts 82867724 # Number of load instructions
> system.cpu1.num_store_insts 74675005 # Number of store instructions
> system.cpu1.num_idle_cycles 93871458813.181076 # Number of idle cycles
> system.cpu1.num_busy_cycles 1077941905.818921 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.011353 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.988647 # Percentage of idle cycles
> system.cpu1.Branches 98303933 # Number of branches fetched
1581,1611c1571,1601
< system.cpu1.op_class::IntAlu 356171607 69.09% 69.09% # Class of executed instruction
< system.cpu1.op_class::IntMult 1079497 0.21% 69.30% # Class of executed instruction
< system.cpu1.op_class::IntDiv 59940 0.01% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 68277 0.01% 69.32% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 69.32% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.32% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.32% # Class of executed instruction
< system.cpu1.op_class::MemRead 82712263 16.04% 85.36% # Class of executed instruction
< system.cpu1.op_class::MemWrite 75453972 14.64% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 359137164 69.35% 69.35% # Class of executed instruction
> system.cpu1.op_class::IntMult 1056908 0.20% 69.56% # Class of executed instruction
> system.cpu1.op_class::IntDiv 59454 0.01% 69.57% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 36204 0.01% 69.58% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction
> system.cpu1.op_class::MemRead 82867724 16.00% 85.58% # Class of executed instruction
> system.cpu1.op_class::MemWrite 74675005 14.42% 100.00% # Class of executed instruction
1614c1604
< system.cpu1.op_class::total 515545598 # Class of executed instruction
---
> system.cpu1.op_class::total 517832459 # Class of executed instruction
1616,1722c1606,1712
< system.cpu1.kern.inst.quiesce 7070 # number of quiesce instructions executed
< system.cpu1.dcache.tags.replacements 5176711 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 457.282743 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 152806636 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5177218 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 29.515202 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8391490917000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.282743 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893130 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.893130 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 321544722 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 321544722 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 77092949 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 77092949 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 71608224 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 71608224 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188155 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 188155 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 187532 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 187532 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684198 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1684198 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1657450 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1657450 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 148701173 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 148701173 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 148889328 # number of overall hits
< system.cpu1.dcache.overall_hits::total 148889328 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 2950342 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 2950342 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1305907 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1305907 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 613815 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 613815 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 479868 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 479868 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172330 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 172330 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 197330 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 197330 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 4256249 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 4256249 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 4870064 # number of overall misses
< system.cpu1.dcache.overall_misses::total 4870064 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42135771000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 42135771000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22153910000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 22153910000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 15218762000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 15218762000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2580362000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2580362000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4225919000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 4225919000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2953000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2953000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 64289681000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 64289681000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 64289681000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 64289681000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 80043291 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 80043291 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 72914131 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 72914131 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 801970 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 801970 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 667400 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 667400 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1856528 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1856528 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1854780 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1854780 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 152957422 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 152957422 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 153759392 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 153759392 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036859 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.036859 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017910 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765384 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765384 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.719011 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.719011 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092824 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092824 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106390 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106390 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027826 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031673 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.031673 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 14490 # number of quiesce instructions executed
> system.cpu1.dcache.tags.replacements 5147651 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5148159 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 29.564853 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8409197794000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 420.489425 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.821268 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.821268 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 443 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 320234661 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 320234661 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 77182580 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 77182580 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 70763723 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 70763723 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181716 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 181716 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197136 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 197136 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768276 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1768276 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1725683 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1725683 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 147946303 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 147946303 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 148128019 # number of overall hits
> system.cpu1.dcache.overall_hits::total 148128019 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 2911211 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 2911211 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1304261 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1304261 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 646630 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 646630 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 461157 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 461157 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158092 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 158092 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198973 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 198973 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 4215472 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 4215472 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 4862102 # number of overall misses
> system.cpu1.dcache.overall_misses::total 4862102 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46228111000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 46228111000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27445585000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 27445585000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22477695000 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 22477695000 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2400515000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2400515000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4867748500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4867748500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2101500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2101500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 73673696000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 73673696000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 73673696000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 73673696000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 80093791 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 80093791 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 72067984 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 72067984 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828346 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 828346 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 658293 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 658293 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1926368 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1926368 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1924656 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1924656 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 152161775 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 152161775 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 152990121 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 152990121 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036348 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.036348 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018098 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.018098 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780628 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780628 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.700535 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.700535 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082067 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082067 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103381 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103381 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027704 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.027704 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031780 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.031780 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025 # average StoreCondReq miss latency
1725,1728c1715,1718
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 15104.774415 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 13200.993046 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17476.974346 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 15152.643034 # average overall miss latency
1737,1822c1727,1812
< system.cpu1.dcache.writebacks::writebacks 3350646 # number of writebacks
< system.cpu1.dcache.writebacks::total 3350646 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17552 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 17552 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 421 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 421 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45020 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45020 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 17973 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 17973 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 17973 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 17973 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932790 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2932790 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1305486 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1305486 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 613815 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 613815 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 479868 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 479868 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127310 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127310 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 197330 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 197330 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4238276 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4238276 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4852091 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4852091 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 12503 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25653 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38342874000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38342874000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20834838000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20834838000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12333914500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12333914500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14738894000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14738894000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690256500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690256500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4028650000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4028650000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2892000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2892000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59177712000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 59177712000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71511626500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 71511626500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2070021000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2070021000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2282534000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2282534000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4352555000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4352555000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036640 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036640 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017904 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017904 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765384 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765384 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.719011 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.719011 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068574 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068574 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106390 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106390 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027709 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.027709 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031556 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.031556 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 3396408 # number of writebacks
> system.cpu1.dcache.writebacks::total 3396408 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16912 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 16912 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 462 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 462 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41725 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41725 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 17374 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 17374 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 17374 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 17374 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2894299 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 2894299 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1303799 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1303799 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 646630 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 646630 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 461157 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 461157 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116367 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116367 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198973 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 198973 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4198098 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4198098 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 4844728 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 4844728 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 20770 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40100 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41851387000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41851387000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26109084500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26109084500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14515592000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14515592000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 22016538000 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 22016538000 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587242500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587242500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4668803500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4668803500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2073500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2073500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67960471500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 67960471500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 82476063500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 82476063500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3614060000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3614060000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3361466500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3361466500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975526500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6975526500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036136 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036136 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780628 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780628 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.700535 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.700535 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060407 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060407 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103381 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103381 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027590 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031667 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.031667 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747 # average StoreCondReq mshr miss latency
1825,1834c1815,1824
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302 # average overall mshr uncacheable latency
1836,1844c1826,1834
< system.cpu1.icache.tags.replacements 5209177 # number of replacements
< system.cpu1.icache.tags.tagsinuse 496.272261 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 431983494 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5209689 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 82.919248 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8391463454000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.272261 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969282 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.969282 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 4679241 # number of replacements
> system.cpu1.icache.tags.tagsinuse 495.918258 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 436326798 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 4679753 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 93.237143 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8409166313000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.918258 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968590 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.968590 # Average percentage of cache occupancy
1846,1848c1836,1838
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 440 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 359 # Occupied blocks per task id
1851,1888c1841,1878
< system.cpu1.icache.tags.tag_accesses 879596070 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 879596070 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 431983494 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 431983494 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 431983494 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 431983494 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 431983494 # number of overall hits
< system.cpu1.icache.overall_hits::total 431983494 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 5209694 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 5209694 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 5209694 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 5209694 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 5209694 # number of overall misses
< system.cpu1.icache.overall_misses::total 5209694 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53989351000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 53989351000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 53989351000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 53989351000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 53989351000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 53989351000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 437193188 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 437193188 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 437193188 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 437193188 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 437193188 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 437193188 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011916 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.011916 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011916 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.011916 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011916 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.011916 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10363.248014 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10363.248014 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 886692857 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 886692857 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 436326798 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 436326798 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 436326798 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 436326798 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 436326798 # number of overall hits
> system.cpu1.icache.overall_hits::total 436326798 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 4679754 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 4679754 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 4679754 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 4679754 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 4679754 # number of overall misses
> system.cpu1.icache.overall_misses::total 4679754 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52951180000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 52951180000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 52951180000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 52951180000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 52951180000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 52951180000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 441006552 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 441006552 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 441006552 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 441006552 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 441006552 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 441006552 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010612 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.010612 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010612 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.010612 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010612 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.010612 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 11314.949461 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 11314.949461 # average overall miss latency
1897,1902c1887,1892
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5209694 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5209694 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5209694 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5209694 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5209694 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5209694 # number of overall MSHR misses
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4679754 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 4679754 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 4679754 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 4679754 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 4679754 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 4679754 # number of overall MSHR misses
1907,1932c1897,1922
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51384504000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 51384504000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51384504000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 51384504000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51384504000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 51384504000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9739500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9739500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9739500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 9739500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011916 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.011916 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.011916 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9863.248014 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50611303500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 50611303500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50611303500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 50611303500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50611303500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 50611303500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14521500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14521500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14521500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 14521500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010612 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.010612 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.010612 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364 # average overall mshr uncacheable latency
1934,1936c1924,1926
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 7168932 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 7168932 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7337880 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7337888 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
1939,2094c1929,2088
< system.cpu1.l2cache.prefetcher.pfSpanPage 888356 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 2018400 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13471.145620 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 17736817 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2034046 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 8.719968 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 9876432033500 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 5731.708202 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.533292 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 100.125774 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3516.826700 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3218.371115 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 832.580536 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.349836 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004366 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006111 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.214650 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.196434 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050817 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.822213 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1631 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 762 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2682 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6101 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5119 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099548 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850342 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 350300692 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 350300692 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 208719 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141350 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 350069 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 3350644 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 3350644 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65287 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 65287 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34260 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 34260 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 879078 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 879078 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4680645 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 4680645 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2771065 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2771065 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 220708 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 220708 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 208719 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141350 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 4680645 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3650143 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 8680857 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 208719 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141350 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 4680645 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3650143 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 8680857 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10729 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9390 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 20119 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 125786 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 125786 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 163059 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 163059 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 237067 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 237067 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 529049 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 529049 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 902850 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 902850 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 257687 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 257687 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10729 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9390 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 529049 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1139917 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1689085 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10729 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9390 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 529049 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1139917 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1689085 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 428489500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 413569000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 842058500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2736210500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 2736210500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3427875000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3427875000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2800500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2800500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9388085997 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 9388085997 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15677246500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15677246500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28842829500 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28842829500 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 12565083500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 12565083500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 428489500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 413569000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15677246500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 38230915497 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 54750220497 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 428489500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 413569000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15677246500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 38230915497 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 54750220497 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 219448 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150740 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 370188 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 3350644 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 3350644 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 191073 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 191073 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 197319 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 197319 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1116145 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1116145 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5209694 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 5209694 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3673915 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3673915 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 478395 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 478395 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 219448 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150740 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5209694 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4790060 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 10369942 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 219448 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150740 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5209694 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4790060 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 10369942 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.062293 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.054348 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.658314 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.658314 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826373 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826373 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 899040 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 2034185 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13437.783654 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 16644740 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2049737 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 8.120427 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9820320151000 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 6510.894270 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 71.649917 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 96.755911 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2809.884427 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3040.183540 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 908.415590 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.397393 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004373 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005906 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.171502 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.185558 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055445 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.820177 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1547 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13928 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 636 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2599 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5864 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5395 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.094421 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 332457854 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 332457854 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 236423 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 125548 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 361971 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 3396406 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 3396406 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 63344 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 63344 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31004 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 31004 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 898756 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 898756 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4166985 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 4166985 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2749875 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2749875 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 193932 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 193932 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 236423 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 125548 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 4166985 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3648631 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 8177587 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 236423 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 125548 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 4166985 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3648631 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 8177587 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9552 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7233 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 16785 # number of ReadReq misses
> system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
> system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 123356 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 123356 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167961 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 167961 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 219942 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 219942 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 512769 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 512769 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 907421 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 907421 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265828 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 265828 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9552 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7233 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 512769 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1127363 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1656917 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9552 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7233 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 512769 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1127363 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1656917 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 404155000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 336372500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 740527500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3749073000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 3749073000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 4008183000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 4008183000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2030999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2030999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12972852500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 12972852500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18777464000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18777464000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34592386500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34592386500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 20042243500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 20042243500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 404155000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 336372500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18777464000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 47565239000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 67083230500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 404155000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 336372500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18777464000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 47565239000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 67083230500 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 245975 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 132781 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 378756 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 3396407 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 3396407 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186700 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 186700 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198965 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 198965 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1118698 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1118698 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4679754 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 4679754 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3657296 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3657296 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 459760 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 459760 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 245975 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 132781 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 4679754 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4775994 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 9834504 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 245975 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 132781 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 4679754 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4775994 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 9834504 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.054473 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.044316 # miss rate for ReadReq accesses
> system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
> system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.660718 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.660718 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.844174 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.844174 # miss rate for SCUpgradeReq accesses
2097,2141c2091,2135
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.212398 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.212398 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.101551 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.101551 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245746 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245746 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.538649 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.538649 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.062293 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.101551 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.237976 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.162883 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.048891 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.062293 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.101551 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.237976 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.162883 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44043.556976 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41853.894329 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21752.901754 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21752.901754 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21022.298677 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21022.298677 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 254590.909091 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 254590.909091 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39600.981988 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39600.981988 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 29632.881831 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 29632.881831 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31946.424655 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31946.424655 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 48761.029854 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 48761.029854 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44043.556976 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29632.881831 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33538.332613 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 32414.129838 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39937.505825 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44043.556976 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29632.881831 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33538.332613 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 32414.129838 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.196605 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.196605 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.109572 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.109572 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248113 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248113 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.578189 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.578189 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.054473 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109572 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.236048 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.168480 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038833 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.054473 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109572 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.236048 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.168480 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46505.253698 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44118.409294 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30392.303577 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30392.303577 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23863.771947 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23863.771947 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 253874.875000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 253874.875000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58983.061443 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58983.061443 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36619.733252 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36619.733252 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38121.650810 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38121.650810 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 75395.532073 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 75395.532073 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46505.253698 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36619.733252 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42191.591351 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 40486.777853 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42311.034338 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46505.253698 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36619.733252 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42191.591351 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 40486.777853 # average overall miss latency
2150,2191c2144,2189
< system.cpu1.l2cache.writebacks::writebacks 952252 # number of writebacks
< system.cpu1.l2cache.writebacks::total 952252 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3771 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 3771 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 320 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 320 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4091 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 4091 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4091 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 4091 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10729 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9390 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 20119 # number of ReadReq MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 95458 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::total 95458 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 646749 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 646749 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 125786 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 125786 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 163059 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 163059 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 11 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 233296 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 233296 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 529049 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 529049 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 902530 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 902530 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 257687 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 257687 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10729 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9390 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 529049 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1135826 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1684994 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10729 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9390 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 529049 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1135826 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 646749 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2331743 # number of overall MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 1015409 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1015409 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7242 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 7242 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 595 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 595 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7837 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 7837 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7837 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 7837 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9552 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7233 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 16785 # number of ReadReq MSHR misses
> system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
> system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 96130 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::total 96130 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 687356 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 687356 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 123356 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 123356 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167961 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167961 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 212700 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 212700 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 512769 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 512769 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 906826 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 906826 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 265827 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 265827 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9552 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7233 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 512769 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1119526 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1649080 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9552 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7233 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 512769 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1119526 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 687356 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2336436 # number of overall MSHR misses
2193,2196c2191,2194
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 12613 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 20880 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable
2198,2240c2196,2240
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25763 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 364115500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 357229000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 721344500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 24507257017 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 24507257017 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2611582999 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2611582999 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2531997500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2531997500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2434500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2434500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7622486997 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7622486997 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12502952500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12502952500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23395380000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23395380000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11018961500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11018961500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 364115500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 357229000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12502952500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31017866997 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 44242163997 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 364115500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 357229000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12502952500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31017866997 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 24507257017 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 68749421014 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8914500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1969997000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1978911500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2183909000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2183909000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8914500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4153906000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4162820500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.054348 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40210 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 292974500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 639817500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 44220457933 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 44220457933 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4206113500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4206113500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3161211000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3161211000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1862999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1862999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10724509000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10724509000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15700856000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15700856000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29099850500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29099850500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 18447195500 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 18447195500 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 292974500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15700856000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39824359500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 56165033000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 346843000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 292974500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15700856000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39824359500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 44220457933 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 100385490933 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13696500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3447900000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3461596500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3216491500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3216491500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13696500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6664391500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6678088000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044316 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
> system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
2245,2248c2245,2248
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.658314 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.658314 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826373 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826373 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.660718 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.660718 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.844174 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.844174 # mshr miss rate for SCUpgradeReq accesses
2251,2267c2251,2267
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.209019 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.209019 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101551 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245659 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245659 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.538649 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.538649 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.162488 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.048891 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.062293 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101551 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237121 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.190132 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.190132 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109572 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247950 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247950 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578186 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578186 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167683 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for overall accesses
2269,2307c2269,2307
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224856 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.237575 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538 # average overall mshr uncacheable latency
2309,2340c2309,2346
< system.cpu1.toL2Bus.trans_dist::ReadReq 557907 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 9467454 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 13150 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 6658964 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 9333240 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 797552 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 400874 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 357340 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 454404 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1816504 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1125838 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5209694 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5632852 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 585123 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 478395 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15628224 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16712375 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332083 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 514043 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 33186725 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333420856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 527793939 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205920 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1755584 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 864176299 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 9912470 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 31389750 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 1.322129 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.467292 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 20369965 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10454543 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 477453 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 477447 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 508237 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 8929000 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 19330 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 19330 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 4444983 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 8042862 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 852297 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 366971 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363003 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 446864 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1185291 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1125998 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4679754 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4554667 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 467005 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 459760 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14038440 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16622497 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 296146 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 569967 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 31527050 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 299504632 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 528992733 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1062248 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1967800 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 831527413 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5090691 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 25485456 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.028305 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.165844 # Request fanout histogram
2342,2344c2348,2350
< system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 21278201 67.79% 67.79% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 10111549 32.21% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 24764094 97.17% 97.17% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 721356 2.83% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
2346c2352
< system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2348,2349c2354,2355
< system.cpu1.toL2Bus.snoop_fanout::total 31389750 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 14234291993 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 25485456 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 13733891999 # Layer occupancy (ticks)
2351c2357
< system.cpu1.toL2Bus.snoopLayer0.occupancy 190598993 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 167318993 # Layer occupancy (ticks)
2353c2359
< system.cpu1.toL2Bus.respLayer0.occupancy 7814651000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 7019739500 # Layer occupancy (ticks)
2355c2361
< system.cpu1.toL2Bus.respLayer1.occupancy 7637949368 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7617418010 # Layer occupancy (ticks)
2357c2363
< system.cpu1.toL2Bus.respLayer2.occupancy 181343000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 163365000 # Layer occupancy (ticks)
2359c2365
< system.cpu1.toL2Bus.respLayer3.occupancy 294595499 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 323992499 # Layer occupancy (ticks)
2361,2365c2367,2371
< system.iobus.trans_dist::ReadReq 40360 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40360 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136623 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40317 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40317 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136619 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136619 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47666 # Packet count per connected master and slave (bytes)
2380,2382c2386,2388
< system.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122600 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes)
2385,2386c2391,2392
< system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353872 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47686 # Cumulative packet size per connected master and slave (bytes)
2401,2403c2407,2409
< system.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155707 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes)
2406,2407c2412,2413
< system.iobus.pkt_size::total 7496887 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36194000 # Layer occupancy (ticks)
2435c2441
< system.iobus.reqLayer27.occupancy 569839842 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 565735913 # Layer occupancy (ticks)
2439c2445
< system.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92712000 # Layer occupancy (ticks)
2441c2447
< system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks)
2445,2446c2451,2452
< system.iocache.tags.replacements 115629 # number of replacements
< system.iocache.tags.tagsinuse 11.301329 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115577 # number of replacements
> system.iocache.tags.tagsinuse 11.281807 # Cycle average of tags in use
2448c2454
< system.iocache.tags.sampled_refs 115645 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks.
2450,2455c2456,2461
< system.iocache.tags.warmup_cycle 9148621285000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 7.403816 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 3.897512 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.462739 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.243595 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.706333 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9206321837000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.831702 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.450105 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.239481 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.465632 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.705113 # Average percentage of cache occupancy
2459,2460c2465,2466
< system.iocache.tags.tag_accesses 1041045 # Number of tag accesses
< system.iocache.tags.data_accesses 1041045 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1040721 # Number of tag accesses
> system.iocache.tags.data_accesses 1040721 # Number of data accesses
2462,2463c2468,2469
< system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses
2469,2470c2475,2476
< system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8944 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8908 # number of demand (read+write) misses
2472,2473c2478,2479
< system.iocache.overall_misses::realview.ide 8904 # number of overall misses
< system.iocache.overall_misses::total 8944 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8868 # number of overall misses
> system.iocache.overall_misses::total 8908 # number of overall misses
2475,2476c2481,2482
< system.iocache.ReadReq_miss_latency::realview.ide 1656855076 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1662050076 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1668103306 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1673298306 # number of ReadReq miss cycles
2479,2480c2485,2486
< system.iocache.WriteLineReq_miss_latency::realview.ide 12632251766 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12632251766 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13929903607 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13929903607 # number of WriteLineReq miss cycles
2482,2483c2488,2489
< system.iocache.demand_miss_latency::realview.ide 1656855076 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1662419076 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1668103306 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1673667306 # number of demand (read+write) miss cycles
2485,2486c2491,2492
< system.iocache.overall_miss_latency::realview.ide 1656855076 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1662419076 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1668103306 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1673667306 # number of overall miss cycles
2488,2489c2494,2495
< system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses)
2495,2496c2501,2502
< system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses
2498,2499c2504,2505
< system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses
2514,2515c2520,2521
< system.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 185890.848451 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 187905.480741 # average ReadReq miss latency
2518,2519c2524,2525
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118359.303707 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 130517.798581 # average WriteLineReq miss latency
2521,2522c2527,2528
< system.iocache.demand_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 185869.753578 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 187883.622137 # average overall miss latency
2524,2526c2530,2532
< system.iocache.overall_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 185869.753578 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 32671 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 187883.622137 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 33272 # number of cycles access was blocked
2528c2534
< system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3491 # number of cycles access was blocked
2530c2536
< system.iocache.avg_blocked_cycles::no_mshrs 9.525073 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.530793 # average number of cycles each access was blocked
2534,2535c2540,2541
< system.iocache.writebacks::writebacks 106695 # number of writebacks
< system.iocache.writebacks::total 106695 # number of writebacks
---
> system.iocache.writebacks::writebacks 106694 # number of writebacks
> system.iocache.writebacks::total 106694 # number of writebacks
2537,2538c2543,2544
< system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses
2544,2545c2550,2551
< system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses
2547,2548c2553,2554
< system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses
2550,2551c2556,2557
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1211655076 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1215000076 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224703306 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1228048306 # number of ReadReq MSHR miss cycles
2554,2555c2560,2561
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7295851766 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7295851766 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8593503607 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8593503607 # number of WriteLineReq MSHR miss cycles
2557,2558c2563,2564
< system.iocache.demand_mshr_miss_latency::realview.ide 1211655076 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1215219076 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1224703306 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1228267306 # number of demand (read+write) MSHR miss cycles
2560,2561c2566,2567
< system.iocache.overall_mshr_miss_latency::realview.ide 1211655076 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1215219076 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1224703306 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1228267306 # number of overall MSHR miss cycles
2576,2577c2582,2583
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138103.665539 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741 # average ReadReq mshr miss latency
2580,2581c2586,2587
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581 # average WriteLineReq mshr miss latency
2583,2584c2589,2590
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency
2586,2587c2592,2593
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency
2589,2593c2595,2599
< system.l2c.tags.replacements 1275038 # number of replacements
< system.l2c.tags.tagsinuse 63572.316878 # Cycle average of tags in use
< system.l2c.tags.total_refs 4892898 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1334308 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 3.666993 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 1400633 # number of replacements
> system.l2c.tags.tagsinuse 63705.794368 # Cycle average of tags in use
> system.l2c.tags.total_refs 5028924 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1460176 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 3.444053 # Average number of references to valid blocks.
2595,2892c2601,2897
< system.l2c.tags.occ_blocks::writebacks 18943.726739 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 66.506889 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 88.082899 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 3576.388780 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 7769.332592 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6333.160086 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 237.192415 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 333.040502 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3918.032205 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 9111.997525 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.289058 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.001344 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.054571 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.118551 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.096636 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003619 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.005082 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.059784 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.139038 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.201338 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.970037 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 10413 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 223 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 48634 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 260 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 499 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 9654 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1442 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 42029 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.158890 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003403 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.742096 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 61952788 # Number of tag accesses
< system.l2c.tags.data_accesses 61952788 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 2200570 # number of Writeback hits
< system.l2c.Writeback_hits::total 2200570 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 25702 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 29550 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 55252 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 5421 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 6216 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 11637 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 145994 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 170556 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 316550 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4694 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3455 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 439478 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 496055 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 255928 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5679 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4922 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 484783 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 520043 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283587 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2498624 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 4694 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 3455 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 439478 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 642049 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 255928 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 5679 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4922 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 484783 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 690599 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 283587 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2815174 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 4694 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 3455 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 439478 # number of overall hits
< system.l2c.overall_hits::cpu0.data 642049 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 255928 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 5679 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4922 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 484783 # number of overall hits
< system.l2c.overall_hits::cpu1.data 690599 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 283587 # number of overall hits
< system.l2c.overall_hits::total 2815174 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 41366 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 45574 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 86940 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 9742 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 11031 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 20773 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 487808 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 146598 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 634406 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 811 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 757 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 42366 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 114531 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 184040 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2399 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2560 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 44266 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 108963 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176139 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 676832 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 811 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 757 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 42366 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 602339 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 184040 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 2399 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 2560 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 44266 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 255561 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 176139 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1311238 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 811 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 757 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 42366 # number of overall misses
< system.l2c.overall_misses::cpu0.data 602339 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 184040 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 2399 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 2560 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 44266 # number of overall misses
< system.l2c.overall_misses::cpu1.data 255561 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 176139 # number of overall misses
< system.l2c.overall_misses::total 1311238 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 225555000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 234735000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 460290000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 48941500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 54202000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 103143500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 40891325500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 11909713000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 52801038500 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 72944500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 67955000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3540995500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 10155548500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 211977500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 227366000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3707983000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 9711131500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 68879114830 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 72944500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 67955000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 3540995500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 51046874000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 211977500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 227366000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 3707983000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 21620844500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 121680153330 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 72944500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 67955000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 3540995500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 51046874000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21472556269 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 211977500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 227366000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 3707983000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 21620844500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19710657061 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 121680153330 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 2200570 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 2200570 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 67068 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 75124 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 142192 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 15163 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 17247 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 32410 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 633802 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 317154 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 950956 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5505 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4212 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 481844 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 610586 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 439968 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8078 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7482 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 529049 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 629006 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 459726 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3175456 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 5505 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 4212 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 481844 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1244388 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 439968 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 8078 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 7482 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 529049 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 946160 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 459726 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4126412 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 5505 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 4212 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 481844 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1244388 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 439968 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 8078 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 7482 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 529049 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 946160 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 459726 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4126412 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.616777 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.606650 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.611427 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.642485 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639589 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.640944 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.769654 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.462230 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.667124 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.179725 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.087925 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187576 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.342155 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.083671 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173230 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.213145 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.179725 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.087925 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.484044 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.342155 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.083671 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.270103 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.317767 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.147321 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.179725 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.087925 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.484044 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.418303 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.296979 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.342155 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.083671 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.270103 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383139 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.317767 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5452.666441 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5150.634133 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 5294.340925 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5023.763088 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4913.607107 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 4965.267414 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83826.680784 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81240.624019 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 83229.096982 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89768.824306 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83581.067365 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88670.739800 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88814.843750 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83765.937740 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89123.202371 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 101766.930095 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89768.824306 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 83581.067365 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 84747.748361 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88814.843750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 83765.937740 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 84601.502185 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 92797.915657 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89943.896424 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89768.824306 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 83581.067365 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 84747.748361 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 116673.311612 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88360.775323 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88814.843750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 83765.937740 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 84601.502185 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111903.990945 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 92797.915657 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.tags.occ_blocks::writebacks 18928.346727 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 167.390384 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 216.986390 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4428.367994 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 11717.643832 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11340.141344 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 156.822011 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 230.353384 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 2614.971757 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 4665.203250 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9239.567296 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.288824 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002554 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.003311 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.067572 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.178797 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173037 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002393 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.003515 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.039901 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.071185 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140985 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.972073 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 10769 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 48480 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 265 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 409 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 10095 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1411 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 41942 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.164322 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.739746 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 64230359 # Number of tag accesses
> system.l2c.tags.data_accesses 64230359 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 2314762 # number of Writeback hits
> system.l2c.Writeback_hits::total 2314762 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 28623 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 30874 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 59497 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 6079 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 5789 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 11868 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 160432 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 145801 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 306233 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5516 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4550 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 461560 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 521601 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 265120 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 4769 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3407 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 473807 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 524703 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 267683 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2532716 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 5516 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4550 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 461560 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 682033 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 265120 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 4769 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 3407 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 473807 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 670504 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 267683 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2838949 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 5516 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4550 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 461560 # number of overall hits
> system.l2c.overall_hits::cpu0.data 682033 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 265120 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 4769 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 3407 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 473807 # number of overall hits
> system.l2c.overall_hits::cpu1.data 670504 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 267683 # number of overall hits
> system.l2c.overall_hits::total 2838949 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 45739 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 41402 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 87141 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 10551 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 10041 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 20592 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 478288 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 167740 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 646028 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1990 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2246 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 51456 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 156048 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 188933 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1431 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1351 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 38962 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 102025 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 234272 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 778714 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 1990 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 2246 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 51456 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 634336 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 188933 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 1431 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1351 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 38962 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 269765 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1424742 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 1990 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 2246 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 51456 # number of overall misses
> system.l2c.overall_misses::cpu0.data 634336 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 188933 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 1431 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1351 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 38962 # number of overall misses
> system.l2c.overall_misses::cpu1.data 269765 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 234272 # number of overall misses
> system.l2c.overall_misses::total 1424742 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 656419000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 602429500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 1258848500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 138505500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 121106000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 259611500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 64575954000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 22241696500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 86817650500 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 275343500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 312648500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6939841000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 21911323500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 199825500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 189752500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5267042000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 14361628000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 119572711026 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 275343500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 312648500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 6939841000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 86487277500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 199825500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 189752500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 5267042000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 36603324500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 206390361526 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 275343500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 312648500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 6939841000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 86487277500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30784141526 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 199825500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 189752500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 5267042000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 36603324500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39331165000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 206390361526 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 2314762 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 2314762 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 74362 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 72276 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 146638 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 16630 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 15830 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 32460 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 638720 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 313541 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 952261 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7506 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6796 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 513016 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 677649 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 454053 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6200 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 4758 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 512769 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 626728 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 501955 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3311430 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 7506 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 6796 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 513016 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1316369 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 454053 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 6200 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 4758 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 512769 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 940269 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 501955 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4263691 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 7506 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 6796 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 513016 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1316369 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 454053 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 6200 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 4758 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 512769 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 940269 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 501955 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4263691 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.615086 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.572832 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.594259 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634456 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.634302 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.634381 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.748823 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.534986 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.678415 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.330489 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100301 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.230279 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.283943 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075984 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.162790 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.235159 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.330489 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.100301 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.481883 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.283943 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.075984 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.286902 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.334157 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.265121 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.330489 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.100301 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.481883 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.416103 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.230806 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.283943 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.075984 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.286902 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.466719 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.334157 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14351.406896 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14550.734264 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 14446.110327 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13127.239124 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12061.149288 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 12607.396076 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 135014.790252 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132596.259091 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 134386.823017 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 139202.359751 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134869.422419 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140413.997616 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140453.367876 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135184.076793 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140765.773095 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 153551.510601 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 139202.359751 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 134869.422419 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 136343.006703 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140453.367876 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 135184.076793 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 135685.965563 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 144861.568990 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138363.567839 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 139202.359751 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 134869.422419 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 136343.006703 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139640.461216 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140453.367876 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 135184.076793 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 135685.965563 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 144861.568990 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 455 # number of cycles access was blocked
2894c2899
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
2896c2901
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked
2900,2960c2905,2965
< system.l2c.writebacks::writebacks 1000989 # number of writebacks
< system.l2c.writebacks::total 1000989 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 84 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 16 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 106 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 84 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 290 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 84 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 16 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 106 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 84 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 16 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 106 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 290 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 40865 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 40865 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 41366 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 45574 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 86940 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9742 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11031 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 20773 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 487808 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 146598 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 634406 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 811 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 757 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 42282 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 114515 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 184040 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2399 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2560 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44160 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 108879 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 176139 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 676542 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 811 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 757 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 42282 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 602323 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 184040 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 2399 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 2560 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 44160 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 255477 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 176139 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1310948 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 811 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 757 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 42282 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 602323 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 184040 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 2399 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 2560 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 44160 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 255477 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 176139 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1310948 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 1097098 # number of writebacks
> system.l2c.writebacks::total 1097098 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 101 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 79 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 220 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 101 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 29 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 79 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 101 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 29 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 79 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 220 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 44502 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 44502 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 45739 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 41402 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 87141 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10551 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10041 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 20592 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 478288 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 167740 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 646028 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1990 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2246 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 51355 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 156019 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1431 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1351 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 38883 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 102014 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 778494 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 1990 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 2246 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 51355 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 634307 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 1431 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1351 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 38883 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 269754 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1424522 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 1990 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 2246 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 51355 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 634307 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 188933 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 1431 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1351 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 38883 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 269754 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 234272 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1424522 # number of overall MSHR misses
2962c2967
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17296 # number of ReadReq MSHR uncacheable
2964,2968c2969,2973
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 12501 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 81967 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38603 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 20768 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 81299 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18619 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 37949 # number of WriteReq MSHR uncacheable
2970c2975
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35915 # number of overall MSHR uncacheable misses
2972,3028c2977,3033
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25651 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 120570 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 858580500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 946408001 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1804988501 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 202067500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 228990999 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 431058499 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 36013245500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 10443733000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 46456978500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 64834500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 60385000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3112031500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 9009218000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19632156269 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 187987500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 201766000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3258945500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8616011500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17949267061 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 62092602830 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 64834500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 60385000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 3112031500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 45022463500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 19632156269 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 187987500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 201766000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 3258945500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 19059744500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 17949267061 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 108549581330 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 64834500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 60385000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 3112031500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 45022463500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19632156269 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187987500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 201766000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 3258945500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 19059744500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17949267061 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 108549581330 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3773796500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6934000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1744943000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 8203700500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3449741500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1960350500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5410092000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2678027000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7223538000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6934000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3705293500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 13613792500 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40098 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 119248 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3380760500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3033576500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 6414337000 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 808671000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 769117000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1577788000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 59793074000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 20564296500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 80357370500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 255443500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 290188500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6414337000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 20347560500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28894811526 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 185515500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 176242500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4869464500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13340357000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36988445000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 111762365526 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 255443500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 290188500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 6414337000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 80140634500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28894811526 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 185515500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 176242500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 4869464500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 33904653500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 36988445000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 192119736026 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 255443500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 290188500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 6414337000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 80140634500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28894811526 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 185515500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 176242500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 4869464500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 33904653500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36988445000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 192119736026 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854189000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2429636000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11716500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3074041000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 10369582500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2635303500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2887877500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5523181000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854189000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5064939500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11716500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5961918500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 15892763500 # number of overall MSHR uncacheable cycles
3031,3127c3036,3132
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.616777 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.606650 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.611427 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.642485 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639589 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.640944 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.769654 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462230 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.667124 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187549 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173097 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.213053 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.317697 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.317697 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123 # average overall mshr uncacheable latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.615086 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.572832 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.594259 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.634456 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.634302 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.634381 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.748823 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534986 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.678415 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.230236 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.162772 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235093 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.334105 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.265121 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.330489 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100104 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.481861 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.416103 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.230806 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.283943 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075829 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.286890 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.466719 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.334105 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73914.176086 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73271.255012 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73608.714612 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76644.014785 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76597.649636 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76621.406371 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 125014.790252 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122596.259091 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 124386.823017 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130417.195983 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130769.864921 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143562.269621 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124901.898549 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 126343.607275 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125233.765399 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125687.305842 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 134866.106684 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140473.866790 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148018.152928 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 127548.709086 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 141538.401633 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149398.732540 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145542.201376 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 141025.741334 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148683.687466 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 133274.885113 # average overall mshr uncacheable latency
3129,3140c3134,3146
< system.membus.trans_dist::ReadReq 81967 # Transaction distribution
< system.membus.trans_dist::ReadResp 767450 # Transaction distribution
< system.membus.trans_dist::WriteReq 38603 # Transaction distribution
< system.membus.trans_dist::WriteResp 38603 # Transaction distribution
< system.membus.trans_dist::Writeback 1107684 # Transaction distribution
< system.membus.trans_dist::CleanEvict 202348 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 391044 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 311393 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 114065 # Transaction distribution
< system.membus.trans_dist::ReadExReq 650749 # Transaction distribution
< system.membus.trans_dist::ReadExResp 628057 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 685483 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 81299 # Transaction distribution
> system.membus.trans_dist::ReadResp 868698 # Transaction distribution
> system.membus.trans_dist::WriteReq 37949 # Transaction distribution
> system.membus.trans_dist::WriteResp 37949 # Transaction distribution
> system.membus.trans_dist::Writeback 1203792 # Transaction distribution
> system.membus.trans_dist::CleanEvict 220565 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 376258 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 321655 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 113911 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.membus.trans_dist::ReadExReq 660250 # Transaction distribution
> system.membus.trans_dist::ReadExResp 639853 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 787399 # Transaction distribution
3143c3149
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122600 # Packet count per connected master and slave (bytes)
3145,3151c3151,3157
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26828 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4735959 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4885501 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342529 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 342529 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5228030 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24206 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5071225 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5218123 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341689 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 341689 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5559812 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155707 # Cumulative packet size per connected master and slave (bytes)
3153,3160c3159,3166
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53656 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147705452 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 147915041 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264128 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7264128 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 155179169 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 613936 # Total snoops (count)
< system.membus.snoop_fanout::samples 3578377 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48412 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 161136300 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 161340623 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7239232 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7239232 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 168579855 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 607627 # Total snoops (count)
> system.membus.snoop_fanout::samples 3798608 # Request fanout histogram
3165c3171
< system.membus.snoop_fanout::1 3578377 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3798608 100.00% 100.00% # Request fanout histogram
3170,3171c3176,3177
< system.membus.snoop_fanout::total 3578377 # Request fanout histogram
< system.membus.reqLayer0.occupancy 101272500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3798608 # Request fanout histogram
> system.membus.reqLayer0.occupancy 101169498 # Layer occupancy (ticks)
3173c3179
< system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3175c3181
< system.membus.reqLayer2.occupancy 23177500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 20972999 # Layer occupancy (ticks)
3177c3183
< system.membus.reqLayer5.occupancy 7575699049 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 8203462570 # Layer occupancy (ticks)
3179c3185
< system.membus.respLayer2.occupancy 7326536131 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 7924808506 # Layer occupancy (ticks)
3181c3187
< system.membus.respLayer3.occupancy 229377455 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 230064369 # Layer occupancy (ticks)
3235,3248c3241,3260
< system.toL2Bus.trans_dist::ReadReq 81969 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4074898 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38603 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 3308322 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1226405 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 439947 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 323030 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 762977 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1086983 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1086983 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4000171 # Transaction distribution
---
> system.toL2Bus.snoop_filter.tot_requests 10304168 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 5242935 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 1823032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 155703 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 143721 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 11982 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 81301 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4203748 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 37949 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 37949 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 3518592 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 1268318 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 429580 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 333523 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 763103 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 68 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 1086913 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 1086913 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4129694 # Transaction distribution
3250,3259c3262,3271
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7169000 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6360157 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 13529157 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 219530790 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185908027 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 405438817 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 3048406 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 11669556 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.129089 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.335298 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7476293 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6448186 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 13924479 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230559242 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190965829 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 421525071 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3161630 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 12055300 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.328437 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.471756 # Request fanout histogram
3261,3263c3273,3275
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 10163148 87.09% 87.09% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 1506408 12.91% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 8107870 67.26% 67.26% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3935448 32.64% 99.90% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 11982 0.10% 100.00% # Request fanout histogram
3265c3277
< system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3267,3268c3279,3280
< system.toL2Bus.snoop_fanout::total 11669556 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 7690985653 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 12055300 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 7945670452 # Layer occupancy (ticks)
3270c3282
< system.toL2Bus.snoopLayer0.occupancy 2550000 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2561165 # Layer occupancy (ticks)
3272c3284
< system.toL2Bus.respLayer0.occupancy 4244781764 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4404072117 # Layer occupancy (ticks)
3274c3286
< system.toL2Bus.respLayer1.occupancy 3859650249 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3899520231 # Layer occupancy (ticks)