3,5c3,5
< sim_seconds 47.367818 # Number of seconds simulated
< sim_ticks 47367817574000 # Number of ticks simulated
< final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.526955 # Number of seconds simulated
> sim_ticks 47526954967000 # Number of ticks simulated
> final_tick 47526954967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 678056 # Simulator instruction rate (inst/s)
< host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
< host_mem_usage 751768 # Number of bytes of host memory used
< host_seconds 1245.10 # Real time elapsed on the host
< sim_insts 844246943 # Number of instructions simulated
< sim_ops 993804803 # Number of ops (including micro ops) simulated
---
> host_inst_rate 679404 # Simulator instruction rate (inst/s)
> host_op_rate 799114 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36258651928 # Simulator tick rate (ticks/s)
> host_mem_usage 756696 # Number of bytes of host memory used
> host_seconds 1310.78 # Real time elapsed on the host
> sim_insts 890546366 # Number of instructions simulated
> sim_ops 1047459319 # Number of ops (including micro ops) simulated
16,32c16,32
< system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory
< system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory
< system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 120896 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 123520 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 3402100 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 13323656 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 13846976 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 139776 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 143808 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 3041464 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 11124432 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 15361728 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 416704 # Number of bytes read from this memory
> system.physmem.bytes_read::total 61045060 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 3402100 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 3041464 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6443564 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 78583104 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34,48c34,48
< system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory
< system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 78603688 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 1889 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 1930 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 93565 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 208195 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 216359 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 2184 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 2247 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 47611 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 173832 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 240027 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6511 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 994350 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1227861 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50,67c50,67
< system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1230435 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 2544 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 2599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 71583 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 280339 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 291350 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 2941 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 3026 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 63995 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 234066 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 323221 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8768 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1284430 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 71583 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 63995 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 135577 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1653443 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
69,126c69,126
< system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 684685 # Number of read requests accepted
< system.physmem.writeReqs 1596629 # Number of write requests accepted
< system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue
< system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 42136 # Per bank write bursts
< system.physmem.perBankRdBursts::1 44080 # Per bank write bursts
< system.physmem.perBankRdBursts::2 34958 # Per bank write bursts
< system.physmem.perBankRdBursts::3 41288 # Per bank write bursts
< system.physmem.perBankRdBursts::4 39326 # Per bank write bursts
< system.physmem.perBankRdBursts::5 49165 # Per bank write bursts
< system.physmem.perBankRdBursts::6 40428 # Per bank write bursts
< system.physmem.perBankRdBursts::7 47118 # Per bank write bursts
< system.physmem.perBankRdBursts::8 36254 # Per bank write bursts
< system.physmem.perBankRdBursts::9 81044 # Per bank write bursts
< system.physmem.perBankRdBursts::10 36070 # Per bank write bursts
< system.physmem.perBankRdBursts::11 40557 # Per bank write bursts
< system.physmem.perBankRdBursts::12 34453 # Per bank write bursts
< system.physmem.perBankRdBursts::13 38158 # Per bank write bursts
< system.physmem.perBankRdBursts::14 37145 # Per bank write bursts
< system.physmem.perBankRdBursts::15 42231 # Per bank write bursts
< system.physmem.perBankWrBursts::0 97165 # Per bank write bursts
< system.physmem.perBankWrBursts::1 99476 # Per bank write bursts
< system.physmem.perBankWrBursts::2 95543 # Per bank write bursts
< system.physmem.perBankWrBursts::3 98326 # Per bank write bursts
< system.physmem.perBankWrBursts::4 92692 # Per bank write bursts
< system.physmem.perBankWrBursts::5 102230 # Per bank write bursts
< system.physmem.perBankWrBursts::6 96747 # Per bank write bursts
< system.physmem.perBankWrBursts::7 98806 # Per bank write bursts
< system.physmem.perBankWrBursts::8 93672 # Per bank write bursts
< system.physmem.perBankWrBursts::9 100275 # Per bank write bursts
< system.physmem.perBankWrBursts::10 92352 # Per bank write bursts
< system.physmem.perBankWrBursts::11 96579 # Per bank write bursts
< system.physmem.perBankWrBursts::12 94667 # Per bank write bursts
< system.physmem.perBankWrBursts::13 97213 # Per bank write bursts
< system.physmem.perBankWrBursts::14 92658 # Per bank write bursts
< system.physmem.perBankWrBursts::15 99164 # Per bank write bursts
---
> system.physmem.bw_write::total 1653876 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1653443 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2544 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 2599 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 71583 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 280772 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 291350 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 2941 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 3026 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 63995 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 234066 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 323221 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8768 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2938306 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 994350 # Number of read requests accepted
> system.physmem.writeReqs 1902822 # Number of write requests accepted
> system.physmem.readBursts 994350 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1902822 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 63617152 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue
> system.physmem.bytesWritten 118663680 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 61045060 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 121636456 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 48679 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 115330 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 57482 # Per bank write bursts
> system.physmem.perBankRdBursts::1 61474 # Per bank write bursts
> system.physmem.perBankRdBursts::2 58055 # Per bank write bursts
> system.physmem.perBankRdBursts::3 62815 # Per bank write bursts
> system.physmem.perBankRdBursts::4 61744 # Per bank write bursts
> system.physmem.perBankRdBursts::5 72443 # Per bank write bursts
> system.physmem.perBankRdBursts::6 62137 # Per bank write bursts
> system.physmem.perBankRdBursts::7 62898 # Per bank write bursts
> system.physmem.perBankRdBursts::8 53757 # Per bank write bursts
> system.physmem.perBankRdBursts::9 98485 # Per bank write bursts
> system.physmem.perBankRdBursts::10 53699 # Per bank write bursts
> system.physmem.perBankRdBursts::11 61424 # Per bank write bursts
> system.physmem.perBankRdBursts::12 50178 # Per bank write bursts
> system.physmem.perBankRdBursts::13 60766 # Per bank write bursts
> system.physmem.perBankRdBursts::14 57507 # Per bank write bursts
> system.physmem.perBankRdBursts::15 59154 # Per bank write bursts
> system.physmem.perBankWrBursts::0 114707 # Per bank write bursts
> system.physmem.perBankWrBursts::1 119877 # Per bank write bursts
> system.physmem.perBankWrBursts::2 118693 # Per bank write bursts
> system.physmem.perBankWrBursts::3 118700 # Per bank write bursts
> system.physmem.perBankWrBursts::4 118108 # Per bank write bursts
> system.physmem.perBankWrBursts::5 125436 # Per bank write bursts
> system.physmem.perBankWrBursts::6 113884 # Per bank write bursts
> system.physmem.perBankWrBursts::7 116296 # Per bank write bursts
> system.physmem.perBankWrBursts::8 112515 # Per bank write bursts
> system.physmem.perBankWrBursts::9 116242 # Per bank write bursts
> system.physmem.perBankWrBursts::10 112992 # Per bank write bursts
> system.physmem.perBankWrBursts::11 118745 # Per bank write bursts
> system.physmem.perBankWrBursts::12 107808 # Per bank write bursts
> system.physmem.perBankWrBursts::13 111387 # Per bank write bursts
> system.physmem.perBankWrBursts::14 114155 # Per bank write bursts
> system.physmem.perBankWrBursts::15 114575 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 352 # Number of times write queue was full causing retry
< system.physmem.totGap 47367814519500 # Total gap between requests
---
> system.physmem.numWrRetry 406 # Number of times write queue was full causing retry
> system.physmem.totGap 47526951912500 # Total gap between requests
133c133
< system.physmem.readPktSize::3 37 # Read request sizes (log2)
---
> system.physmem.readPktSize::3 25 # Read request sizes (log2)
136c136
< system.physmem.readPktSize::6 641448 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 951125 # Read request sizes (log2)
140c140
< system.physmem.writePktSize::3 2601 # Write request sizes (log2)
---
> system.physmem.writePktSize::3 2572 # Write request sizes (log2)
143,165c143,165
< system.physmem.writePktSize::6 1594026 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1900248 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 698116 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 83658 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 42191 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 36638 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 31495 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 28119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 24839 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 21358 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 17624 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 4596 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1385 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1018 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 839 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 651 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 464 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 363 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 218 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
191,258c191,258
< system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 55966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 69244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 86453 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 95710 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 99723 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 98450 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 98652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 98653 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 101180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 101256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 102685 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 108850 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 104999 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 104785 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 118151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 108223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 102687 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 99179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 6890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 5415 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 5566 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 6838 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 6775 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 6308 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 6158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 7224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 5430 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 4899 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 4456 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 5091 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 4051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 3523 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 3763 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2982 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 2416 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1572 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 928 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 971 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 818 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 686 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 685 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 630 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 505 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 480 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 450 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 474 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 421 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1611 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 1054851 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 172.802142 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 106.115345 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 242.100455 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 681651 64.62% 64.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 201380 19.09% 83.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 48895 4.64% 88.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 24340 2.31% 90.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 17755 1.68% 92.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 11649 1.10% 93.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8558 0.81% 94.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 7940 0.75% 95.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 52683 4.99% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1054851 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 92018 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 10.802300 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 106.341779 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 92015 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
261,309c261,308
< system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads
< system.physmem.totQLat 20326500723 # Total ticks spent queuing
< system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 92018 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 92018 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.149536 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.827281 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 17.009129 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 90131 97.95% 97.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 760 0.83% 98.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 32 0.03% 98.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 41 0.04% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 142 0.15% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 182 0.20% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 347 0.38% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 116 0.13% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 35 0.04% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 63 0.07% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 31 0.03% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 15 0.02% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 6 0.01% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 5 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 16 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 24 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::576-591 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 92018 # Writes before turning the bus around for reads
> system.physmem.totQLat 36585898476 # Total ticks spent queuing
> system.physmem.totMemAccLat 55223735976 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 4970090000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 36806.07 # Average queueing delay per DRAM burst
311,315c310,314
< system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 55556.07 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.50 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.56 # Average system write bandwidth in MiByte/s
317c316
< system.physmem.busUtil 0.02 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.03 # Data bus utilization in percentage
320,338c319,337
< system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
< system.physmem.readRowHits 509481 # Number of row buffer hits during reads
< system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
< system.physmem.avgGap 20763390.98 # Average gap between requests
< system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
---
> system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing
> system.physmem.readRowHits 744165 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1049121 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 74.86 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 56.58 # Row buffer hit rate for writes
> system.physmem.avgGap 16404601.42 # Average gap between requests
> system.physmem.pageHitRate 62.96 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4105851120 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2240295750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 3892535400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 6128142480 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1214897373855 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27450471155250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31785964742895 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.798736 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45665609957576 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1587029340000 # Time in different power states
340c339
< system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 274315218424 # Time in different power states
342,352c341,351
< system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
---
> system.physmem_1.actEnergy 3868822440 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2110964625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 3860766000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5886555120 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1202076105075 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27461717882250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31783750484550 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.752146 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45684364167822 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1587029340000 # Time in different power states
354c353
< system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 255557515928 # Time in different power states
418,439c417,438
< system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walks 101631 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 101631 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9048 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76119 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 101620 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 0.113167 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 36.075158 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-1023 101619 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 101620 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 85178 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 84047 98.67% 98.67% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 953 1.12% 99.79% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 46 0.05% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 63 0.07% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 53 0.06% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
442,451c441,452
< system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 85178 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 6479942056 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 1.123756 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 -801929896 -12.38% -12.38% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::1 7281871952 112.38% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 6479942056 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 76120 89.38% 89.38% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 9048 10.62% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 85168 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101631 # Table walker requests started/completed, data/inst
453,454c454,455
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101631 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85168 # Table walker requests started/completed, data/inst
456,457c457,458
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85168 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 186799 # Table walker requests started/completed, data/inst
460,463c461,464
< system.cpu0.dtb.read_hits 81219280 # DTB read hits
< system.cpu0.dtb.read_misses 71070 # DTB read misses
< system.cpu0.dtb.write_hits 73504932 # DTB write hits
< system.cpu0.dtb.write_misses 24397 # DTB write misses
---
> system.cpu0.dtb.read_hits 83767358 # DTB read hits
> system.cpu0.dtb.read_misses 74871 # DTB read misses
> system.cpu0.dtb.write_hits 75914688 # DTB write hits
> system.cpu0.dtb.write_misses 26760 # DTB write misses
466,468c467,469
< system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 32159 # Number of entries that have been flushed from TLB
470c471
< system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 3900 # Number of TLB faults due to prefetch
472,474c473,475
< system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
< system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 8424 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 83842229 # DTB read accesses
> system.cpu0.dtb.write_accesses 75941448 # DTB write accesses
476,478c477,479
< system.cpu0.dtb.hits 154724212 # DTB hits
< system.cpu0.dtb.misses 95467 # DTB misses
< system.cpu0.dtb.accesses 154819679 # DTB accesses
---
> system.cpu0.dtb.hits 159682046 # DTB hits
> system.cpu0.dtb.misses 101631 # DTB misses
> system.cpu0.dtb.accesses 159783677 # DTB accesses
508,532c509,529
< system.cpu0.itb.walker.walks 56383 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 55722 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 55722 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 543 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49598 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 55722 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 55722 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 55722 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 50141 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 48785 97.30% 97.30% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 1144 2.28% 99.58% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 57 0.11% 99.69% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 79 0.16% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 56 0.11% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 50141 # Table walker service (enqueue to completion) latency
536,538c533,535
< system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 49598 98.92% 98.92% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 543 1.08% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 50141 # Table walker page sizes translated
540,541c537,538
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55722 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55722 # Table walker requests started/completed, data/inst
543,547c540,544
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 434853798 # ITB inst hits
< system.cpu0.itb.inst_misses 56383 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50141 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50141 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 105863 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 444122432 # ITB inst hits
> system.cpu0.itb.inst_misses 55722 # ITB inst misses
554,556c551,553
< system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 22526 # Number of entries that have been flushed from TLB
563,567c560,564
< system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
< system.cpu0.itb.hits 434853798 # DTB hits
< system.cpu0.itb.misses 56383 # DTB misses
< system.cpu0.itb.accesses 434910181 # DTB accesses
< system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 444178154 # ITB inst accesses
> system.cpu0.itb.hits 444122432 # DTB hits
> system.cpu0.itb.misses 55722 # DTB misses
> system.cpu0.itb.accesses 444178154 # DTB accesses
> system.cpu0.numCycles 95053909934 # number of cpu cycles simulated
570,623c567,620
< system.cpu0.committedInsts 434594659 # Number of instructions committed
< system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
< system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 468245604 # number of integer instructions
< system.cpu0.num_fp_insts 368958 # number of float instructions
< system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
< system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
< system.cpu0.num_mem_refs 154715442 # number of memory refs
< system.cpu0.num_load_insts 81215665 # Number of load instructions
< system.cpu0.num_store_insts 73499777 # Number of store instructions
< system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
< system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
< system.cpu0.Branches 96525602 # Number of branches fetched
< system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
< system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
< system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
< system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
< system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
< system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
---
> system.cpu0.committedInsts 443872382 # Number of instructions committed
> system.cpu0.committedOps 521690846 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 479475231 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 421225 # Number of float alu accesses
> system.cpu0.num_func_calls 26535732 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 67239811 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 479475231 # number of integer instructions
> system.cpu0.num_fp_insts 421225 # number of float instructions
> system.cpu0.num_int_register_reads 693782505 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 380162379 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 701849 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 304628 # number of times the floating registers were written
> system.cpu0.num_cc_register_reads 115037577 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 114748059 # number of times the CC registers were written
> system.cpu0.num_mem_refs 159672530 # number of memory refs
> system.cpu0.num_load_insts 83761106 # Number of load instructions
> system.cpu0.num_store_insts 75911424 # Number of store instructions
> system.cpu0.num_idle_cycles 93959856753.206024 # Number of idle cycles
> system.cpu0.num_busy_cycles 1094053180.793977 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.011510 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.988490 # Percentage of idle cycles
> system.cpu0.Branches 99058393 # Number of branches fetched
> system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
> system.cpu0.op_class::IntAlu 361081858 69.17% 69.17% # Class of executed instruction
> system.cpu0.op_class::IntMult 1125018 0.22% 69.39% # Class of executed instruction
> system.cpu0.op_class::IntDiv 61306 0.01% 69.40% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 43308 0.01% 69.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
> system.cpu0.op_class::MemRead 83761106 16.05% 85.46% # Class of executed instruction
> system.cpu0.op_class::MemWrite 75911424 14.54% 100.00% # Class of executed instruction
626c623
< system.cpu0.op_class::total 510121531 # Class of executed instruction
---
> system.cpu0.op_class::total 521984020 # Class of executed instruction
628,734c625,731
< system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
< system.cpu0.dcache.tags.replacements 5284481 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits
< system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits
< system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits
< system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses
< system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses
< system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses
< system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles
< system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses
< system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency
< system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency
< system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency
---
> system.cpu0.kern.inst.quiesce 5106 # number of quiesce instructions executed
> system.cpu0.dcache.tags.replacements 5414405 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 480.206026 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 154030593 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5414914 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 28.445621 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 4071814500 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.206026 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937902 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.937902 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 324790756 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 324790756 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 77996551 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 77996551 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 71694037 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 71694037 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 187802 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 187802 # number of SoftPFReq hits
> system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 131287 # number of WriteInvalidateReq hits
> system.cpu0.dcache.WriteInvalidateReq_hits::total 131287 # number of WriteInvalidateReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1831493 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1831493 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787873 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1787873 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 149690588 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 149690588 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 149878390 # number of overall hits
> system.cpu0.dcache.overall_hits::total 149878390 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 2964325 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 2964325 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1343066 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1343066 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 617580 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 617580 # number of SoftPFReq misses
> system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 739156 # number of WriteInvalidateReq misses
> system.cpu0.dcache.WriteInvalidateReq_misses::total 739156 # number of WriteInvalidateReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153043 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 153043 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195288 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 195288 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 4307391 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 4307391 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 4924971 # number of overall misses
> system.cpu0.dcache.overall_misses::total 4924971 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44154787210 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 44154787210 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26046845450 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 26046845450 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30884044772 # number of WriteInvalidateReq miss cycles
> system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30884044772 # number of WriteInvalidateReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2257944026 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2257944026 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4202199390 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4202199390 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2186500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2186500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 70201632660 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 70201632660 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 70201632660 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 70201632660 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 80960876 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 80960876 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 73037103 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 73037103 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 805382 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 805382 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 870443 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu0.dcache.WriteInvalidateReq_accesses::total 870443 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1984536 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 1984536 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1983161 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 1983161 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 153997979 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 153997979 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 154803361 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 154803361 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036614 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.036614 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018389 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.018389 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766816 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766816 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.849172 # miss rate for WriteInvalidateReq accesses
> system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.849172 # miss rate for WriteInvalidateReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077118 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077118 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098473 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098473 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027970 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.027970 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031814 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.031814 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718 # average WriteReq miss latency
> system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673 # average WriteInvalidateReq miss latency
> system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673 # average WriteInvalidateReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090 # average StoreCondReq miss latency
737,740c734,737
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 16297.947565 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 14254.222545 # average overall miss latency
749,828c746,831
< system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks
< system.cpu0.dcache.writebacks::total 3634622 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses
< system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency
< system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 3655915 # number of writebacks
> system.cpu0.dcache.writebacks::total 3655915 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 33290 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 33290 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21376 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 21376 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42886 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42886 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 54666 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 54666 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 54666 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 54666 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2931035 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 2931035 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1321690 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1321690 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 611921 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 611921 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 739156 # number of WriteInvalidateReq MSHR misses
> system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 739156 # number of WriteInvalidateReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110157 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110157 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195288 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 195288 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4252725 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4252725 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 4864646 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 4864646 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16584 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34617 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38329059920 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38329059920 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23455096050 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23455096050 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13388812156 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13388812156 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29772038228 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29772038228 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1440580476 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1440580476 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3899742610 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3899742610 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2117500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2117500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61784155970 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 61784155970 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75172968126 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 75172968126 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2701006250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2701006250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2792188500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2792188500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5493194750 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5493194750 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018096 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018096 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759790 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759790 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.849172 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.849172 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055508 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055508 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098473 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098473 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027615 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031425 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.031425 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267 # average WriteInvalidateReq mshr miss latency
> system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267 # average WriteInvalidateReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098 # average StoreCondReq mshr miss latency
831,840c834,843
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483 # average overall mshr uncacheable latency
842,848c845,851
< system.cpu0.icache.tags.replacements 4499955 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.replacements 5032307 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.899757 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 439089613 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 5032819 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 87.245262 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 33435686250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899757 # Average occupied blocks per requestor
852,854c855,857
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
856,893c859,896
< system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits
< system.cpu0.icache.overall_hits::total 430353331 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses
< system.cpu0.icache.overall_misses::total 4500467 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 893277683 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 893277683 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 439089613 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 439089613 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 439089613 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 439089613 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 439089613 # number of overall hits
> system.cpu0.icache.overall_hits::total 439089613 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 5032819 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 5032819 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 5032819 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 5032819 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 5032819 # number of overall misses
> system.cpu0.icache.overall_misses::total 5032819 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52854361147 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 52854361147 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 52854361147 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 52854361147 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 52854361147 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 52854361147 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 444122432 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 444122432 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 444122432 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 444122432 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 444122432 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 444122432 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011332 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.011332 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011332 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.011332 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011332 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.011332 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10501.939598 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10501.939598 # average overall miss latency
902,913c905,920
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5032819 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 5032819 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 5032819 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 5032819 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 5032819 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 5032819 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
> system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47804251855 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 47804251855 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47804251855 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 47804251855 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47804251855 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 47804251855 # number of overall MSHR miss cycles
918,933c925,940
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011332 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.011332 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.011332 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9498.504090 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000 # average overall mshr uncacheable latency
935,937c942,944
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 7625512 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 7211191 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 7211221 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue
940,1017c947,1021
< system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2276475 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16164.000425 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 9930056 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 4.331391 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 5342662500 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 7643.384526 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.376858 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.669060 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1070.606892 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.466515 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003502 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004618 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226984 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219608 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065345 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.986572 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1394 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085083 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 232158629 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 232158629 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 184213 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122134 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 3989528 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 2659243 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 3634621 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 3634621 # number of Writeback hits
< system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 174040 # number of WriteInvalidateReq hits
< system.cpu0.l2cache.WriteInvalidateReq_hits::total 174040 # number of WriteInvalidateReq hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 97614 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 97614 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30602 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 30602 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869323 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 869323 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 184213 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122134 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 3989528 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3528566 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 7824441 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 184213 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122134 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 3989528 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3528566 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 7824441 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8450 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6821 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 510939 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 880615 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 1406825 # number of ReadReq misses
< system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
< system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
< system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570673 # number of WriteInvalidateReq misses
< system.cpu0.l2cache.WriteInvalidateReq_misses::total 570673 # number of WriteInvalidateReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121192 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 121192 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 152342 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 152342 # number of SCUpgradeReq misses
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 945331 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2374120 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16169.428044 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 10531211 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2389368 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 4.407530 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 5341335500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 8264.618229 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 69.150581 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 77.449352 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3311.410043 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3382.587139 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1064.212699 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.504432 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004221 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004727 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.202112 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206457 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.064954 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.986904 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1373 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13790 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 780 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3709 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6679 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3275 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083801 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.841675 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 244043620 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 244043620 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 211402 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128647 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4517111 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 2702351 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 7559511 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 3655914 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 3655914 # number of Writeback hits
> system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 175642 # number of WriteInvalidateReq hits
> system.cpu0.l2cache.WriteInvalidateReq_hits::total 175642 # number of WriteInvalidateReq hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102383 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 102383 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30801 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 30801 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 876779 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 876779 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 211402 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128647 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 4517111 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3579130 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 8436290 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 211402 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128647 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 4517111 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3579130 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 8436290 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10881 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8892 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 515708 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 950762 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 1486243 # number of ReadReq misses
> system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 562136 # number of WriteInvalidateReq misses
> system.cpu0.l2cache.WriteInvalidateReq_misses::total 562136 # number of WriteInvalidateReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 120119 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 120119 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 164484 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 164484 # number of SCUpgradeReq misses
1020,1069c1024,1073
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228613 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 228613 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8450 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6821 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 510939 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1109228 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1635438 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8450 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6821 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 510939 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1109228 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1635438 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 233396250 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 201613986 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15055870276 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 27344253636 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 42835134148 # number of ReadReq miss cycles
< system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214216390 # number of WriteInvalidateReq miss cycles
< system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214216390 # number of WriteInvalidateReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2669808389 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 2669808389 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3193098671 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3193098671 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1181000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1181000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10520875436 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 10520875436 # number of ReadExReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 233396250 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 201613986 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15055870276 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 37865129072 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 53356009584 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 233396250 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 201613986 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15055870276 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 37865129072 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 53356009584 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 192663 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 128955 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4500467 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3539858 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 8361943 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 3634622 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 3634622 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 744713 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.WriteInvalidateReq_accesses::total 744713 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218806 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 218806 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 182944 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 182944 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 240029 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 240029 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10881 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8892 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 515708 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1190791 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 1726272 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10881 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8892 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 515708 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1190791 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 1726272 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 393469249 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355451999 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15907969852 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 31938942740 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 48595833840 # number of ReadReq miss cycles
> system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 181717619 # number of WriteInvalidateReq miss cycles
> system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 181717619 # number of WriteInvalidateReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2563026586 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 2563026586 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3399427212 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3399427212 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2070498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2070498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12166293140 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 12166293140 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 393469249 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355451999 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15907969852 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 44105235880 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 60762126980 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 393469249 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355451999 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15907969852 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 44105235880 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 60762126980 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222283 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 137539 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5032819 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3653113 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 9045754 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 3655914 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 3655914 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 737778 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.WriteInvalidateReq_accesses::total 737778 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 222502 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 222502 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195285 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 195285 # number of SCUpgradeReq accesses(hits+misses)
1072,1096c1076,1098
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1097936 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1097936 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 192663 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 128955 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 4500467 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 4637794 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 9459879 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 192663 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 128955 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 4500467 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 4637794 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 9459879 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052894 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.113530 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.248771 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.168241 # miss rate for ReadReq accesses
< system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
< system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
< system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.766299 # miss rate for WriteInvalidateReq accesses
< system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.766299 # miss rate for WriteInvalidateReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.553879 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.553879 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832725 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832725 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1116808 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1116808 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222283 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 137539 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 5032819 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 4769921 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 10162562 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 222283 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 137539 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 5032819 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 4769921 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 10162562 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064651 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102469 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.260261 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.164303 # miss rate for ReadReq accesses
> system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.761931 # miss rate for WriteInvalidateReq accesses
> system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.761931 # miss rate for WriteInvalidateReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.539856 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.539856 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.842277 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.842277 # miss rate for SCUpgradeReq accesses
1099,1135c1101,1137
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.208221 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208221 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052894 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.113530 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.239171 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.172881 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052894 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.113530 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.239171 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.172881 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 29557.834042 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29467.060209 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31051.314861 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30448.089953 # average ReadReq miss latency
< system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.375022 # average WriteInvalidateReq miss latency
< system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.375022 # average WriteInvalidateReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22029.576119 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22029.576119 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20960.067946 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20960.067946 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 393666.666667 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 393666.666667 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46020.460061 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46020.460061 # average ReadExReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 32624.905123 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 32624.905123 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214924 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.214924 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064651 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102469 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249646 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.169866 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064651 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102469 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249646 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.169866 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550 # average ReadReq miss latency
> system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 323.262732 # average WriteInvalidateReq miss latency
> system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 323.262732 # average WriteInvalidateReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20667.221201 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 690166 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 690166 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50686.763433 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50686.763433 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395 # average overall miss latency
1144,1168c1146,1168
< system.cpu0.l2cache.writebacks::writebacks 1283433 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1283433 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 443 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 443 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3351 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 3351 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3794 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 3794 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3794 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 3794 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8450 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6821 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 510939 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 880172 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 1406382 # number of ReadReq MSHR misses
< system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
< system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 635942 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570673 # number of WriteInvalidateReq MSHR misses
< system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570673 # number of WriteInvalidateReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121192 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121192 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 152342 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 152342 # number of SCUpgradeReq MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 1321734 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1321734 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 498 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6011 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 6011 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6509 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6509 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6509 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6509 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10881 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8892 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 515708 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 950264 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 1485745 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 659076 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 562136 # number of WriteInvalidateReq MSHR misses
> system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 562136 # number of WriteInvalidateReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 120119 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 120119 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 164484 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 164484 # number of SCUpgradeReq MSHR misses
1171,1211c1171,1219
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 225262 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 225262 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8450 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6821 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 510939 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1105434 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1631644 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8450 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6821 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 510939 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1105434 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2267586 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 157112514 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11720586224 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 21558629277 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33614638265 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 23030840367 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24220184845 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24220184845 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529730528 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529730528 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2304861456 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304861456 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1005500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1005500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8691962659 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8691962659 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 234018 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 234018 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10881 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8892 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 515708 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1184282 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 1719763 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10881 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8892 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 515708 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1184282 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2378839 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59709 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77742 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 297082001 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 12538366148 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25676104173 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 38833742573 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32139076466 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24223804784 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24223804784 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2466827080 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2466827080 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2435399890 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2435399890 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1771498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1771498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9980703954 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9980703954 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 297082001 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12538366148 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 35656808127 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 48814446527 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 297082001 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12538366148 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 35656808127 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 80953522993 # number of overall MSHR miss cycles
1213,1216c1221,1224
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2568327500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6036578500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2656940000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2656940000 # number of WriteReq MSHR uncacheable cycles
1218,1226c1226,1232
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
< system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5225267500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8693518500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.260124 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.164248 # mshr miss rate for ReadReq accesses
1229,1234c1235,1240
< system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.761931 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.761931 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.539856 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.539856 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.842277 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.842277 # mshr miss rate for SCUpgradeReq accesses
1237,1247c1243,1253
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209542 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209542 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.169225 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for overall accesses
1249,1285c1255,1291
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency
< system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.234079 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427 # average WriteInvalidateReq mshr miss latency
> system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427 # average WriteInvalidateReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900 # average overall mshr uncacheable latency
1287,1315c1293,1321
< system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 11389901 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 9301467 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 18033 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 3655914 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 950949 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1103178 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 737778 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 440847 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 362789 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 484218 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1248974 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1125262 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10151888 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15745151 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 304033 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 517558 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 26718630 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 322272916 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 593126965 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1100312 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1778264 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 918278457 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 4307980 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 19190741 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 1.234424 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.423639 # Request fanout histogram
1318,1321c1324,1325
< system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::1 14691964 76.56% 76.56% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 4498777 23.44% 100.00% # Request fanout histogram
1323,1326c1327,1330
< system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::total 19190741 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 11979643994 # Layer occupancy (ticks)
1328c1332
< system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 187059488 # Layer occupancy (ticks)
1330c1334
< system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 7611089646 # Layer occupancy (ticks)
1332c1336
< system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 7824710310 # Layer occupancy (ticks)
1334c1338
< system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 166780001 # Layer occupancy (ticks)
1336c1340
< system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 295551751 # Layer occupancy (ticks)
1367,1375c1371,1379
< system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.dtb.walker.walks 115983 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 115983 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11170 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89969 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 115964 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 0.064675 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 22.024176 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-511 115963 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1377,1400c1381,1405
< system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkWaitTime::total 115964 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 101158 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 99918 98.77% 98.77% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1061 1.05% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.03% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 72 0.07% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 53 0.05% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 101158 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 3223072220 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.344065 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.475063 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 2114124352 65.59% 65.59% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::1 1108947868 34.41% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 3223072220 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 89969 88.96% 88.96% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 11170 11.04% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 101139 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 115983 # Table walker requests started/completed, data/inst
1402,1403c1407,1408
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 115983 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 101139 # Table walker requests started/completed, data/inst
1405,1406c1410,1411
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 101139 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 217122 # Table walker requests started/completed, data/inst
1409,1412c1414,1417
< system.cpu1.dtb.read_hits 78277454 # DTB read hits
< system.cpu1.dtb.read_misses 68245 # DTB read misses
< system.cpu1.dtb.write_hits 71517077 # DTB write hits
< system.cpu1.dtb.write_misses 24264 # DTB write misses
---
> system.cpu1.dtb.read_hits 83993689 # DTB read hits
> system.cpu1.dtb.read_misses 86321 # DTB read misses
> system.cpu1.dtb.write_hits 76478778 # DTB write hits
> system.cpu1.dtb.write_misses 29662 # DTB write misses
1415,1417c1420,1422
< system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 42752 # Number of entries that have been flushed from TLB
1419c1424
< system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch
1421,1423c1426,1428
< system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
< system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 11385 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 84080010 # DTB read accesses
> system.cpu1.dtb.write_accesses 76508440 # DTB write accesses
1425,1427c1430,1432
< system.cpu1.dtb.hits 149794531 # DTB hits
< system.cpu1.dtb.misses 92509 # DTB misses
< system.cpu1.dtb.accesses 149887040 # DTB accesses
---
> system.cpu1.dtb.hits 160472467 # DTB hits
> system.cpu1.dtb.misses 115983 # DTB misses
> system.cpu1.dtb.accesses 160588450 # DTB accesses
1457,1489c1462,1488
< system.cpu1.itb.walker.walks 60524 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 60651 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 60651 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 616 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54731 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 60651 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 60651 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 60651 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 55347 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 53969 97.51% 97.51% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 1178 2.13% 99.64% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 42 0.08% 99.71% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.12% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 60 0.11% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.04% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 55347 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 2053569352 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 2053569352 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 2053569352 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 54731 98.89% 98.89% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 616 1.11% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 55347 # Table walker page sizes translated
1491,1492c1490,1491
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60651 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60651 # Table walker requests started/completed, data/inst
1494,1498c1493,1497
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 409921957 # ITB inst hits
< system.cpu1.itb.inst_misses 60524 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55347 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55347 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 115998 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 446979774 # ITB inst hits
> system.cpu1.itb.inst_misses 60651 # ITB inst misses
1505,1507c1504,1506
< system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 29800 # Number of entries that have been flushed from TLB
1514,1518c1513,1517
< system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
< system.cpu1.itb.hits 409921957 # DTB hits
< system.cpu1.itb.misses 60524 # DTB misses
< system.cpu1.itb.accesses 409982481 # DTB accesses
< system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 447040425 # ITB inst accesses
> system.cpu1.itb.hits 446979774 # DTB hits
> system.cpu1.itb.misses 60651 # DTB misses
> system.cpu1.itb.accesses 447040425 # DTB accesses
> system.cpu1.numCycles 95053909934 # number of cpu cycles simulated
1521,1574c1520,1573
< system.cpu1.committedInsts 409652284 # Number of instructions committed
< system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
< system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 446181756 # number of integer instructions
< system.cpu1.num_fp_insts 565626 # number of float instructions
< system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
< system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
< system.cpu1.num_mem_refs 149782083 # number of memory refs
< system.cpu1.num_load_insts 78271508 # Number of load instructions
< system.cpu1.num_store_insts 71510575 # Number of store instructions
< system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
< system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
< system.cpu1.Branches 91673037 # Number of branches fetched
< system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
< system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
< system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
< system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
< system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
< system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
---
> system.cpu1.committedInsts 446673984 # Number of instructions committed
> system.cpu1.committedOps 525768473 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 482657433 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 472663 # Number of float alu accesses
> system.cpu1.num_func_calls 26533376 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 68272280 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 482657433 # number of integer instructions
> system.cpu1.num_fp_insts 472663 # number of float instructions
> system.cpu1.num_int_register_reads 706740468 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 383340050 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 750974 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 430296 # number of times the floating registers were written
> system.cpu1.num_cc_register_reads 118015071 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 117677935 # number of times the CC registers were written
> system.cpu1.num_mem_refs 160465117 # number of memory refs
> system.cpu1.num_load_insts 83993061 # Number of load instructions
> system.cpu1.num_store_insts 76472056 # Number of store instructions
> system.cpu1.num_idle_cycles 93999959015.450027 # Number of idle cycles
> system.cpu1.num_busy_cycles 1053950918.549978 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.011088 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.988912 # Percentage of idle cycles
> system.cpu1.Branches 99666047 # Number of branches fetched
> system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
> system.cpu1.op_class::IntAlu 364374913 69.26% 69.26% # Class of executed instruction
> system.cpu1.op_class::IntMult 1108574 0.21% 69.47% # Class of executed instruction
> system.cpu1.op_class::IntDiv 57501 0.01% 69.48% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 68224 0.01% 69.50% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
> system.cpu1.op_class::MemRead 83993061 15.97% 85.46% # Class of executed instruction
> system.cpu1.op_class::MemWrite 76472056 14.54% 100.00% # Class of executed instruction
1577c1576
< system.cpu1.op_class::total 484255317 # Class of executed instruction
---
> system.cpu1.op_class::total 526074372 # Class of executed instruction
1579,1686c1578,1685
< system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed
< system.cpu1.dcache.tags.replacements 4752540 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits
< system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits
< system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits
< system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses
< system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses
< system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses
< system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles
< system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses
< system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency
< system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency
< system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 14059 # number of quiesce instructions executed
> system.cpu1.dcache.tags.replacements 5413042 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 455.092206 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 154856630 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5413554 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 28.605354 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8382280704500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.092206 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888852 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.888852 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 326337345 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 326337345 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 78172197 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 78172197 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 72471418 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 72471418 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183858 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 183858 # number of SoftPFReq hits
> system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197039 # number of WriteInvalidateReq hits
> system.cpu1.dcache.WriteInvalidateReq_hits::total 197039 # number of WriteInvalidateReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1730902 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1730902 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1704111 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1704111 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 150643615 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 150643615 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 150827473 # number of overall hits
> system.cpu1.dcache.overall_hits::total 150827473 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 3026410 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 3026410 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1374450 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1374450 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 681215 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 681215 # number of SoftPFReq misses
> system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 497314 # number of WriteInvalidateReq misses
> system.cpu1.dcache.WriteInvalidateReq_misses::total 497314 # number of WriteInvalidateReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 177400 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 177400 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202765 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 202765 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 4400860 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 4400860 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 5082075 # number of overall misses
> system.cpu1.dcache.overall_misses::total 5082075 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44105582717 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 44105582717 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23281173553 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 23281173553 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13579881027 # number of WriteInvalidateReq miss cycles
> system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13579881027 # number of WriteInvalidateReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2688373759 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2688373759 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4348203540 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4348203540 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1867000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1867000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 67386756270 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 67386756270 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 67386756270 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 67386756270 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 81198607 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 81198607 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 73845868 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 73845868 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 865073 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 865073 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 694353 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu1.dcache.WriteInvalidateReq_accesses::total 694353 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1908302 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1908302 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906876 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1906876 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 155044475 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 155044475 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 155909548 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 155909548 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037272 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.037272 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018612 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.018612 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787465 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787465 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.716226 # miss rate for WriteInvalidateReq accesses
> system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.716226 # miss rate for WriteInvalidateReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092962 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092962 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106334 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106334 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028385 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.028385 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032596 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.032596 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999 # average WriteReq miss latency
> system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316 # average WriteInvalidateReq miss latency
> system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316 # average WriteInvalidateReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840 # average StoreCondReq miss latency
1689,1692c1688,1691
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387 # average overall miss latency
1701,1780c1700,1785
< system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks
< system.cpu1.dcache.writebacks::total 3063492 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses
< system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency
< system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 3550271 # number of writebacks
> system.cpu1.dcache.writebacks::total 3550271 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18006 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 18006 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 425 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 425 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44886 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44886 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 18431 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 18431 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 18431 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 18431 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3008404 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 3008404 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1374025 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1374025 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 681215 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 681215 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 497314 # number of WriteInvalidateReq MSHR misses
> system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497314 # number of WriteInvalidateReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 132514 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 132514 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202765 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 202765 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4382429 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4382429 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5063644 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5063644 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21725 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 41838 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38446720676 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38446720676 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21137642197 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21137642197 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605784836 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605784836 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12830642973 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12830642973 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690394742 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690394742 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4033173960 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4033173960 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1807000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1807000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59584362873 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 59584362873 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73190147709 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 73190147709 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3727466501 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3727466501 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3465674500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3465674500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7193141001 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7193141001 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037050 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037050 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018607 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018607 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787465 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787465 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.716226 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.716226 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069441 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069441 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106334 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106334 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028266 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032478 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.032478 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917 # average WriteInvalidateReq mshr miss latency
> system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917 # average WriteInvalidateReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406 # average StoreCondReq mshr miss latency
1783,1792c1788,1797
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384 # average overall mshr uncacheable latency
1794,1802c1799,1807
< system.cpu1.icache.tags.replacements 5523110 # number of replacements
< system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 4892397 # number of replacements
> system.cpu1.icache.tags.tagsinuse 496.394395 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 442086860 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 4892909 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 90.352561 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8382252985250 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.394395 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969520 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.969520 # Average percentage of cache occupancy
1804,1807c1809,1812
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
1809,1846c1814,1851
< system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits
< system.cpu1.icache.overall_hits::total 404398330 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses
< system.cpu1.icache.overall_misses::total 5523627 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 898852462 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 898852462 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 442086860 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 442086860 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 442086860 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 442086860 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 442086860 # number of overall hits
> system.cpu1.icache.overall_hits::total 442086860 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 4892914 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 4892914 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 4892914 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 4892914 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 4892914 # number of overall misses
> system.cpu1.icache.overall_misses::total 4892914 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51771462698 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 51771462698 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 51771462698 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 51771462698 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 51771462698 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 51771462698 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 446979774 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 446979774 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 446979774 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 446979774 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 446979774 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 446979774 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010947 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.010947 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010947 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.010947 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010947 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.010947 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10580.905918 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10580.905918 # average overall miss latency
1855,1886c1860,1895
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5523627 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5523627 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5523627 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5523627 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4892914 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 4892914 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 4892914 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 4892914 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 4892914 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 4892914 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
> system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 46862593334 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 46862593334 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 46862593334 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 46862593334 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 46862593334 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 46862593334 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10105750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10105750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10105750 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 10105750 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010947 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.010947 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.010947 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9577.645005 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545 # average overall mshr uncacheable latency
1888,1890c1897,1899
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7631682 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7631760 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue
1893,1968c1902,1978
< system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 1638473 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1616 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 229858181 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 229858181 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 196843 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 146711 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5082589 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 2590406 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 3063492 # number of Writeback hits
< system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 265137 # number of WriteInvalidateReq hits
< system.cpu1.l2cache.WriteInvalidateReq_hits::total 265137 # number of WriteInvalidateReq hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 50742 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 50742 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 28295 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 28295 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 777406 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 777406 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 196843 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 146711 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 5082589 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3367812 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 8793955 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 196843 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3367812 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 8793955 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9130 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7601 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 441038 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 776098 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 1233867 # number of ReadReq misses
< system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 229595 # number of WriteInvalidateReq misses
< system.cpu1.l2cache.WriteInvalidateReq_misses::total 229595 # number of WriteInvalidateReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120541 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 120541 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 147968 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 147968 # number of SCUpgradeReq misses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 935080 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 2142260 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13497.078408 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 10799538 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2158371 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 5.003560 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9893608612000 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 5297.531895 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.016993 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.104378 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3470.735386 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3768.987855 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 794.701900 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.323336 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004762 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005316 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.211837 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.230041 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048505 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.823796 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1633 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14403 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1571 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5509 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6302 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099670 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.879089 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 240281832 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 240281832 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 248777 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141659 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4360207 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 2869888 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 7620531 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 3550270 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 3550270 # number of Writeback hits
> system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 228063 # number of WriteInvalidateReq hits
> system.cpu1.l2cache.WriteInvalidateReq_hits::total 228063 # number of WriteInvalidateReq hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 73786 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 73786 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35221 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 35221 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953536 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 953536 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 248777 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141659 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 4360207 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3823424 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 8574067 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 248777 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141659 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 4360207 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3823424 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 8574067 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9961 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7958 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 532707 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 952245 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 1502871 # number of ReadReq misses
> system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
> system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
> system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 267701 # number of WriteInvalidateReq misses
> system.cpu1.l2cache.WriteInvalidateReq_misses::total 267701 # number of WriteInvalidateReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120750 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 120750 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167539 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 167539 # number of SCUpgradeReq misses
1971,2020c1981,2030
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 207551 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 207551 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9130 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7601 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 441038 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 983649 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1441418 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9130 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7601 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 441038 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 983649 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1441418 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 287537248 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 274641499 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 13255864672 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 23821498253 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 37639541672 # number of ReadReq miss cycles
< system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 209637116 # number of WriteInvalidateReq miss cycles
< system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 209637116 # number of WriteInvalidateReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2569493734 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 2569493734 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3076594441 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3076594441 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1773498 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1773498 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8057830380 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 8057830380 # number of ReadExReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 287537248 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 274641499 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 13255864672 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 31879328633 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 45697372052 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 287537248 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 274641499 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 13255864672 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 31879328633 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 45697372052 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 205973 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 154312 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5523627 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3366504 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 9250416 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 3063492 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 494732 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.WriteInvalidateReq_accesses::total 494732 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 171283 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 171283 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 176263 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227703 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 227703 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9961 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7958 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 532707 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1179948 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1730574 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9961 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7958 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 532707 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1179948 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1730574 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 394640977 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358915726 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16056528318 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31264991014 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 48075076035 # number of ReadReq miss cycles
> system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 240883663 # number of WriteInvalidateReq miss cycles
> system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 240883663 # number of WriteInvalidateReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2642176746 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 2642176746 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3519293594 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3519293594 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1767000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1767000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9869071556 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 9869071556 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 394640977 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358915726 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16056528318 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 41134062570 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 57944147591 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 394640977 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358915726 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16056528318 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 41134062570 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 57944147591 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 258738 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149617 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4892914 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3822133 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 9123402 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 3550271 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 3550271 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 495764 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495764 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194536 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 194536 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202760 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 202760 # number of SCUpgradeReq accesses(hits+misses)
2023,2045c2033,2057
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 984957 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 984957 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 205973 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 154312 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5523627 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4351461 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 10235373 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 205973 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 154312 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5523627 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4351461 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 10235373 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049257 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079846 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.230535 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.133385 # miss rate for ReadReq accesses
< system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.464080 # miss rate for WriteInvalidateReq accesses
< system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.464080 # miss rate for WriteInvalidateReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.703753 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.703753 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.839473 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.839473 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1181239 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1181239 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 258738 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149617 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 4892914 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 5003372 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 10304641 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 258738 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149617 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 4892914 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 5003372 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 10304641 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053189 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.108873 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.249140 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.164727 # miss rate for ReadReq accesses
> system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
> system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
> system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.539977 # miss rate for WriteInvalidateReq accesses
> system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.539977 # miss rate for WriteInvalidateReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.620708 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.620708 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826292 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826292 # miss rate for SCUpgradeReq accesses
2048,2084c2060,2096
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210721 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210721 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049257 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079846 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.226050 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.140827 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049257 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079846 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.226050 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.140827 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36132.285094 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30056.060185 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30505.347555 # average ReadReq miss latency
< system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 913.073525 # average WriteInvalidateReq miss latency
< system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 913.073525 # average WriteInvalidateReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21316.346587 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21316.346587 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20792.295909 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20792.295909 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354699.600000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354699.600000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38823.375363 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38823.375363 # average ReadExReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 31703.067432 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 31703.067432 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.192766 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.192766 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053189 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.108873 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.235831 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.167941 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053189 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.108873 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.235831 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.167941 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081 # average ReadReq miss latency
> system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 899.823546 # average WriteInvalidateReq miss latency
> system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 899.823546 # average WriteInvalidateReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21881.380919 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21881.380919 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21005.817117 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21005.817117 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 353400 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 353400 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43341.860037 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43341.860037 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 33482.617670 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 33482.617670 # average overall miss latency
2093,2115c2105,2131
< system.cpu1.l2cache.writebacks::writebacks 764216 # number of writebacks
< system.cpu1.l2cache.writebacks::total 764216 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2534 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 2534 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 2857 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 2857 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 2857 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9130 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7601 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 441038 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 775775 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 1233544 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 524912 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 229595 # number of WriteInvalidateReq MSHR misses
< system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 229595 # number of WriteInvalidateReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120541 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120541 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 147968 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147968 # number of SCUpgradeReq MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 1053113 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1053113 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 432 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 432 # number of ReadReq MSHR hits
> system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits
> system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7197 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 7197 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7629 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 7629 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7629 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 7629 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9961 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7958 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 532707 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 951813 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 1502439 # number of ReadReq MSHR misses
> system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
> system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 707306 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 267700 # number of WriteInvalidateReq MSHR misses
> system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 267700 # number of WriteInvalidateReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120750 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120750 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167539 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167539 # number of SCUpgradeReq MSHR misses
2118,2171c2134,2197
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 205017 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 205017 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9130 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7601 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 441038 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 980792 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1438561 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9130 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7601 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 441038 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 980792 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 1963473 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224849501 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10375497328 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 18713747169 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29541935250 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 220506 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 220506 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9961 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7958 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 532707 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1172319 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1722945 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9961 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7958 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 532707 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1172319 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2430251 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21835 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 41948 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 306561274 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 12577785182 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 24989286886 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38202866865 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35407537019 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9092223824 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9092223824 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2448079564 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2448079564 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2512705540 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2512705540 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1507000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1507000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7591763498 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7591763498 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 306561274 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12577785182 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32581050384 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 45794630363 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 306561274 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12577785182 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32581050384 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 81202167382 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9241250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3553660750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3562902000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3314826000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3314826000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9241250 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6868486750 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6877728000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.249027 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.164680 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
> system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
2174,2179c2200,2205
< system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.539975 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.620708 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.620708 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826292 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826292 # mshr miss rate for SCUpgradeReq accesses
2182,2192c2208,2218
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.186673 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.186673 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167201 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for overall accesses
2194,2230c2220,2256
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
< system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.235840 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957 # average WriteInvalidateReq mshr miss latency
> system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957 # average WriteInvalidateReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 301400 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 301400 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716 # average overall mshr uncacheable latency
2232,2260c2258,2286
< system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 11407818 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 9339972 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 20113 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 3550271 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 1013669 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1157980 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495764 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 395206 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 367201 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 457834 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1341582 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1187599 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9786048 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15579584 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 330806 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 594855 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 26291293 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 313146936 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 585201818 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1196936 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2069904 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 901615594 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 4634762 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 19271924 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 1.253755 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.435159 # Request fanout histogram
2263,2266c2289,2290
< system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::1 14381570 74.62% 74.62% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 4890354 25.38% 100.00% # Request fanout histogram
2268,2271c2292,2295
< system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::total 19271924 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 11505600998 # Layer occupancy (ticks)
2273c2297
< system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 168563993 # Layer occupancy (ticks)
2275c2299
< system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 7347478432 # Layer occupancy (ticks)
2277c2301
< system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 8042476622 # Layer occupancy (ticks)
2279c2303
< system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 181503274 # Layer occupancy (ticks)
2281c2305
< system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 336447522 # Layer occupancy (ticks)
2283,2286c2307,2310
< system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
< system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 40366 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40366 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136641 # Transaction distribution
> system.iobus.trans_dist::WriteResp 29913 # Transaction distribution
2288c2312
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
2303,2305c2327,2329
< system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122716 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes)
2308,2309c2332,2333
< system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes)
2324,2326c2348,2350
< system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155823 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes)
2329,2330c2353,2354
< system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496797 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36274000 # Layer occupancy (ticks)
2358c2382
< system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 607607215 # Layer occupancy (ticks)
2362c2386
< system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92806000 # Layer occupancy (ticks)
2364c2388
< system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148515621 # Layer occupancy (ticks)
2368,2369c2392,2393
< system.iocache.tags.replacements 115606 # number of replacements
< system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115613 # number of replacements
> system.iocache.tags.tagsinuse 11.298152 # Cycle average of tags in use
2371c2395
< system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115629 # Sample count of references to valid blocks.
2373,2378c2397,2402
< system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9179138787000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 7.392909 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 3.905243 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.462057 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.244078 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy
2382,2383c2406,2407
< system.iocache.tags.tag_accesses 1040802 # Number of tag accesses
< system.iocache.tags.data_accesses 1040802 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1040838 # Number of tag accesses
> system.iocache.tags.data_accesses 1040838 # Number of data accesses
2385,2386c2409,2410
< system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses
2392,2393c2416,2417
< system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8881 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8921 # number of demand (read+write) misses
2395,2396c2419,2420
< system.iocache.overall_misses::realview.ide 8877 # number of overall misses
< system.iocache.overall_misses::total 8917 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8881 # number of overall misses
> system.iocache.overall_misses::total 8921 # number of overall misses
2398,2399c2422,2423
< system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1629816861 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1635012361 # number of ReadReq miss cycles
2402,2403c2426,2427
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles
---
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19901379733 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 19901379733 # number of WriteInvalidateReq miss cycles
2405,2406c2429,2430
< system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1629816861 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1635381361 # number of demand (read+write) miss cycles
2408,2409c2432,2433
< system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1629816861 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1635381361 # number of overall miss cycles
2411,2412c2435,2436
< system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses)
2418,2419c2442,2443
< system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8881 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8921 # number of demand (read+write) accesses
2421,2422c2445,2446
< system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8881 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8921 # number of overall (read+write) accesses
2437,2438c2461,2462
< system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 183338.457165 # average ReadReq miss latency
2441,2442c2465,2466
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency
---
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773 # average WriteInvalidateReq miss latency
2444,2445c2468,2469
< system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 183318.166237 # average overall miss latency
2447,2449c2471,2473
< system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 183318.166237 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 110961 # number of cycles access was blocked
2451c2475
< system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 16203 # number of cycles access was blocked
2453c2477
< system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.848176 # average number of cycles each access was blocked
2457,2458c2481,2482
< system.iocache.writebacks::writebacks 106699 # number of writebacks
< system.iocache.writebacks::total 106699 # number of writebacks
---
> system.iocache.writebacks::writebacks 106702 # number of writebacks
> system.iocache.writebacks::total 106702 # number of writebacks
2460,2461c2484,2485
< system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8881 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8918 # number of ReadReq MSHR misses
2467,2468c2491,2492
< system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8881 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8921 # number of demand (read+write) MSHR misses
2470,2471c2494,2495
< system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8881 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8921 # number of overall MSHR misses
2473,2474c2497,2498
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166890035 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1170160535 # number of ReadReq MSHR miss cycles
2477,2478c2501,2502
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles
---
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14351455801 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14351455801 # number of WriteInvalidateReq MSHR miss cycles
2480,2481c2504,2505
< system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1166890035 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1170373535 # number of demand (read+write) MSHR miss cycles
2483,2484c2507,2508
< system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1166890035 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1170373535 # number of overall MSHR miss cycles
2499,2500c2523,2524
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510 # average ReadReq mshr miss latency
2503,2504c2527,2528
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276 # average WriteInvalidateReq mshr miss latency
2506,2507c2530,2531
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency
2509,2510c2533,2534
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency
2512,2832c2536,2857
< system.l2c.tags.replacements 1063912 # number of replacements
< system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use
< system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.001634 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.115208 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.979281 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 9644 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 191 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 49666 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 226 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 9286 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 43236 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.147156 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.002914 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.757843 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 50574940 # Number of tag accesses
< system.l2c.tags.data_accesses 50574940 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 5180 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 4259 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 469863 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 537542 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 313027 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 4490 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 3587 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 401752 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 405704 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 231220 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 2376624 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 2047649 # number of Writeback hits
< system.l2c.Writeback_hits::total 2047649 # number of Writeback hits
< system.l2c.WriteInvalidateReq_hits::cpu0.data 135493 # number of WriteInvalidateReq hits
< system.l2c.WriteInvalidateReq_hits::cpu1.data 115685 # number of WriteInvalidateReq hits
< system.l2c.WriteInvalidateReq_hits::total 251178 # number of WriteInvalidateReq hits
< system.l2c.UpgradeReq_hits::cpu0.data 31239 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 22507 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 53746 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 6431 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 5062 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 11493 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 47681 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 46115 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 93796 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 5180 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 4259 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 469863 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 585223 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 313027 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 4490 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 3587 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 401752 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 451819 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 231220 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2470420 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 5180 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 4259 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 469863 # number of overall hits
< system.l2c.overall_hits::cpu0.data 585223 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 313027 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 4490 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 3587 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 401752 # number of overall hits
< system.l2c.overall_hits::cpu1.data 451819 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 231220 # number of overall hits
< system.l2c.overall_hits::total 2470420 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 577 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.itb.walker 634 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.inst 41076 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 94183 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 149529 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 1129 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.itb.walker 1344 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 39286 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 84710 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 531147 # number of ReadReq misses
< system.l2c.WriteInvalidateReq_misses::cpu0.data 427179 # number of WriteInvalidateReq misses
< system.l2c.WriteInvalidateReq_misses::cpu1.data 105657 # number of WriteInvalidateReq misses
< system.l2c.WriteInvalidateReq_misses::total 532836 # number of WriteInvalidateReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 47914 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 38699 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 86613 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 10572 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 7951 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 18523 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 64089 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 43672 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 107761 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 577 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 634 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 41076 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 158272 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 149529 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1129 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1344 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 39286 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 128382 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) misses
< system.l2c.demand_misses::total 638908 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 577 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 634 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 41076 # number of overall misses
< system.l2c.overall_misses::cpu0.data 158272 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 149529 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1129 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1344 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 39286 # number of overall misses
< system.l2c.overall_misses::cpu1.data 128382 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 118679 # number of overall misses
< system.l2c.overall_misses::total 638908 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 51297750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 55466264 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 3464868273 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 8461586857 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 98269250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.itb.walker 120308250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 3289147097 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 7432991468 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 55049336677 # number of ReadReq miss cycles
< system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 56781694 # number of WriteInvalidateReq miss cycles
< system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 44775578 # number of WriteInvalidateReq miss cycles
< system.l2c.WriteInvalidateReq_miss_latency::total 101557272 # number of WriteInvalidateReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 267824472 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 195648800 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 463473272 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46262535 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41400197 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 87662732 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 5583608052 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 3566659435 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 9150267487 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 51297750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 55466264 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 3464868273 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 14045194909 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 98269250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 120308250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 3289147097 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 10999650903 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 64199604164 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 51297750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 55466264 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 3464868273 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 14045194909 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 98269250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 120308250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 3289147097 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 10999650903 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 64199604164 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 5757 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 4893 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 510939 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 631725 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 462556 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 5619 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 4931 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 441038 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 490414 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 349899 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2907771 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 2047649 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 2047649 # number of Writeback accesses(hits+misses)
< system.l2c.WriteInvalidateReq_accesses::cpu0.data 562672 # number of WriteInvalidateReq accesses(hits+misses)
< system.l2c.WriteInvalidateReq_accesses::cpu1.data 221342 # number of WriteInvalidateReq accesses(hits+misses)
< system.l2c.WriteInvalidateReq_accesses::total 784014 # number of WriteInvalidateReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 79153 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 61206 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 140359 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 17003 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 13013 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 30016 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 111770 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 89787 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 201557 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 5757 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 4893 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 510939 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 743495 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462556 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 5619 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 4931 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 441038 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 580201 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 349899 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 3109328 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 5757 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 4893 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 510939 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 743495 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462556 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 5619 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 4931 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 441038 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 580201 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 349899 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 3109328 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129573 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.080393 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.149089 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.272561 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.089076 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.172732 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.182665 # miss rate for ReadReq accesses
< system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.759197 # miss rate for WriteInvalidateReq accesses
< system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.477347 # miss rate for WriteInvalidateReq accesses
< system.l2c.WriteInvalidateReq_miss_rate::total 0.679626 # miss rate for WriteInvalidateReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605334 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.632275 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.617082 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.621773 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.611004 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.617104 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.573401 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.486396 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.534643 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.129573 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.080393 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.212876 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.272561 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.089076 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.221272 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.205481 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.129573 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.080393 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.212876 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.272561 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.089076 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.221272 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.205481 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87486.220820 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84352.621312 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 89841.976333 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89515.066964 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83723.135392 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 87746.328273 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 103642.375231 # average ReadReq miss latency
< system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 132.922484 # average WriteInvalidateReq miss latency
< system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 423.782409 # average WriteInvalidateReq miss latency
< system.l2c.WriteInvalidateReq_avg_miss_latency::total 190.597617 # average WriteInvalidateReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5589.691364 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5055.655185 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 5351.082078 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4375.949205 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5206.916992 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 4732.642229 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87122.720779 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81669.248832 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 84912.607409 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 100483.331190 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 100483.331190 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 154 # number of cycles access was blocked
---
> system.l2c.tags.replacements 1448041 # number of replacements
> system.l2c.tags.tagsinuse 64131.287175 # Cycle average of tags in use
> system.l2c.tags.total_refs 4245095 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1507106 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.816720 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 11172879000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 19347.050639 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 116.894544 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 154.865125 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 3200.431152 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 7856.746302 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9704.320174 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 227.109782 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 297.906768 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3324.337079 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 8639.334854 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.295213 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001784 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.002363 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.048835 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.119884 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148076 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003465 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.004546 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.050725 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.131826 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.171849 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 10716 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 48031 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 38 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 439 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 10237 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1326 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 4887 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 41702 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.163513 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.004852 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.732895 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 58352089 # Number of tag accesses
> system.l2c.tags.data_accesses 58352089 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 5485 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 4305 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 465111 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 536784 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 265347 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 5257 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 3875 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 485070 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 556488 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 285641 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 2613363 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 2374848 # number of Writeback hits
> system.l2c.Writeback_hits::total 2374848 # number of Writeback hits
> system.l2c.WriteInvalidateReq_hits::cpu0.data 123464 # number of WriteInvalidateReq hits
> system.l2c.WriteInvalidateReq_hits::cpu1.data 121626 # number of WriteInvalidateReq hits
> system.l2c.WriteInvalidateReq_hits::total 245090 # number of WriteInvalidateReq hits
> system.l2c.UpgradeReq_hits::cpu0.data 24332 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 31013 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 55345 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 5518 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 6203 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 11721 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 54595 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 49708 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 104303 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 5485 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4305 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 465111 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 591379 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 265347 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5257 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 3875 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 485070 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 606196 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 285641 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2717666 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 5485 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4305 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 465111 # number of overall hits
> system.l2c.overall_hits::cpu0.data 591379 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 265347 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5257 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 3875 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 485070 # number of overall hits
> system.l2c.overall_hits::cpu1.data 606196 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 285641 # number of overall hits
> system.l2c.overall_hits::total 2717666 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 1889 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.itb.walker 1930 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.inst 50597 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 131294 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 2185 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.itb.walker 2247 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 47637 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 122248 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 816645 # number of ReadReq misses
> system.l2c.WriteInvalidateReq_misses::cpu0.data 431801 # number of WriteInvalidateReq misses
> system.l2c.WriteInvalidateReq_misses::cpu1.data 136823 # number of WriteInvalidateReq misses
> system.l2c.WriteInvalidateReq_misses::total 568624 # number of WriteInvalidateReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 44180 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 43907 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 88087 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 9646 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 11002 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 20648 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 78703 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 53921 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 132624 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 1889 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 1930 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 50597 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 209997 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 2185 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 2247 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 47637 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 176169 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) misses
> system.l2c.demand_misses::total 949269 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 1889 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 1930 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 50597 # number of overall misses
> system.l2c.overall_misses::cpu0.data 209997 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 216525 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 2185 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 2247 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 47637 # number of overall misses
> system.l2c.overall_misses::cpu1.data 176169 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 240093 # number of overall misses
> system.l2c.overall_misses::total 949269 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170785750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 176668500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 4301026862 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 11907133634 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 192678771 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 202084771 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 4020493910 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 11059922872 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 90717840977 # number of ReadReq miss cycles
> system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51822854 # number of WriteInvalidateReq miss cycles
> system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41218687 # number of WriteInvalidateReq miss cycles
> system.l2c.WriteInvalidateReq_miss_latency::total 93041541 # number of WriteInvalidateReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 233428095 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 271641854 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 505069949 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51474876 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56093222 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 107568098 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 6900295884 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 4492674608 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 11392970492 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 170785750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 176668500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 4301026862 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 18807429518 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 192678771 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 202084771 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 4020493910 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 15552597480 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 102110811469 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 170785750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 176668500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 4301026862 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 18807429518 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 192678771 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 202084771 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 4020493910 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 15552597480 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 102110811469 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 7374 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 6235 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 515708 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 668078 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 481872 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 7442 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 6122 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 532707 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 678736 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 525734 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 3430008 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 2374848 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 2374848 # number of Writeback accesses(hits+misses)
> system.l2c.WriteInvalidateReq_accesses::cpu0.data 555265 # number of WriteInvalidateReq accesses(hits+misses)
> system.l2c.WriteInvalidateReq_accesses::cpu1.data 258449 # number of WriteInvalidateReq accesses(hits+misses)
> system.l2c.WriteInvalidateReq_accesses::total 813714 # number of WriteInvalidateReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 68512 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 74920 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 143432 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 15164 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 17205 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 32369 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 133298 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 103629 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 236927 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 7374 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 6235 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 515708 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 801376 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 481872 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 7442 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 6122 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 532707 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 782365 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525734 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 3666935 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 7374 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 6235 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 515708 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 801376 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 481872 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 7442 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 6122 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 532707 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 782365 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525734 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 3666935 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309543 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.098112 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.196525 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.367037 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.089424 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.180111 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.238088 # miss rate for ReadReq accesses
> system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.777649 # miss rate for WriteInvalidateReq accesses
> system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.529400 # miss rate for WriteInvalidateReq accesses
> system.l2c.WriteInvalidateReq_miss_rate::total 0.698801 # miss rate for WriteInvalidateReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.644851 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.586052 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.614138 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636112 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639465 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.637894 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.590429 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.520327 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.559767 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.309543 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.098112 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.262046 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.367037 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.089424 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.225175 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.258873 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.309543 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.098112 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.262046 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.367037 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.089424 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.225175 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.258873 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 111086.017764 # average ReadReq miss latency
> system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 120.015595 # average WriteInvalidateReq miss latency
> system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 301.255542 # average WriteInvalidateReq miss latency
> system.l2c.WriteInvalidateReq_avg_miss_latency::total 163.625772 # average WriteInvalidateReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5283.569375 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6186.755050 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 5733.762632 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5336.396019 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5098.456826 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 5209.613425 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 85904.289510 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 107567.835323 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 107567.835323 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 328 # number of cycles access was blocked
2834c2859
< system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked
2836c2861
< system.l2c.avg_blocked_cycles::no_mshrs 154 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 23.428571 # average number of cycles each access was blocked
2840,2949c2865,2987
< system.l2c.writebacks::writebacks 850996 # number of writebacks
< system.l2c.writebacks::total 850996 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu0.inst 92 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu0.data 20 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.inst 88 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 92 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 88 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 92 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 88 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 223 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 577 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 634 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.inst 40984 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 94163 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1129 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1344 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 39198 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 84689 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 530924 # number of ReadReq MSHR misses
< system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 427179 # number of WriteInvalidateReq MSHR misses
< system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 105657 # number of WriteInvalidateReq MSHR misses
< system.l2c.WriteInvalidateReq_mshr_misses::total 532836 # number of WriteInvalidateReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 47914 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 38699 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 86613 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10572 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7951 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 18523 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 64089 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 43672 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 107761 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 577 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 634 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 40984 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 158252 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1129 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1344 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 39198 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 128361 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 638685 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 577 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 634 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 40984 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 158252 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1129 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1344 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 39198 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 128361 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 638685 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 47468736 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2944278477 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7281223143 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 103357750 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2790521653 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6370080782 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 48441561155 # number of ReadReq MSHR miss cycles
< system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13848705306 # number of WriteInvalidateReq MSHR miss cycles
< system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3323050924 # number of WriteInvalidateReq MSHR miss cycles
< system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17171756230 # number of WriteInvalidateReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 851924300 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 688614575 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1540538875 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 188348548 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 142101429 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 330449977 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4782492948 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3019981565 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 7802474513 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 47468736 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 2944278477 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 12063716091 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 103357750 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 2790521653 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 9390062347 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 56244035668 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 47468736 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 2944278477 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 12063716091 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 2790521653 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 9390062347 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles
---
> system.l2c.writebacks::writebacks 1121159 # number of writebacks
> system.l2c.writebacks::total 1121159 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.inst 120 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu0.data 25 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.inst 120 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::cpu1.data 30 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 120 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 120 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 30 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 120 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 120 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 30 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 296 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1889 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1930 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.inst 50477 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 131269 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2184 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2247 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 47517 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 122218 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 816349 # number of ReadReq MSHR misses
> system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 431801 # number of WriteInvalidateReq MSHR misses
> system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 136823 # number of WriteInvalidateReq MSHR misses
> system.l2c.WriteInvalidateReq_mshr_misses::total 568624 # number of WriteInvalidateReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 44180 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 43907 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 88087 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9646 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11002 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 20648 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 78703 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 53921 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 132624 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 1889 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 1930 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 50477 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 209972 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 2184 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 2247 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 47517 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 176139 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 948973 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 1889 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 1930 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 50477 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 209972 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 2184 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 2247 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 47517 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 176139 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 948973 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21723 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 81542 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38146 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 41836 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 119688 # number of overall MSHR uncacheable misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152273500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3658828888 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10259837116 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173733729 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3415229090 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9525126628 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 80569024173 # number of ReadReq MSHR miss cycles
> system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13996588148 # number of WriteInvalidateReq MSHR miss cycles
> system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4310102313 # number of WriteInvalidateReq MSHR miss cycles
> system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18306690461 # number of WriteInvalidateReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 786063539 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 780665261 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 1566728800 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 172133111 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 196209961 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 368343072 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5916837616 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3817995892 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 9734833508 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 152273500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 3658828888 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 16176674732 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173733729 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 3415229090 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 13343122520 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 90303857681 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 152273500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 3658828888 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 16176674732 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173733729 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 3415229090 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 13343122520 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 90303857681 # number of overall MSHR miss cycles
2951,2957c2989,2995
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2243809000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7049250 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3129187250 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 7985805000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2322501000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2942063000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5264564000 # number of WriteReq MSHR uncacheable cycles
2959,3065c2997,3103
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses
< system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses
< system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses
< system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency
< system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency
< system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency
< system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4566310000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7049250 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6071250250 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 13250369000 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.196488 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.180067 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.238002 # mshr miss rate for ReadReq accesses
> system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.777649 # mshr miss rate for WriteInvalidateReq accesses
> system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.529400 # mshr miss rate for WriteInvalidateReq accesses
> system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.698801 # mshr miss rate for WriteInvalidateReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.644851 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586052 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.614138 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636112 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639465 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.637894 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590429 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520327 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.559767 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.258792 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.258792 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050 # average ReadReq mshr miss latency
> system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254 # average WriteInvalidateReq mshr miss latency
> system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584 # average WriteInvalidateReq mshr miss latency
> system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992 # average WriteInvalidateReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378 # average overall mshr uncacheable latency
3067,3080c3105,3118
< system.membus.trans_dist::ReadReq 622157 # Transaction distribution
< system.membus.trans_dist::ReadResp 622157 # Transaction distribution
< system.membus.trans_dist::WriteReq 38973 # Transaction distribution
< system.membus.trans_dist::WriteResp 38973 # Transaction distribution
< system.membus.trans_dist::Writeback 957695 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
< system.membus.trans_dist::ReadExReq 123220 # Transaction distribution
< system.membus.trans_dist::ReadExResp 104410 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 906809 # Transaction distribution
> system.membus.trans_dist::ReadResp 906809 # Transaction distribution
> system.membus.trans_dist::WriteReq 38146 # Transaction distribution
> system.membus.trans_dist::WriteResp 38146 # Transaction distribution
> system.membus.trans_dist::Writeback 1227861 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 672387 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 672387 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 370275 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 320224 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 115346 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution
> system.membus.trans_dist::ReadExReq 145002 # Transaction distribution
> system.membus.trans_dist::ReadExResp 128981 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122716 # Packet count per connected master and slave (bytes)
3082,3088c3120,3126
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24970 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5055890 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5203668 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335590 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 335590 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5539258 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155823 # Cumulative packet size per connected master and slave (bytes)
3090,3097c3128,3135
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 581158 # Total snoops (count)
< system.membus.snoop_fanout::samples 2928688 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49940 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168605292 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 168811259 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14076224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 14076224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 182887483 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 594337 # Total snoops (count)
> system.membus.snoop_fanout::samples 3681134 # Request fanout histogram
3102c3140
< system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3681134 100.00% 100.00% # Request fanout histogram
3107,3108c3145,3146
< system.membus.snoop_fanout::total 2928688 # Request fanout histogram
< system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3681134 # Request fanout histogram
> system.membus.reqLayer0.occupancy 100790999 # Layer occupancy (ticks)
3112c3150
< system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 21573500 # Layer occupancy (ticks)
3114c3152
< system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 11112792344 # Layer occupancy (ticks)
3116c3154
< system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 5991933811 # Layer occupancy (ticks)
3118c3156
< system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 151912879 # Layer occupancy (ticks)
3162,3185c3200,3223
< system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 1518303 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadReq 4327568 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4320333 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38146 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 2374848 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 920665 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateResp 813714 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 419012 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 331945 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 750957 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 292509 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 292509 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7096014 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6270717 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 13366731 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 236480377 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202778754 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 439259131 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 1555479 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 8704899 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.013311 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.114603 # Request fanout histogram
3188,3189c3226,3227
< system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 8589027 98.67% 98.67% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 115872 1.33% 100.00% # Request fanout histogram
3193,3194c3231,3232
< system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 8704899 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 7795939791 # Layer occupancy (ticks)
3196c3234
< system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2526000 # Layer occupancy (ticks)
3198c3236
< system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3978610795 # Layer occupancy (ticks)
3200c3238
< system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3846379763 # Layer occupancy (ticks)