Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.522770 # Number of seconds simulated 4sim_ticks 47522770414500 # Number of ticks simulated 5final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.522770 # Number of seconds simulated 4sim_ticks 47522770414500 # Number of ticks simulated 5final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 967829 # Simulator instruction rate (inst/s) 8host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52174728436 # Simulator tick rate (ticks/s) 10host_mem_usage 796444 # Number of bytes of host memory used 11host_seconds 910.84 # Real time elapsed on the host	7host_inst_rate 594104 # Simulator instruction rate (inst/s) 8host_op_rate 698838 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32027606991 # Simulator tick rate (ticks/s) 10host_mem_usage 752504 # Number of bytes of host memory used 11host_seconds 1483.81 # Real time elapsed on the host
12sim_insts 881535802 # Number of instructions simulated 13sim_ops 1036940641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9313680 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 12080896 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 425472 # Number of bytes read from this memory 28system.physmem.bytes_read::total 56631876 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 3323828 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2499960 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 5823788 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 75221696 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 75242280 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1465 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1507 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 92342 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 215816 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 229901 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 2146 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2116 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 39150 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 145539 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 188764 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6648 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 925394 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1175339 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1177913 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 1973 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2030 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 69942 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 290627 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 309613 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2850 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 52606 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 195984 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 254213 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 8953 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1191679 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 69942 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 52606 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 122547 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1582856 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1583289 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1582856 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 1973 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2030 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 69942 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 291060 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 309613 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2850 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 52606 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 195984 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 254213 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 8953 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2774968 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 925394 # Number of read requests accepted 85system.physmem.writeReqs 1177913 # Number of write requests accepted 86system.physmem.readBursts 925394 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1177913 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 59200512 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 24704 # Total number of bytes read from write queue 90system.physmem.bytesWritten 75241664 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 56631876 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 75242280 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 386 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 52385 # Per bank write bursts 97system.physmem.perBankRdBursts::1 62471 # Per bank write bursts 98system.physmem.perBankRdBursts::2 52469 # Per bank write bursts 99system.physmem.perBankRdBursts::3 57006 # Per bank write bursts 100system.physmem.perBankRdBursts::4 52192 # Per bank write bursts 101system.physmem.perBankRdBursts::5 61065 # Per bank write bursts 102system.physmem.perBankRdBursts::6 52770 # Per bank write bursts 103system.physmem.perBankRdBursts::7 53841 # Per bank write bursts 104system.physmem.perBankRdBursts::8 49119 # Per bank write bursts 105system.physmem.perBankRdBursts::9 95933 # Per bank write bursts 106system.physmem.perBankRdBursts::10 50791 # Per bank write bursts 107system.physmem.perBankRdBursts::11 57135 # Per bank write bursts 108system.physmem.perBankRdBursts::12 57588 # Per bank write bursts 109system.physmem.perBankRdBursts::13 62036 # Per bank write bursts 110system.physmem.perBankRdBursts::14 54549 # Per bank write bursts 111system.physmem.perBankRdBursts::15 53658 # Per bank write bursts 112system.physmem.perBankWrBursts::0 70290 # Per bank write bursts 113system.physmem.perBankWrBursts::1 77699 # Per bank write bursts 114system.physmem.perBankWrBursts::2 70837 # Per bank write bursts 115system.physmem.perBankWrBursts::3 75524 # Per bank write bursts 116system.physmem.perBankWrBursts::4 70767 # Per bank write bursts 117system.physmem.perBankWrBursts::5 75365 # Per bank write bursts 118system.physmem.perBankWrBursts::6 70544 # Per bank write bursts 119system.physmem.perBankWrBursts::7 72537 # Per bank write bursts 120system.physmem.perBankWrBursts::8 71114 # Per bank write bursts 121system.physmem.perBankWrBursts::9 74364 # Per bank write bursts 122system.physmem.perBankWrBursts::10 70757 # Per bank write bursts 123system.physmem.perBankWrBursts::11 75591 # Per bank write bursts 124system.physmem.perBankWrBursts::12 74466 # Per bank write bursts 125system.physmem.perBankWrBursts::13 78806 # Per bank write bursts 126system.physmem.perBankWrBursts::14 73579 # Per bank write bursts 127system.physmem.perBankWrBursts::15 73411 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 43 # Number of times write queue was full causing retry 130system.physmem.totGap 47522767065000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 43195 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 882169 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1175339 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 655692 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 79783 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 38713 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 33532 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28749 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 25275 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 22122 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 17971 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 15915 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 2679 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1375 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 894 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 696 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 480 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 338 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 279 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 203 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 31337 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 39682 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 50193 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 56075 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 61286 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 64392 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 67139 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 68853 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 71615 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 71812 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 75238 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 77530 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 73364 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 73677 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 78266 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 71127 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 65923 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 63783 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 2418 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 1729 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1342 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 671 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 613 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 609 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 401 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 451 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 408 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 398 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 326 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 274 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 325 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 200 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 176 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 108 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 971842 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 138.337154 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 95.235739 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 185.809364 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 667325 68.67% 68.67% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 188611 19.41% 88.07% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 42123 4.33% 92.41% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 19056 1.96% 94.37% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 13469 1.39% 95.75% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 8562 0.88% 96.64% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6056 0.62% 97.26% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5131 0.53% 97.79% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 21509 2.21% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 971842 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 61007 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 15.162244 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 130.580515 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 61004 100.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 61007 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 61007 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 19.270756 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.528593 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 7.773323 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 49057 80.41% 80.41% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 4844 7.94% 88.35% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 2913 4.77% 93.13% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 1752 2.87% 96.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 961 1.58% 97.57% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 299 0.49% 98.06% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 177 0.29% 98.35% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 148 0.24% 98.60% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 74 0.12% 98.72% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 52 0.09% 98.80% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 27 0.04% 98.85% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 55 0.09% 98.94% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 405 0.66% 99.60% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 51 0.08% 99.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 50 0.08% 99.77% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 25 0.04% 99.87% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 4 0.01% 99.88% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 4 0.01% 99.89% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 4 0.01% 99.89% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 4 0.01% 99.90% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 8 0.01% 99.92% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::124-127 2 0.00% 99.92% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::132-135 4 0.01% 99.96% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::148-151 3 0.00% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::total 61007 # Writes before turning the bus around for reads 306system.physmem.totQLat 29196891613 # Total ticks spent queuing 307system.physmem.totMemAccLat 46540791613 # Total ticks spent from burst creation until serviced by the DRAM 308system.physmem.totBusLat 4625040000 # Total ticks spent in databus transfers 309system.physmem.avgQLat 31563.93 # Average queueing delay per DRAM burst 310system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 311system.physmem.avgMemAccLat 50313.93 # Average memory access latency per DRAM burst 312system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 313system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 314system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s 315system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 316system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 317system.physmem.busUtil 0.02 # Data bus utilization in percentage 318system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 319system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 320system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 321system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing 322system.physmem.readRowHits 690198 # Number of row buffer hits during reads 323system.physmem.writeRowHits 438618 # Number of row buffer hits during writes 324system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads 325system.physmem.writeRowHitRate 37.31 # Row buffer hit rate for writes 326system.physmem.avgGap 22594308.42 # Average gap between requests 327system.physmem.pageHitRate 53.74 # Row buffer hit rate, read and write combined 328system.physmem_0.actEnergy 3631876920 # Energy for activate commands per rank (pJ) 329system.physmem_0.preEnergy 1981678875 # Energy for precharge commands per rank (pJ) 330system.physmem_0.readEnergy 3464752200 # Energy for read commands per rank (pJ) 331system.physmem_0.writeEnergy 3781488240 # Energy for write commands per rank (pJ) 332system.physmem_0.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) 333system.physmem_0.actBackEnergy 1186873055955 # Energy for active background per rank (pJ) 334system.physmem_0.preBackEnergy 27472545160500 # Energy for precharge background per rank (pJ) 335system.physmem_0.totalEnergy 31776234305010 # Total energy per rank (pJ) 336system.physmem_0.averagePower 668.652826 # Core power per rank (mW) 337system.physmem_0.memoryStateTime::IDLE 45702691627494 # Time in different power states 338system.physmem_0.memoryStateTime::REF 1586889720000 # Time in different power states 339system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 340system.physmem_0.memoryStateTime::ACT 233188460006 # Time in different power states 341system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 342system.physmem_1.actEnergy 3715248600 # Energy for activate commands per rank (pJ) 343system.physmem_1.preEnergy 2027169375 # Energy for precharge commands per rank (pJ) 344system.physmem_1.readEnergy 3750271200 # Energy for read commands per rank (pJ) 345system.physmem_1.writeEnergy 3836730240 # Energy for write commands per rank (pJ) 346system.physmem_1.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) 347system.physmem_1.actBackEnergy 1194406095015 # Energy for active background per rank (pJ) 348system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) 349system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) 350system.physmem_1.averagePower 668.682174 # Core power per rank (mW) 351system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states 352system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states 353system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 354system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states 355system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 356system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 357system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 360system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 362system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 365system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 366system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 368system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 369system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 370system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 383system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 384system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 385system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 386system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 387system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 388system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 389system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 390system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 391system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 392system.cpu_clk_domain.clock 500 # Clock period in ticks 393system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 403system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 404system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 405system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 406system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 407system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 412system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 413system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 423system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 424system.cpu0.dtb.walker.walks 111522 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting 429system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::0-2047 111497 100.00% 100.00% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::total 111498 # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkCompletionTime::samples 96090 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::0-32767 91679 95.41% 95.41% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3478 3.62% 99.03% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::65536-98303 141 0.15% 99.18% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::98304-131071 658 0.68% 99.86% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.88% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::163840-196607 14 0.01% 99.89% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.03% 99.93% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.02% 99.94% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.96% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::294912-327679 23 0.02% 99.99% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::total 96090 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walksPending::samples 2194735056 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::mean 1.089935 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::0 -197382796 -8.99% -8.99% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::1 2392117852 108.99% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::total 2194735056 # Table walker pending requests distribution 460system.cpu0.dtb.walker.walkPageSizes::4K 84024 87.46% 87.46% # Table walker page sizes translated 461system.cpu0.dtb.walker.walkPageSizes::2M 12043 12.54% 100.00% # Table walker page sizes translated 462system.cpu0.dtb.walker.walkPageSizes::total 96067 # Table walker page sizes translated 463system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111522 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111522 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96067 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96067 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin::total 207589 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.inst_hits 0 # ITB inst hits 471system.cpu0.dtb.inst_misses 0 # ITB inst misses 472system.cpu0.dtb.read_hits 86856517 # DTB read hits 473system.cpu0.dtb.read_misses 84644 # DTB read misses 474system.cpu0.dtb.write_hits 78666499 # DTB write hits 475system.cpu0.dtb.write_misses 26878 # DTB write misses 476system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 477system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 479system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID	12sim_insts 881535802 # Number of instructions simulated 13sim_ops 1036940641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13811400 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 14713664 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 137344 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 135424 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2499960 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9313680 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 12080896 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 425472 # Number of bytes read from this memory 28system.physmem.bytes_read::total 56631876 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 3323828 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2499960 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 5823788 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 75221696 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 75242280 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1465 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1507 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 92342 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 215816 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 229901 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 2146 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2116 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 39150 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 145539 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 188764 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6648 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 925394 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1175339 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1177913 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 1973 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2030 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 69942 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 290627 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 309613 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2850 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 52606 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 195984 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 254213 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 8953 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1191679 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 69942 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 52606 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 122547 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1582856 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1583289 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1582856 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 1973 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2030 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 69942 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 291060 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 309613 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2850 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 52606 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 195984 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 254213 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 8953 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2774968 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 925394 # Number of read requests accepted 85system.physmem.writeReqs 1177913 # Number of write requests accepted 86system.physmem.readBursts 925394 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1177913 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 59200512 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 24704 # Total number of bytes read from write queue 90system.physmem.bytesWritten 75241664 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 56631876 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 75242280 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 386 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 52385 # Per bank write bursts 97system.physmem.perBankRdBursts::1 62471 # Per bank write bursts 98system.physmem.perBankRdBursts::2 52469 # Per bank write bursts 99system.physmem.perBankRdBursts::3 57006 # Per bank write bursts 100system.physmem.perBankRdBursts::4 52192 # Per bank write bursts 101system.physmem.perBankRdBursts::5 61065 # Per bank write bursts 102system.physmem.perBankRdBursts::6 52770 # Per bank write bursts 103system.physmem.perBankRdBursts::7 53841 # Per bank write bursts 104system.physmem.perBankRdBursts::8 49119 # Per bank write bursts 105system.physmem.perBankRdBursts::9 95933 # Per bank write bursts 106system.physmem.perBankRdBursts::10 50791 # Per bank write bursts 107system.physmem.perBankRdBursts::11 57135 # Per bank write bursts 108system.physmem.perBankRdBursts::12 57588 # Per bank write bursts 109system.physmem.perBankRdBursts::13 62036 # Per bank write bursts 110system.physmem.perBankRdBursts::14 54549 # Per bank write bursts 111system.physmem.perBankRdBursts::15 53658 # Per bank write bursts 112system.physmem.perBankWrBursts::0 70290 # Per bank write bursts 113system.physmem.perBankWrBursts::1 77699 # Per bank write bursts 114system.physmem.perBankWrBursts::2 70837 # Per bank write bursts 115system.physmem.perBankWrBursts::3 75524 # Per bank write bursts 116system.physmem.perBankWrBursts::4 70767 # Per bank write bursts 117system.physmem.perBankWrBursts::5 75365 # Per bank write bursts 118system.physmem.perBankWrBursts::6 70544 # Per bank write bursts 119system.physmem.perBankWrBursts::7 72537 # Per bank write bursts 120system.physmem.perBankWrBursts::8 71114 # Per bank write bursts 121system.physmem.perBankWrBursts::9 74364 # Per bank write bursts 122system.physmem.perBankWrBursts::10 70757 # Per bank write bursts 123system.physmem.perBankWrBursts::11 75591 # Per bank write bursts 124system.physmem.perBankWrBursts::12 74466 # Per bank write bursts 125system.physmem.perBankWrBursts::13 78806 # Per bank write bursts 126system.physmem.perBankWrBursts::14 73579 # Per bank write bursts 127system.physmem.perBankWrBursts::15 73411 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 43 # Number of times write queue was full causing retry 130system.physmem.totGap 47522767065000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 43195 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 882169 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1175339 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 655692 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 79783 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 38713 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 33532 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28749 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 25275 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 22122 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 17971 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 15915 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 2679 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1375 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 894 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 696 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 480 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 338 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 279 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 203 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 31337 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 39682 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 50193 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 56075 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 61286 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 64392 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 67139 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 68853 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 71615 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 71812 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 75238 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 77530 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 73364 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 73677 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 78266 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 71127 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 65923 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 63783 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 2418 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 1729 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1342 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 671 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 613 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 609 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 401 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 451 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 408 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 398 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 326 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 274 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 325 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 200 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 212 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 176 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 176 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 108 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 971842 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 138.337154 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 95.235739 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 185.809364 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 667325 68.67% 68.67% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 188611 19.41% 88.07% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 42123 4.33% 92.41% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 19056 1.96% 94.37% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 13469 1.39% 95.75% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 8562 0.88% 96.64% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6056 0.62% 97.26% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5131 0.53% 97.79% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 21509 2.21% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 971842 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 61007 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 15.162244 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 130.580515 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 61004 100.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 61007 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 61007 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 19.270756 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.528593 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 7.773323 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 49057 80.41% 80.41% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 4844 7.94% 88.35% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 2913 4.77% 93.13% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 1752 2.87% 96.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 961 1.58% 97.57% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 299 0.49% 98.06% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 177 0.29% 98.35% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 148 0.24% 98.60% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 74 0.12% 98.72% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 52 0.09% 98.80% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 27 0.04% 98.85% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 55 0.09% 98.94% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 405 0.66% 99.60% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 51 0.08% 99.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 50 0.08% 99.77% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 25 0.04% 99.87% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 4 0.01% 99.88% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 4 0.01% 99.89% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 4 0.01% 99.89% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 4 0.01% 99.90% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 8 0.01% 99.92% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::124-127 2 0.00% 99.92% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::132-135 4 0.01% 99.96% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 1 0.00% 99.97% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::148-151 3 0.00% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::total 61007 # Writes before turning the bus around for reads 306system.physmem.totQLat 29196891613 # Total ticks spent queuing 307system.physmem.totMemAccLat 46540791613 # Total ticks spent from burst creation until serviced by the DRAM 308system.physmem.totBusLat 4625040000 # Total ticks spent in databus transfers 309system.physmem.avgQLat 31563.93 # Average queueing delay per DRAM burst 310system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 311system.physmem.avgMemAccLat 50313.93 # Average memory access latency per DRAM burst 312system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 313system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 314system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s 315system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 316system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 317system.physmem.busUtil 0.02 # Data bus utilization in percentage 318system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 319system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 320system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 321system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing 322system.physmem.readRowHits 690198 # Number of row buffer hits during reads 323system.physmem.writeRowHits 438618 # Number of row buffer hits during writes 324system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads 325system.physmem.writeRowHitRate 37.31 # Row buffer hit rate for writes 326system.physmem.avgGap 22594308.42 # Average gap between requests 327system.physmem.pageHitRate 53.74 # Row buffer hit rate, read and write combined 328system.physmem_0.actEnergy 3631876920 # Energy for activate commands per rank (pJ) 329system.physmem_0.preEnergy 1981678875 # Energy for precharge commands per rank (pJ) 330system.physmem_0.readEnergy 3464752200 # Energy for read commands per rank (pJ) 331system.physmem_0.writeEnergy 3781488240 # Energy for write commands per rank (pJ) 332system.physmem_0.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) 333system.physmem_0.actBackEnergy 1186873055955 # Energy for active background per rank (pJ) 334system.physmem_0.preBackEnergy 27472545160500 # Energy for precharge background per rank (pJ) 335system.physmem_0.totalEnergy 31776234305010 # Total energy per rank (pJ) 336system.physmem_0.averagePower 668.652826 # Core power per rank (mW) 337system.physmem_0.memoryStateTime::IDLE 45702691627494 # Time in different power states 338system.physmem_0.memoryStateTime::REF 1586889720000 # Time in different power states 339system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 340system.physmem_0.memoryStateTime::ACT 233188460006 # Time in different power states 341system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 342system.physmem_1.actEnergy 3715248600 # Energy for activate commands per rank (pJ) 343system.physmem_1.preEnergy 2027169375 # Energy for precharge commands per rank (pJ) 344system.physmem_1.readEnergy 3750271200 # Energy for read commands per rank (pJ) 345system.physmem_1.writeEnergy 3836730240 # Energy for write commands per rank (pJ) 346system.physmem_1.refreshEnergy 3103956292320 # Energy for refresh commands per rank (pJ) 347system.physmem_1.actBackEnergy 1194406095015 # Energy for active background per rank (pJ) 348system.physmem_1.preBackEnergy 27465937231500 # Energy for precharge background per rank (pJ) 349system.physmem_1.totalEnergy 31777629038250 # Total energy per rank (pJ) 350system.physmem_1.averagePower 668.682174 # Core power per rank (mW) 351system.physmem_1.memoryStateTime::IDLE 45691606890492 # Time in different power states 352system.physmem_1.memoryStateTime::REF 1586889720000 # Time in different power states 353system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 354system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states 355system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 356system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 357system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 360system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 362system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 365system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 366system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 368system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 369system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 370system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 383system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 384system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 385system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 386system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 387system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 388system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 389system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 390system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 391system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 392system.cpu_clk_domain.clock 500 # Clock period in ticks 393system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 403system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 404system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 405system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 406system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 407system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 410system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 412system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 413system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 423system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 424system.cpu0.dtb.walker.walks 111522 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84023 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting 429system.cpu0.dtb.walker.walkWaitTime::samples 111498 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::mean 0.224219 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::stdev 74.869765 # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::0-2047 111497 100.00% 100.00% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::total 111498 # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkCompletionTime::samples 96090 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::mean 22204.527006 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::gmean 20954.891968 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::stdev 12694.708371 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::0-32767 91679 95.41% 95.41% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3478 3.62% 99.03% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::65536-98303 141 0.15% 99.18% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::98304-131071 658 0.68% 99.86% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.88% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::163840-196607 14 0.01% 99.89% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.03% 99.93% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.02% 99.94% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.96% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::294912-327679 23 0.02% 99.99% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::total 96090 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walksPending::samples 2194735056 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::mean 1.089935 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::0 -197382796 -8.99% -8.99% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::1 2392117852 108.99% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::total 2194735056 # Table walker pending requests distribution 460system.cpu0.dtb.walker.walkPageSizes::4K 84024 87.46% 87.46% # Table walker page sizes translated 461system.cpu0.dtb.walker.walkPageSizes::2M 12043 12.54% 100.00% # Table walker page sizes translated 462system.cpu0.dtb.walker.walkPageSizes::total 96067 # Table walker page sizes translated 463system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111522 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111522 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96067 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96067 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin::total 207589 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.inst_hits 0 # ITB inst hits 471system.cpu0.dtb.inst_misses 0 # ITB inst misses 472system.cpu0.dtb.read_hits 86856517 # DTB read hits 473system.cpu0.dtb.read_misses 84644 # DTB read misses 474system.cpu0.dtb.write_hits 78666499 # DTB write hits 475system.cpu0.dtb.write_misses 26878 # DTB write misses 476system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 477system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 478system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 479system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
480system.cpu0.dtb.flush_entries 37476 # Number of entries that have been flushed from TLB	480system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB
481system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 482system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch 483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions 485system.cpu0.dtb.read_accesses 86941161 # DTB read accesses 486system.cpu0.dtb.write_accesses 78693377 # DTB write accesses 487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 488system.cpu0.dtb.hits 165523016 # DTB hits 489system.cpu0.dtb.misses 111522 # DTB misses 490system.cpu0.dtb.accesses 165634538 # DTB accesses 491system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 492system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 501system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 502system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 503system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 504system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 505system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 506system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 507system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 508system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 510system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 511system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 512system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 513system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 514system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 515system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 516system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 517system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 518system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 519system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 520system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 521system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 522system.cpu0.itb.walker.walks 57441 # Table walker walks requested 523system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors 524system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate 525system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate 526system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377 # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517 # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::0-65535 50947 98.14% 98.14% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::65536-131071 829 1.60% 99.74% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::131072-196607 33 0.06% 99.80% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.89% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::262144-327679 45 0.09% 99.98% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::total 51913 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution 544system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution 545system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution 546system.cpu0.itb.walker.walkPageSizes::4K 51280 98.78% 98.78% # Table walker page sizes translated 547system.cpu0.itb.walker.walkPageSizes::2M 633 1.22% 100.00% # Table walker page sizes translated 548system.cpu0.itb.walker.walkPageSizes::total 51913 # Table walker page sizes translated 549system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57441 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57441 # Table walker requests started/completed, data/inst 552system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 553system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51913 # Table walker requests started/completed, data/inst 554system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51913 # Table walker requests started/completed, data/inst 555system.cpu0.itb.walker.walkRequestOrigin::total 109354 # Table walker requests started/completed, data/inst 556system.cpu0.itb.inst_hits 461199865 # ITB inst hits 557system.cpu0.itb.inst_misses 57441 # ITB inst misses 558system.cpu0.itb.read_hits 0 # DTB read hits 559system.cpu0.itb.read_misses 0 # DTB read misses 560system.cpu0.itb.write_hits 0 # DTB write hits 561system.cpu0.itb.write_misses 0 # DTB write misses 562system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 563system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 564system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 565system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID	481system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 482system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch 483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu0.dtb.perms_faults 9143 # Number of TLB faults due to permissions restrictions 485system.cpu0.dtb.read_accesses 86941161 # DTB read accesses 486system.cpu0.dtb.write_accesses 78693377 # DTB write accesses 487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 488system.cpu0.dtb.hits 165523016 # DTB hits 489system.cpu0.dtb.misses 111522 # DTB misses 490system.cpu0.dtb.accesses 165634538 # DTB accesses 491system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 492system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 501system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 502system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 503system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 504system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 505system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 506system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 507system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 508system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 510system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 511system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 512system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 513system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 514system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 515system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 516system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 517system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 518system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 519system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 520system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 521system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 522system.cpu0.itb.walker.walks 57441 # Table walker walks requested 523system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors 524system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate 525system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51280 # Level at which table walker walks with long descriptors terminate 526system.cpu0.itb.walker.walkWaitTime::samples 57441 # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::0 57441 100.00% 100.00% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::total 57441 # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkCompletionTime::samples 51913 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::mean 24992.593377 # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::gmean 23133.831517 # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::stdev 17289.167601 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::0-65535 50947 98.14% 98.14% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::65536-131071 829 1.60% 99.74% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::131072-196607 33 0.06% 99.80% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.89% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::262144-327679 45 0.09% 99.98% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::total 51913 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution 544system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution 545system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution 546system.cpu0.itb.walker.walkPageSizes::4K 51280 98.78% 98.78% # Table walker page sizes translated 547system.cpu0.itb.walker.walkPageSizes::2M 633 1.22% 100.00% # Table walker page sizes translated 548system.cpu0.itb.walker.walkPageSizes::total 51913 # Table walker page sizes translated 549system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57441 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57441 # Table walker requests started/completed, data/inst 552system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 553system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51913 # Table walker requests started/completed, data/inst 554system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51913 # Table walker requests started/completed, data/inst 555system.cpu0.itb.walker.walkRequestOrigin::total 109354 # Table walker requests started/completed, data/inst 556system.cpu0.itb.inst_hits 461199865 # ITB inst hits 557system.cpu0.itb.inst_misses 57441 # ITB inst misses 558system.cpu0.itb.read_hits 0 # DTB read hits 559system.cpu0.itb.read_misses 0 # DTB read misses 560system.cpu0.itb.write_hits 0 # DTB write hits 561system.cpu0.itb.write_misses 0 # DTB write misses 562system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 563system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 564system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 565system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
566system.cpu0.itb.flush_entries 26626 # Number of entries that have been flushed from TLB	566system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB
567system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 568system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 569system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 570system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 571system.cpu0.itb.read_accesses 0 # DTB read accesses 572system.cpu0.itb.write_accesses 0 # DTB write accesses 573system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses 574system.cpu0.itb.hits 461199865 # DTB hits 575system.cpu0.itb.misses 57441 # DTB misses 576system.cpu0.itb.accesses 461257306 # DTB accesses 577system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions 578system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state 579system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state 580system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state 581system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state 582system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state 583system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state 584system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state 585system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state 586system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 587system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 588system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 589system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states 597system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states 598system.cpu0.numCycles 95045540829 # number of cpu cycles simulated 599system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 600system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 601system.cpu0.kern.inst.arm 0 # number of arm instructions executed 602system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed 603system.cpu0.committedInsts 460929213 # Number of instructions committed 604system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed 605system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses 606system.cpu0.num_fp_alu_accesses 434558 # Number of float alu accesses 607system.cpu0.num_func_calls 27781850 # number of times a function call or return occured 608system.cpu0.num_conditional_control_insts 69589132 # number of instructions that are conditional controls 609system.cpu0.num_int_insts 497492129 # number of integer instructions 610system.cpu0.num_fp_insts 434558 # number of float instructions 611system.cpu0.num_int_register_reads 719293830 # number of times the integer registers were read 612system.cpu0.num_int_register_writes 394367415 # number of times the integer registers were written 613system.cpu0.num_fp_register_reads 718787 # number of times the floating registers were read 614system.cpu0.num_fp_register_writes 331792 # number of times the floating registers were written 615system.cpu0.num_cc_register_reads 119457726 # number of times the CC registers were read 616system.cpu0.num_cc_register_writes 119087316 # number of times the CC registers were written 617system.cpu0.num_mem_refs 165514046 # number of memory refs 618system.cpu0.num_load_insts 86852092 # Number of load instructions 619system.cpu0.num_store_insts 78661954 # Number of store instructions 620system.cpu0.num_idle_cycles 93905101360.384018 # Number of idle cycles 621system.cpu0.num_busy_cycles 1140439468.615976 # Number of busy cycles 622system.cpu0.not_idle_fraction 0.011999 # Percentage of non-idle cycles 623system.cpu0.idle_fraction 0.988001 # Percentage of idle cycles 624system.cpu0.Branches 102755128 # Number of branches fetched 625system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 626system.cpu0.op_class::IntAlu 374676211 69.19% 69.19% # Class of executed instruction 627system.cpu0.op_class::IntMult 1194745 0.22% 69.41% # Class of executed instruction 628system.cpu0.op_class::IntDiv 63344 0.01% 69.43% # Class of executed instruction 629system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 630system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 631system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 632system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 633system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 634system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 635system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 636system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 637system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 638system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 639system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 640system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 641system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 642system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 643system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 644system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 645system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 646system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction 647system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 648system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction 649system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction 650system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 651system.cpu0.op_class::SimdFloatMisc 45411 0.01% 69.43% # Class of executed instruction 652system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction 653system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction 654system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction 655system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction 656system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction 657system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 658system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 659system.cpu0.op_class::total 541493758 # Class of executed instruction 660system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 661system.cpu0.dcache.tags.replacements 5689621 # number of replacements 662system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use 663system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. 664system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. 665system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. 666system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. 667system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor 668system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy 669system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy 670system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 671system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 672system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id 673system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id 674system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 675system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses 676system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses 677system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 678system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits 679system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits 680system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits 681system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits 682system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits 683system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits 684system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits 685system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits 686system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1824290 # number of LoadLockedReq hits 687system.cpu0.dcache.LoadLockedReq_hits::total 1824290 # number of LoadLockedReq hits 688system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1791894 # number of StoreCondReq hits 689system.cpu0.dcache.StoreCondReq_hits::total 1791894 # number of StoreCondReq hits 690system.cpu0.dcache.demand_hits::cpu0.data 155334822 # number of demand (read+write) hits 691system.cpu0.dcache.demand_hits::total 155334822 # number of demand (read+write) hits 692system.cpu0.dcache.overall_hits::cpu0.data 155534211 # number of overall hits 693system.cpu0.dcache.overall_hits::total 155534211 # number of overall hits 694system.cpu0.dcache.ReadReq_misses::cpu0.data 3104051 # number of ReadReq misses 695system.cpu0.dcache.ReadReq_misses::total 3104051 # number of ReadReq misses 696system.cpu0.dcache.WriteReq_misses::cpu0.data 1401631 # number of WriteReq misses 697system.cpu0.dcache.WriteReq_misses::total 1401631 # number of WriteReq misses 698system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634089 # number of SoftPFReq misses 699system.cpu0.dcache.SoftPFReq_misses::total 634089 # number of SoftPFReq misses 700system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792659 # number of WriteLineReq misses 701system.cpu0.dcache.WriteLineReq_misses::total 792659 # number of WriteLineReq misses 702system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174131 # number of LoadLockedReq misses 703system.cpu0.dcache.LoadLockedReq_misses::total 174131 # number of LoadLockedReq misses 704system.cpu0.dcache.StoreCondReq_misses::cpu0.data 205146 # number of StoreCondReq misses 705system.cpu0.dcache.StoreCondReq_misses::total 205146 # number of StoreCondReq misses 706system.cpu0.dcache.demand_misses::cpu0.data 5298341 # number of demand (read+write) misses 707system.cpu0.dcache.demand_misses::total 5298341 # number of demand (read+write) misses 708system.cpu0.dcache.overall_misses::cpu0.data 5932430 # number of overall misses 709system.cpu0.dcache.overall_misses::total 5932430 # number of overall misses 710system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46355544000 # number of ReadReq miss cycles 711system.cpu0.dcache.ReadReq_miss_latency::total 46355544000 # number of ReadReq miss cycles 712system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29179707500 # number of WriteReq miss cycles 713system.cpu0.dcache.WriteReq_miss_latency::total 29179707500 # number of WriteReq miss cycles 714system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25804948000 # number of WriteLineReq miss cycles 715system.cpu0.dcache.WriteLineReq_miss_latency::total 25804948000 # number of WriteLineReq miss cycles 716system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2634324500 # number of LoadLockedReq miss cycles 717system.cpu0.dcache.LoadLockedReq_miss_latency::total 2634324500 # number of LoadLockedReq miss cycles 718system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5093103500 # number of StoreCondReq miss cycles 719system.cpu0.dcache.StoreCondReq_miss_latency::total 5093103500 # number of StoreCondReq miss cycles 720system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3129500 # number of StoreCondFailReq miss cycles 721system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3129500 # number of StoreCondFailReq miss cycles 722system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500 # number of demand (read+write) miss cycles 723system.cpu0.dcache.demand_miss_latency::total 101340199500 # number of demand (read+write) miss cycles 724system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500 # number of overall miss cycles 725system.cpu0.dcache.overall_miss_latency::total 101340199500 # number of overall miss cycles 726system.cpu0.dcache.ReadReq_accesses::cpu0.data 83997021 # number of ReadReq accesses(hits+misses) 727system.cpu0.dcache.ReadReq_accesses::total 83997021 # number of ReadReq accesses(hits+misses) 728system.cpu0.dcache.WriteReq_accesses::cpu0.data 75681254 # number of WriteReq accesses(hits+misses) 729system.cpu0.dcache.WriteReq_accesses::total 75681254 # number of WriteReq accesses(hits+misses) 730system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 833478 # number of SoftPFReq accesses(hits+misses) 731system.cpu0.dcache.SoftPFReq_accesses::total 833478 # number of SoftPFReq accesses(hits+misses) 732system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954888 # number of WriteLineReq accesses(hits+misses) 733system.cpu0.dcache.WriteLineReq_accesses::total 954888 # number of WriteLineReq accesses(hits+misses) 734system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998421 # number of LoadLockedReq accesses(hits+misses) 735system.cpu0.dcache.LoadLockedReq_accesses::total 1998421 # number of LoadLockedReq accesses(hits+misses) 736system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1997040 # number of StoreCondReq accesses(hits+misses) 737system.cpu0.dcache.StoreCondReq_accesses::total 1997040 # number of StoreCondReq accesses(hits+misses) 738system.cpu0.dcache.demand_accesses::cpu0.data 160633163 # number of demand (read+write) accesses 739system.cpu0.dcache.demand_accesses::total 160633163 # number of demand (read+write) accesses 740system.cpu0.dcache.overall_accesses::cpu0.data 161466641 # number of overall (read+write) accesses 741system.cpu0.dcache.overall_accesses::total 161466641 # number of overall (read+write) accesses 742system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036954 # miss rate for ReadReq accesses 743system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses 744system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018520 # miss rate for WriteReq accesses 745system.cpu0.dcache.WriteReq_miss_rate::total 0.018520 # miss rate for WriteReq accesses 746system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760775 # miss rate for SoftPFReq accesses 747system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760775 # miss rate for SoftPFReq accesses 748system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.830107 # miss rate for WriteLineReq accesses 749system.cpu0.dcache.WriteLineReq_miss_rate::total 0.830107 # miss rate for WriteLineReq accesses 750system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087134 # miss rate for LoadLockedReq accesses 751system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087134 # miss rate for LoadLockedReq accesses 752system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102725 # miss rate for StoreCondReq accesses 753system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102725 # miss rate for StoreCondReq accesses 754system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032984 # miss rate for demand accesses 755system.cpu0.dcache.demand_miss_rate::total 0.032984 # miss rate for demand accesses 756system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036741 # miss rate for overall accesses 757system.cpu0.dcache.overall_miss_rate::total 0.036741 # miss rate for overall accesses 758system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073 # average ReadReq miss latency 759system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073 # average ReadReq miss latency 760system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784 # average WriteReq miss latency 761system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784 # average WriteReq miss latency 762system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058 # average WriteLineReq miss latency 763system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058 # average WriteLineReq miss latency 764system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200 # average LoadLockedReq miss latency 765system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200 # average LoadLockedReq miss latency 766system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844 # average StoreCondReq miss latency 767system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844 # average StoreCondReq miss latency 768system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 769system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 770system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401 # average overall miss latency 771system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401 # average overall miss latency 772system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653 # average overall miss latency 773system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653 # average overall miss latency 774system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 775system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 776system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 777system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 778system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 779system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 780system.cpu0.dcache.writebacks::writebacks 5689621 # number of writebacks 781system.cpu0.dcache.writebacks::total 5689621 # number of writebacks 782system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25484 # number of ReadReq MSHR hits 783system.cpu0.dcache.ReadReq_mshr_hits::total 25484 # number of ReadReq MSHR hits 784system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21272 # number of WriteReq MSHR hits 785system.cpu0.dcache.WriteReq_mshr_hits::total 21272 # number of WriteReq MSHR hits 786system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45280 # number of LoadLockedReq MSHR hits 787system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45280 # number of LoadLockedReq MSHR hits 788system.cpu0.dcache.demand_mshr_hits::cpu0.data 46756 # number of demand (read+write) MSHR hits 789system.cpu0.dcache.demand_mshr_hits::total 46756 # number of demand (read+write) MSHR hits 790system.cpu0.dcache.overall_mshr_hits::cpu0.data 46756 # number of overall MSHR hits 791system.cpu0.dcache.overall_mshr_hits::total 46756 # number of overall MSHR hits 792system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3078567 # number of ReadReq MSHR misses 793system.cpu0.dcache.ReadReq_mshr_misses::total 3078567 # number of ReadReq MSHR misses 794system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380359 # number of WriteReq MSHR misses 795system.cpu0.dcache.WriteReq_mshr_misses::total 1380359 # number of WriteReq MSHR misses 796system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 632927 # number of SoftPFReq MSHR misses 797system.cpu0.dcache.SoftPFReq_mshr_misses::total 632927 # number of SoftPFReq MSHR misses 798system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792659 # number of WriteLineReq MSHR misses 799system.cpu0.dcache.WriteLineReq_mshr_misses::total 792659 # number of WriteLineReq MSHR misses 800system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128851 # number of LoadLockedReq MSHR misses 801system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128851 # number of LoadLockedReq MSHR misses 802system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 205146 # number of StoreCondReq MSHR misses 803system.cpu0.dcache.StoreCondReq_mshr_misses::total 205146 # number of StoreCondReq MSHR misses 804system.cpu0.dcache.demand_mshr_misses::cpu0.data 5251585 # number of demand (read+write) MSHR misses 805system.cpu0.dcache.demand_mshr_misses::total 5251585 # number of demand (read+write) MSHR misses 806system.cpu0.dcache.overall_mshr_misses::cpu0.data 5884512 # number of overall MSHR misses 807system.cpu0.dcache.overall_mshr_misses::total 5884512 # number of overall MSHR misses 808system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable 809system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27617 # number of ReadReq MSHR uncacheable 810system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable 811system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable 812system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses 813system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54182 # number of overall MSHR uncacheable misses 814system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42188847000 # number of ReadReq MSHR miss cycles 815system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42188847000 # number of ReadReq MSHR miss cycles 816system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27459987000 # number of WriteReq MSHR miss cycles 817system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27459987000 # number of WriteReq MSHR miss cycles 818system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13648405000 # number of SoftPFReq MSHR miss cycles 819system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13648405000 # number of SoftPFReq MSHR miss cycles 820system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25012289000 # number of WriteLineReq MSHR miss cycles 821system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25012289000 # number of WriteLineReq MSHR miss cycles 822system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1718421000 # number of LoadLockedReq MSHR miss cycles 823system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1718421000 # number of LoadLockedReq MSHR miss cycles 824system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4888014500 # number of StoreCondReq MSHR miss cycles 825system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4888014500 # number of StoreCondReq MSHR miss cycles 826system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3072500 # number of StoreCondFailReq MSHR miss cycles 827system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3072500 # number of StoreCondFailReq MSHR miss cycles 828system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94661123000 # number of demand (read+write) MSHR miss cycles 829system.cpu0.dcache.demand_mshr_miss_latency::total 94661123000 # number of demand (read+write) MSHR miss cycles 830system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000 # number of overall MSHR miss cycles 831system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000 # number of overall MSHR miss cycles 832system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5072174500 # number of ReadReq MSHR uncacheable cycles 833system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5072174500 # number of ReadReq MSHR uncacheable cycles 834system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5072174500 # number of overall MSHR uncacheable cycles 835system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5072174500 # number of overall MSHR uncacheable cycles 836system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036651 # mshr miss rate for ReadReq accesses 837system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036651 # mshr miss rate for ReadReq accesses 838system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for WriteReq accesses 839system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018239 # mshr miss rate for WriteReq accesses 840system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759381 # mshr miss rate for SoftPFReq accesses 841system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759381 # mshr miss rate for SoftPFReq accesses 842system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830107 # mshr miss rate for WriteLineReq accesses 843system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830107 # mshr miss rate for WriteLineReq accesses 844system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064476 # mshr miss rate for LoadLockedReq accesses 845system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064476 # mshr miss rate for LoadLockedReq accesses 846system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102725 # mshr miss rate for StoreCondReq accesses 847system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102725 # mshr miss rate for StoreCondReq accesses 848system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032693 # mshr miss rate for demand accesses 849system.cpu0.dcache.demand_mshr_miss_rate::total 0.032693 # mshr miss rate for demand accesses 850system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036444 # mshr miss rate for overall accesses 851system.cpu0.dcache.overall_mshr_miss_rate::total 0.036444 # mshr miss rate for overall accesses 852system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542 # average ReadReq mshr miss latency 853system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542 # average ReadReq mshr miss latency 854system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146 # average WriteReq mshr miss latency 855system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146 # average WriteReq mshr miss latency 856system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133 # average SoftPFReq mshr miss latency 857system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133 # average SoftPFReq mshr miss latency 858system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058 # average WriteLineReq mshr miss latency 859system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058 # average WriteLineReq mshr miss latency 860system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194 # average LoadLockedReq mshr miss latency 861system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194 # average LoadLockedReq mshr miss latency 862system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695 # average StoreCondReq mshr miss latency 863system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695 # average StoreCondReq mshr miss latency 864system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 865system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 866system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency 867system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency 868system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency 869system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency 870system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency 871system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency 872system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency 873system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency 874system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 875system.cpu0.icache.tags.replacements 5142905 # number of replacements 876system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use 877system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. 878system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. 879system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. 880system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. 881system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor 882system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy 883system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy 884system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 885system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 886system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 887system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id 888system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 889system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 890system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses 891system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses 892system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 893system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits 894system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits 895system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits 896system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits 897system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits 898system.cpu0.icache.overall_hits::total 456056448 # number of overall hits 899system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses 900system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses 901system.cpu0.icache.demand_misses::cpu0.inst 5143417 # number of demand (read+write) misses 902system.cpu0.icache.demand_misses::total 5143417 # number of demand (read+write) misses 903system.cpu0.icache.overall_misses::cpu0.inst 5143417 # number of overall misses 904system.cpu0.icache.overall_misses::total 5143417 # number of overall misses 905system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54463305000 # number of ReadReq miss cycles 906system.cpu0.icache.ReadReq_miss_latency::total 54463305000 # number of ReadReq miss cycles 907system.cpu0.icache.demand_miss_latency::cpu0.inst 54463305000 # number of demand (read+write) miss cycles 908system.cpu0.icache.demand_miss_latency::total 54463305000 # number of demand (read+write) miss cycles 909system.cpu0.icache.overall_miss_latency::cpu0.inst 54463305000 # number of overall miss cycles 910system.cpu0.icache.overall_miss_latency::total 54463305000 # number of overall miss cycles 911system.cpu0.icache.ReadReq_accesses::cpu0.inst 461199865 # number of ReadReq accesses(hits+misses) 912system.cpu0.icache.ReadReq_accesses::total 461199865 # number of ReadReq accesses(hits+misses) 913system.cpu0.icache.demand_accesses::cpu0.inst 461199865 # number of demand (read+write) accesses 914system.cpu0.icache.demand_accesses::total 461199865 # number of demand (read+write) accesses 915system.cpu0.icache.overall_accesses::cpu0.inst 461199865 # number of overall (read+write) accesses 916system.cpu0.icache.overall_accesses::total 461199865 # number of overall (read+write) accesses 917system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011152 # miss rate for ReadReq accesses 918system.cpu0.icache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses 919system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011152 # miss rate for demand accesses 920system.cpu0.icache.demand_miss_rate::total 0.011152 # miss rate for demand accesses 921system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011152 # miss rate for overall accesses 922system.cpu0.icache.overall_miss_rate::total 0.011152 # miss rate for overall accesses 923system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360 # average ReadReq miss latency 924system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360 # average ReadReq miss latency 925system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency 926system.cpu0.icache.demand_avg_miss_latency::total 10588.934360 # average overall miss latency 927system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency 928system.cpu0.icache.overall_avg_miss_latency::total 10588.934360 # average overall miss latency 929system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 930system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 931system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 932system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 933system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 934system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 935system.cpu0.icache.writebacks::writebacks 5142905 # number of writebacks 936system.cpu0.icache.writebacks::total 5142905 # number of writebacks 937system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5143417 # number of ReadReq MSHR misses 938system.cpu0.icache.ReadReq_mshr_misses::total 5143417 # number of ReadReq MSHR misses 939system.cpu0.icache.demand_mshr_misses::cpu0.inst 5143417 # number of demand (read+write) MSHR misses 940system.cpu0.icache.demand_mshr_misses::total 5143417 # number of demand (read+write) MSHR misses 941system.cpu0.icache.overall_mshr_misses::cpu0.inst 5143417 # number of overall MSHR misses 942system.cpu0.icache.overall_mshr_misses::total 5143417 # number of overall MSHR misses 943system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 944system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 945system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 946system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 947system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51891596500 # number of ReadReq MSHR miss cycles 948system.cpu0.icache.ReadReq_mshr_miss_latency::total 51891596500 # number of ReadReq MSHR miss cycles 949system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51891596500 # number of demand (read+write) MSHR miss cycles 950system.cpu0.icache.demand_mshr_miss_latency::total 51891596500 # number of demand (read+write) MSHR miss cycles 951system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51891596500 # number of overall MSHR miss cycles 952system.cpu0.icache.overall_mshr_miss_latency::total 51891596500 # number of overall MSHR miss cycles 953system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles 954system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles 955system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles 956system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles 957system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for ReadReq accesses 958system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011152 # mshr miss rate for ReadReq accesses 959system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for demand accesses 960system.cpu0.icache.demand_mshr_miss_rate::total 0.011152 # mshr miss rate for demand accesses 961system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for overall accesses 962system.cpu0.icache.overall_mshr_miss_rate::total 0.011152 # mshr miss rate for overall accesses 963system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average ReadReq mshr miss latency 964system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10088.934360 # average ReadReq mshr miss latency 965system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 966system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 967system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 968system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 969system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency 970system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency 971system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency 972system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency 973system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 974system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued 975system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified 976system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 977system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 978system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 979system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing 980system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 981system.cpu0.l2cache.tags.replacements 2348165 # number of replacements 982system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use 983system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks. 984system.cpu0.l2cache.tags.sampled_refs 2364235 # Sample count of references to valid blocks. 985system.cpu0.l2cache.tags.avg_refs 6.485817 # Average number of references to valid blocks. 986system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. 987system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915 # Average occupied blocks per requestor 988system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.858641 # Average occupied blocks per requestor 989system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.489283 # Average occupied blocks per requestor 990system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 784.884937 # Average occupied blocks per requestor 991system.cpu0.l2cache.tags.occ_percent::writebacks 0.928250 # Average percentage of cache occupancy 992system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003776 # Average percentage of cache occupancy 993system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004852 # Average percentage of cache occupancy 994system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047906 # Average percentage of cache occupancy 995system.cpu0.l2cache.tags.occ_percent::total 0.984783 # Average percentage of cache occupancy 996system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id 997system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 998system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14708 # Occupied blocks per task id 999system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 1000system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 179 # Occupied blocks per task id 1001system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 589 # Occupied blocks per task id 1002system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 529 # Occupied blocks per task id 1003system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id 1004system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id 1005system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 1006system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id 1011system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id 1012system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 1013system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id 1014system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses 1015system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses 1016system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1017system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits 1018system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits 1019system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits 1020system.cpu0.l2cache.WritebackDirty_hits::writebacks 3764500 # number of WritebackDirty hits 1021system.cpu0.l2cache.WritebackDirty_hits::total 3764500 # number of WritebackDirty hits 1022system.cpu0.l2cache.WritebackClean_hits::writebacks 7067152 # number of WritebackClean hits 1023system.cpu0.l2cache.WritebackClean_hits::total 7067152 # number of WritebackClean hits 1024system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 393 # number of UpgradeReq hits 1025system.cpu0.l2cache.UpgradeReq_hits::total 393 # number of UpgradeReq hits 1026system.cpu0.l2cache.ReadExReq_hits::cpu0.data 904509 # number of ReadExReq hits 1027system.cpu0.l2cache.ReadExReq_hits::total 904509 # number of ReadExReq hits 1028system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4682717 # number of ReadCleanReq hits 1029system.cpu0.l2cache.ReadCleanReq_hits::total 4682717 # number of ReadCleanReq hits 1030system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2902504 # number of ReadSharedReq hits 1031system.cpu0.l2cache.ReadSharedReq_hits::total 2902504 # number of ReadSharedReq hits 1032system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213097 # number of InvalidateReq hits 1033system.cpu0.l2cache.InvalidateReq_hits::total 213097 # number of InvalidateReq hits 1034system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 263860 # number of demand (read+write) hits 1035system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148030 # number of demand (read+write) hits 1036system.cpu0.l2cache.demand_hits::cpu0.inst 4682717 # number of demand (read+write) hits 1037system.cpu0.l2cache.demand_hits::cpu0.data 3807013 # number of demand (read+write) hits 1038system.cpu0.l2cache.demand_hits::total 8901620 # number of demand (read+write) hits 1039system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 263860 # number of overall hits 1040system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148030 # number of overall hits 1041system.cpu0.l2cache.overall_hits::cpu0.inst 4682717 # number of overall hits 1042system.cpu0.l2cache.overall_hits::cpu0.data 3807013 # number of overall hits 1043system.cpu0.l2cache.overall_hits::total 8901620 # number of overall hits 1044system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9421 # number of ReadReq misses 1045system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7390 # number of ReadReq misses 1046system.cpu0.l2cache.ReadReq_misses::total 16811 # number of ReadReq misses 1047system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 243749 # number of UpgradeReq misses 1048system.cpu0.l2cache.UpgradeReq_misses::total 243749 # number of UpgradeReq misses 1049system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 205138 # number of SCUpgradeReq misses 1050system.cpu0.l2cache.SCUpgradeReq_misses::total 205138 # number of SCUpgradeReq misses 1051system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 1052system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 1053system.cpu0.l2cache.ReadExReq_misses::cpu0.data 251209 # number of ReadExReq misses 1054system.cpu0.l2cache.ReadExReq_misses::total 251209 # number of ReadExReq misses 1055system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 460700 # number of ReadCleanReq misses 1056system.cpu0.l2cache.ReadCleanReq_misses::total 460700 # number of ReadCleanReq misses 1057system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 937841 # number of ReadSharedReq misses 1058system.cpu0.l2cache.ReadSharedReq_misses::total 937841 # number of ReadSharedReq misses 1059system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577609 # number of InvalidateReq misses 1060system.cpu0.l2cache.InvalidateReq_misses::total 577609 # number of InvalidateReq misses 1061system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9421 # number of demand (read+write) misses 1062system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7390 # number of demand (read+write) misses 1063system.cpu0.l2cache.demand_misses::cpu0.inst 460700 # number of demand (read+write) misses 1064system.cpu0.l2cache.demand_misses::cpu0.data 1189050 # number of demand (read+write) misses 1065system.cpu0.l2cache.demand_misses::total 1666561 # number of demand (read+write) misses 1066system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9421 # number of overall misses 1067system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7390 # number of overall misses 1068system.cpu0.l2cache.overall_misses::cpu0.inst 460700 # number of overall misses 1069system.cpu0.l2cache.overall_misses::cpu0.data 1189050 # number of overall misses 1070system.cpu0.l2cache.overall_misses::total 1666561 # number of overall misses 1071system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 332469500 # number of ReadReq miss cycles 1072system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 285177500 # number of ReadReq miss cycles 1073system.cpu0.l2cache.ReadReq_miss_latency::total 617647000 # number of ReadReq miss cycles 1074system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 1968962500 # number of UpgradeReq miss cycles 1075system.cpu0.l2cache.UpgradeReq_miss_latency::total 1968962500 # number of UpgradeReq miss cycles 1076system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1588151500 # number of SCUpgradeReq miss cycles 1077system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1588151500 # number of SCUpgradeReq miss cycles 1078system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2987000 # number of SCUpgradeFailReq miss cycles 1079system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2987000 # number of SCUpgradeFailReq miss cycles 1080system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12588187000 # number of ReadExReq miss cycles 1081system.cpu0.l2cache.ReadExReq_miss_latency::total 12588187000 # number of ReadExReq miss cycles 1082system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 16045103500 # number of ReadCleanReq miss cycles 1083system.cpu0.l2cache.ReadCleanReq_miss_latency::total 16045103500 # number of ReadCleanReq miss cycles 1084system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 32885800500 # number of ReadSharedReq miss cycles 1085system.cpu0.l2cache.ReadSharedReq_miss_latency::total 32885800500 # number of ReadSharedReq miss cycles 1086system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 322469500 # number of InvalidateReq miss cycles 1087system.cpu0.l2cache.InvalidateReq_miss_latency::total 322469500 # number of InvalidateReq miss cycles 1088system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 332469500 # number of demand (read+write) miss cycles 1089system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 285177500 # number of demand (read+write) miss cycles 1090system.cpu0.l2cache.demand_miss_latency::cpu0.inst 16045103500 # number of demand (read+write) miss cycles 1091system.cpu0.l2cache.demand_miss_latency::cpu0.data 45473987500 # number of demand (read+write) miss cycles 1092system.cpu0.l2cache.demand_miss_latency::total 62136738000 # number of demand (read+write) miss cycles 1093system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 332469500 # number of overall miss cycles 1094system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 285177500 # number of overall miss cycles 1095system.cpu0.l2cache.overall_miss_latency::cpu0.inst 16045103500 # number of overall miss cycles 1096system.cpu0.l2cache.overall_miss_latency::cpu0.data 45473987500 # number of overall miss cycles 1097system.cpu0.l2cache.overall_miss_latency::total 62136738000 # number of overall miss cycles 1098system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 273281 # number of ReadReq accesses(hits+misses) 1099system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155420 # number of ReadReq accesses(hits+misses) 1100system.cpu0.l2cache.ReadReq_accesses::total 428701 # number of ReadReq accesses(hits+misses) 1101system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3764500 # number of WritebackDirty accesses(hits+misses) 1102system.cpu0.l2cache.WritebackDirty_accesses::total 3764500 # number of WritebackDirty accesses(hits+misses) 1103system.cpu0.l2cache.WritebackClean_accesses::writebacks 7067152 # number of WritebackClean accesses(hits+misses) 1104system.cpu0.l2cache.WritebackClean_accesses::total 7067152 # number of WritebackClean accesses(hits+misses) 1105system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244142 # number of UpgradeReq accesses(hits+misses) 1106system.cpu0.l2cache.UpgradeReq_accesses::total 244142 # number of UpgradeReq accesses(hits+misses) 1107system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 205138 # number of SCUpgradeReq accesses(hits+misses) 1108system.cpu0.l2cache.SCUpgradeReq_accesses::total 205138 # number of SCUpgradeReq accesses(hits+misses) 1109system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1110system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1111system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1155718 # number of ReadExReq accesses(hits+misses) 1112system.cpu0.l2cache.ReadExReq_accesses::total 1155718 # number of ReadExReq accesses(hits+misses) 1113system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5143417 # number of ReadCleanReq accesses(hits+misses) 1114system.cpu0.l2cache.ReadCleanReq_accesses::total 5143417 # number of ReadCleanReq accesses(hits+misses) 1115system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3840345 # number of ReadSharedReq accesses(hits+misses) 1116system.cpu0.l2cache.ReadSharedReq_accesses::total 3840345 # number of ReadSharedReq accesses(hits+misses) 1117system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790706 # number of InvalidateReq accesses(hits+misses) 1118system.cpu0.l2cache.InvalidateReq_accesses::total 790706 # number of InvalidateReq accesses(hits+misses) 1119system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 273281 # number of demand (read+write) accesses 1120system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155420 # number of demand (read+write) accesses 1121system.cpu0.l2cache.demand_accesses::cpu0.inst 5143417 # number of demand (read+write) accesses 1122system.cpu0.l2cache.demand_accesses::cpu0.data 4996063 # number of demand (read+write) accesses 1123system.cpu0.l2cache.demand_accesses::total 10568181 # number of demand (read+write) accesses 1124system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 273281 # number of overall (read+write) accesses 1125system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155420 # number of overall (read+write) accesses 1126system.cpu0.l2cache.overall_accesses::cpu0.inst 5143417 # number of overall (read+write) accesses 1127system.cpu0.l2cache.overall_accesses::cpu0.data 4996063 # number of overall (read+write) accesses 1128system.cpu0.l2cache.overall_accesses::total 10568181 # number of overall (read+write) accesses 1129system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for ReadReq accesses 1130system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047549 # miss rate for ReadReq accesses 1131system.cpu0.l2cache.ReadReq_miss_rate::total 0.039214 # miss rate for ReadReq accesses 1132system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998390 # miss rate for UpgradeReq accesses 1133system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998390 # miss rate for UpgradeReq accesses 1134system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1135system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1136system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1137system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1138system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217362 # miss rate for ReadExReq accesses 1139system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217362 # miss rate for ReadExReq accesses 1140system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089571 # miss rate for ReadCleanReq accesses 1141system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089571 # miss rate for ReadCleanReq accesses 1142system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244207 # miss rate for ReadSharedReq accesses 1143system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244207 # miss rate for ReadSharedReq accesses 1144system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730498 # miss rate for InvalidateReq accesses 1145system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730498 # miss rate for InvalidateReq accesses 1146system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for demand accesses 1147system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047549 # miss rate for demand accesses 1148system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089571 # miss rate for demand accesses 1149system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237997 # miss rate for demand accesses 1150system.cpu0.l2cache.demand_miss_rate::total 0.157696 # miss rate for demand accesses 1151system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for overall accesses 1152system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047549 # miss rate for overall accesses 1153system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089571 # miss rate for overall accesses 1154system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237997 # miss rate for overall accesses 1155system.cpu0.l2cache.overall_miss_rate::total 0.157696 # miss rate for overall accesses 1156system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average ReadReq miss latency 1157system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38589.648173 # average ReadReq miss latency 1158system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36740.646006 # average ReadReq miss latency 1159system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 8077.828012 # average UpgradeReq miss latency 1160system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8077.828012 # average UpgradeReq miss latency 1161system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7741.868888 # average SCUpgradeReq miss latency 1162system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7741.868888 # average SCUpgradeReq miss latency 1163system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 373375 # average SCUpgradeFailReq miss latency 1164system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 373375 # average SCUpgradeFailReq miss latency 1165system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50110.414038 # average ReadExReq miss latency 1166system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50110.414038 # average ReadExReq miss latency 1167system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34827.661168 # average ReadCleanReq miss latency 1168system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34827.661168 # average ReadCleanReq miss latency 1169system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35065.432733 # average ReadSharedReq miss latency 1170system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35065.432733 # average ReadSharedReq miss latency 1171system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 558.283372 # average InvalidateReq miss latency 1172system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 558.283372 # average InvalidateReq miss latency 1173system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average overall miss latency 1174system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38589.648173 # average overall miss latency 1175system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34827.661168 # average overall miss latency 1176system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38243.965771 # average overall miss latency 1177system.cpu0.l2cache.demand_avg_miss_latency::total 37284.406631 # average overall miss latency 1178system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average overall miss latency 1179system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38589.648173 # average overall miss latency 1180system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34827.661168 # average overall miss latency 1181system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38243.965771 # average overall miss latency 1182system.cpu0.l2cache.overall_avg_miss_latency::total 37284.406631 # average overall miss latency 1183system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu0.l2cache.unused_prefetches 37568 # number of HardPF blocks evicted w/o reference 1190system.cpu0.l2cache.writebacks::writebacks 1506522 # number of writebacks 1191system.cpu0.l2cache.writebacks::total 1506522 # number of writebacks 1192system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5548 # number of ReadExReq MSHR hits 1193system.cpu0.l2cache.ReadExReq_mshr_hits::total 5548 # number of ReadExReq MSHR hits 1194system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 408 # number of ReadSharedReq MSHR hits 1195system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 408 # number of ReadSharedReq MSHR hits 1196system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5956 # number of demand (read+write) MSHR hits 1197system.cpu0.l2cache.demand_mshr_hits::total 5956 # number of demand (read+write) MSHR hits 1198system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5956 # number of overall MSHR hits 1199system.cpu0.l2cache.overall_mshr_hits::total 5956 # number of overall MSHR hits 1200system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9421 # number of ReadReq MSHR misses 1201system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7390 # number of ReadReq MSHR misses 1202system.cpu0.l2cache.ReadReq_mshr_misses::total 16811 # number of ReadReq MSHR misses 1203system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 719381 # number of HardPFReq MSHR misses 1204system.cpu0.l2cache.HardPFReq_mshr_misses::total 719381 # number of HardPFReq MSHR misses 1205system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 243749 # number of UpgradeReq MSHR misses 1206system.cpu0.l2cache.UpgradeReq_mshr_misses::total 243749 # number of UpgradeReq MSHR misses 1207system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 205138 # number of SCUpgradeReq MSHR misses 1208system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 205138 # number of SCUpgradeReq MSHR misses 1209system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1210system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1211system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 245661 # number of ReadExReq MSHR misses 1212system.cpu0.l2cache.ReadExReq_mshr_misses::total 245661 # number of ReadExReq MSHR misses 1213system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 460700 # number of ReadCleanReq MSHR misses 1214system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 460700 # number of ReadCleanReq MSHR misses 1215system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 937433 # number of ReadSharedReq MSHR misses 1216system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 937433 # number of ReadSharedReq MSHR misses 1217system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577609 # number of InvalidateReq MSHR misses 1218system.cpu0.l2cache.InvalidateReq_mshr_misses::total 577609 # number of InvalidateReq MSHR misses 1219system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9421 # number of demand (read+write) MSHR misses 1220system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7390 # number of demand (read+write) MSHR misses 1221system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 460700 # number of demand (read+write) MSHR misses 1222system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1183094 # number of demand (read+write) MSHR misses 1223system.cpu0.l2cache.demand_mshr_misses::total 1660605 # number of demand (read+write) MSHR misses 1224system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9421 # number of overall MSHR misses 1225system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7390 # number of overall MSHR misses 1226system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 460700 # number of overall MSHR misses 1227system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1183094 # number of overall MSHR misses 1228system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 719381 # number of overall MSHR misses 1229system.cpu0.l2cache.overall_mshr_misses::total 2379986 # number of overall MSHR misses 1230system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1231system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable 1232system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70742 # number of ReadReq MSHR uncacheable 1233system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable 1234system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable 1235system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1236system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses 1237system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 97307 # number of overall MSHR uncacheable misses 1238system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of ReadReq MSHR miss cycles 1239system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 240837500 # number of ReadReq MSHR miss cycles 1240system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 516781000 # number of ReadReq MSHR miss cycles 1241system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of HardPFReq MSHR miss cycles 1242system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32427966574 # number of HardPFReq MSHR miss cycles 1243system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5063458500 # number of UpgradeReq MSHR miss cycles 1244system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5063458500 # number of UpgradeReq MSHR miss cycles 1245system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3348331499 # number of SCUpgradeReq MSHR miss cycles 1246system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3348331499 # number of SCUpgradeReq MSHR miss cycles 1247system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2645000 # number of SCUpgradeFailReq MSHR miss cycles 1248system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2645000 # number of SCUpgradeFailReq MSHR miss cycles 1249system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10596762500 # number of ReadExReq MSHR miss cycles 1250system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10596762500 # number of ReadExReq MSHR miss cycles 1251system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13280903500 # number of ReadCleanReq MSHR miss cycles 1252system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13280903500 # number of ReadCleanReq MSHR miss cycles 1253system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27229516500 # number of ReadSharedReq MSHR miss cycles 1254system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27229516500 # number of ReadSharedReq MSHR miss cycles 1255system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18926305000 # number of InvalidateReq MSHR miss cycles 1256system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18926305000 # number of InvalidateReq MSHR miss cycles 1257system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of demand (read+write) MSHR miss cycles 1258system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 240837500 # number of demand (read+write) MSHR miss cycles 1259system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13280903500 # number of demand (read+write) MSHR miss cycles 1260system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37826279000 # number of demand (read+write) MSHR miss cycles 1261system.cpu0.l2cache.demand_mshr_miss_latency::total 51623963500 # number of demand (read+write) MSHR miss cycles 1262system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of overall MSHR miss cycles 1263system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 240837500 # number of overall MSHR miss cycles 1264system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13280903500 # number of overall MSHR miss cycles 1265system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37826279000 # number of overall MSHR miss cycles 1266system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of overall MSHR miss cycles 1267system.cpu0.l2cache.overall_mshr_miss_latency::total 84051930074 # number of overall MSHR miss cycles 1268system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles 1269system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850886500 # number of ReadReq MSHR uncacheable cycles 1270system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346919000 # number of ReadReq MSHR uncacheable cycles 1271system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles 1272system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850886500 # number of overall MSHR uncacheable cycles 1273system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346919000 # number of overall MSHR uncacheable cycles 1274system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for ReadReq accesses 1275system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for ReadReq accesses 1276system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039214 # mshr miss rate for ReadReq accesses 1277system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1278system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1279system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998390 # mshr miss rate for UpgradeReq accesses 1280system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998390 # mshr miss rate for UpgradeReq accesses 1281system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1282system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1283system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1284system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1285system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212561 # mshr miss rate for ReadExReq accesses 1286system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212561 # mshr miss rate for ReadExReq accesses 1287system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for ReadCleanReq accesses 1288system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089571 # mshr miss rate for ReadCleanReq accesses 1289system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.244101 # mshr miss rate for ReadSharedReq accesses 1290system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244101 # mshr miss rate for ReadSharedReq accesses 1291system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730498 # mshr miss rate for InvalidateReq accesses 1292system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730498 # mshr miss rate for InvalidateReq accesses 1293system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for demand accesses 1294system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for demand accesses 1295system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for demand accesses 1296system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for demand accesses 1297system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses 1298system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for overall accesses 1299system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for overall accesses 1300system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for overall accesses 1301system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for overall accesses 1302system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1303system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225203 # mshr miss rate for overall accesses 1304system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average ReadReq mshr miss latency 1305system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average ReadReq mshr miss latency 1306system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006 # average ReadReq mshr miss latency 1307system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average HardPFReq mshr miss latency 1308system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675 # average HardPFReq mshr miss latency 1309system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301 # average UpgradeReq mshr miss latency 1310system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301 # average UpgradeReq mshr miss latency 1311system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666 # average SCUpgradeReq mshr miss latency 1312system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666 # average SCUpgradeReq mshr miss latency 1313system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 330625 # average SCUpgradeFailReq mshr miss latency 1314system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 330625 # average SCUpgradeFailReq mshr miss latency 1315system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443 # average ReadExReq mshr miss latency 1316system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443 # average ReadExReq mshr miss latency 1317system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average ReadCleanReq mshr miss latency 1318system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168 # average ReadCleanReq mshr miss latency 1319system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485 # average ReadSharedReq mshr miss latency 1320system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485 # average ReadSharedReq mshr miss latency 1321system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985 # average InvalidateReq mshr miss latency 1322system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985 # average InvalidateReq mshr miss latency 1323system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency 1324system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency 1325system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency 1326system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency 1327system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131 # average overall mshr miss latency 1328system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency 1329system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency 1330system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency 1331system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency 1332system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average overall mshr miss latency 1333system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748 # average overall mshr miss latency 1334system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency 1335system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911 # average ReadReq mshr uncacheable latency 1336system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448 # average ReadReq mshr uncacheable latency 1337system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency 1338system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency 1339system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency 1340system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. 1341system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1342system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1343system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. 1344system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1345system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1346system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1347system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution 1348system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution 1349system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution 1350system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution 1351system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution 1352system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution 1353system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution 1354system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution 1355system.cpu0.toL2Bus.trans_dist::UpgradeReq 441648 # Transaction distribution 1356system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 374962 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::UpgradeResp 517397 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::ReadExReq 1188175 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::ReadExResp 1165072 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5143417 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4741538 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::InvalidateReq 839102 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::InvalidateResp 790706 # Transaction distribution 1366system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15515989 # Packet count per connected master and slave (bytes) 1367system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18442402 # Packet count per connected master and slave (bytes) 1368system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326965 # Packet count per connected master and slave (bytes) 1369system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 595128 # Packet count per connected master and slave (bytes) 1370system.cpu0.toL2Bus.pkt_count::total 34880484 # Packet count per connected master and slave (bytes) 1371system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 658497108 # Cumulative packet size per connected master and slave (bytes) 1372system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690726071 # Cumulative packet size per connected master and slave (bytes) 1373system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1243360 # Cumulative packet size per connected master and slave (bytes) 1374system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2186248 # Cumulative packet size per connected master and slave (bytes) 1375system.cpu0.toL2Bus.pkt_size::total 1352652787 # Cumulative packet size per connected master and slave (bytes) 1376system.cpu0.toL2Bus.snoops 6279047 # Total snoops (count) 1377system.cpu0.toL2Bus.snoop_fanout::samples 18012222 # Request fanout histogram 1378system.cpu0.toL2Bus.snoop_fanout::mean 0.113865 # Request fanout histogram 1379system.cpu0.toL2Bus.snoop_fanout::stdev 0.317693 # Request fanout histogram 1380system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1381system.cpu0.toL2Bus.snoop_fanout::0 15961520 88.61% 88.61% # Request fanout histogram 1382system.cpu0.toL2Bus.snoop_fanout::1 2050439 11.38% 100.00% # Request fanout histogram 1383system.cpu0.toL2Bus.snoop_fanout::2 263 0.00% 100.00% # Request fanout histogram 1384system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1385system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1386system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1387system.cpu0.toL2Bus.snoop_fanout::total 18012222 # Request fanout histogram 1388system.cpu0.toL2Bus.reqLayer0.occupancy 22247152499 # Layer occupancy (ticks) 1389system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1390system.cpu0.toL2Bus.snoopLayer0.occupancy 190413774 # Layer occupancy (ticks) 1391system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1392system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) 1393system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1394system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) 1395system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1396system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) 1397system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1398system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) 1399system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1400system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1401system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1402system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1404system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1405system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1406system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1407system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1408system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1409system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1410system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1411system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1412system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1413system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1414system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1415system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1416system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1417system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1418system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1419system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1420system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1421system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1422system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1423system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1424system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1425system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1426system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1427system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1428system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1429system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1430system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1431system.cpu1.dtb.walker.walks 105013 # Table walker walks requested 1432system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors 1433system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate 1434system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate 1435system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 1436system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency 1437system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency 1438system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency 1439system.cpu1.dtb.walker.walkWaitTime::0-511 105005 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1440system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1441system.cpu1.dtb.walker.walkWaitTime::total 105006 # Table walker wait (enqueue to first request) latency 1442system.cpu1.dtb.walker.walkCompletionTime::samples 89755 # Table walker service (enqueue to completion) latency 1443system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523 # Table walker service (enqueue to completion) latency 1444system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457 # Table walker service (enqueue to completion) latency 1445system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739 # Table walker service (enqueue to completion) latency 1446system.cpu1.dtb.walker.walkCompletionTime::0-65535 88364 98.45% 98.45% # Table walker service (enqueue to completion) latency 1447system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1205 1.34% 99.79% # Table walker service (enqueue to completion) latency 1448system.cpu1.dtb.walker.walkCompletionTime::131072-196607 34 0.04% 99.83% # Table walker service (enqueue to completion) latency 1449system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.08% 99.91% # Table walker service (enqueue to completion) latency 1450system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.07% 99.97% # Table walker service (enqueue to completion) latency 1451system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 1452system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1453system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1454system.cpu1.dtb.walker.walkCompletionTime::total 89755 # Table walker service (enqueue to completion) latency 1455system.cpu1.dtb.walker.walksPending::samples -3159480544 # Table walker pending requests distribution 1456system.cpu1.dtb.walker.walksPending::mean 0.804201 # Table walker pending requests distribution 1457system.cpu1.dtb.walker.walksPending::stdev 0.396815 # Table walker pending requests distribution 1458system.cpu1.dtb.walker.walksPending::0 -618623648 19.58% 19.58% # Table walker pending requests distribution 1459system.cpu1.dtb.walker.walksPending::1 -2540856896 80.42% 100.00% # Table walker pending requests distribution 1460system.cpu1.dtb.walker.walksPending::total -3159480544 # Table walker pending requests distribution 1461system.cpu1.dtb.walker.walkPageSizes::4K 79078 88.11% 88.11% # Table walker page sizes translated 1462system.cpu1.dtb.walker.walkPageSizes::2M 10670 11.89% 100.00% # Table walker page sizes translated 1463system.cpu1.dtb.walker.walkPageSizes::total 89748 # Table walker page sizes translated 1464system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105013 # Table walker requests started/completed, data/inst 1465system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1466system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105013 # Table walker requests started/completed, data/inst 1467system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89748 # Table walker requests started/completed, data/inst 1468system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1469system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89748 # Table walker requests started/completed, data/inst 1470system.cpu1.dtb.walker.walkRequestOrigin::total 194761 # Table walker requests started/completed, data/inst 1471system.cpu1.dtb.inst_hits 0 # ITB inst hits 1472system.cpu1.dtb.inst_misses 0 # ITB inst misses 1473system.cpu1.dtb.read_hits 79229823 # DTB read hits 1474system.cpu1.dtb.read_misses 76992 # DTB read misses 1475system.cpu1.dtb.write_hits 72255246 # DTB write hits 1476system.cpu1.dtb.write_misses 28021 # DTB write misses 1477system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1478system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1479system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1480system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID	567system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 568system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 569system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 570system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 571system.cpu0.itb.read_accesses 0 # DTB read accesses 572system.cpu0.itb.write_accesses 0 # DTB write accesses 573system.cpu0.itb.inst_accesses 461257306 # ITB inst accesses 574system.cpu0.itb.hits 461199865 # DTB hits 575system.cpu0.itb.misses 57441 # DTB misses 576system.cpu0.itb.accesses 461257306 # DTB accesses 577system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions 578system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state 579system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state 580system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state 581system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state 582system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state 583system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state 584system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state 585system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state 586system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state 587system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 588system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 589system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states 597system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states 598system.cpu0.numCycles 95045540829 # number of cpu cycles simulated 599system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 600system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 601system.cpu0.kern.inst.arm 0 # number of arm instructions executed 602system.cpu0.kern.inst.quiesce 13927 # number of quiesce instructions executed 603system.cpu0.committedInsts 460929213 # Number of instructions committed 604system.cpu0.committedOps 541179982 # Number of ops (including micro ops) committed 605system.cpu0.num_int_alu_accesses 497492129 # Number of integer alu accesses 606system.cpu0.num_fp_alu_accesses 434558 # Number of float alu accesses 607system.cpu0.num_func_calls 27781850 # number of times a function call or return occured 608system.cpu0.num_conditional_control_insts 69589132 # number of instructions that are conditional controls 609system.cpu0.num_int_insts 497492129 # number of integer instructions 610system.cpu0.num_fp_insts 434558 # number of float instructions 611system.cpu0.num_int_register_reads 719293830 # number of times the integer registers were read 612system.cpu0.num_int_register_writes 394367415 # number of times the integer registers were written 613system.cpu0.num_fp_register_reads 718787 # number of times the floating registers were read 614system.cpu0.num_fp_register_writes 331792 # number of times the floating registers were written 615system.cpu0.num_cc_register_reads 119457726 # number of times the CC registers were read 616system.cpu0.num_cc_register_writes 119087316 # number of times the CC registers were written 617system.cpu0.num_mem_refs 165514046 # number of memory refs 618system.cpu0.num_load_insts 86852092 # Number of load instructions 619system.cpu0.num_store_insts 78661954 # Number of store instructions 620system.cpu0.num_idle_cycles 93905101360.384018 # Number of idle cycles 621system.cpu0.num_busy_cycles 1140439468.615976 # Number of busy cycles 622system.cpu0.not_idle_fraction 0.011999 # Percentage of non-idle cycles 623system.cpu0.idle_fraction 0.988001 # Percentage of idle cycles 624system.cpu0.Branches 102755128 # Number of branches fetched 625system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 626system.cpu0.op_class::IntAlu 374676211 69.19% 69.19% # Class of executed instruction 627system.cpu0.op_class::IntMult 1194745 0.22% 69.41% # Class of executed instruction 628system.cpu0.op_class::IntDiv 63344 0.01% 69.43% # Class of executed instruction 629system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 630system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 631system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 632system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 633system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 634system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 635system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 636system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 637system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 638system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 639system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 640system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 641system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 642system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 643system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 644system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 645system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 646system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction 647system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 648system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction 649system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction 650system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 651system.cpu0.op_class::SimdFloatMisc 45411 0.01% 69.43% # Class of executed instruction 652system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction 653system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction 654system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction 655system.cpu0.op_class::MemRead 86852092 16.04% 85.47% # Class of executed instruction 656system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Class of executed instruction 657system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 658system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 659system.cpu0.op_class::total 541493758 # Class of executed instruction 660system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 661system.cpu0.dcache.tags.replacements 5689621 # number of replacements 662system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use 663system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. 664system.cpu0.dcache.tags.sampled_refs 5690133 # Sample count of references to valid blocks. 665system.cpu0.dcache.tags.avg_refs 28.045414 # Average number of references to valid blocks. 666system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. 667system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.423656 # Average occupied blocks per requestor 668system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993015 # Average percentage of cache occupancy 669system.cpu0.dcache.tags.occ_percent::total 0.993015 # Average percentage of cache occupancy 670system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 671system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 672system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id 673system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id 674system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 675system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses 676system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses 677system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 678system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits 679system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits 680system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits 681system.cpu0.dcache.WriteReq_hits::total 74279623 # number of WriteReq hits 682system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199389 # number of SoftPFReq hits 683system.cpu0.dcache.SoftPFReq_hits::total 199389 # number of SoftPFReq hits 684system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162229 # number of WriteLineReq hits 685system.cpu0.dcache.WriteLineReq_hits::total 162229 # number of WriteLineReq hits 686system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1824290 # number of LoadLockedReq hits 687system.cpu0.dcache.LoadLockedReq_hits::total 1824290 # number of LoadLockedReq hits 688system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1791894 # number of StoreCondReq hits 689system.cpu0.dcache.StoreCondReq_hits::total 1791894 # number of StoreCondReq hits 690system.cpu0.dcache.demand_hits::cpu0.data 155334822 # number of demand (read+write) hits 691system.cpu0.dcache.demand_hits::total 155334822 # number of demand (read+write) hits 692system.cpu0.dcache.overall_hits::cpu0.data 155534211 # number of overall hits 693system.cpu0.dcache.overall_hits::total 155534211 # number of overall hits 694system.cpu0.dcache.ReadReq_misses::cpu0.data 3104051 # number of ReadReq misses 695system.cpu0.dcache.ReadReq_misses::total 3104051 # number of ReadReq misses 696system.cpu0.dcache.WriteReq_misses::cpu0.data 1401631 # number of WriteReq misses 697system.cpu0.dcache.WriteReq_misses::total 1401631 # number of WriteReq misses 698system.cpu0.dcache.SoftPFReq_misses::cpu0.data 634089 # number of SoftPFReq misses 699system.cpu0.dcache.SoftPFReq_misses::total 634089 # number of SoftPFReq misses 700system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792659 # number of WriteLineReq misses 701system.cpu0.dcache.WriteLineReq_misses::total 792659 # number of WriteLineReq misses 702system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174131 # number of LoadLockedReq misses 703system.cpu0.dcache.LoadLockedReq_misses::total 174131 # number of LoadLockedReq misses 704system.cpu0.dcache.StoreCondReq_misses::cpu0.data 205146 # number of StoreCondReq misses 705system.cpu0.dcache.StoreCondReq_misses::total 205146 # number of StoreCondReq misses 706system.cpu0.dcache.demand_misses::cpu0.data 5298341 # number of demand (read+write) misses 707system.cpu0.dcache.demand_misses::total 5298341 # number of demand (read+write) misses 708system.cpu0.dcache.overall_misses::cpu0.data 5932430 # number of overall misses 709system.cpu0.dcache.overall_misses::total 5932430 # number of overall misses 710system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46355544000 # number of ReadReq miss cycles 711system.cpu0.dcache.ReadReq_miss_latency::total 46355544000 # number of ReadReq miss cycles 712system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29179707500 # number of WriteReq miss cycles 713system.cpu0.dcache.WriteReq_miss_latency::total 29179707500 # number of WriteReq miss cycles 714system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25804948000 # number of WriteLineReq miss cycles 715system.cpu0.dcache.WriteLineReq_miss_latency::total 25804948000 # number of WriteLineReq miss cycles 716system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2634324500 # number of LoadLockedReq miss cycles 717system.cpu0.dcache.LoadLockedReq_miss_latency::total 2634324500 # number of LoadLockedReq miss cycles 718system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5093103500 # number of StoreCondReq miss cycles 719system.cpu0.dcache.StoreCondReq_miss_latency::total 5093103500 # number of StoreCondReq miss cycles 720system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3129500 # number of StoreCondFailReq miss cycles 721system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3129500 # number of StoreCondFailReq miss cycles 722system.cpu0.dcache.demand_miss_latency::cpu0.data 101340199500 # number of demand (read+write) miss cycles 723system.cpu0.dcache.demand_miss_latency::total 101340199500 # number of demand (read+write) miss cycles 724system.cpu0.dcache.overall_miss_latency::cpu0.data 101340199500 # number of overall miss cycles 725system.cpu0.dcache.overall_miss_latency::total 101340199500 # number of overall miss cycles 726system.cpu0.dcache.ReadReq_accesses::cpu0.data 83997021 # number of ReadReq accesses(hits+misses) 727system.cpu0.dcache.ReadReq_accesses::total 83997021 # number of ReadReq accesses(hits+misses) 728system.cpu0.dcache.WriteReq_accesses::cpu0.data 75681254 # number of WriteReq accesses(hits+misses) 729system.cpu0.dcache.WriteReq_accesses::total 75681254 # number of WriteReq accesses(hits+misses) 730system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 833478 # number of SoftPFReq accesses(hits+misses) 731system.cpu0.dcache.SoftPFReq_accesses::total 833478 # number of SoftPFReq accesses(hits+misses) 732system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954888 # number of WriteLineReq accesses(hits+misses) 733system.cpu0.dcache.WriteLineReq_accesses::total 954888 # number of WriteLineReq accesses(hits+misses) 734system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1998421 # number of LoadLockedReq accesses(hits+misses) 735system.cpu0.dcache.LoadLockedReq_accesses::total 1998421 # number of LoadLockedReq accesses(hits+misses) 736system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1997040 # number of StoreCondReq accesses(hits+misses) 737system.cpu0.dcache.StoreCondReq_accesses::total 1997040 # number of StoreCondReq accesses(hits+misses) 738system.cpu0.dcache.demand_accesses::cpu0.data 160633163 # number of demand (read+write) accesses 739system.cpu0.dcache.demand_accesses::total 160633163 # number of demand (read+write) accesses 740system.cpu0.dcache.overall_accesses::cpu0.data 161466641 # number of overall (read+write) accesses 741system.cpu0.dcache.overall_accesses::total 161466641 # number of overall (read+write) accesses 742system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036954 # miss rate for ReadReq accesses 743system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses 744system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018520 # miss rate for WriteReq accesses 745system.cpu0.dcache.WriteReq_miss_rate::total 0.018520 # miss rate for WriteReq accesses 746system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760775 # miss rate for SoftPFReq accesses 747system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760775 # miss rate for SoftPFReq accesses 748system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.830107 # miss rate for WriteLineReq accesses 749system.cpu0.dcache.WriteLineReq_miss_rate::total 0.830107 # miss rate for WriteLineReq accesses 750system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087134 # miss rate for LoadLockedReq accesses 751system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087134 # miss rate for LoadLockedReq accesses 752system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102725 # miss rate for StoreCondReq accesses 753system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102725 # miss rate for StoreCondReq accesses 754system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032984 # miss rate for demand accesses 755system.cpu0.dcache.demand_miss_rate::total 0.032984 # miss rate for demand accesses 756system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036741 # miss rate for overall accesses 757system.cpu0.dcache.overall_miss_rate::total 0.036741 # miss rate for overall accesses 758system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14933.886073 # average ReadReq miss latency 759system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.886073 # average ReadReq miss latency 760system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20818.394784 # average WriteReq miss latency 761system.cpu0.dcache.WriteReq_avg_miss_latency::total 20818.394784 # average WriteReq miss latency 762system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32554.917058 # average WriteLineReq miss latency 763system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32554.917058 # average WriteLineReq miss latency 764system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15128.406200 # average LoadLockedReq miss latency 765system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15128.406200 # average LoadLockedReq miss latency 766system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24826.725844 # average StoreCondReq miss latency 767system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24826.725844 # average StoreCondReq miss latency 768system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 769system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 770system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19126.779401 # average overall miss latency 771system.cpu0.dcache.demand_avg_miss_latency::total 19126.779401 # average overall miss latency 772system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17082.409653 # average overall miss latency 773system.cpu0.dcache.overall_avg_miss_latency::total 17082.409653 # average overall miss latency 774system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 775system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 776system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 777system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 778system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 779system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 780system.cpu0.dcache.writebacks::writebacks 5689621 # number of writebacks 781system.cpu0.dcache.writebacks::total 5689621 # number of writebacks 782system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25484 # number of ReadReq MSHR hits 783system.cpu0.dcache.ReadReq_mshr_hits::total 25484 # number of ReadReq MSHR hits 784system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21272 # number of WriteReq MSHR hits 785system.cpu0.dcache.WriteReq_mshr_hits::total 21272 # number of WriteReq MSHR hits 786system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45280 # number of LoadLockedReq MSHR hits 787system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45280 # number of LoadLockedReq MSHR hits 788system.cpu0.dcache.demand_mshr_hits::cpu0.data 46756 # number of demand (read+write) MSHR hits 789system.cpu0.dcache.demand_mshr_hits::total 46756 # number of demand (read+write) MSHR hits 790system.cpu0.dcache.overall_mshr_hits::cpu0.data 46756 # number of overall MSHR hits 791system.cpu0.dcache.overall_mshr_hits::total 46756 # number of overall MSHR hits 792system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3078567 # number of ReadReq MSHR misses 793system.cpu0.dcache.ReadReq_mshr_misses::total 3078567 # number of ReadReq MSHR misses 794system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380359 # number of WriteReq MSHR misses 795system.cpu0.dcache.WriteReq_mshr_misses::total 1380359 # number of WriteReq MSHR misses 796system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 632927 # number of SoftPFReq MSHR misses 797system.cpu0.dcache.SoftPFReq_mshr_misses::total 632927 # number of SoftPFReq MSHR misses 798system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792659 # number of WriteLineReq MSHR misses 799system.cpu0.dcache.WriteLineReq_mshr_misses::total 792659 # number of WriteLineReq MSHR misses 800system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128851 # number of LoadLockedReq MSHR misses 801system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128851 # number of LoadLockedReq MSHR misses 802system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 205146 # number of StoreCondReq MSHR misses 803system.cpu0.dcache.StoreCondReq_mshr_misses::total 205146 # number of StoreCondReq MSHR misses 804system.cpu0.dcache.demand_mshr_misses::cpu0.data 5251585 # number of demand (read+write) MSHR misses 805system.cpu0.dcache.demand_mshr_misses::total 5251585 # number of demand (read+write) MSHR misses 806system.cpu0.dcache.overall_mshr_misses::cpu0.data 5884512 # number of overall MSHR misses 807system.cpu0.dcache.overall_mshr_misses::total 5884512 # number of overall MSHR misses 808system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable 809system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27617 # number of ReadReq MSHR uncacheable 810system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable 811system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable 812system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses 813system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54182 # number of overall MSHR uncacheable misses 814system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42188847000 # number of ReadReq MSHR miss cycles 815system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42188847000 # number of ReadReq MSHR miss cycles 816system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27459987000 # number of WriteReq MSHR miss cycles 817system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27459987000 # number of WriteReq MSHR miss cycles 818system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13648405000 # number of SoftPFReq MSHR miss cycles 819system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13648405000 # number of SoftPFReq MSHR miss cycles 820system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25012289000 # number of WriteLineReq MSHR miss cycles 821system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25012289000 # number of WriteLineReq MSHR miss cycles 822system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1718421000 # number of LoadLockedReq MSHR miss cycles 823system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1718421000 # number of LoadLockedReq MSHR miss cycles 824system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4888014500 # number of StoreCondReq MSHR miss cycles 825system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4888014500 # number of StoreCondReq MSHR miss cycles 826system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3072500 # number of StoreCondFailReq MSHR miss cycles 827system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3072500 # number of StoreCondFailReq MSHR miss cycles 828system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94661123000 # number of demand (read+write) MSHR miss cycles 829system.cpu0.dcache.demand_mshr_miss_latency::total 94661123000 # number of demand (read+write) MSHR miss cycles 830system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108309528000 # number of overall MSHR miss cycles 831system.cpu0.dcache.overall_mshr_miss_latency::total 108309528000 # number of overall MSHR miss cycles 832system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5072174500 # number of ReadReq MSHR uncacheable cycles 833system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5072174500 # number of ReadReq MSHR uncacheable cycles 834system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5072174500 # number of overall MSHR uncacheable cycles 835system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5072174500 # number of overall MSHR uncacheable cycles 836system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036651 # mshr miss rate for ReadReq accesses 837system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036651 # mshr miss rate for ReadReq accesses 838system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for WriteReq accesses 839system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018239 # mshr miss rate for WriteReq accesses 840system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759381 # mshr miss rate for SoftPFReq accesses 841system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759381 # mshr miss rate for SoftPFReq accesses 842system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.830107 # mshr miss rate for WriteLineReq accesses 843system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.830107 # mshr miss rate for WriteLineReq accesses 844system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064476 # mshr miss rate for LoadLockedReq accesses 845system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064476 # mshr miss rate for LoadLockedReq accesses 846system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102725 # mshr miss rate for StoreCondReq accesses 847system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102725 # mshr miss rate for StoreCondReq accesses 848system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032693 # mshr miss rate for demand accesses 849system.cpu0.dcache.demand_mshr_miss_rate::total 0.032693 # mshr miss rate for demand accesses 850system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036444 # mshr miss rate for overall accesses 851system.cpu0.dcache.overall_mshr_miss_rate::total 0.036444 # mshr miss rate for overall accesses 852system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13704.053542 # average ReadReq mshr miss latency 853system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13704.053542 # average ReadReq mshr miss latency 854system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19893.366146 # average WriteReq mshr miss latency 855system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19893.366146 # average WriteReq mshr miss latency 856system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21563.948133 # average SoftPFReq mshr miss latency 857system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21563.948133 # average SoftPFReq mshr miss latency 858system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31554.917058 # average WriteLineReq mshr miss latency 859system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31554.917058 # average WriteLineReq mshr miss latency 860system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13336.497194 # average LoadLockedReq mshr miss latency 861system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.497194 # average LoadLockedReq mshr miss latency 862system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23827.003695 # average StoreCondReq mshr miss latency 863system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23827.003695 # average StoreCondReq mshr miss latency 864system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 865system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 866system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18025.248187 # average overall mshr miss latency 867system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18025.248187 # average overall mshr miss latency 868system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18405.864072 # average overall mshr miss latency 869system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18405.864072 # average overall mshr miss latency 870system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 # average ReadReq mshr uncacheable latency 871system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency 872system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency 873system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency 874system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 875system.cpu0.icache.tags.replacements 5142905 # number of replacements 876system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use 877system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. 878system.cpu0.icache.tags.sampled_refs 5143417 # Sample count of references to valid blocks. 879system.cpu0.icache.tags.avg_refs 88.667990 # Average number of references to valid blocks. 880system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. 881system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.908178 # Average occupied blocks per requestor 882system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999821 # Average percentage of cache occupancy 883system.cpu0.icache.tags.occ_percent::total 0.999821 # Average percentage of cache occupancy 884system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 885system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 886system.cpu0.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 887system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id 888system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 889system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 890system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses 891system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses 892system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 893system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits 894system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits 895system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits 896system.cpu0.icache.demand_hits::total 456056448 # number of demand (read+write) hits 897system.cpu0.icache.overall_hits::cpu0.inst 456056448 # number of overall hits 898system.cpu0.icache.overall_hits::total 456056448 # number of overall hits 899system.cpu0.icache.ReadReq_misses::cpu0.inst 5143417 # number of ReadReq misses 900system.cpu0.icache.ReadReq_misses::total 5143417 # number of ReadReq misses 901system.cpu0.icache.demand_misses::cpu0.inst 5143417 # number of demand (read+write) misses 902system.cpu0.icache.demand_misses::total 5143417 # number of demand (read+write) misses 903system.cpu0.icache.overall_misses::cpu0.inst 5143417 # number of overall misses 904system.cpu0.icache.overall_misses::total 5143417 # number of overall misses 905system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54463305000 # number of ReadReq miss cycles 906system.cpu0.icache.ReadReq_miss_latency::total 54463305000 # number of ReadReq miss cycles 907system.cpu0.icache.demand_miss_latency::cpu0.inst 54463305000 # number of demand (read+write) miss cycles 908system.cpu0.icache.demand_miss_latency::total 54463305000 # number of demand (read+write) miss cycles 909system.cpu0.icache.overall_miss_latency::cpu0.inst 54463305000 # number of overall miss cycles 910system.cpu0.icache.overall_miss_latency::total 54463305000 # number of overall miss cycles 911system.cpu0.icache.ReadReq_accesses::cpu0.inst 461199865 # number of ReadReq accesses(hits+misses) 912system.cpu0.icache.ReadReq_accesses::total 461199865 # number of ReadReq accesses(hits+misses) 913system.cpu0.icache.demand_accesses::cpu0.inst 461199865 # number of demand (read+write) accesses 914system.cpu0.icache.demand_accesses::total 461199865 # number of demand (read+write) accesses 915system.cpu0.icache.overall_accesses::cpu0.inst 461199865 # number of overall (read+write) accesses 916system.cpu0.icache.overall_accesses::total 461199865 # number of overall (read+write) accesses 917system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011152 # miss rate for ReadReq accesses 918system.cpu0.icache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses 919system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011152 # miss rate for demand accesses 920system.cpu0.icache.demand_miss_rate::total 0.011152 # miss rate for demand accesses 921system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011152 # miss rate for overall accesses 922system.cpu0.icache.overall_miss_rate::total 0.011152 # miss rate for overall accesses 923system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10588.934360 # average ReadReq miss latency 924system.cpu0.icache.ReadReq_avg_miss_latency::total 10588.934360 # average ReadReq miss latency 925system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency 926system.cpu0.icache.demand_avg_miss_latency::total 10588.934360 # average overall miss latency 927system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10588.934360 # average overall miss latency 928system.cpu0.icache.overall_avg_miss_latency::total 10588.934360 # average overall miss latency 929system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 930system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 931system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 932system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 933system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 934system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 935system.cpu0.icache.writebacks::writebacks 5142905 # number of writebacks 936system.cpu0.icache.writebacks::total 5142905 # number of writebacks 937system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5143417 # number of ReadReq MSHR misses 938system.cpu0.icache.ReadReq_mshr_misses::total 5143417 # number of ReadReq MSHR misses 939system.cpu0.icache.demand_mshr_misses::cpu0.inst 5143417 # number of demand (read+write) MSHR misses 940system.cpu0.icache.demand_mshr_misses::total 5143417 # number of demand (read+write) MSHR misses 941system.cpu0.icache.overall_mshr_misses::cpu0.inst 5143417 # number of overall MSHR misses 942system.cpu0.icache.overall_mshr_misses::total 5143417 # number of overall MSHR misses 943system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 944system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 945system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 946system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 947system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51891596500 # number of ReadReq MSHR miss cycles 948system.cpu0.icache.ReadReq_mshr_miss_latency::total 51891596500 # number of ReadReq MSHR miss cycles 949system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51891596500 # number of demand (read+write) MSHR miss cycles 950system.cpu0.icache.demand_mshr_miss_latency::total 51891596500 # number of demand (read+write) MSHR miss cycles 951system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51891596500 # number of overall MSHR miss cycles 952system.cpu0.icache.overall_mshr_miss_latency::total 51891596500 # number of overall MSHR miss cycles 953system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles 954system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles 955system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles 956system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles 957system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for ReadReq accesses 958system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011152 # mshr miss rate for ReadReq accesses 959system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for demand accesses 960system.cpu0.icache.demand_mshr_miss_rate::total 0.011152 # mshr miss rate for demand accesses 961system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011152 # mshr miss rate for overall accesses 962system.cpu0.icache.overall_mshr_miss_rate::total 0.011152 # mshr miss rate for overall accesses 963system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average ReadReq mshr miss latency 964system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10088.934360 # average ReadReq mshr miss latency 965system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 966system.cpu0.icache.demand_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 967system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10088.934360 # average overall mshr miss latency 968system.cpu0.icache.overall_avg_mshr_miss_latency::total 10088.934360 # average overall mshr miss latency 969system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency 970system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency 971system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency 972system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency 973system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 974system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued 975system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified 976system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue 977system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 978system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 979system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing 980system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 981system.cpu0.l2cache.tags.replacements 2348165 # number of replacements 982system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use 983system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks. 984system.cpu0.l2cache.tags.sampled_refs 2364235 # Sample count of references to valid blocks. 985system.cpu0.l2cache.tags.avg_refs 6.485817 # Average number of references to valid blocks. 986system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. 987system.cpu0.l2cache.tags.occ_blocks::writebacks 15208.455915 # Average occupied blocks per requestor 988system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.858641 # Average occupied blocks per requestor 989system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.489283 # Average occupied blocks per requestor 990system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 784.884937 # Average occupied blocks per requestor 991system.cpu0.l2cache.tags.occ_percent::writebacks 0.928250 # Average percentage of cache occupancy 992system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003776 # Average percentage of cache occupancy 993system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004852 # Average percentage of cache occupancy 994system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047906 # Average percentage of cache occupancy 995system.cpu0.l2cache.tags.occ_percent::total 0.984783 # Average percentage of cache occupancy 996system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id 997system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 998system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14708 # Occupied blocks per task id 999system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 1000system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 179 # Occupied blocks per task id 1001system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 589 # Occupied blocks per task id 1002system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 529 # Occupied blocks per task id 1003system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id 1004system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id 1005system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 1006system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4517 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3841 # Occupied blocks per task id 1011system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id 1012system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 1013system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id 1014system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses 1015system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses 1016system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1017system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits 1018system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits 1019system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits 1020system.cpu0.l2cache.WritebackDirty_hits::writebacks 3764500 # number of WritebackDirty hits 1021system.cpu0.l2cache.WritebackDirty_hits::total 3764500 # number of WritebackDirty hits 1022system.cpu0.l2cache.WritebackClean_hits::writebacks 7067152 # number of WritebackClean hits 1023system.cpu0.l2cache.WritebackClean_hits::total 7067152 # number of WritebackClean hits 1024system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 393 # number of UpgradeReq hits 1025system.cpu0.l2cache.UpgradeReq_hits::total 393 # number of UpgradeReq hits 1026system.cpu0.l2cache.ReadExReq_hits::cpu0.data 904509 # number of ReadExReq hits 1027system.cpu0.l2cache.ReadExReq_hits::total 904509 # number of ReadExReq hits 1028system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4682717 # number of ReadCleanReq hits 1029system.cpu0.l2cache.ReadCleanReq_hits::total 4682717 # number of ReadCleanReq hits 1030system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2902504 # number of ReadSharedReq hits 1031system.cpu0.l2cache.ReadSharedReq_hits::total 2902504 # number of ReadSharedReq hits 1032system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213097 # number of InvalidateReq hits 1033system.cpu0.l2cache.InvalidateReq_hits::total 213097 # number of InvalidateReq hits 1034system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 263860 # number of demand (read+write) hits 1035system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148030 # number of demand (read+write) hits 1036system.cpu0.l2cache.demand_hits::cpu0.inst 4682717 # number of demand (read+write) hits 1037system.cpu0.l2cache.demand_hits::cpu0.data 3807013 # number of demand (read+write) hits 1038system.cpu0.l2cache.demand_hits::total 8901620 # number of demand (read+write) hits 1039system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 263860 # number of overall hits 1040system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148030 # number of overall hits 1041system.cpu0.l2cache.overall_hits::cpu0.inst 4682717 # number of overall hits 1042system.cpu0.l2cache.overall_hits::cpu0.data 3807013 # number of overall hits 1043system.cpu0.l2cache.overall_hits::total 8901620 # number of overall hits 1044system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9421 # number of ReadReq misses 1045system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7390 # number of ReadReq misses 1046system.cpu0.l2cache.ReadReq_misses::total 16811 # number of ReadReq misses 1047system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 243749 # number of UpgradeReq misses 1048system.cpu0.l2cache.UpgradeReq_misses::total 243749 # number of UpgradeReq misses 1049system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 205138 # number of SCUpgradeReq misses 1050system.cpu0.l2cache.SCUpgradeReq_misses::total 205138 # number of SCUpgradeReq misses 1051system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 1052system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 1053system.cpu0.l2cache.ReadExReq_misses::cpu0.data 251209 # number of ReadExReq misses 1054system.cpu0.l2cache.ReadExReq_misses::total 251209 # number of ReadExReq misses 1055system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 460700 # number of ReadCleanReq misses 1056system.cpu0.l2cache.ReadCleanReq_misses::total 460700 # number of ReadCleanReq misses 1057system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 937841 # number of ReadSharedReq misses 1058system.cpu0.l2cache.ReadSharedReq_misses::total 937841 # number of ReadSharedReq misses 1059system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577609 # number of InvalidateReq misses 1060system.cpu0.l2cache.InvalidateReq_misses::total 577609 # number of InvalidateReq misses 1061system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9421 # number of demand (read+write) misses 1062system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7390 # number of demand (read+write) misses 1063system.cpu0.l2cache.demand_misses::cpu0.inst 460700 # number of demand (read+write) misses 1064system.cpu0.l2cache.demand_misses::cpu0.data 1189050 # number of demand (read+write) misses 1065system.cpu0.l2cache.demand_misses::total 1666561 # number of demand (read+write) misses 1066system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9421 # number of overall misses 1067system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7390 # number of overall misses 1068system.cpu0.l2cache.overall_misses::cpu0.inst 460700 # number of overall misses 1069system.cpu0.l2cache.overall_misses::cpu0.data 1189050 # number of overall misses 1070system.cpu0.l2cache.overall_misses::total 1666561 # number of overall misses 1071system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 332469500 # number of ReadReq miss cycles 1072system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 285177500 # number of ReadReq miss cycles 1073system.cpu0.l2cache.ReadReq_miss_latency::total 617647000 # number of ReadReq miss cycles 1074system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 1968962500 # number of UpgradeReq miss cycles 1075system.cpu0.l2cache.UpgradeReq_miss_latency::total 1968962500 # number of UpgradeReq miss cycles 1076system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1588151500 # number of SCUpgradeReq miss cycles 1077system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1588151500 # number of SCUpgradeReq miss cycles 1078system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2987000 # number of SCUpgradeFailReq miss cycles 1079system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2987000 # number of SCUpgradeFailReq miss cycles 1080system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12588187000 # number of ReadExReq miss cycles 1081system.cpu0.l2cache.ReadExReq_miss_latency::total 12588187000 # number of ReadExReq miss cycles 1082system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 16045103500 # number of ReadCleanReq miss cycles 1083system.cpu0.l2cache.ReadCleanReq_miss_latency::total 16045103500 # number of ReadCleanReq miss cycles 1084system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 32885800500 # number of ReadSharedReq miss cycles 1085system.cpu0.l2cache.ReadSharedReq_miss_latency::total 32885800500 # number of ReadSharedReq miss cycles 1086system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 322469500 # number of InvalidateReq miss cycles 1087system.cpu0.l2cache.InvalidateReq_miss_latency::total 322469500 # number of InvalidateReq miss cycles 1088system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 332469500 # number of demand (read+write) miss cycles 1089system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 285177500 # number of demand (read+write) miss cycles 1090system.cpu0.l2cache.demand_miss_latency::cpu0.inst 16045103500 # number of demand (read+write) miss cycles 1091system.cpu0.l2cache.demand_miss_latency::cpu0.data 45473987500 # number of demand (read+write) miss cycles 1092system.cpu0.l2cache.demand_miss_latency::total 62136738000 # number of demand (read+write) miss cycles 1093system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 332469500 # number of overall miss cycles 1094system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 285177500 # number of overall miss cycles 1095system.cpu0.l2cache.overall_miss_latency::cpu0.inst 16045103500 # number of overall miss cycles 1096system.cpu0.l2cache.overall_miss_latency::cpu0.data 45473987500 # number of overall miss cycles 1097system.cpu0.l2cache.overall_miss_latency::total 62136738000 # number of overall miss cycles 1098system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 273281 # number of ReadReq accesses(hits+misses) 1099system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155420 # number of ReadReq accesses(hits+misses) 1100system.cpu0.l2cache.ReadReq_accesses::total 428701 # number of ReadReq accesses(hits+misses) 1101system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3764500 # number of WritebackDirty accesses(hits+misses) 1102system.cpu0.l2cache.WritebackDirty_accesses::total 3764500 # number of WritebackDirty accesses(hits+misses) 1103system.cpu0.l2cache.WritebackClean_accesses::writebacks 7067152 # number of WritebackClean accesses(hits+misses) 1104system.cpu0.l2cache.WritebackClean_accesses::total 7067152 # number of WritebackClean accesses(hits+misses) 1105system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244142 # number of UpgradeReq accesses(hits+misses) 1106system.cpu0.l2cache.UpgradeReq_accesses::total 244142 # number of UpgradeReq accesses(hits+misses) 1107system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 205138 # number of SCUpgradeReq accesses(hits+misses) 1108system.cpu0.l2cache.SCUpgradeReq_accesses::total 205138 # number of SCUpgradeReq accesses(hits+misses) 1109system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1110system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1111system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1155718 # number of ReadExReq accesses(hits+misses) 1112system.cpu0.l2cache.ReadExReq_accesses::total 1155718 # number of ReadExReq accesses(hits+misses) 1113system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5143417 # number of ReadCleanReq accesses(hits+misses) 1114system.cpu0.l2cache.ReadCleanReq_accesses::total 5143417 # number of ReadCleanReq accesses(hits+misses) 1115system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3840345 # number of ReadSharedReq accesses(hits+misses) 1116system.cpu0.l2cache.ReadSharedReq_accesses::total 3840345 # number of ReadSharedReq accesses(hits+misses) 1117system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790706 # number of InvalidateReq accesses(hits+misses) 1118system.cpu0.l2cache.InvalidateReq_accesses::total 790706 # number of InvalidateReq accesses(hits+misses) 1119system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 273281 # number of demand (read+write) accesses 1120system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155420 # number of demand (read+write) accesses 1121system.cpu0.l2cache.demand_accesses::cpu0.inst 5143417 # number of demand (read+write) accesses 1122system.cpu0.l2cache.demand_accesses::cpu0.data 4996063 # number of demand (read+write) accesses 1123system.cpu0.l2cache.demand_accesses::total 10568181 # number of demand (read+write) accesses 1124system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 273281 # number of overall (read+write) accesses 1125system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155420 # number of overall (read+write) accesses 1126system.cpu0.l2cache.overall_accesses::cpu0.inst 5143417 # number of overall (read+write) accesses 1127system.cpu0.l2cache.overall_accesses::cpu0.data 4996063 # number of overall (read+write) accesses 1128system.cpu0.l2cache.overall_accesses::total 10568181 # number of overall (read+write) accesses 1129system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for ReadReq accesses 1130system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047549 # miss rate for ReadReq accesses 1131system.cpu0.l2cache.ReadReq_miss_rate::total 0.039214 # miss rate for ReadReq accesses 1132system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998390 # miss rate for UpgradeReq accesses 1133system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998390 # miss rate for UpgradeReq accesses 1134system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1135system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1136system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1137system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1138system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.217362 # miss rate for ReadExReq accesses 1139system.cpu0.l2cache.ReadExReq_miss_rate::total 0.217362 # miss rate for ReadExReq accesses 1140system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089571 # miss rate for ReadCleanReq accesses 1141system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089571 # miss rate for ReadCleanReq accesses 1142system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244207 # miss rate for ReadSharedReq accesses 1143system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244207 # miss rate for ReadSharedReq accesses 1144system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730498 # miss rate for InvalidateReq accesses 1145system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730498 # miss rate for InvalidateReq accesses 1146system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for demand accesses 1147system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047549 # miss rate for demand accesses 1148system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089571 # miss rate for demand accesses 1149system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237997 # miss rate for demand accesses 1150system.cpu0.l2cache.demand_miss_rate::total 0.157696 # miss rate for demand accesses 1151system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.034474 # miss rate for overall accesses 1152system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047549 # miss rate for overall accesses 1153system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089571 # miss rate for overall accesses 1154system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237997 # miss rate for overall accesses 1155system.cpu0.l2cache.overall_miss_rate::total 0.157696 # miss rate for overall accesses 1156system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average ReadReq miss latency 1157system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38589.648173 # average ReadReq miss latency 1158system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36740.646006 # average ReadReq miss latency 1159system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 8077.828012 # average UpgradeReq miss latency 1160system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8077.828012 # average UpgradeReq miss latency 1161system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7741.868888 # average SCUpgradeReq miss latency 1162system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7741.868888 # average SCUpgradeReq miss latency 1163system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 373375 # average SCUpgradeFailReq miss latency 1164system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 373375 # average SCUpgradeFailReq miss latency 1165system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50110.414038 # average ReadExReq miss latency 1166system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50110.414038 # average ReadExReq miss latency 1167system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34827.661168 # average ReadCleanReq miss latency 1168system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34827.661168 # average ReadCleanReq miss latency 1169system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35065.432733 # average ReadSharedReq miss latency 1170system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35065.432733 # average ReadSharedReq miss latency 1171system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 558.283372 # average InvalidateReq miss latency 1172system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 558.283372 # average InvalidateReq miss latency 1173system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average overall miss latency 1174system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38589.648173 # average overall miss latency 1175system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34827.661168 # average overall miss latency 1176system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38243.965771 # average overall miss latency 1177system.cpu0.l2cache.demand_avg_miss_latency::total 37284.406631 # average overall miss latency 1178system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35290.255811 # average overall miss latency 1179system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38589.648173 # average overall miss latency 1180system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34827.661168 # average overall miss latency 1181system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38243.965771 # average overall miss latency 1182system.cpu0.l2cache.overall_avg_miss_latency::total 37284.406631 # average overall miss latency 1183system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu0.l2cache.unused_prefetches 37568 # number of HardPF blocks evicted w/o reference 1190system.cpu0.l2cache.writebacks::writebacks 1506522 # number of writebacks 1191system.cpu0.l2cache.writebacks::total 1506522 # number of writebacks 1192system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5548 # number of ReadExReq MSHR hits 1193system.cpu0.l2cache.ReadExReq_mshr_hits::total 5548 # number of ReadExReq MSHR hits 1194system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 408 # number of ReadSharedReq MSHR hits 1195system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 408 # number of ReadSharedReq MSHR hits 1196system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5956 # number of demand (read+write) MSHR hits 1197system.cpu0.l2cache.demand_mshr_hits::total 5956 # number of demand (read+write) MSHR hits 1198system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5956 # number of overall MSHR hits 1199system.cpu0.l2cache.overall_mshr_hits::total 5956 # number of overall MSHR hits 1200system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9421 # number of ReadReq MSHR misses 1201system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7390 # number of ReadReq MSHR misses 1202system.cpu0.l2cache.ReadReq_mshr_misses::total 16811 # number of ReadReq MSHR misses 1203system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 719381 # number of HardPFReq MSHR misses 1204system.cpu0.l2cache.HardPFReq_mshr_misses::total 719381 # number of HardPFReq MSHR misses 1205system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 243749 # number of UpgradeReq MSHR misses 1206system.cpu0.l2cache.UpgradeReq_mshr_misses::total 243749 # number of UpgradeReq MSHR misses 1207system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 205138 # number of SCUpgradeReq MSHR misses 1208system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 205138 # number of SCUpgradeReq MSHR misses 1209system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1210system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1211system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 245661 # number of ReadExReq MSHR misses 1212system.cpu0.l2cache.ReadExReq_mshr_misses::total 245661 # number of ReadExReq MSHR misses 1213system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 460700 # number of ReadCleanReq MSHR misses 1214system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 460700 # number of ReadCleanReq MSHR misses 1215system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 937433 # number of ReadSharedReq MSHR misses 1216system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 937433 # number of ReadSharedReq MSHR misses 1217system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577609 # number of InvalidateReq MSHR misses 1218system.cpu0.l2cache.InvalidateReq_mshr_misses::total 577609 # number of InvalidateReq MSHR misses 1219system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9421 # number of demand (read+write) MSHR misses 1220system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7390 # number of demand (read+write) MSHR misses 1221system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 460700 # number of demand (read+write) MSHR misses 1222system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1183094 # number of demand (read+write) MSHR misses 1223system.cpu0.l2cache.demand_mshr_misses::total 1660605 # number of demand (read+write) MSHR misses 1224system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9421 # number of overall MSHR misses 1225system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7390 # number of overall MSHR misses 1226system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 460700 # number of overall MSHR misses 1227system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1183094 # number of overall MSHR misses 1228system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 719381 # number of overall MSHR misses 1229system.cpu0.l2cache.overall_mshr_misses::total 2379986 # number of overall MSHR misses 1230system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1231system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable 1232system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70742 # number of ReadReq MSHR uncacheable 1233system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable 1234system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26565 # number of WriteReq MSHR uncacheable 1235system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1236system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses 1237system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 97307 # number of overall MSHR uncacheable misses 1238system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of ReadReq MSHR miss cycles 1239system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 240837500 # number of ReadReq MSHR miss cycles 1240system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 516781000 # number of ReadReq MSHR miss cycles 1241system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of HardPFReq MSHR miss cycles 1242system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32427966574 # number of HardPFReq MSHR miss cycles 1243system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5063458500 # number of UpgradeReq MSHR miss cycles 1244system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5063458500 # number of UpgradeReq MSHR miss cycles 1245system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3348331499 # number of SCUpgradeReq MSHR miss cycles 1246system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3348331499 # number of SCUpgradeReq MSHR miss cycles 1247system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2645000 # number of SCUpgradeFailReq MSHR miss cycles 1248system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2645000 # number of SCUpgradeFailReq MSHR miss cycles 1249system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10596762500 # number of ReadExReq MSHR miss cycles 1250system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10596762500 # number of ReadExReq MSHR miss cycles 1251system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13280903500 # number of ReadCleanReq MSHR miss cycles 1252system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13280903500 # number of ReadCleanReq MSHR miss cycles 1253system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27229516500 # number of ReadSharedReq MSHR miss cycles 1254system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27229516500 # number of ReadSharedReq MSHR miss cycles 1255system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18926305000 # number of InvalidateReq MSHR miss cycles 1256system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18926305000 # number of InvalidateReq MSHR miss cycles 1257system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of demand (read+write) MSHR miss cycles 1258system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 240837500 # number of demand (read+write) MSHR miss cycles 1259system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13280903500 # number of demand (read+write) MSHR miss cycles 1260system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37826279000 # number of demand (read+write) MSHR miss cycles 1261system.cpu0.l2cache.demand_mshr_miss_latency::total 51623963500 # number of demand (read+write) MSHR miss cycles 1262system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 275943500 # number of overall MSHR miss cycles 1263system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 240837500 # number of overall MSHR miss cycles 1264system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13280903500 # number of overall MSHR miss cycles 1265system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37826279000 # number of overall MSHR miss cycles 1266system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32427966574 # number of overall MSHR miss cycles 1267system.cpu0.l2cache.overall_mshr_miss_latency::total 84051930074 # number of overall MSHR miss cycles 1268system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles 1269system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850886500 # number of ReadReq MSHR uncacheable cycles 1270system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346919000 # number of ReadReq MSHR uncacheable cycles 1271system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles 1272system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850886500 # number of overall MSHR uncacheable cycles 1273system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346919000 # number of overall MSHR uncacheable cycles 1274system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for ReadReq accesses 1275system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for ReadReq accesses 1276system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.039214 # mshr miss rate for ReadReq accesses 1277system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1278system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1279system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998390 # mshr miss rate for UpgradeReq accesses 1280system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998390 # mshr miss rate for UpgradeReq accesses 1281system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1282system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1283system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1284system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1285system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212561 # mshr miss rate for ReadExReq accesses 1286system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212561 # mshr miss rate for ReadExReq accesses 1287system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for ReadCleanReq accesses 1288system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089571 # mshr miss rate for ReadCleanReq accesses 1289system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.244101 # mshr miss rate for ReadSharedReq accesses 1290system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244101 # mshr miss rate for ReadSharedReq accesses 1291system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730498 # mshr miss rate for InvalidateReq accesses 1292system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730498 # mshr miss rate for InvalidateReq accesses 1293system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for demand accesses 1294system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for demand accesses 1295system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for demand accesses 1296system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for demand accesses 1297system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses 1298system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034474 # mshr miss rate for overall accesses 1299system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047549 # mshr miss rate for overall accesses 1300system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089571 # mshr miss rate for overall accesses 1301system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236805 # mshr miss rate for overall accesses 1302system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1303system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225203 # mshr miss rate for overall accesses 1304system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average ReadReq mshr miss latency 1305system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average ReadReq mshr miss latency 1306system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30740.646006 # average ReadReq mshr miss latency 1307system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average HardPFReq mshr miss latency 1308system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45077.596675 # average HardPFReq mshr miss latency 1309system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20773.248301 # average UpgradeReq mshr miss latency 1310system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20773.248301 # average UpgradeReq mshr miss latency 1311system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16322.336666 # average SCUpgradeReq mshr miss latency 1312system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16322.336666 # average SCUpgradeReq mshr miss latency 1313system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 330625 # average SCUpgradeFailReq mshr miss latency 1314system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 330625 # average SCUpgradeFailReq mshr miss latency 1315system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43135.713443 # average ReadExReq mshr miss latency 1316system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43135.713443 # average ReadExReq mshr miss latency 1317system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average ReadCleanReq mshr miss latency 1318system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28827.661168 # average ReadCleanReq mshr miss latency 1319system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29046.893485 # average ReadSharedReq mshr miss latency 1320system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29046.893485 # average ReadSharedReq mshr miss latency 1321system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32766.637985 # average InvalidateReq mshr miss latency 1322system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32766.637985 # average InvalidateReq mshr miss latency 1323system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency 1324system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency 1325system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency 1326system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency 1327system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31087.443131 # average overall mshr miss latency 1328system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29290.255811 # average overall mshr miss latency 1329system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32589.648173 # average overall mshr miss latency 1330system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28827.661168 # average overall mshr miss latency 1331system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31972.336095 # average overall mshr miss latency 1332system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45077.596675 # average overall mshr miss latency 1333system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35316.144748 # average overall mshr miss latency 1334system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency 1335system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175648.567911 # average ReadReq mshr uncacheable latency 1336system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117990.995448 # average ReadReq mshr uncacheable latency 1337system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency 1338system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89529.483961 # average overall mshr uncacheable latency 1339system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85779.224516 # average overall mshr uncacheable latency 1340system.cpu0.toL2Bus.snoop_filter.tot_requests 22441141 # Total number of requests made to the snoop filter. 1341system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11511110 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1342system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1343system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. 1344system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1345system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1346system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1347system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution 1348system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution 1349system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution 1350system.cpu0.toL2Bus.trans_dist::WriteResp 26565 # Transaction distribution 1351system.cpu0.toL2Bus.trans_dist::WritebackDirty 5274768 # Transaction distribution 1352system.cpu0.toL2Bus.trans_dist::WritebackClean 7068022 # Transaction distribution 1353system.cpu0.toL2Bus.trans_dist::CleanEvict 2298392 # Transaction distribution 1354system.cpu0.toL2Bus.trans_dist::HardPFReq 883953 # Transaction distribution 1355system.cpu0.toL2Bus.trans_dist::UpgradeReq 441648 # Transaction distribution 1356system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 374962 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::UpgradeResp 517397 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::ReadExReq 1188175 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::ReadExResp 1165072 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5143417 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4741538 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::InvalidateReq 839102 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::InvalidateResp 790706 # Transaction distribution 1366system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15515989 # Packet count per connected master and slave (bytes) 1367system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18442402 # Packet count per connected master and slave (bytes) 1368system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326965 # Packet count per connected master and slave (bytes) 1369system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 595128 # Packet count per connected master and slave (bytes) 1370system.cpu0.toL2Bus.pkt_count::total 34880484 # Packet count per connected master and slave (bytes) 1371system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 658497108 # Cumulative packet size per connected master and slave (bytes) 1372system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690726071 # Cumulative packet size per connected master and slave (bytes) 1373system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1243360 # Cumulative packet size per connected master and slave (bytes) 1374system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2186248 # Cumulative packet size per connected master and slave (bytes) 1375system.cpu0.toL2Bus.pkt_size::total 1352652787 # Cumulative packet size per connected master and slave (bytes) 1376system.cpu0.toL2Bus.snoops 6279047 # Total snoops (count) 1377system.cpu0.toL2Bus.snoop_fanout::samples 18012222 # Request fanout histogram 1378system.cpu0.toL2Bus.snoop_fanout::mean 0.113865 # Request fanout histogram 1379system.cpu0.toL2Bus.snoop_fanout::stdev 0.317693 # Request fanout histogram 1380system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1381system.cpu0.toL2Bus.snoop_fanout::0 15961520 88.61% 88.61% # Request fanout histogram 1382system.cpu0.toL2Bus.snoop_fanout::1 2050439 11.38% 100.00% # Request fanout histogram 1383system.cpu0.toL2Bus.snoop_fanout::2 263 0.00% 100.00% # Request fanout histogram 1384system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1385system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1386system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1387system.cpu0.toL2Bus.snoop_fanout::total 18012222 # Request fanout histogram 1388system.cpu0.toL2Bus.reqLayer0.occupancy 22247152499 # Layer occupancy (ticks) 1389system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1390system.cpu0.toL2Bus.snoopLayer0.occupancy 190413774 # Layer occupancy (ticks) 1391system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1392system.cpu0.toL2Bus.respLayer0.occupancy 7758250500 # Layer occupancy (ticks) 1393system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1394system.cpu0.toL2Bus.respLayer1.occupancy 8155256101 # Layer occupancy (ticks) 1395system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1396system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # Layer occupancy (ticks) 1397system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1398system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) 1399system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1400system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1401system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1402system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1404system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1405system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1406system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1407system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1408system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1409system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1410system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1411system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1412system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1413system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1414system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1415system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1416system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1417system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1418system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1419system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1420system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1421system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1422system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1423system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1424system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1425system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1426system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1427system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1428system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1429system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1430system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1431system.cpu1.dtb.walker.walks 105013 # Table walker walks requested 1432system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors 1433system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate 1434system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79078 # Level at which table walker walks with long descriptors terminate 1435system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 1436system.cpu1.dtb.walker.walkWaitTime::samples 105006 # Table walker wait (enqueue to first request) latency 1437system.cpu1.dtb.walker.walkWaitTime::mean 0.076186 # Table walker wait (enqueue to first request) latency 1438system.cpu1.dtb.walker.walkWaitTime::stdev 24.687831 # Table walker wait (enqueue to first request) latency 1439system.cpu1.dtb.walker.walkWaitTime::0-511 105005 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1440system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1441system.cpu1.dtb.walker.walkWaitTime::total 105006 # Table walker wait (enqueue to first request) latency 1442system.cpu1.dtb.walker.walkCompletionTime::samples 89755 # Table walker service (enqueue to completion) latency 1443system.cpu1.dtb.walker.walkCompletionTime::mean 22913.865523 # Table walker service (enqueue to completion) latency 1444system.cpu1.dtb.walker.walkCompletionTime::gmean 21179.498457 # Table walker service (enqueue to completion) latency 1445system.cpu1.dtb.walker.walkCompletionTime::stdev 15867.258739 # Table walker service (enqueue to completion) latency 1446system.cpu1.dtb.walker.walkCompletionTime::0-65535 88364 98.45% 98.45% # Table walker service (enqueue to completion) latency 1447system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1205 1.34% 99.79% # Table walker service (enqueue to completion) latency 1448system.cpu1.dtb.walker.walkCompletionTime::131072-196607 34 0.04% 99.83% # Table walker service (enqueue to completion) latency 1449system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.08% 99.91% # Table walker service (enqueue to completion) latency 1450system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.07% 99.97% # Table walker service (enqueue to completion) latency 1451system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 1452system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1453system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1454system.cpu1.dtb.walker.walkCompletionTime::total 89755 # Table walker service (enqueue to completion) latency 1455system.cpu1.dtb.walker.walksPending::samples -3159480544 # Table walker pending requests distribution 1456system.cpu1.dtb.walker.walksPending::mean 0.804201 # Table walker pending requests distribution 1457system.cpu1.dtb.walker.walksPending::stdev 0.396815 # Table walker pending requests distribution 1458system.cpu1.dtb.walker.walksPending::0 -618623648 19.58% 19.58% # Table walker pending requests distribution 1459system.cpu1.dtb.walker.walksPending::1 -2540856896 80.42% 100.00% # Table walker pending requests distribution 1460system.cpu1.dtb.walker.walksPending::total -3159480544 # Table walker pending requests distribution 1461system.cpu1.dtb.walker.walkPageSizes::4K 79078 88.11% 88.11% # Table walker page sizes translated 1462system.cpu1.dtb.walker.walkPageSizes::2M 10670 11.89% 100.00% # Table walker page sizes translated 1463system.cpu1.dtb.walker.walkPageSizes::total 89748 # Table walker page sizes translated 1464system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105013 # Table walker requests started/completed, data/inst 1465system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1466system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105013 # Table walker requests started/completed, data/inst 1467system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89748 # Table walker requests started/completed, data/inst 1468system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1469system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89748 # Table walker requests started/completed, data/inst 1470system.cpu1.dtb.walker.walkRequestOrigin::total 194761 # Table walker requests started/completed, data/inst 1471system.cpu1.dtb.inst_hits 0 # ITB inst hits 1472system.cpu1.dtb.inst_misses 0 # ITB inst misses 1473system.cpu1.dtb.read_hits 79229823 # DTB read hits 1474system.cpu1.dtb.read_misses 76992 # DTB read misses 1475system.cpu1.dtb.write_hits 72255246 # DTB write hits 1476system.cpu1.dtb.write_misses 28021 # DTB write misses 1477system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1478system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1479system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1480system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1481system.cpu1.dtb.flush_entries 37178 # Number of entries that have been flushed from TLB	1481system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB
1482system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1483system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch 1484system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1485system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions 1486system.cpu1.dtb.read_accesses 79306815 # DTB read accesses 1487system.cpu1.dtb.write_accesses 72283267 # DTB write accesses 1488system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1489system.cpu1.dtb.hits 151485069 # DTB hits 1490system.cpu1.dtb.misses 105013 # DTB misses 1491system.cpu1.dtb.accesses 151590082 # DTB accesses 1492system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1493system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1494system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1495system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1496system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1497system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1498system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1499system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1500system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1501system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1502system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1503system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1504system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1505system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1506system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1507system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1508system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1509system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1510system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1511system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1512system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1513system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1514system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1515system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1516system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1517system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1518system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1519system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1520system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1521system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1522system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1523system.cpu1.itb.walker.walks 58945 # Table walker walks requested 1524system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors 1525system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate 1526system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate 1527system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency 1528system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1529system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency 1530system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency 1531system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928 # Table walker service (enqueue to completion) latency 1532system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193 # Table walker service (enqueue to completion) latency 1533system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304 # Table walker service (enqueue to completion) latency 1534system.cpu1.itb.walker.walkCompletionTime::0-32767 48130 89.77% 89.77% # Table walker service (enqueue to completion) latency 1535system.cpu1.itb.walker.walkCompletionTime::32768-65535 4065 7.58% 97.36% # Table walker service (enqueue to completion) latency 1536system.cpu1.itb.walker.walkCompletionTime::65536-98303 53 0.10% 97.45% # Table walker service (enqueue to completion) latency 1537system.cpu1.itb.walker.walkCompletionTime::98304-131071 1140 2.13% 99.58% # Table walker service (enqueue to completion) latency 1538system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.64% # Table walker service (enqueue to completion) latency 1539system.cpu1.itb.walker.walkCompletionTime::163840-196607 18 0.03% 99.67% # Table walker service (enqueue to completion) latency 1540system.cpu1.itb.walker.walkCompletionTime::196608-229375 57 0.11% 99.78% # Table walker service (enqueue to completion) latency 1541system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.82% # Table walker service (enqueue to completion) latency 1542system.cpu1.itb.walker.walkCompletionTime::262144-294911 51 0.10% 99.91% # Table walker service (enqueue to completion) latency 1543system.cpu1.itb.walker.walkCompletionTime::294912-327679 22 0.04% 99.96% # Table walker service (enqueue to completion) latency 1544system.cpu1.itb.walker.walkCompletionTime::327680-360447 16 0.03% 99.99% # Table walker service (enqueue to completion) latency 1545system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1546system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 1547system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1548system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::total 53613 # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walksPending::samples -1503172148 # Table walker pending requests distribution 1551system.cpu1.itb.walker.walksPending::0 -1503172148 100.00% 100.00% # Table walker pending requests distribution 1552system.cpu1.itb.walker.walksPending::total -1503172148 # Table walker pending requests distribution 1553system.cpu1.itb.walker.walkPageSizes::4K 53052 98.95% 98.95% # Table walker page sizes translated 1554system.cpu1.itb.walker.walkPageSizes::2M 561 1.05% 100.00% # Table walker page sizes translated 1555system.cpu1.itb.walker.walkPageSizes::total 53613 # Table walker page sizes translated 1556system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1557system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58945 # Table walker requests started/completed, data/inst 1558system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58945 # Table walker requests started/completed, data/inst 1559system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1560system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53613 # Table walker requests started/completed, data/inst 1561system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53613 # Table walker requests started/completed, data/inst 1562system.cpu1.itb.walker.walkRequestOrigin::total 112558 # Table walker requests started/completed, data/inst 1563system.cpu1.itb.inst_hits 420888418 # ITB inst hits 1564system.cpu1.itb.inst_misses 58945 # ITB inst misses 1565system.cpu1.itb.read_hits 0 # DTB read hits 1566system.cpu1.itb.read_misses 0 # DTB read misses 1567system.cpu1.itb.write_hits 0 # DTB write hits 1568system.cpu1.itb.write_misses 0 # DTB write misses 1569system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1570system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1571system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1572system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID	1482system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1483system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch 1484system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1485system.cpu1.dtb.perms_faults 10425 # Number of TLB faults due to permissions restrictions 1486system.cpu1.dtb.read_accesses 79306815 # DTB read accesses 1487system.cpu1.dtb.write_accesses 72283267 # DTB write accesses 1488system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1489system.cpu1.dtb.hits 151485069 # DTB hits 1490system.cpu1.dtb.misses 105013 # DTB misses 1491system.cpu1.dtb.accesses 151590082 # DTB accesses 1492system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1493system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1494system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1495system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1496system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1497system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1498system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1499system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1500system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1501system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1502system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1503system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1504system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1505system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1506system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1507system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1508system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1509system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1510system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1511system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1512system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1513system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1514system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1515system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1516system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1517system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1518system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1519system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1520system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1521system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1522system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1523system.cpu1.itb.walker.walks 58945 # Table walker walks requested 1524system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors 1525system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate 1526system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53052 # Level at which table walker walks with long descriptors terminate 1527system.cpu1.itb.walker.walkWaitTime::samples 58945 # Table walker wait (enqueue to first request) latency 1528system.cpu1.itb.walker.walkWaitTime::0 58945 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1529system.cpu1.itb.walker.walkWaitTime::total 58945 # Table walker wait (enqueue to first request) latency 1530system.cpu1.itb.walker.walkCompletionTime::samples 53613 # Table walker service (enqueue to completion) latency 1531system.cpu1.itb.walker.walkCompletionTime::mean 26471.741928 # Table walker service (enqueue to completion) latency 1532system.cpu1.itb.walker.walkCompletionTime::gmean 23919.780193 # Table walker service (enqueue to completion) latency 1533system.cpu1.itb.walker.walkCompletionTime::stdev 20610.282304 # Table walker service (enqueue to completion) latency 1534system.cpu1.itb.walker.walkCompletionTime::0-32767 48130 89.77% 89.77% # Table walker service (enqueue to completion) latency 1535system.cpu1.itb.walker.walkCompletionTime::32768-65535 4065 7.58% 97.36% # Table walker service (enqueue to completion) latency 1536system.cpu1.itb.walker.walkCompletionTime::65536-98303 53 0.10% 97.45% # Table walker service (enqueue to completion) latency 1537system.cpu1.itb.walker.walkCompletionTime::98304-131071 1140 2.13% 99.58% # Table walker service (enqueue to completion) latency 1538system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.64% # Table walker service (enqueue to completion) latency 1539system.cpu1.itb.walker.walkCompletionTime::163840-196607 18 0.03% 99.67% # Table walker service (enqueue to completion) latency 1540system.cpu1.itb.walker.walkCompletionTime::196608-229375 57 0.11% 99.78% # Table walker service (enqueue to completion) latency 1541system.cpu1.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.82% # Table walker service (enqueue to completion) latency 1542system.cpu1.itb.walker.walkCompletionTime::262144-294911 51 0.10% 99.91% # Table walker service (enqueue to completion) latency 1543system.cpu1.itb.walker.walkCompletionTime::294912-327679 22 0.04% 99.96% # Table walker service (enqueue to completion) latency 1544system.cpu1.itb.walker.walkCompletionTime::327680-360447 16 0.03% 99.99% # Table walker service (enqueue to completion) latency 1545system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1546system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 1547system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1548system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::total 53613 # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walksPending::samples -1503172148 # Table walker pending requests distribution 1551system.cpu1.itb.walker.walksPending::0 -1503172148 100.00% 100.00% # Table walker pending requests distribution 1552system.cpu1.itb.walker.walksPending::total -1503172148 # Table walker pending requests distribution 1553system.cpu1.itb.walker.walkPageSizes::4K 53052 98.95% 98.95% # Table walker page sizes translated 1554system.cpu1.itb.walker.walkPageSizes::2M 561 1.05% 100.00% # Table walker page sizes translated 1555system.cpu1.itb.walker.walkPageSizes::total 53613 # Table walker page sizes translated 1556system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1557system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58945 # Table walker requests started/completed, data/inst 1558system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58945 # Table walker requests started/completed, data/inst 1559system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1560system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53613 # Table walker requests started/completed, data/inst 1561system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53613 # Table walker requests started/completed, data/inst 1562system.cpu1.itb.walker.walkRequestOrigin::total 112558 # Table walker requests started/completed, data/inst 1563system.cpu1.itb.inst_hits 420888418 # ITB inst hits 1564system.cpu1.itb.inst_misses 58945 # ITB inst misses 1565system.cpu1.itb.read_hits 0 # DTB read hits 1566system.cpu1.itb.read_misses 0 # DTB read misses 1567system.cpu1.itb.write_hits 0 # DTB write hits 1568system.cpu1.itb.write_misses 0 # DTB write misses 1569system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1570system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1571system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID 1572system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1573system.cpu1.itb.flush_entries 25875 # Number of entries that have been flushed from TLB	1573system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB
1574system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1575system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1576system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1577system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1578system.cpu1.itb.read_accesses 0 # DTB read accesses 1579system.cpu1.itb.write_accesses 0 # DTB write accesses 1580system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses 1581system.cpu1.itb.hits 420888418 # DTB hits 1582system.cpu1.itb.misses 58945 # DTB misses 1583system.cpu1.itb.accesses 420947363 # DTB accesses 1584system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions 1585system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state 1586system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state 1587system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state 1588system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state 1589system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state 1590system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state 1591system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state 1592system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 1593system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 1594system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 1595system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state 1596system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1597system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state 1598system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state 1599system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states 1600system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states 1601system.cpu1.numCycles 95045540824 # number of cpu cycles simulated 1602system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1603system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1604system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1605system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed 1606system.cpu1.committedInsts 420606589 # Number of instructions committed 1607system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed 1608system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses 1609system.cpu1.num_fp_alu_accesses 465343 # Number of float alu accesses 1610system.cpu1.num_func_calls 25050170 # number of times a function call or return occured 1611system.cpu1.num_conditional_control_insts 64233743 # number of instructions that are conditional controls 1612system.cpu1.num_int_insts 455422102 # number of integer instructions 1613system.cpu1.num_fp_insts 465343 # number of float instructions 1614system.cpu1.num_int_register_reads 665130045 # number of times the integer registers were read 1615system.cpu1.num_int_register_writes 361560137 # number of times the integer registers were written 1616system.cpu1.num_fp_register_reads 742394 # number of times the floating registers were read 1617system.cpu1.num_fp_register_writes 410584 # number of times the floating registers were written 1618system.cpu1.num_cc_register_reads 110025684 # number of times the CC registers were read 1619system.cpu1.num_cc_register_writes 109785328 # number of times the CC registers were written 1620system.cpu1.num_mem_refs 151477231 # number of memory refs 1621system.cpu1.num_load_insts 79227868 # Number of load instructions 1622system.cpu1.num_store_insts 72249363 # Number of store instructions 1623system.cpu1.num_idle_cycles 94048242615.068481 # Number of idle cycles 1624system.cpu1.num_busy_cycles 997298208.931515 # Number of busy cycles 1625system.cpu1.not_idle_fraction 0.010493 # Percentage of non-idle cycles 1626system.cpu1.idle_fraction 0.989507 # Percentage of idle cycles 1627system.cpu1.Branches 93889993 # Number of branches fetched 1628system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1629system.cpu1.op_class::IntAlu 343412693 69.23% 69.23% # Class of executed instruction 1630system.cpu1.op_class::IntMult 1029907 0.21% 69.44% # Class of executed instruction 1631system.cpu1.op_class::IntDiv 56328 0.01% 69.45% # Class of executed instruction 1632system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction 1633system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction 1634system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction 1635system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction 1636system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction 1637system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction 1638system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction 1639system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction 1640system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction 1641system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction 1642system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction 1643system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction 1644system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction 1645system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction 1646system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction 1647system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction 1648system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction 1649system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.45% # Class of executed instruction 1650system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction 1651system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.45% # Class of executed instruction 1652system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.45% # Class of executed instruction 1653system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction 1654system.cpu1.op_class::SimdFloatMisc 66396 0.01% 69.46% # Class of executed instruction 1655system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction 1656system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction 1657system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction 1658system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction 1659system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction 1660system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1661system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1662system.cpu1.op_class::total 496042597 # Class of executed instruction 1663system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1664system.cpu1.dcache.tags.replacements 5018466 # number of replacements 1665system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use 1666system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. 1667system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. 1668system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. 1669system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. 1670system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor 1671system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy 1672system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy 1673system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1674system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1675system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 1676system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 1677system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1678system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1679system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses 1680system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses 1681system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1682system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits 1683system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits 1684system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits 1685system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits 1686system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits 1687system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits 1688system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits 1689system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits 1690system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1665176 # number of LoadLockedReq hits 1691system.cpu1.dcache.LoadLockedReq_hits::total 1665176 # number of LoadLockedReq hits 1692system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1621987 # number of StoreCondReq hits 1693system.cpu1.dcache.StoreCondReq_hits::total 1621987 # number of StoreCondReq hits 1694system.cpu1.dcache.demand_hits::cpu1.data 142401211 # number of demand (read+write) hits 1695system.cpu1.dcache.demand_hits::total 142401211 # number of demand (read+write) hits 1696system.cpu1.dcache.overall_hits::cpu1.data 142575772 # number of overall hits 1697system.cpu1.dcache.overall_hits::total 142575772 # number of overall hits 1698system.cpu1.dcache.ReadReq_misses::cpu1.data 2838030 # number of ReadReq misses 1699system.cpu1.dcache.ReadReq_misses::total 2838030 # number of ReadReq misses 1700system.cpu1.dcache.WriteReq_misses::cpu1.data 1310627 # number of WriteReq misses 1701system.cpu1.dcache.WriteReq_misses::total 1310627 # number of WriteReq misses 1702system.cpu1.dcache.SoftPFReq_misses::cpu1.data 624714 # number of SoftPFReq misses 1703system.cpu1.dcache.SoftPFReq_misses::total 624714 # number of SoftPFReq misses 1704system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447850 # number of WriteLineReq misses 1705system.cpu1.dcache.WriteLineReq_misses::total 447850 # number of WriteLineReq misses 1706system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162703 # number of LoadLockedReq misses 1707system.cpu1.dcache.LoadLockedReq_misses::total 162703 # number of LoadLockedReq misses 1708system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204676 # number of StoreCondReq misses 1709system.cpu1.dcache.StoreCondReq_misses::total 204676 # number of StoreCondReq misses 1710system.cpu1.dcache.demand_misses::cpu1.data 4596507 # number of demand (read+write) misses 1711system.cpu1.dcache.demand_misses::total 4596507 # number of demand (read+write) misses 1712system.cpu1.dcache.overall_misses::cpu1.data 5221221 # number of overall misses 1713system.cpu1.dcache.overall_misses::total 5221221 # number of overall misses 1714system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40862074000 # number of ReadReq miss cycles 1715system.cpu1.dcache.ReadReq_miss_latency::total 40862074000 # number of ReadReq miss cycles 1716system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24688918000 # number of WriteReq miss cycles 1717system.cpu1.dcache.WriteReq_miss_latency::total 24688918000 # number of WriteReq miss cycles 1718system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10778682000 # number of WriteLineReq miss cycles 1719system.cpu1.dcache.WriteLineReq_miss_latency::total 10778682000 # number of WriteLineReq miss cycles 1720system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2442456000 # number of LoadLockedReq miss cycles 1721system.cpu1.dcache.LoadLockedReq_miss_latency::total 2442456000 # number of LoadLockedReq miss cycles 1722system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5069864000 # number of StoreCondReq miss cycles 1723system.cpu1.dcache.StoreCondReq_miss_latency::total 5069864000 # number of StoreCondReq miss cycles 1724system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3108000 # number of StoreCondFailReq miss cycles 1725system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3108000 # number of StoreCondFailReq miss cycles 1726system.cpu1.dcache.demand_miss_latency::cpu1.data 76329674000 # number of demand (read+write) miss cycles 1727system.cpu1.dcache.demand_miss_latency::total 76329674000 # number of demand (read+write) miss cycles 1728system.cpu1.dcache.overall_miss_latency::cpu1.data 76329674000 # number of overall miss cycles 1729system.cpu1.dcache.overall_miss_latency::total 76329674000 # number of overall miss cycles 1730system.cpu1.dcache.ReadReq_accesses::cpu1.data 76591652 # number of ReadReq accesses(hits+misses) 1731system.cpu1.dcache.ReadReq_accesses::total 76591652 # number of ReadReq accesses(hits+misses) 1732system.cpu1.dcache.WriteReq_accesses::cpu1.data 69796106 # number of WriteReq accesses(hits+misses) 1733system.cpu1.dcache.WriteReq_accesses::total 69796106 # number of WriteReq accesses(hits+misses) 1734system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799275 # number of SoftPFReq accesses(hits+misses) 1735system.cpu1.dcache.SoftPFReq_accesses::total 799275 # number of SoftPFReq accesses(hits+misses) 1736system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 609960 # number of WriteLineReq accesses(hits+misses) 1737system.cpu1.dcache.WriteLineReq_accesses::total 609960 # number of WriteLineReq accesses(hits+misses) 1738system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1827879 # number of LoadLockedReq accesses(hits+misses) 1739system.cpu1.dcache.LoadLockedReq_accesses::total 1827879 # number of LoadLockedReq accesses(hits+misses) 1740system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1826663 # number of StoreCondReq accesses(hits+misses) 1741system.cpu1.dcache.StoreCondReq_accesses::total 1826663 # number of StoreCondReq accesses(hits+misses) 1742system.cpu1.dcache.demand_accesses::cpu1.data 146997718 # number of demand (read+write) accesses 1743system.cpu1.dcache.demand_accesses::total 146997718 # number of demand (read+write) accesses 1744system.cpu1.dcache.overall_accesses::cpu1.data 147796993 # number of overall (read+write) accesses 1745system.cpu1.dcache.overall_accesses::total 147796993 # number of overall (read+write) accesses 1746system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037054 # miss rate for ReadReq accesses 1747system.cpu1.dcache.ReadReq_miss_rate::total 0.037054 # miss rate for ReadReq accesses 1748system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018778 # miss rate for WriteReq accesses 1749system.cpu1.dcache.WriteReq_miss_rate::total 0.018778 # miss rate for WriteReq accesses 1750system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.781601 # miss rate for SoftPFReq accesses 1751system.cpu1.dcache.SoftPFReq_miss_rate::total 0.781601 # miss rate for SoftPFReq accesses 1752system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734228 # miss rate for WriteLineReq accesses 1753system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734228 # miss rate for WriteLineReq accesses 1754system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089012 # miss rate for LoadLockedReq accesses 1755system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089012 # miss rate for LoadLockedReq accesses 1756system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112049 # miss rate for StoreCondReq accesses 1757system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112049 # miss rate for StoreCondReq accesses 1758system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031269 # miss rate for demand accesses 1759system.cpu1.dcache.demand_miss_rate::total 0.031269 # miss rate for demand accesses 1760system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035327 # miss rate for overall accesses 1761system.cpu1.dcache.overall_miss_rate::total 0.035327 # miss rate for overall accesses 1762system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599 # average ReadReq miss latency 1763system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599 # average ReadReq miss latency 1764system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180 # average WriteReq miss latency 1765system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180 # average WriteReq miss latency 1766system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389 # average WriteLineReq miss latency 1767system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389 # average WriteLineReq miss latency 1768system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327 # average LoadLockedReq miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327 # average LoadLockedReq miss latency 1770system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890 # average StoreCondReq miss latency 1771system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890 # average StoreCondReq miss latency 1772system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1773system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1774system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134 # average overall miss latency 1775system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134 # average overall miss latency 1776system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381 # average overall miss latency 1777system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381 # average overall miss latency 1778system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1779system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1780system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1781system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1782system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1783system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1784system.cpu1.dcache.writebacks::writebacks 5018466 # number of writebacks 1785system.cpu1.dcache.writebacks::total 5018466 # number of writebacks 1786system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16365 # number of ReadReq MSHR hits 1787system.cpu1.dcache.ReadReq_mshr_hits::total 16365 # number of ReadReq MSHR hits 1788system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 405 # number of WriteReq MSHR hits 1789system.cpu1.dcache.WriteReq_mshr_hits::total 405 # number of WriteReq MSHR hits 1790system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42163 # number of LoadLockedReq MSHR hits 1791system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42163 # number of LoadLockedReq MSHR hits 1792system.cpu1.dcache.demand_mshr_hits::cpu1.data 16770 # number of demand (read+write) MSHR hits 1793system.cpu1.dcache.demand_mshr_hits::total 16770 # number of demand (read+write) MSHR hits 1794system.cpu1.dcache.overall_mshr_hits::cpu1.data 16770 # number of overall MSHR hits 1795system.cpu1.dcache.overall_mshr_hits::total 16770 # number of overall MSHR hits 1796system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2821665 # number of ReadReq MSHR misses 1797system.cpu1.dcache.ReadReq_mshr_misses::total 2821665 # number of ReadReq MSHR misses 1798system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1310222 # number of WriteReq MSHR misses 1799system.cpu1.dcache.WriteReq_mshr_misses::total 1310222 # number of WriteReq MSHR misses 1800system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 624714 # number of SoftPFReq MSHR misses 1801system.cpu1.dcache.SoftPFReq_mshr_misses::total 624714 # number of SoftPFReq MSHR misses 1802system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 447850 # number of WriteLineReq MSHR misses 1803system.cpu1.dcache.WriteLineReq_mshr_misses::total 447850 # number of WriteLineReq MSHR misses 1804system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses 1805system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses 1806system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204676 # number of StoreCondReq MSHR misses 1807system.cpu1.dcache.StoreCondReq_mshr_misses::total 204676 # number of StoreCondReq MSHR misses 1808system.cpu1.dcache.demand_mshr_misses::cpu1.data 4579737 # number of demand (read+write) MSHR misses 1809system.cpu1.dcache.demand_mshr_misses::total 4579737 # number of demand (read+write) MSHR misses 1810system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204451 # number of overall MSHR misses 1811system.cpu1.dcache.overall_mshr_misses::total 5204451 # number of overall MSHR misses 1812system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable 1813system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11035 # number of ReadReq MSHR uncacheable 1814system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable 1815system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable 1816system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses 1817system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22984 # number of overall MSHR uncacheable misses 1818system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37160053500 # number of ReadReq MSHR miss cycles 1819system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37160053500 # number of ReadReq MSHR miss cycles 1820system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23356658000 # number of WriteReq MSHR miss cycles 1821system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23356658000 # number of WriteReq MSHR miss cycles 1822system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12967475000 # number of SoftPFReq MSHR miss cycles 1823system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12967475000 # number of SoftPFReq MSHR miss cycles 1824system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10330832000 # number of WriteLineReq MSHR miss cycles 1825system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10330832000 # number of WriteLineReq MSHR miss cycles 1826system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654542500 # number of LoadLockedReq MSHR miss cycles 1827system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1654542500 # number of LoadLockedReq MSHR miss cycles 1828system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4865246000 # number of StoreCondReq MSHR miss cycles 1829system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4865246000 # number of StoreCondReq MSHR miss cycles 1830system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3050000 # number of StoreCondFailReq MSHR miss cycles 1831system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3050000 # number of StoreCondFailReq MSHR miss cycles 1832system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70847543500 # number of demand (read+write) MSHR miss cycles 1833system.cpu1.dcache.demand_mshr_miss_latency::total 70847543500 # number of demand (read+write) MSHR miss cycles 1834system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83815018500 # number of overall MSHR miss cycles 1835system.cpu1.dcache.overall_mshr_miss_latency::total 83815018500 # number of overall MSHR miss cycles 1836system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1894238000 # number of ReadReq MSHR uncacheable cycles 1837system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1894238000 # number of ReadReq MSHR uncacheable cycles 1838system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1894238000 # number of overall MSHR uncacheable cycles 1839system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1894238000 # number of overall MSHR uncacheable cycles 1840system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036840 # mshr miss rate for ReadReq accesses 1841system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036840 # mshr miss rate for ReadReq accesses 1842system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018772 # mshr miss rate for WriteReq accesses 1843system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018772 # mshr miss rate for WriteReq accesses 1844system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.781601 # mshr miss rate for SoftPFReq accesses 1845system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.781601 # mshr miss rate for SoftPFReq accesses 1846system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734228 # mshr miss rate for WriteLineReq accesses 1847system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734228 # mshr miss rate for WriteLineReq accesses 1848system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065945 # mshr miss rate for LoadLockedReq accesses 1849system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065945 # mshr miss rate for LoadLockedReq accesses 1850system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112049 # mshr miss rate for StoreCondReq accesses 1851system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112049 # mshr miss rate for StoreCondReq accesses 1852system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031155 # mshr miss rate for demand accesses 1853system.cpu1.dcache.demand_mshr_miss_rate::total 0.031155 # mshr miss rate for demand accesses 1854system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035214 # mshr miss rate for overall accesses 1855system.cpu1.dcache.overall_mshr_miss_rate::total 0.035214 # mshr miss rate for overall accesses 1856system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299 # average ReadReq mshr miss latency 1857system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299 # average ReadReq mshr miss latency 1858system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946 # average WriteReq mshr miss latency 1859system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946 # average WriteReq mshr miss latency 1860system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613 # average SoftPFReq mshr miss latency 1861system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613 # average SoftPFReq mshr miss latency 1862system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389 # average WriteLineReq mshr miss latency 1863system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389 # average WriteLineReq mshr miss latency 1864system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776 # average LoadLockedReq mshr miss latency 1865system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776 # average LoadLockedReq mshr miss latency 1866system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265 # average StoreCondReq mshr miss latency 1867system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265 # average StoreCondReq mshr miss latency 1868system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1869system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1870system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency 1871system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency 1872system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency 1873system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency 1874system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency 1875system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency 1876system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency 1877system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency 1878system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1879system.cpu1.icache.tags.replacements 4797887 # number of replacements 1880system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use 1881system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. 1882system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. 1883system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. 1884system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. 1885system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor 1886system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy 1887system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy 1888system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1889system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 1890system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id 1891system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id 1892system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 1893system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1894system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses 1895system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses 1896system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1897system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits 1898system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits 1899system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits 1900system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits 1901system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits 1902system.cpu1.icache.overall_hits::total 416090013 # number of overall hits 1903system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses 1904system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses 1905system.cpu1.icache.demand_misses::cpu1.inst 4798405 # number of demand (read+write) misses 1906system.cpu1.icache.demand_misses::total 4798405 # number of demand (read+write) misses 1907system.cpu1.icache.overall_misses::cpu1.inst 4798405 # number of overall misses 1908system.cpu1.icache.overall_misses::total 4798405 # number of overall misses 1909system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50998473000 # number of ReadReq miss cycles 1910system.cpu1.icache.ReadReq_miss_latency::total 50998473000 # number of ReadReq miss cycles 1911system.cpu1.icache.demand_miss_latency::cpu1.inst 50998473000 # number of demand (read+write) miss cycles 1912system.cpu1.icache.demand_miss_latency::total 50998473000 # number of demand (read+write) miss cycles 1913system.cpu1.icache.overall_miss_latency::cpu1.inst 50998473000 # number of overall miss cycles 1914system.cpu1.icache.overall_miss_latency::total 50998473000 # number of overall miss cycles 1915system.cpu1.icache.ReadReq_accesses::cpu1.inst 420888418 # number of ReadReq accesses(hits+misses) 1916system.cpu1.icache.ReadReq_accesses::total 420888418 # number of ReadReq accesses(hits+misses) 1917system.cpu1.icache.demand_accesses::cpu1.inst 420888418 # number of demand (read+write) accesses 1918system.cpu1.icache.demand_accesses::total 420888418 # number of demand (read+write) accesses 1919system.cpu1.icache.overall_accesses::cpu1.inst 420888418 # number of overall (read+write) accesses 1920system.cpu1.icache.overall_accesses::total 420888418 # number of overall (read+write) accesses 1921system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011401 # miss rate for ReadReq accesses 1922system.cpu1.icache.ReadReq_miss_rate::total 0.011401 # miss rate for ReadReq accesses 1923system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011401 # miss rate for demand accesses 1924system.cpu1.icache.demand_miss_rate::total 0.011401 # miss rate for demand accesses 1925system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011401 # miss rate for overall accesses 1926system.cpu1.icache.overall_miss_rate::total 0.011401 # miss rate for overall accesses 1927system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10628.213542 # average ReadReq miss latency 1928system.cpu1.icache.ReadReq_avg_miss_latency::total 10628.213542 # average ReadReq miss latency 1929system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency 1930system.cpu1.icache.demand_avg_miss_latency::total 10628.213542 # average overall miss latency 1931system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency 1932system.cpu1.icache.overall_avg_miss_latency::total 10628.213542 # average overall miss latency 1933system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1934system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1935system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1936system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1937system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1938system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1939system.cpu1.icache.writebacks::writebacks 4797887 # number of writebacks 1940system.cpu1.icache.writebacks::total 4797887 # number of writebacks 1941system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4798405 # number of ReadReq MSHR misses 1942system.cpu1.icache.ReadReq_mshr_misses::total 4798405 # number of ReadReq MSHR misses 1943system.cpu1.icache.demand_mshr_misses::cpu1.inst 4798405 # number of demand (read+write) MSHR misses 1944system.cpu1.icache.demand_mshr_misses::total 4798405 # number of demand (read+write) MSHR misses 1945system.cpu1.icache.overall_mshr_misses::cpu1.inst 4798405 # number of overall MSHR misses 1946system.cpu1.icache.overall_mshr_misses::total 4798405 # number of overall MSHR misses 1947system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1948system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1949system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1950system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1951system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48599271000 # number of ReadReq MSHR miss cycles 1952system.cpu1.icache.ReadReq_mshr_miss_latency::total 48599271000 # number of ReadReq MSHR miss cycles 1953system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48599271000 # number of demand (read+write) MSHR miss cycles 1954system.cpu1.icache.demand_mshr_miss_latency::total 48599271000 # number of demand (read+write) MSHR miss cycles 1955system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48599271000 # number of overall MSHR miss cycles 1956system.cpu1.icache.overall_mshr_miss_latency::total 48599271000 # number of overall MSHR miss cycles 1957system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226500 # number of ReadReq MSHR uncacheable cycles 1958system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226500 # number of ReadReq MSHR uncacheable cycles 1959system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226500 # number of overall MSHR uncacheable cycles 1960system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226500 # number of overall MSHR uncacheable cycles 1961system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for ReadReq accesses 1962system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011401 # mshr miss rate for ReadReq accesses 1963system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for demand accesses 1964system.cpu1.icache.demand_mshr_miss_rate::total 0.011401 # mshr miss rate for demand accesses 1965system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for overall accesses 1966system.cpu1.icache.overall_mshr_miss_rate::total 0.011401 # mshr miss rate for overall accesses 1967system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average ReadReq mshr miss latency 1968system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10128.213646 # average ReadReq mshr miss latency 1969system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1970system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1971system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1972system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1973system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency 1974system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency 1975system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency 1976system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency 1977system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1978system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued 1979system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified 1980system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1981system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1982system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1983system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing 1984system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1985system.cpu1.l2cache.tags.replacements 1970256 # number of replacements 1986system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use 1987system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. 1988system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks. 1989system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks. 1990system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit. 1991system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor 1992system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor 1993system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 64.411311 # Average occupied blocks per requestor 1994system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 905.409563 # Average occupied blocks per requestor 1995system.cpu1.l2cache.tags.occ_percent::writebacks 0.749966 # Average percentage of cache occupancy 1996system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002697 # Average percentage of cache occupancy 1997system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003931 # Average percentage of cache occupancy 1998system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055262 # Average percentage of cache occupancy 1999system.cpu1.l2cache.tags.occ_percent::total 0.811856 # Average percentage of cache occupancy 2000system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1582 # Occupied blocks per task id 2001system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 2002system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13889 # Occupied blocks per task id 2003system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id 2004system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id 2005system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id 2006system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2007system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 38 # Occupied blocks per task id 2008system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id 2009system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2010system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 2011system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id 2012system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id 2013system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id 2014system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id 2015system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 2016system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id 2017system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses 2018system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses 2019system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2020system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits 2021system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits 2022system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits 2023system.cpu1.l2cache.WritebackDirty_hits::writebacks 3174179 # number of WritebackDirty hits 2024system.cpu1.l2cache.WritebackDirty_hits::total 3174179 # number of WritebackDirty hits 2025system.cpu1.l2cache.WritebackClean_hits::writebacks 6641283 # number of WritebackClean hits 2026system.cpu1.l2cache.WritebackClean_hits::total 6641283 # number of WritebackClean hits 2027system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits 2028system.cpu1.l2cache.UpgradeReq_hits::total 549 # number of UpgradeReq hits 2029system.cpu1.l2cache.ReadExReq_hits::cpu1.data 848093 # number of ReadExReq hits 2030system.cpu1.l2cache.ReadExReq_hits::total 848093 # number of ReadExReq hits 2031system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4339488 # number of ReadCleanReq hits 2032system.cpu1.l2cache.ReadCleanReq_hits::total 4339488 # number of ReadCleanReq hits 2033system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2669176 # number of ReadSharedReq hits 2034system.cpu1.l2cache.ReadSharedReq_hits::total 2669176 # number of ReadSharedReq hits 2035system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 193952 # number of InvalidateReq hits 2036system.cpu1.l2cache.InvalidateReq_hits::total 193952 # number of InvalidateReq hits 2037system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 241732 # number of demand (read+write) hits 2038system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150683 # number of demand (read+write) hits 2039system.cpu1.l2cache.demand_hits::cpu1.inst 4339488 # number of demand (read+write) hits 2040system.cpu1.l2cache.demand_hits::cpu1.data 3517269 # number of demand (read+write) hits 2041system.cpu1.l2cache.demand_hits::total 8249172 # number of demand (read+write) hits 2042system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 241732 # number of overall hits 2043system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150683 # number of overall hits 2044system.cpu1.l2cache.overall_hits::cpu1.inst 4339488 # number of overall hits 2045system.cpu1.l2cache.overall_hits::cpu1.data 3517269 # number of overall hits 2046system.cpu1.l2cache.overall_hits::total 8249172 # number of overall hits 2047system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10752 # number of ReadReq misses 2048system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9335 # number of ReadReq misses 2049system.cpu1.l2cache.ReadReq_misses::total 20087 # number of ReadReq misses 2050system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 209731 # number of UpgradeReq misses 2051system.cpu1.l2cache.UpgradeReq_misses::total 209731 # number of UpgradeReq misses 2052system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 204666 # number of SCUpgradeReq misses 2053system.cpu1.l2cache.SCUpgradeReq_misses::total 204666 # number of SCUpgradeReq misses 2054system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # number of SCUpgradeFailReq misses 2055system.cpu1.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 2056system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253892 # number of ReadExReq misses 2057system.cpu1.l2cache.ReadExReq_misses::total 253892 # number of ReadExReq misses 2058system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458917 # number of ReadCleanReq misses 2059system.cpu1.l2cache.ReadCleanReq_misses::total 458917 # number of ReadCleanReq misses 2060system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 897743 # number of ReadSharedReq misses 2061system.cpu1.l2cache.ReadSharedReq_misses::total 897743 # number of ReadSharedReq misses 2062system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252003 # number of InvalidateReq misses 2063system.cpu1.l2cache.InvalidateReq_misses::total 252003 # number of InvalidateReq misses 2064system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10752 # number of demand (read+write) misses 2065system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9335 # number of demand (read+write) misses 2066system.cpu1.l2cache.demand_misses::cpu1.inst 458917 # number of demand (read+write) misses 2067system.cpu1.l2cache.demand_misses::cpu1.data 1151635 # number of demand (read+write) misses 2068system.cpu1.l2cache.demand_misses::total 1630639 # number of demand (read+write) misses 2069system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10752 # number of overall misses 2070system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9335 # number of overall misses 2071system.cpu1.l2cache.overall_misses::cpu1.inst 458917 # number of overall misses 2072system.cpu1.l2cache.overall_misses::cpu1.data 1151635 # number of overall misses 2073system.cpu1.l2cache.overall_misses::total 1630639 # number of overall misses 2074system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 421263500 # number of ReadReq miss cycles 2075system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 385353500 # number of ReadReq miss cycles 2076system.cpu1.l2cache.ReadReq_miss_latency::total 806617000 # number of ReadReq miss cycles 2077system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1909199500 # number of UpgradeReq miss cycles 2078system.cpu1.l2cache.UpgradeReq_miss_latency::total 1909199500 # number of UpgradeReq miss cycles 2079system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1509536500 # number of SCUpgradeReq miss cycles 2080system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1509536500 # number of SCUpgradeReq miss cycles 2081system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2962499 # number of SCUpgradeFailReq miss cycles 2082system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2962499 # number of SCUpgradeFailReq miss cycles 2083system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10235182000 # number of ReadExReq miss cycles 2084system.cpu1.l2cache.ReadExReq_miss_latency::total 10235182000 # number of ReadExReq miss cycles 2085system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15333921500 # number of ReadCleanReq miss cycles 2086system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15333921500 # number of ReadCleanReq miss cycles 2087system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29041295500 # number of ReadSharedReq miss cycles 2088system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29041295500 # number of ReadSharedReq miss cycles 2089system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 413814500 # number of InvalidateReq miss cycles 2090system.cpu1.l2cache.InvalidateReq_miss_latency::total 413814500 # number of InvalidateReq miss cycles 2091system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 421263500 # number of demand (read+write) miss cycles 2092system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 385353500 # number of demand (read+write) miss cycles 2093system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15333921500 # number of demand (read+write) miss cycles 2094system.cpu1.l2cache.demand_miss_latency::cpu1.data 39276477500 # number of demand (read+write) miss cycles 2095system.cpu1.l2cache.demand_miss_latency::total 55417016000 # number of demand (read+write) miss cycles 2096system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 421263500 # number of overall miss cycles 2097system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 385353500 # number of overall miss cycles 2098system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15333921500 # number of overall miss cycles 2099system.cpu1.l2cache.overall_miss_latency::cpu1.data 39276477500 # number of overall miss cycles 2100system.cpu1.l2cache.overall_miss_latency::total 55417016000 # number of overall miss cycles 2101system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 252484 # number of ReadReq accesses(hits+misses) 2102system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 160018 # number of ReadReq accesses(hits+misses) 2103system.cpu1.l2cache.ReadReq_accesses::total 412502 # number of ReadReq accesses(hits+misses) 2104system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3174179 # number of WritebackDirty accesses(hits+misses) 2105system.cpu1.l2cache.WritebackDirty_accesses::total 3174179 # number of WritebackDirty accesses(hits+misses) 2106system.cpu1.l2cache.WritebackClean_accesses::writebacks 6641283 # number of WritebackClean accesses(hits+misses) 2107system.cpu1.l2cache.WritebackClean_accesses::total 6641283 # number of WritebackClean accesses(hits+misses) 2108system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 210280 # number of UpgradeReq accesses(hits+misses) 2109system.cpu1.l2cache.UpgradeReq_accesses::total 210280 # number of UpgradeReq accesses(hits+misses) 2110system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 204666 # number of SCUpgradeReq accesses(hits+misses) 2111system.cpu1.l2cache.SCUpgradeReq_accesses::total 204666 # number of SCUpgradeReq accesses(hits+misses) 2112system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 2113system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 2114system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1101985 # number of ReadExReq accesses(hits+misses) 2115system.cpu1.l2cache.ReadExReq_accesses::total 1101985 # number of ReadExReq accesses(hits+misses) 2116system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4798405 # number of ReadCleanReq accesses(hits+misses) 2117system.cpu1.l2cache.ReadCleanReq_accesses::total 4798405 # number of ReadCleanReq accesses(hits+misses) 2118system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3566919 # number of ReadSharedReq accesses(hits+misses) 2119system.cpu1.l2cache.ReadSharedReq_accesses::total 3566919 # number of ReadSharedReq accesses(hits+misses) 2120system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 445955 # number of InvalidateReq accesses(hits+misses) 2121system.cpu1.l2cache.InvalidateReq_accesses::total 445955 # number of InvalidateReq accesses(hits+misses) 2122system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 252484 # number of demand (read+write) accesses 2123system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 160018 # number of demand (read+write) accesses 2124system.cpu1.l2cache.demand_accesses::cpu1.inst 4798405 # number of demand (read+write) accesses 2125system.cpu1.l2cache.demand_accesses::cpu1.data 4668904 # number of demand (read+write) accesses 2126system.cpu1.l2cache.demand_accesses::total 9879811 # number of demand (read+write) accesses 2127system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 252484 # number of overall (read+write) accesses 2128system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 160018 # number of overall (read+write) accesses 2129system.cpu1.l2cache.overall_accesses::cpu1.inst 4798405 # number of overall (read+write) accesses 2130system.cpu1.l2cache.overall_accesses::cpu1.data 4668904 # number of overall (read+write) accesses 2131system.cpu1.l2cache.overall_accesses::total 9879811 # number of overall (read+write) accesses 2132system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for ReadReq accesses 2133system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses 2134system.cpu1.l2cache.ReadReq_miss_rate::total 0.048696 # miss rate for ReadReq accesses 2135system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997389 # miss rate for UpgradeReq accesses 2136system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997389 # miss rate for UpgradeReq accesses 2137system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2138system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2139system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2140system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2141system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230395 # miss rate for ReadExReq accesses 2142system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230395 # miss rate for ReadExReq accesses 2143system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095639 # miss rate for ReadCleanReq accesses 2144system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095639 # miss rate for ReadCleanReq accesses 2145system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.251686 # miss rate for ReadSharedReq accesses 2146system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.251686 # miss rate for ReadSharedReq accesses 2147system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565086 # miss rate for InvalidateReq accesses 2148system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565086 # miss rate for InvalidateReq accesses 2149system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for demand accesses 2150system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses 2151system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095639 # miss rate for demand accesses 2152system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246661 # miss rate for demand accesses 2153system.cpu1.l2cache.demand_miss_rate::total 0.165048 # miss rate for demand accesses 2154system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for overall accesses 2155system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses 2156system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095639 # miss rate for overall accesses 2157system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246661 # miss rate for overall accesses 2158system.cpu1.l2cache.overall_miss_rate::total 0.165048 # miss rate for overall accesses 2159system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average ReadReq miss latency 2160system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41280.503482 # average ReadReq miss latency 2161system.cpu1.l2cache.ReadReq_avg_miss_latency::total 40156.170658 # average ReadReq miss latency 2162system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9103.086811 # average UpgradeReq miss latency 2163system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9103.086811 # average UpgradeReq miss latency 2164system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7375.609530 # average SCUpgradeReq miss latency 2165system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7375.609530 # average SCUpgradeReq miss latency 2166system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 296249.900000 # average SCUpgradeFailReq miss latency 2167system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 296249.900000 # average SCUpgradeFailReq miss latency 2168system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40313.133143 # average ReadExReq miss latency 2169system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40313.133143 # average ReadExReq miss latency 2170system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33413.278436 # average ReadCleanReq miss latency 2171system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33413.278436 # average ReadCleanReq miss latency 2172system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32349.230793 # average ReadSharedReq miss latency 2173system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32349.230793 # average ReadSharedReq miss latency 2174system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1642.101483 # average InvalidateReq miss latency 2175system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1642.101483 # average InvalidateReq miss latency 2176system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average overall miss latency 2177system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41280.503482 # average overall miss latency 2178system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33413.278436 # average overall miss latency 2179system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34104.970325 # average overall miss latency 2180system.cpu1.l2cache.demand_avg_miss_latency::total 33984.846431 # average overall miss latency 2181system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average overall miss latency 2182system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41280.503482 # average overall miss latency 2183system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33413.278436 # average overall miss latency 2184system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34104.970325 # average overall miss latency 2185system.cpu1.l2cache.overall_avg_miss_latency::total 33984.846431 # average overall miss latency 2186system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2187system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2188system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2189system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2190system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2191system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2192system.cpu1.l2cache.unused_prefetches 39843 # number of HardPF blocks evicted w/o reference 2193system.cpu1.l2cache.writebacks::writebacks 1100180 # number of writebacks 2194system.cpu1.l2cache.writebacks::total 1100180 # number of writebacks 2195system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4729 # number of ReadExReq MSHR hits 2196system.cpu1.l2cache.ReadExReq_mshr_hits::total 4729 # number of ReadExReq MSHR hits 2197system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 266 # number of ReadSharedReq MSHR hits 2198system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 266 # number of ReadSharedReq MSHR hits 2199system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits 2200system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 2201system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4995 # number of demand (read+write) MSHR hits 2202system.cpu1.l2cache.demand_mshr_hits::total 4995 # number of demand (read+write) MSHR hits 2203system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4995 # number of overall MSHR hits 2204system.cpu1.l2cache.overall_mshr_hits::total 4995 # number of overall MSHR hits 2205system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10752 # number of ReadReq MSHR misses 2206system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9335 # number of ReadReq MSHR misses 2207system.cpu1.l2cache.ReadReq_mshr_misses::total 20087 # number of ReadReq MSHR misses 2208system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 687556 # number of HardPFReq MSHR misses 2209system.cpu1.l2cache.HardPFReq_mshr_misses::total 687556 # number of HardPFReq MSHR misses 2210system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 209731 # number of UpgradeReq MSHR misses 2211system.cpu1.l2cache.UpgradeReq_mshr_misses::total 209731 # number of UpgradeReq MSHR misses 2212system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 204666 # number of SCUpgradeReq MSHR misses 2213system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 204666 # number of SCUpgradeReq MSHR misses 2214system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 10 # number of SCUpgradeFailReq MSHR misses 2215system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 2216system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249163 # number of ReadExReq MSHR misses 2217system.cpu1.l2cache.ReadExReq_mshr_misses::total 249163 # number of ReadExReq MSHR misses 2218system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 458917 # number of ReadCleanReq MSHR misses 2219system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 458917 # number of ReadCleanReq MSHR misses 2220system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 897477 # number of ReadSharedReq MSHR misses 2221system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 897477 # number of ReadSharedReq MSHR misses 2222system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252001 # number of InvalidateReq MSHR misses 2223system.cpu1.l2cache.InvalidateReq_mshr_misses::total 252001 # number of InvalidateReq MSHR misses 2224system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10752 # number of demand (read+write) MSHR misses 2225system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9335 # number of demand (read+write) MSHR misses 2226system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 458917 # number of demand (read+write) MSHR misses 2227system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1146640 # number of demand (read+write) MSHR misses 2228system.cpu1.l2cache.demand_mshr_misses::total 1625644 # number of demand (read+write) MSHR misses 2229system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10752 # number of overall MSHR misses 2230system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9335 # number of overall MSHR misses 2231system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 458917 # number of overall MSHR misses 2232system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1146640 # number of overall MSHR misses 2233system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 687556 # number of overall MSHR misses 2234system.cpu1.l2cache.overall_mshr_misses::total 2313200 # number of overall MSHR misses 2235system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2236system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable 2237system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11145 # number of ReadReq MSHR uncacheable 2238system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable 2239system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable 2240system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2241system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses 2242system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23094 # number of overall MSHR uncacheable misses 2243system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of ReadReq MSHR miss cycles 2244system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 329343500 # number of ReadReq MSHR miss cycles 2245system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 686095000 # number of ReadReq MSHR miss cycles 2246system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of HardPFReq MSHR miss cycles 2247system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27876431726 # number of HardPFReq MSHR miss cycles 2248system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4396610500 # number of UpgradeReq MSHR miss cycles 2249system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4396610500 # number of UpgradeReq MSHR miss cycles 2250system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3329007000 # number of SCUpgradeReq MSHR miss cycles 2251system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3329007000 # number of SCUpgradeReq MSHR miss cycles 2252system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2614499 # number of SCUpgradeFailReq MSHR miss cycles 2253system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2614499 # number of SCUpgradeFailReq MSHR miss cycles 2254system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8260901500 # number of ReadExReq MSHR miss cycles 2255system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8260901500 # number of ReadExReq MSHR miss cycles 2256system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12580419500 # number of ReadCleanReq MSHR miss cycles 2257system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12580419500 # number of ReadCleanReq MSHR miss cycles 2258system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23624853500 # number of ReadSharedReq MSHR miss cycles 2259system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23624853500 # number of ReadSharedReq MSHR miss cycles 2260system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6839135500 # number of InvalidateReq MSHR miss cycles 2261system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6839135500 # number of InvalidateReq MSHR miss cycles 2262system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of demand (read+write) MSHR miss cycles 2263system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329343500 # number of demand (read+write) MSHR miss cycles 2264system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12580419500 # number of demand (read+write) MSHR miss cycles 2265system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31885755000 # number of demand (read+write) MSHR miss cycles 2266system.cpu1.l2cache.demand_mshr_miss_latency::total 45152269500 # number of demand (read+write) MSHR miss cycles 2267system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of overall MSHR miss cycles 2268system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329343500 # number of overall MSHR miss cycles 2269system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12580419500 # number of overall MSHR miss cycles 2270system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31885755000 # number of overall MSHR miss cycles 2271system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of overall MSHR miss cycles 2272system.cpu1.l2cache.overall_mshr_miss_latency::total 73028701226 # number of overall MSHR miss cycles 2273system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401500 # number of ReadReq MSHR uncacheable cycles 2274system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1805437500 # number of ReadReq MSHR uncacheable cycles 2275system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1814839000 # number of ReadReq MSHR uncacheable cycles 2276system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401500 # number of overall MSHR uncacheable cycles 2277system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1805437500 # number of overall MSHR uncacheable cycles 2278system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1814839000 # number of overall MSHR uncacheable cycles 2279system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for ReadReq accesses 2280system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for ReadReq accesses 2281system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048696 # mshr miss rate for ReadReq accesses 2282system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2283system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2284system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997389 # mshr miss rate for UpgradeReq accesses 2285system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997389 # mshr miss rate for UpgradeReq accesses 2286system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2287system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2288system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2289system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2290system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226104 # mshr miss rate for ReadExReq accesses 2291system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226104 # mshr miss rate for ReadExReq accesses 2292system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for ReadCleanReq accesses 2293system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095639 # mshr miss rate for ReadCleanReq accesses 2294system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251611 # mshr miss rate for ReadSharedReq accesses 2295system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251611 # mshr miss rate for ReadSharedReq accesses 2296system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565082 # mshr miss rate for InvalidateReq accesses 2297system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565082 # mshr miss rate for InvalidateReq accesses 2298system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for demand accesses 2299system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for demand accesses 2300system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for demand accesses 2301system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for demand accesses 2302system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164542 # mshr miss rate for demand accesses 2303system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for overall accesses 2304system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for overall accesses 2305system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for overall accesses 2306system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for overall accesses 2307system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2308system.cpu1.l2cache.overall_mshr_miss_rate::total 0.234134 # mshr miss rate for overall accesses 2309system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average ReadReq mshr miss latency 2310system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average ReadReq mshr miss latency 2311system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658 # average ReadReq mshr miss latency 2312system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average HardPFReq mshr miss latency 2313system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544 # average HardPFReq mshr miss latency 2314system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200 # average UpgradeReq mshr miss latency 2315system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200 # average UpgradeReq mshr miss latency 2316system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497 # average SCUpgradeReq mshr miss latency 2317system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497 # average SCUpgradeReq mshr miss latency 2318system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000 # average SCUpgradeFailReq mshr miss latency 2319system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000 # average SCUpgradeFailReq mshr miss latency 2320system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626 # average ReadExReq mshr miss latency 2321system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626 # average ReadExReq mshr miss latency 2322system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average ReadCleanReq mshr miss latency 2323system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436 # average ReadCleanReq mshr miss latency 2324system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135 # average ReadSharedReq mshr miss latency 2325system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135 # average ReadSharedReq mshr miss latency 2326system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892 # average InvalidateReq mshr miss latency 2327system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892 # average InvalidateReq mshr miss latency 2328system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency 2329system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency 2330system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency 2331system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency 2332system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552 # average overall mshr miss latency 2333system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency 2334system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency 2335system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency 2336system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency 2337system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average overall mshr miss latency 2338system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456 # average overall mshr miss latency 2339system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average ReadReq mshr uncacheable latency 2340system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214 # average ReadReq mshr uncacheable latency 2341system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503 # average ReadReq mshr uncacheable latency 2342system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average overall mshr uncacheable latency 2343system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency 2344system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency 2345system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. 2346system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2347system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2348system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. 2349system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2350system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2351system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2352system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution 2353system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution 2354system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution 2355system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution 2356system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution 2357system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution 2358system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution 2359system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution 2360system.cpu1.toL2Bus.trans_dist::UpgradeReq 390891 # Transaction distribution 2361system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 375101 # Transaction distribution 2362system.cpu1.toL2Bus.trans_dist::UpgradeResp 483493 # Transaction distribution 2363system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution 2364system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 2365system.cpu1.toL2Bus.trans_dist::ReadExReq 1131381 # Transaction distribution 2366system.cpu1.toL2Bus.trans_dist::ReadExResp 1109621 # Transaction distribution 2367system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4798405 # Transaction distribution 2368system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4426002 # Transaction distribution 2369system.cpu1.toL2Bus.trans_dist::InvalidateReq 496716 # Transaction distribution 2370system.cpu1.toL2Bus.trans_dist::InvalidateResp 445955 # Transaction distribution 2371system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14394916 # Packet count per connected master and slave (bytes) 2372system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16294669 # Packet count per connected master and slave (bytes) 2373system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 336160 # Packet count per connected master and slave (bytes) 2374system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 556294 # Packet count per connected master and slave (bytes) 2375system.cpu1.toL2Bus.pkt_count::total 31582039 # Packet count per connected master and slave (bytes) 2376system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614163064 # Cumulative packet size per connected master and slave (bytes) 2377system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 626579614 # Cumulative packet size per connected master and slave (bytes) 2378system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1280144 # Cumulative packet size per connected master and slave (bytes) 2379system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2019872 # Cumulative packet size per connected master and slave (bytes) 2380system.cpu1.toL2Bus.pkt_size::total 1244042694 # Cumulative packet size per connected master and slave (bytes) 2381system.cpu1.toL2Bus.snoops 5755928 # Total snoops (count) 2382system.cpu1.toL2Bus.snoop_fanout::samples 16349135 # Request fanout histogram 2383system.cpu1.toL2Bus.snoop_fanout::mean 0.122449 # Request fanout histogram 2384system.cpu1.toL2Bus.snoop_fanout::stdev 0.327837 # Request fanout histogram 2385system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2386system.cpu1.toL2Bus.snoop_fanout::0 14347367 87.76% 87.76% # Request fanout histogram 2387system.cpu1.toL2Bus.snoop_fanout::1 2001594 12.24% 100.00% # Request fanout histogram 2388system.cpu1.toL2Bus.snoop_fanout::2 174 0.00% 100.00% # Request fanout histogram 2389system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2390system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2391system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2392system.cpu1.toL2Bus.snoop_fanout::total 16349135 # Request fanout histogram 2393system.cpu1.toL2Bus.reqLayer0.occupancy 20146131499 # Layer occupancy (ticks) 2394system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2395system.cpu1.toL2Bus.snoopLayer0.occupancy 187574309 # Layer occupancy (ticks) 2396system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2397system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) 2398system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2399system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) 2400system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2401system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) 2402system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2403system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) 2404system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2405system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2406system.iobus.trans_dist::ReadReq 40346 # Transaction distribution 2407system.iobus.trans_dist::ReadResp 40346 # Transaction distribution 2408system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 2409system.iobus.trans_dist::WriteResp 136634 # Transaction distribution 2410system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) 2411system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2412system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2413system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2414system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2415system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2416system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2417system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2418system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2419system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2420system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2421system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2422system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2423system.iobus.pkt_count_system.bridge.master::total 122674 # Packet count per connected master and slave (bytes) 2424system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) 2425system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) 2426system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2427system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2428system.iobus.pkt_count::total 353960 # Packet count per connected master and slave (bytes) 2429system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47760 # Cumulative packet size per connected master and slave (bytes) 2430system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2431system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2432system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2433system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2434system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2435system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2436system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2437system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2438system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2439system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2440system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2441system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2442system.iobus.pkt_size_system.bridge.master::total 155781 # Cumulative packet size per connected master and slave (bytes) 2443system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) 2444system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) 2445system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2446system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2447system.iobus.pkt_size::total 7496707 # Cumulative packet size per connected master and slave (bytes) 2448system.iobus.reqLayer0.occupancy 36949503 # Layer occupancy (ticks) 2449system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2450system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 2451system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2452system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 2453system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2454system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2455system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2456system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 2457system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2458system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2459system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2460system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2461system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2462system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 2463system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2464system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2465system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2466system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 2467system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2468system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 2469system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2470system.iobus.reqLayer23.occupancy 26494000 # Layer occupancy (ticks) 2471system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2472system.iobus.reqLayer24.occupancy 37417500 # Layer occupancy (ticks) 2473system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2474system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) 2475system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2476system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) 2477system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2478system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) 2479system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2480system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2481system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2482system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2483system.iocache.tags.replacements 115585 # number of replacements 2484system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use 2485system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2486system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 2487system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2488system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. 2489system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor 2490system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor 2491system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy 2492system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy 2493system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy 2494system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2495system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2496system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2497system.iocache.tags.tag_accesses 1040784 # Number of tag accesses 2498system.iocache.tags.data_accesses 1040784 # Number of data accesses 2499system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2500system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2501system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses 2502system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses 2503system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2504system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2505system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2506system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2507system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2508system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses 2509system.iocache.demand_misses::total 115643 # number of demand (read+write) misses 2510system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2511system.iocache.overall_misses::realview.ide 115603 # number of overall misses 2512system.iocache.overall_misses::total 115643 # number of overall misses 2513system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2514system.iocache.ReadReq_miss_latency::realview.ide 1623231612 # number of ReadReq miss cycles 2515system.iocache.ReadReq_miss_latency::total 1628431112 # number of ReadReq miss cycles 2516system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2517system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2518system.iocache.WriteLineReq_miss_latency::realview.ide 12905416814 # number of WriteLineReq miss cycles 2519system.iocache.WriteLineReq_miss_latency::total 12905416814 # number of WriteLineReq miss cycles 2520system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 2521system.iocache.demand_miss_latency::realview.ide 14528648426 # number of demand (read+write) miss cycles 2522system.iocache.demand_miss_latency::total 14534216926 # number of demand (read+write) miss cycles 2523system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 2524system.iocache.overall_miss_latency::realview.ide 14528648426 # number of overall miss cycles 2525system.iocache.overall_miss_latency::total 14534216926 # number of overall miss cycles 2526system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2527system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) 2528system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) 2529system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2530system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2531system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2532system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2533system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2534system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses 2535system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses 2536system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2537system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses 2538system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses 2539system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2540system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2541system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2542system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2543system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2544system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2545system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2546system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2547system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2548system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2549system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2550system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2551system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2552system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2553system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563 # average ReadReq miss latency 2554system.iocache.ReadReq_avg_miss_latency::total 182723.419210 # average ReadReq miss latency 2555system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2556system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2557system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348 # average WriteLineReq miss latency 2558system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348 # average WriteLineReq miss latency 2559system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2560system.iocache.demand_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency 2561system.iocache.demand_avg_miss_latency::total 125681.769982 # average overall miss latency 2562system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2563system.iocache.overall_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency 2564system.iocache.overall_avg_miss_latency::total 125681.769982 # average overall miss latency 2565system.iocache.blocked_cycles::no_mshrs 31595 # number of cycles access was blocked 2566system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2567system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked 2568system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2569system.iocache.avg_blocked_cycles::no_mshrs 9.192610 # average number of cycles each access was blocked 2570system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2571system.iocache.writebacks::writebacks 106695 # number of writebacks 2572system.iocache.writebacks::total 106695 # number of writebacks 2573system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2574system.iocache.ReadReq_mshr_misses::realview.ide 8875 # number of ReadReq MSHR misses 2575system.iocache.ReadReq_mshr_misses::total 8912 # number of ReadReq MSHR misses 2576system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2577system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2578system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2579system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2580system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2581system.iocache.demand_mshr_misses::realview.ide 115603 # number of demand (read+write) MSHR misses 2582system.iocache.demand_mshr_misses::total 115643 # number of demand (read+write) MSHR misses 2583system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2584system.iocache.overall_mshr_misses::realview.ide 115603 # number of overall MSHR misses 2585system.iocache.overall_mshr_misses::total 115643 # number of overall MSHR misses 2586system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2587system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179481612 # number of ReadReq MSHR miss cycles 2588system.iocache.ReadReq_mshr_miss_latency::total 1182831112 # number of ReadReq MSHR miss cycles 2589system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2590system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2591system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7559977711 # number of WriteLineReq MSHR miss cycles 2592system.iocache.WriteLineReq_mshr_miss_latency::total 7559977711 # number of WriteLineReq MSHR miss cycles 2593system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 2594system.iocache.demand_mshr_miss_latency::realview.ide 8739459323 # number of demand (read+write) MSHR miss cycles 2595system.iocache.demand_mshr_miss_latency::total 8743027823 # number of demand (read+write) MSHR miss cycles 2596system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 2597system.iocache.overall_mshr_miss_latency::realview.ide 8739459323 # number of overall MSHR miss cycles 2598system.iocache.overall_mshr_miss_latency::total 8743027823 # number of overall MSHR miss cycles 2599system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2600system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2601system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2602system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2603system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2604system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2605system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2606system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2607system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2608system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2609system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2610system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2611system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2612system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2613system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132899.336563 # average ReadReq mshr miss latency 2614system.iocache.ReadReq_avg_mshr_miss_latency::total 132723.419210 # average ReadReq mshr miss latency 2615system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2616system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2617system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency 2618system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency 2619system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2620system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2621system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency 2622system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2623system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2624system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency 2625system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2626system.l2c.tags.replacements 1336257 # number of replacements 2627system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use 2628system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. 2629system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks. 2630system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks. 2631system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. 2632system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor 2633system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor 2634system.l2c.tags.occ_blocks::cpu0.itb.walker 220.083460 # Average occupied blocks per requestor 2635system.l2c.tags.occ_blocks::cpu0.inst 4065.866850 # Average occupied blocks per requestor 2636system.l2c.tags.occ_blocks::cpu0.data 8220.853874 # Average occupied blocks per requestor 2637system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.282047 # Average occupied blocks per requestor 2638system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.986041 # Average occupied blocks per requestor 2639system.l2c.tags.occ_blocks::cpu1.itb.walker 269.420690 # Average occupied blocks per requestor 2640system.l2c.tags.occ_blocks::cpu1.inst 2932.882407 # Average occupied blocks per requestor 2641system.l2c.tags.occ_blocks::cpu1.data 5116.369986 # Average occupied blocks per requestor 2642system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513 # Average occupied blocks per requestor 2643system.l2c.tags.occ_percent::writebacks 0.352418 # Average percentage of cache occupancy 2644system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002061 # Average percentage of cache occupancy 2645system.l2c.tags.occ_percent::cpu0.itb.walker 0.003358 # Average percentage of cache occupancy 2646system.l2c.tags.occ_percent::cpu0.inst 0.062040 # Average percentage of cache occupancy 2647system.l2c.tags.occ_percent::cpu0.data 0.125440 # Average percentage of cache occupancy 2648system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127034 # Average percentage of cache occupancy 2649system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002502 # Average percentage of cache occupancy 2650system.l2c.tags.occ_percent::cpu1.itb.walker 0.004111 # Average percentage of cache occupancy 2651system.l2c.tags.occ_percent::cpu1.inst 0.044752 # Average percentage of cache occupancy 2652system.l2c.tags.occ_percent::cpu1.data 0.078070 # Average percentage of cache occupancy 2653system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.163171 # Average percentage of cache occupancy 2654system.l2c.tags.occ_percent::total 0.964958 # Average percentage of cache occupancy 2655system.l2c.tags.occ_task_id_blocks::1022 10513 # Occupied blocks per task id 2656system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id 2657system.l2c.tags.occ_task_id_blocks::1024 47867 # Occupied blocks per task id 2658system.l2c.tags.age_task_id_blocks_1022::2 208 # Occupied blocks per task id 2659system.l2c.tags.age_task_id_blocks_1022::3 519 # Occupied blocks per task id 2660system.l2c.tags.age_task_id_blocks_1022::4 9786 # Occupied blocks per task id 2661system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id 2662system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 2663system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 2664system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id 2665system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id 2666system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id 2667system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id 2668system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id 2669system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id 2670system.l2c.tags.tag_accesses 69855982 # Number of tag accesses 2671system.l2c.tags.data_accesses 69855982 # Number of data accesses 2672system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2673system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits 2674system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits 2675system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits 2676system.l2c.UpgradeReq_hits::cpu1.data 130434 # number of UpgradeReq hits 2677system.l2c.UpgradeReq_hits::total 288383 # number of UpgradeReq hits 2678system.l2c.SCUpgradeReq_hits::cpu0.data 36828 # number of SCUpgradeReq hits 2679system.l2c.SCUpgradeReq_hits::cpu1.data 37034 # number of SCUpgradeReq hits 2680system.l2c.SCUpgradeReq_hits::total 73862 # number of SCUpgradeReq hits 2681system.l2c.ReadExReq_hits::cpu0.data 45889 # number of ReadExReq hits 2682system.l2c.ReadExReq_hits::cpu1.data 57251 # number of ReadExReq hits 2683system.l2c.ReadExReq_hits::total 103140 # number of ReadExReq hits 2684system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4670 # number of ReadSharedReq hits 2685system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3337 # number of ReadSharedReq hits 2686system.l2c.ReadSharedReq_hits::cpu0.inst 411404 # number of ReadSharedReq hits 2687system.l2c.ReadSharedReq_hits::cpu0.data 536957 # number of ReadSharedReq hits 2688system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 268808 # number of ReadSharedReq hits 2689system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6004 # number of ReadSharedReq hits 2690system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5313 # number of ReadSharedReq hits 2691system.l2c.ReadSharedReq_hits::cpu1.inst 419752 # number of ReadSharedReq hits 2692system.l2c.ReadSharedReq_hits::cpu1.data 541221 # number of ReadSharedReq hits 2693system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283166 # number of ReadSharedReq hits 2694system.l2c.ReadSharedReq_hits::total 2480632 # number of ReadSharedReq hits 2695system.l2c.InvalidateReq_hits::cpu0.data 118921 # number of InvalidateReq hits 2696system.l2c.InvalidateReq_hits::cpu1.data 122409 # number of InvalidateReq hits 2697system.l2c.InvalidateReq_hits::total 241330 # number of InvalidateReq hits 2698system.l2c.demand_hits::cpu0.dtb.walker 4670 # number of demand (read+write) hits 2699system.l2c.demand_hits::cpu0.itb.walker 3337 # number of demand (read+write) hits 2700system.l2c.demand_hits::cpu0.inst 411404 # number of demand (read+write) hits 2701system.l2c.demand_hits::cpu0.data 582846 # number of demand (read+write) hits 2702system.l2c.demand_hits::cpu0.l2cache.prefetcher 268808 # number of demand (read+write) hits 2703system.l2c.demand_hits::cpu1.dtb.walker 6004 # number of demand (read+write) hits 2704system.l2c.demand_hits::cpu1.itb.walker 5313 # number of demand (read+write) hits 2705system.l2c.demand_hits::cpu1.inst 419752 # number of demand (read+write) hits 2706system.l2c.demand_hits::cpu1.data 598472 # number of demand (read+write) hits 2707system.l2c.demand_hits::cpu1.l2cache.prefetcher 283166 # number of demand (read+write) hits 2708system.l2c.demand_hits::total 2583772 # number of demand (read+write) hits 2709system.l2c.overall_hits::cpu0.dtb.walker 4670 # number of overall hits 2710system.l2c.overall_hits::cpu0.itb.walker 3337 # number of overall hits 2711system.l2c.overall_hits::cpu0.inst 411404 # number of overall hits 2712system.l2c.overall_hits::cpu0.data 582846 # number of overall hits 2713system.l2c.overall_hits::cpu0.l2cache.prefetcher 268808 # number of overall hits 2714system.l2c.overall_hits::cpu1.dtb.walker 6004 # number of overall hits 2715system.l2c.overall_hits::cpu1.itb.walker 5313 # number of overall hits 2716system.l2c.overall_hits::cpu1.inst 419752 # number of overall hits 2717system.l2c.overall_hits::cpu1.data 598472 # number of overall hits 2718system.l2c.overall_hits::cpu1.l2cache.prefetcher 283166 # number of overall hits 2719system.l2c.overall_hits::total 2583772 # number of overall hits 2720system.l2c.UpgradeReq_misses::cpu0.data 61222 # number of UpgradeReq misses 2721system.l2c.UpgradeReq_misses::cpu1.data 59774 # number of UpgradeReq misses 2722system.l2c.UpgradeReq_misses::total 120996 # number of UpgradeReq misses 2723system.l2c.SCUpgradeReq_misses::cpu0.data 13056 # number of SCUpgradeReq misses 2724system.l2c.SCUpgradeReq_misses::cpu1.data 12621 # number of SCUpgradeReq misses 2725system.l2c.SCUpgradeReq_misses::total 25677 # number of SCUpgradeReq misses 2726system.l2c.ReadExReq_misses::cpu0.data 80578 # number of ReadExReq misses 2727system.l2c.ReadExReq_misses::cpu1.data 52729 # number of ReadExReq misses 2728system.l2c.ReadExReq_misses::total 133307 # number of ReadExReq misses 2729system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1465 # number of ReadSharedReq misses 2730system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1507 # number of ReadSharedReq misses 2731system.l2c.ReadSharedReq_misses::cpu0.inst 49296 # number of ReadSharedReq misses 2732system.l2c.ReadSharedReq_misses::cpu0.data 137179 # number of ReadSharedReq misses 2733system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 229932 # number of ReadSharedReq misses 2734system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2146 # number of ReadSharedReq misses 2735system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2116 # number of ReadSharedReq misses 2736system.l2c.ReadSharedReq_misses::cpu1.inst 39165 # number of ReadSharedReq misses 2737system.l2c.ReadSharedReq_misses::cpu1.data 95585 # number of ReadSharedReq misses 2738system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 188965 # number of ReadSharedReq misses 2739system.l2c.ReadSharedReq_misses::total 747356 # number of ReadSharedReq misses 2740system.l2c.InvalidateReq_misses::cpu0.data 446352 # number of InvalidateReq misses 2741system.l2c.InvalidateReq_misses::cpu1.data 114497 # number of InvalidateReq misses 2742system.l2c.InvalidateReq_misses::total 560849 # number of InvalidateReq misses 2743system.l2c.demand_misses::cpu0.dtb.walker 1465 # number of demand (read+write) misses 2744system.l2c.demand_misses::cpu0.itb.walker 1507 # number of demand (read+write) misses 2745system.l2c.demand_misses::cpu0.inst 49296 # number of demand (read+write) misses 2746system.l2c.demand_misses::cpu0.data 217757 # number of demand (read+write) misses 2747system.l2c.demand_misses::cpu0.l2cache.prefetcher 229932 # number of demand (read+write) misses 2748system.l2c.demand_misses::cpu1.dtb.walker 2146 # number of demand (read+write) misses 2749system.l2c.demand_misses::cpu1.itb.walker 2116 # number of demand (read+write) misses 2750system.l2c.demand_misses::cpu1.inst 39165 # number of demand (read+write) misses 2751system.l2c.demand_misses::cpu1.data 148314 # number of demand (read+write) misses 2752system.l2c.demand_misses::cpu1.l2cache.prefetcher 188965 # number of demand (read+write) misses 2753system.l2c.demand_misses::total 880663 # number of demand (read+write) misses 2754system.l2c.overall_misses::cpu0.dtb.walker 1465 # number of overall misses 2755system.l2c.overall_misses::cpu0.itb.walker 1507 # number of overall misses 2756system.l2c.overall_misses::cpu0.inst 49296 # number of overall misses 2757system.l2c.overall_misses::cpu0.data 217757 # number of overall misses 2758system.l2c.overall_misses::cpu0.l2cache.prefetcher 229932 # number of overall misses 2759system.l2c.overall_misses::cpu1.dtb.walker 2146 # number of overall misses 2760system.l2c.overall_misses::cpu1.itb.walker 2116 # number of overall misses 2761system.l2c.overall_misses::cpu1.inst 39165 # number of overall misses 2762system.l2c.overall_misses::cpu1.data 148314 # number of overall misses 2763system.l2c.overall_misses::cpu1.l2cache.prefetcher 188965 # number of overall misses 2764system.l2c.overall_misses::total 880663 # number of overall misses 2765system.l2c.UpgradeReq_miss_latency::cpu0.data 367859500 # number of UpgradeReq miss cycles 2766system.l2c.UpgradeReq_miss_latency::cpu1.data 359764000 # number of UpgradeReq miss cycles 2767system.l2c.UpgradeReq_miss_latency::total 727623500 # number of UpgradeReq miss cycles 2768system.l2c.SCUpgradeReq_miss_latency::cpu0.data 70353500 # number of SCUpgradeReq miss cycles 2769system.l2c.SCUpgradeReq_miss_latency::cpu1.data 71619000 # number of SCUpgradeReq miss cycles 2770system.l2c.SCUpgradeReq_miss_latency::total 141972500 # number of SCUpgradeReq miss cycles 2771system.l2c.ReadExReq_miss_latency::cpu0.data 7055893500 # number of ReadExReq miss cycles 2772system.l2c.ReadExReq_miss_latency::cpu1.data 4403905000 # number of ReadExReq miss cycles 2773system.l2c.ReadExReq_miss_latency::total 11459798500 # number of ReadExReq miss cycles 2774system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 131430500 # number of ReadSharedReq miss cycles 2775system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 136636000 # number of ReadSharedReq miss cycles 2776system.l2c.ReadSharedReq_miss_latency::cpu0.inst 4206937000 # number of ReadSharedReq miss cycles 2777system.l2c.ReadSharedReq_miss_latency::cpu0.data 12205051500 # number of ReadSharedReq miss cycles 2778system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of ReadSharedReq miss cycles 2779system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 192694000 # number of ReadSharedReq miss cycles 2780system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 194855000 # number of ReadSharedReq miss cycles 2781system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3362110000 # number of ReadSharedReq miss cycles 2782system.l2c.ReadSharedReq_miss_latency::cpu1.data 8709641000 # number of ReadSharedReq miss cycles 2783system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of ReadSharedReq miss cycles 2784system.l2c.ReadSharedReq_miss_latency::total 79366262993 # number of ReadSharedReq miss cycles 2785system.l2c.InvalidateReq_miss_latency::cpu0.data 47144000 # number of InvalidateReq miss cycles 2786system.l2c.InvalidateReq_miss_latency::cpu1.data 45361000 # number of InvalidateReq miss cycles 2787system.l2c.InvalidateReq_miss_latency::total 92505000 # number of InvalidateReq miss cycles 2788system.l2c.demand_miss_latency::cpu0.dtb.walker 131430500 # number of demand (read+write) miss cycles 2789system.l2c.demand_miss_latency::cpu0.itb.walker 136636000 # number of demand (read+write) miss cycles 2790system.l2c.demand_miss_latency::cpu0.inst 4206937000 # number of demand (read+write) miss cycles 2791system.l2c.demand_miss_latency::cpu0.data 19260945000 # number of demand (read+write) miss cycles 2792system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of demand (read+write) miss cycles 2793system.l2c.demand_miss_latency::cpu1.dtb.walker 192694000 # number of demand (read+write) miss cycles 2794system.l2c.demand_miss_latency::cpu1.itb.walker 194855000 # number of demand (read+write) miss cycles 2795system.l2c.demand_miss_latency::cpu1.inst 3362110000 # number of demand (read+write) miss cycles 2796system.l2c.demand_miss_latency::cpu1.data 13113546000 # number of demand (read+write) miss cycles 2797system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of demand (read+write) miss cycles 2798system.l2c.demand_miss_latency::total 90826061493 # number of demand (read+write) miss cycles 2799system.l2c.overall_miss_latency::cpu0.dtb.walker 131430500 # number of overall miss cycles 2800system.l2c.overall_miss_latency::cpu0.itb.walker 136636000 # number of overall miss cycles 2801system.l2c.overall_miss_latency::cpu0.inst 4206937000 # number of overall miss cycles 2802system.l2c.overall_miss_latency::cpu0.data 19260945000 # number of overall miss cycles 2803system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of overall miss cycles 2804system.l2c.overall_miss_latency::cpu1.dtb.walker 192694000 # number of overall miss cycles 2805system.l2c.overall_miss_latency::cpu1.itb.walker 194855000 # number of overall miss cycles 2806system.l2c.overall_miss_latency::cpu1.inst 3362110000 # number of overall miss cycles 2807system.l2c.overall_miss_latency::cpu1.data 13113546000 # number of overall miss cycles 2808system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of overall miss cycles 2809system.l2c.overall_miss_latency::total 90826061493 # number of overall miss cycles 2810system.l2c.WritebackDirty_accesses::writebacks 2606701 # number of WritebackDirty accesses(hits+misses) 2811system.l2c.WritebackDirty_accesses::total 2606701 # number of WritebackDirty accesses(hits+misses) 2812system.l2c.UpgradeReq_accesses::cpu0.data 219171 # number of UpgradeReq accesses(hits+misses) 2813system.l2c.UpgradeReq_accesses::cpu1.data 190208 # number of UpgradeReq accesses(hits+misses) 2814system.l2c.UpgradeReq_accesses::total 409379 # number of UpgradeReq accesses(hits+misses) 2815system.l2c.SCUpgradeReq_accesses::cpu0.data 49884 # number of SCUpgradeReq accesses(hits+misses) 2816system.l2c.SCUpgradeReq_accesses::cpu1.data 49655 # number of SCUpgradeReq accesses(hits+misses) 2817system.l2c.SCUpgradeReq_accesses::total 99539 # number of SCUpgradeReq accesses(hits+misses) 2818system.l2c.ReadExReq_accesses::cpu0.data 126467 # number of ReadExReq accesses(hits+misses) 2819system.l2c.ReadExReq_accesses::cpu1.data 109980 # number of ReadExReq accesses(hits+misses) 2820system.l2c.ReadExReq_accesses::total 236447 # number of ReadExReq accesses(hits+misses) 2821system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6135 # number of ReadSharedReq accesses(hits+misses) 2822system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4844 # number of ReadSharedReq accesses(hits+misses) 2823system.l2c.ReadSharedReq_accesses::cpu0.inst 460700 # number of ReadSharedReq accesses(hits+misses) 2824system.l2c.ReadSharedReq_accesses::cpu0.data 674136 # number of ReadSharedReq accesses(hits+misses) 2825system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 498740 # number of ReadSharedReq accesses(hits+misses) 2826system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8150 # number of ReadSharedReq accesses(hits+misses) 2827system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7429 # number of ReadSharedReq accesses(hits+misses) 2828system.l2c.ReadSharedReq_accesses::cpu1.inst 458917 # number of ReadSharedReq accesses(hits+misses) 2829system.l2c.ReadSharedReq_accesses::cpu1.data 636806 # number of ReadSharedReq accesses(hits+misses) 2830system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 472131 # number of ReadSharedReq accesses(hits+misses) 2831system.l2c.ReadSharedReq_accesses::total 3227988 # number of ReadSharedReq accesses(hits+misses) 2832system.l2c.InvalidateReq_accesses::cpu0.data 565273 # number of InvalidateReq accesses(hits+misses) 2833system.l2c.InvalidateReq_accesses::cpu1.data 236906 # number of InvalidateReq accesses(hits+misses) 2834system.l2c.InvalidateReq_accesses::total 802179 # number of InvalidateReq accesses(hits+misses) 2835system.l2c.demand_accesses::cpu0.dtb.walker 6135 # number of demand (read+write) accesses 2836system.l2c.demand_accesses::cpu0.itb.walker 4844 # number of demand (read+write) accesses 2837system.l2c.demand_accesses::cpu0.inst 460700 # number of demand (read+write) accesses 2838system.l2c.demand_accesses::cpu0.data 800603 # number of demand (read+write) accesses 2839system.l2c.demand_accesses::cpu0.l2cache.prefetcher 498740 # number of demand (read+write) accesses 2840system.l2c.demand_accesses::cpu1.dtb.walker 8150 # number of demand (read+write) accesses 2841system.l2c.demand_accesses::cpu1.itb.walker 7429 # number of demand (read+write) accesses 2842system.l2c.demand_accesses::cpu1.inst 458917 # number of demand (read+write) accesses 2843system.l2c.demand_accesses::cpu1.data 746786 # number of demand (read+write) accesses 2844system.l2c.demand_accesses::cpu1.l2cache.prefetcher 472131 # number of demand (read+write) accesses 2845system.l2c.demand_accesses::total 3464435 # number of demand (read+write) accesses 2846system.l2c.overall_accesses::cpu0.dtb.walker 6135 # number of overall (read+write) accesses 2847system.l2c.overall_accesses::cpu0.itb.walker 4844 # number of overall (read+write) accesses 2848system.l2c.overall_accesses::cpu0.inst 460700 # number of overall (read+write) accesses 2849system.l2c.overall_accesses::cpu0.data 800603 # number of overall (read+write) accesses 2850system.l2c.overall_accesses::cpu0.l2cache.prefetcher 498740 # number of overall (read+write) accesses 2851system.l2c.overall_accesses::cpu1.dtb.walker 8150 # number of overall (read+write) accesses 2852system.l2c.overall_accesses::cpu1.itb.walker 7429 # number of overall (read+write) accesses 2853system.l2c.overall_accesses::cpu1.inst 458917 # number of overall (read+write) accesses 2854system.l2c.overall_accesses::cpu1.data 746786 # number of overall (read+write) accesses 2855system.l2c.overall_accesses::cpu1.l2cache.prefetcher 472131 # number of overall (read+write) accesses 2856system.l2c.overall_accesses::total 3464435 # number of overall (read+write) accesses 2857system.l2c.UpgradeReq_miss_rate::cpu0.data 0.279334 # miss rate for UpgradeReq accesses 2858system.l2c.UpgradeReq_miss_rate::cpu1.data 0.314256 # miss rate for UpgradeReq accesses 2859system.l2c.UpgradeReq_miss_rate::total 0.295560 # miss rate for UpgradeReq accesses 2860system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.261727 # miss rate for SCUpgradeReq accesses 2861system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.254174 # miss rate for SCUpgradeReq accesses 2862system.l2c.SCUpgradeReq_miss_rate::total 0.257959 # miss rate for SCUpgradeReq accesses 2863system.l2c.ReadExReq_miss_rate::cpu0.data 0.637146 # miss rate for ReadExReq accesses 2864system.l2c.ReadExReq_miss_rate::cpu1.data 0.479442 # miss rate for ReadExReq accesses 2865system.l2c.ReadExReq_miss_rate::total 0.563792 # miss rate for ReadExReq accesses 2866system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for ReadSharedReq accesses 2867system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311107 # miss rate for ReadSharedReq accesses 2868system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107002 # miss rate for ReadSharedReq accesses 2869system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.203489 # miss rate for ReadSharedReq accesses 2870system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for ReadSharedReq accesses 2871system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for ReadSharedReq accesses 2872system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.284830 # miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085342 # miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.150101 # miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_miss_rate::total 0.231524 # miss rate for ReadSharedReq accesses 2877system.l2c.InvalidateReq_miss_rate::cpu0.data 0.789622 # miss rate for InvalidateReq accesses 2878system.l2c.InvalidateReq_miss_rate::cpu1.data 0.483301 # miss rate for InvalidateReq accesses 2879system.l2c.InvalidateReq_miss_rate::total 0.699157 # miss rate for InvalidateReq accesses 2880system.l2c.demand_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for demand accesses 2881system.l2c.demand_miss_rate::cpu0.itb.walker 0.311107 # miss rate for demand accesses 2882system.l2c.demand_miss_rate::cpu0.inst 0.107002 # miss rate for demand accesses 2883system.l2c.demand_miss_rate::cpu0.data 0.271991 # miss rate for demand accesses 2884system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for demand accesses 2885system.l2c.demand_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for demand accesses 2886system.l2c.demand_miss_rate::cpu1.itb.walker 0.284830 # miss rate for demand accesses 2887system.l2c.demand_miss_rate::cpu1.inst 0.085342 # miss rate for demand accesses 2888system.l2c.demand_miss_rate::cpu1.data 0.198603 # miss rate for demand accesses 2889system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for demand accesses 2890system.l2c.demand_miss_rate::total 0.254201 # miss rate for demand accesses 2891system.l2c.overall_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for overall accesses 2892system.l2c.overall_miss_rate::cpu0.itb.walker 0.311107 # miss rate for overall accesses 2893system.l2c.overall_miss_rate::cpu0.inst 0.107002 # miss rate for overall accesses 2894system.l2c.overall_miss_rate::cpu0.data 0.271991 # miss rate for overall accesses 2895system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for overall accesses 2896system.l2c.overall_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for overall accesses 2897system.l2c.overall_miss_rate::cpu1.itb.walker 0.284830 # miss rate for overall accesses 2898system.l2c.overall_miss_rate::cpu1.inst 0.085342 # miss rate for overall accesses 2899system.l2c.overall_miss_rate::cpu1.data 0.198603 # miss rate for overall accesses 2900system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for overall accesses 2901system.l2c.overall_miss_rate::total 0.254201 # miss rate for overall accesses 2902system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6008.616184 # average UpgradeReq miss latency 2903system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6018.737244 # average UpgradeReq miss latency 2904system.l2c.UpgradeReq_avg_miss_latency::total 6013.616153 # average UpgradeReq miss latency 2905system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5388.595282 # average SCUpgradeReq miss latency 2906system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5674.589969 # average SCUpgradeReq miss latency 2907system.l2c.SCUpgradeReq_avg_miss_latency::total 5529.170074 # average SCUpgradeReq miss latency 2908system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87566.004368 # average ReadExReq miss latency 2909system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83519.600220 # average ReadExReq miss latency 2910system.l2c.ReadExReq_avg_miss_latency::total 85965.466930 # average ReadExReq miss latency 2911system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average ReadSharedReq miss latency 2912system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90667.551427 # average ReadSharedReq miss latency 2913system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85340.331873 # average ReadSharedReq miss latency 2914system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88971.719432 # average ReadSharedReq miss latency 2915system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average ReadSharedReq miss latency 2916system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average ReadSharedReq miss latency 2917system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92086.483932 # average ReadSharedReq miss latency 2918system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85844.759351 # average ReadSharedReq miss latency 2919system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91119.328346 # average ReadSharedReq miss latency 2920system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average ReadSharedReq miss latency 2921system.l2c.ReadSharedReq_avg_miss_latency::total 106196.060503 # average ReadSharedReq miss latency 2922system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 105.620676 # average InvalidateReq miss latency 2923system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 396.176319 # average InvalidateReq miss latency 2924system.l2c.InvalidateReq_avg_miss_latency::total 164.937443 # average InvalidateReq miss latency 2925system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average overall miss latency 2926system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90667.551427 # average overall miss latency 2927system.l2c.demand_avg_miss_latency::cpu0.inst 85340.331873 # average overall miss latency 2928system.l2c.demand_avg_miss_latency::cpu0.data 88451.553796 # average overall miss latency 2929system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average overall miss latency 2930system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average overall miss latency 2931system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92086.483932 # average overall miss latency 2932system.l2c.demand_avg_miss_latency::cpu1.inst 85844.759351 # average overall miss latency 2933system.l2c.demand_avg_miss_latency::cpu1.data 88417.452162 # average overall miss latency 2934system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average overall miss latency 2935system.l2c.demand_avg_miss_latency::total 103133.731624 # average overall miss latency 2936system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average overall miss latency 2937system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90667.551427 # average overall miss latency 2938system.l2c.overall_avg_miss_latency::cpu0.inst 85340.331873 # average overall miss latency 2939system.l2c.overall_avg_miss_latency::cpu0.data 88451.553796 # average overall miss latency 2940system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average overall miss latency 2941system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average overall miss latency 2942system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92086.483932 # average overall miss latency 2943system.l2c.overall_avg_miss_latency::cpu1.inst 85844.759351 # average overall miss latency 2944system.l2c.overall_avg_miss_latency::cpu1.data 88417.452162 # average overall miss latency 2945system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average overall miss latency 2946system.l2c.overall_avg_miss_latency::total 103133.731624 # average overall miss latency 2947system.l2c.blocked_cycles::no_mshrs 237 # number of cycles access was blocked 2948system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2949system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked 2950system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2951system.l2c.avg_blocked_cycles::no_mshrs 237 # average number of cycles each access was blocked 2952system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2953system.l2c.writebacks::writebacks 1068644 # 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number of overall MSHR hits 2966system.l2c.overall_mshr_hits::cpu0.data 7 # number of overall MSHR hits 2967system.l2c.overall_mshr_hits::cpu1.inst 109 # number of overall MSHR hits 2968system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 2969system.l2c.overall_mshr_hits::total 182 # number of overall MSHR hits 2970system.l2c.CleanEvict_mshr_misses::writebacks 46836 # number of CleanEvict MSHR misses 2971system.l2c.CleanEvict_mshr_misses::total 46836 # number of CleanEvict MSHR misses 2972system.l2c.UpgradeReq_mshr_misses::cpu0.data 61222 # number of UpgradeReq MSHR misses 2973system.l2c.UpgradeReq_mshr_misses::cpu1.data 59774 # number of UpgradeReq MSHR misses 2974system.l2c.UpgradeReq_mshr_misses::total 120996 # number of UpgradeReq MSHR misses 2975system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13056 # number of SCUpgradeReq MSHR misses 2976system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12621 # number of SCUpgradeReq MSHR misses 2977system.l2c.SCUpgradeReq_mshr_misses::total 25677 # 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number of overall MSHR misses 3011system.l2c.overall_mshr_misses::cpu1.dtb.walker 2146 # number of overall MSHR misses 3012system.l2c.overall_mshr_misses::cpu1.itb.walker 2116 # number of overall MSHR misses 3013system.l2c.overall_mshr_misses::cpu1.inst 39056 # number of overall MSHR misses 3014system.l2c.overall_mshr_misses::cpu1.data 148290 # number of overall MSHR misses 3015system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of overall MSHR misses 3016system.l2c.overall_mshr_misses::total 880481 # number of overall MSHR misses 3017system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 3018system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable 3019system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 3020system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11033 # number of ReadReq MSHR uncacheable 3021system.l2c.ReadReq_mshr_uncacheable::total 81885 # number of ReadReq MSHR uncacheable 3022system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26565 # 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number of demand (read+write) MSHR miss cycles 3061system.l2c.demand_mshr_miss_latency::cpu1.data 11628713863 # number of demand (read+write) MSHR miss cycles 3062system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of demand (read+write) MSHR miss cycles 3063system.l2c.demand_mshr_miss_latency::total 82006341193 # number of demand (read+write) MSHR miss cycles 3064system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of overall MSHR miss cycles 3065system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 121565002 # number of overall MSHR miss cycles 3066system.l2c.overall_mshr_miss_latency::cpu0.inst 3711112036 # number of overall MSHR miss cycles 3067system.l2c.overall_mshr_miss_latency::cpu0.data 17082952760 # number of overall MSHR miss cycles 3068system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of overall MSHR miss cycles 3069system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of overall MSHR miss cycles 3070system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173694002 # number of overall MSHR miss cycles 3071system.l2c.overall_mshr_miss_latency::cpu1.inst 2962814058 # number of overall MSHR miss cycles 3072system.l2c.overall_mshr_miss_latency::cpu1.data 11628713863 # number of overall MSHR miss cycles 3073system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of overall MSHR miss cycles 3074system.l2c.overall_mshr_miss_latency::total 82006341193 # number of overall MSHR miss cycles 3075system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles 3076system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4353667507 # number of ReadReq MSHR uncacheable cycles 3077system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7421000 # number of ReadReq MSHR uncacheable cycles 3078system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1606781004 # number of ReadReq MSHR uncacheable cycles 3079system.l2c.ReadReq_mshr_uncacheable_latency::total 8687651511 # number of ReadReq MSHR uncacheable cycles 3080system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles 3081system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4353667507 # number of overall MSHR uncacheable cycles 3082system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7421000 # number of overall MSHR uncacheable cycles 3083system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1606781004 # number of overall MSHR uncacheable cycles 3084system.l2c.overall_mshr_uncacheable_latency::total 8687651511 # number of overall MSHR uncacheable cycles 3085system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3086system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3087system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.279334 # mshr miss rate for UpgradeReq accesses 3088system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.314256 # mshr miss rate for UpgradeReq accesses 3089system.l2c.UpgradeReq_mshr_miss_rate::total 0.295560 # mshr miss rate for UpgradeReq accesses 3090system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.261727 # mshr miss rate for SCUpgradeReq accesses 3091system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.254174 # mshr miss rate for SCUpgradeReq accesses 3092system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.257959 # mshr miss rate for SCUpgradeReq accesses 3093system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.637146 # mshr miss rate for ReadExReq accesses 3094system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.479442 # mshr miss rate for ReadExReq accesses 3095system.l2c.ReadExReq_mshr_miss_rate::total 0.563792 # mshr miss rate for ReadExReq accesses 3096system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for ReadSharedReq accesses 3097system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for ReadSharedReq accesses 3098system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for ReadSharedReq accesses 3099system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.203478 # mshr miss rate for ReadSharedReq accesses 3100system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for ReadSharedReq accesses 3101system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for ReadSharedReq accesses 3102system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for ReadSharedReq accesses 3103system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for ReadSharedReq accesses 3104system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.150063 # mshr miss rate for ReadSharedReq accesses 3105system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for ReadSharedReq accesses 3106system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231467 # mshr miss rate for ReadSharedReq accesses 3107system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789622 # mshr miss rate for InvalidateReq accesses 3108system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.483301 # mshr miss rate for InvalidateReq accesses 3109system.l2c.InvalidateReq_mshr_miss_rate::total 0.699157 # mshr miss rate for InvalidateReq accesses 3110system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for demand accesses 3111system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for demand accesses 3112system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for demand accesses 3113system.l2c.demand_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for demand accesses 3114system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for demand accesses 3115system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for demand accesses 3116system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for demand accesses 3117system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for demand accesses 3118system.l2c.demand_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for demand accesses 3119system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for demand accesses 3120system.l2c.demand_mshr_miss_rate::total 0.254149 # mshr miss rate for demand accesses 3121system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for overall accesses 3122system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for overall accesses 3123system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for overall accesses 3124system.l2c.overall_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for overall accesses 3125system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for overall accesses 3126system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for overall accesses 3127system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for overall accesses 3128system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for overall accesses 3129system.l2c.overall_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for overall accesses 3130system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for overall accesses 3131system.l2c.overall_mshr_miss_rate::total 0.254149 # mshr miss rate for overall accesses 3132system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21804.686224 # average UpgradeReq mshr miss latency 3133system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21789.373306 # average UpgradeReq mshr miss latency 3134system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21797.121392 # average UpgradeReq mshr miss latency 3135system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24741.881127 # average SCUpgradeReq mshr miss latency 3136system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24821.487996 # average SCUpgradeReq mshr miss latency 3137system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24781.010243 # average SCUpgradeReq mshr miss latency 3138system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77565.508997 # average ReadExReq mshr miss latency 3139system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73518.653872 # average ReadExReq mshr miss latency 3140system.l2c.ReadExReq_avg_mshr_miss_latency::total 75964.793177 # average ReadExReq mshr miss latency 3141system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average ReadSharedReq mshr miss latency 3142system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average ReadSharedReq mshr miss latency 3143system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average ReadSharedReq mshr miss latency 3144system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78972.962237 # average ReadSharedReq mshr miss latency 3145system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average ReadSharedReq mshr miss latency 3146system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average ReadSharedReq mshr miss latency 3147system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average ReadSharedReq mshr miss latency 3148system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average ReadSharedReq mshr miss latency 3149system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81122.516121 # average ReadSharedReq mshr miss latency 3150system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average ReadSharedReq mshr miss latency 3151system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96202.092831 # average ReadSharedReq mshr miss latency 3152system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19963.677770 # average InvalidateReq mshr miss latency 3153system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20378.857088 # average InvalidateReq mshr miss latency 3154system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20048.436388 # average InvalidateReq mshr miss latency 3155system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency 3156system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency 3157system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency 3158system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency 3159system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency 3160system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency 3161system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency 3162system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency 3163system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency 3164system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency 3165system.l2c.demand_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency 3166system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency 3167system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency 3168system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency 3169system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency 3170system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency 3171system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency 3172system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency 3173system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency 3174system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency 3175system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency 3176system.l2c.overall_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency 3177system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency 3178system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482 # average ReadReq mshr uncacheable latency 3179system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average ReadReq mshr uncacheable latency 3180system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069 # average ReadReq mshr uncacheable latency 3181system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484 # average ReadReq mshr uncacheable latency 3182system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency 3183system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147 # average overall mshr uncacheable latency 3184system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average overall mshr uncacheable latency 3185system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency 3186system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency 3187system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. 3188system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3189system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3190system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3191system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3192system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3193system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3194system.membus.trans_dist::ReadReq 81885 # Transaction distribution 3195system.membus.trans_dist::ReadResp 837971 # Transaction distribution 3196system.membus.trans_dist::WriteReq 38514 # Transaction distribution 3197system.membus.trans_dist::WriteResp 38514 # Transaction distribution 3198system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution 3199system.membus.trans_dist::CleanEvict 216465 # Transaction distribution 3200system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution 3201system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution 3202system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3203system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3204system.membus.trans_dist::ReadExReq 147056 # Transaction distribution 3205system.membus.trans_dist::ReadExResp 129063 # Transaction distribution 3206system.membus.trans_dist::ReadSharedReq 756086 # Transaction distribution 3207system.membus.trans_dist::InvalidateReq 664574 # Transaction distribution 3208system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122674 # Packet count per connected master and slave (bytes) 3209system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3210system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26434 # Packet count per connected master and slave (bytes) 3211system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4433526 # Packet count per connected master and slave (bytes) 3212system.membus.pkt_count_system.l2c.mem_side::total 4582726 # Packet count per connected master and slave (bytes) 3213system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237876 # Packet count per connected master and slave (bytes) 3214system.membus.pkt_count_system.iocache.mem_side::total 237876 # Packet count per connected master and slave (bytes) 3215system.membus.pkt_count::total 4820602 # Packet count per connected master and slave (bytes) 3216system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155781 # Cumulative packet size per connected master and slave (bytes) 3217system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3218system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52868 # Cumulative packet size per connected master and slave (bytes) 3219system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124620204 # Cumulative packet size per connected master and slave (bytes) 3220system.membus.pkt_size_system.l2c.mem_side::total 124829057 # Cumulative packet size per connected master and slave (bytes) 3221system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253952 # Cumulative packet size per connected master and slave (bytes) 3222system.membus.pkt_size_system.iocache.mem_side::total 7253952 # Cumulative packet size per connected master and slave (bytes) 3223system.membus.pkt_size::total 132083009 # Cumulative packet size per connected master and slave (bytes) 3224system.membus.snoops 605187 # Total snoops (count) 3225system.membus.snoop_fanout::samples 2426230 # Request fanout histogram 3226system.membus.snoop_fanout::mean 0.013777 # Request fanout histogram 3227system.membus.snoop_fanout::stdev 0.116566 # Request fanout histogram 3228system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3229system.membus.snoop_fanout::0 2392803 98.62% 98.62% # Request fanout histogram 3230system.membus.snoop_fanout::1 33427 1.38% 100.00% # Request fanout histogram 3231system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3232system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3233system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3234system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3235system.membus.snoop_fanout::total 2426230 # Request fanout histogram 3236system.membus.reqLayer0.occupancy 101268497 # Layer occupancy (ticks) 3237system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3238system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3239system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3240system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) 3241system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3242system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) 3243system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3244system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) 3245system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3246system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) 3247system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3248system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3249system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3250system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3251system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3252system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3253system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3254system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3255system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3256system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3257system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3258system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3259system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3260system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3261system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3262system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3263system.realview.ethernet.txBytes 966 # Bytes Transmitted 3264system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3265system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3266system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3267system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3268system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3269system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3270system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3271system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3272system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3273system.realview.ethernet.totPackets 3 # Total Packets 3274system.realview.ethernet.totBytes 966 # Total Bytes 3275system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3276system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3277system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3278system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3279system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3280system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3281system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3282system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3283system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3284system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3285system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3286system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3287system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3288system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3289system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3290system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3291system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3292system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3293system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3294system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3295system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3296system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3297system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3298system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3299system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3300system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3301system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3302system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3303system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3304system.realview.ethernet.droppedPackets 0 # number of packets dropped 3305system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3306system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3307system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3308system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3309system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3310system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3311system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3312system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3313system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3314system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3315system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3316system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3317system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3318system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3319system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3320system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3321system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3322system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3323system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3324system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3325system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3326system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3327system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3328system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. 3329system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3330system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3331system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. 3332system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3333system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3334system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3335system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution 3336system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution 3337system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution 3338system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution 3339system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution 3340system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution 3341system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution 3342system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution 3343system.toL2Bus.trans_dist::UpgradeResp 1093112 # Transaction distribution 3344system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution 3345system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 3346system.toL2Bus.trans_dist::ReadExReq 292338 # Transaction distribution 3347system.toL2Bus.trans_dist::ReadExResp 292338 # Transaction distribution 3348system.toL2Bus.trans_dist::ReadSharedReq 4001459 # Transaction distribution 3349system.toL2Bus.trans_dist::InvalidateReq 832376 # Transaction distribution 3350system.toL2Bus.trans_dist::InvalidateResp 802179 # Transaction distribution 3351system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8623692 # Packet count per connected master and slave (bytes) 3352system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7234411 # Packet count per connected master and slave (bytes) 3353system.toL2Bus.pkt_count::total 15858103 # Packet count per connected master and slave (bytes) 3354system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 210145531 # Cumulative packet size per connected master and slave (bytes) 3355system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 178915910 # Cumulative packet size per connected master and slave (bytes) 3356system.toL2Bus.pkt_size::total 389061441 # Cumulative packet size per connected master and slave (bytes) 3357system.toL2Bus.snoops 2781791 # Total snoops (count) 3358system.toL2Bus.snoop_fanout::samples 7676067 # Request fanout histogram 3359system.toL2Bus.snoop_fanout::mean 0.360389 # Request fanout histogram 3360system.toL2Bus.snoop_fanout::stdev 0.483218 # Request fanout histogram 3361system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3362system.toL2Bus.snoop_fanout::0 4921172 64.11% 64.11% # Request fanout histogram 3363system.toL2Bus.snoop_fanout::1 2743418 35.74% 99.85% # Request fanout histogram 3364system.toL2Bus.snoop_fanout::2 11477 0.15% 100.00% # Request fanout histogram 3365system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3366system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3367system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3368system.toL2Bus.snoop_fanout::total 7676067 # Request fanout histogram 3369system.toL2Bus.reqLayer0.occupancy 8520913919 # Layer occupancy (ticks) 3370system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3371system.toL2Bus.snoopLayer0.occupancy 2554437 # Layer occupancy (ticks) 3372system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3373system.toL2Bus.respLayer0.occupancy 3920667694 # Layer occupancy (ticks) 3374system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3375system.toL2Bus.respLayer1.occupancy 3580148330 # Layer occupancy (ticks) 3376system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3377 3378---------- End Simulation Statistics ----------	1574system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1575system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1576system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1577system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1578system.cpu1.itb.read_accesses 0 # DTB read accesses 1579system.cpu1.itb.write_accesses 0 # DTB write accesses 1580system.cpu1.itb.inst_accesses 420947363 # ITB inst accesses 1581system.cpu1.itb.hits 420888418 # DTB hits 1582system.cpu1.itb.misses 58945 # DTB misses 1583system.cpu1.itb.accesses 420947363 # DTB accesses 1584system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions 1585system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state 1586system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state 1587system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state 1588system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state 1589system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state 1590system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state 1591system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state 1592system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 1593system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 1594system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 1595system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state 1596system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1597system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state 1598system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state 1599system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states 1600system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states 1601system.cpu1.numCycles 95045540824 # number of cpu cycles simulated 1602system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1603system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1604system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1605system.cpu1.kern.inst.quiesce 4988 # number of quiesce instructions executed 1606system.cpu1.committedInsts 420606589 # Number of instructions committed 1607system.cpu1.committedOps 495760659 # Number of ops (including micro ops) committed 1608system.cpu1.num_int_alu_accesses 455422102 # Number of integer alu accesses 1609system.cpu1.num_fp_alu_accesses 465343 # Number of float alu accesses 1610system.cpu1.num_func_calls 25050170 # number of times a function call or return occured 1611system.cpu1.num_conditional_control_insts 64233743 # number of instructions that are conditional controls 1612system.cpu1.num_int_insts 455422102 # number of integer instructions 1613system.cpu1.num_fp_insts 465343 # number of float instructions 1614system.cpu1.num_int_register_reads 665130045 # number of times the integer registers were read 1615system.cpu1.num_int_register_writes 361560137 # number of times the integer registers were written 1616system.cpu1.num_fp_register_reads 742394 # number of times the floating registers were read 1617system.cpu1.num_fp_register_writes 410584 # number of times the floating registers were written 1618system.cpu1.num_cc_register_reads 110025684 # number of times the CC registers were read 1619system.cpu1.num_cc_register_writes 109785328 # number of times the CC registers were written 1620system.cpu1.num_mem_refs 151477231 # number of memory refs 1621system.cpu1.num_load_insts 79227868 # Number of load instructions 1622system.cpu1.num_store_insts 72249363 # Number of store instructions 1623system.cpu1.num_idle_cycles 94048242615.068481 # Number of idle cycles 1624system.cpu1.num_busy_cycles 997298208.931515 # Number of busy cycles 1625system.cpu1.not_idle_fraction 0.010493 # Percentage of non-idle cycles 1626system.cpu1.idle_fraction 0.989507 # Percentage of idle cycles 1627system.cpu1.Branches 93889993 # Number of branches fetched 1628system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 1629system.cpu1.op_class::IntAlu 343412693 69.23% 69.23% # Class of executed instruction 1630system.cpu1.op_class::IntMult 1029907 0.21% 69.44% # Class of executed instruction 1631system.cpu1.op_class::IntDiv 56328 0.01% 69.45% # Class of executed instruction 1632system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction 1633system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction 1634system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction 1635system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction 1636system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction 1637system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction 1638system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction 1639system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction 1640system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction 1641system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction 1642system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction 1643system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction 1644system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction 1645system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction 1646system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction 1647system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction 1648system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction 1649system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.45% # Class of executed instruction 1650system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction 1651system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.45% # Class of executed instruction 1652system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.45% # Class of executed instruction 1653system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction 1654system.cpu1.op_class::SimdFloatMisc 66396 0.01% 69.46% # Class of executed instruction 1655system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction 1656system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction 1657system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction 1658system.cpu1.op_class::MemRead 79227868 15.97% 85.43% # Class of executed instruction 1659system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Class of executed instruction 1660system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1661system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1662system.cpu1.op_class::total 496042597 # Class of executed instruction 1663system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1664system.cpu1.dcache.tags.replacements 5018466 # number of replacements 1665system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use 1666system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. 1667system.cpu1.dcache.tags.sampled_refs 5018977 # Sample count of references to valid blocks. 1668system.cpu1.dcache.tags.avg_refs 29.144932 # Average number of references to valid blocks. 1669system.cpu1.dcache.tags.warmup_cycle 8378732349000 # Cycle when the warmup percentage was hit. 1670system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.493139 # Average occupied blocks per requestor 1671system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848619 # Average percentage of cache occupancy 1672system.cpu1.dcache.tags.occ_percent::total 0.848619 # Average percentage of cache occupancy 1673system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1674system.cpu1.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 1675system.cpu1.dcache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 1676system.cpu1.dcache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 1677system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1678system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1679system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses 1680system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses 1681system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1682system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits 1683system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits 1684system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits 1685system.cpu1.dcache.WriteReq_hits::total 68485479 # number of WriteReq hits 1686system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174561 # number of SoftPFReq hits 1687system.cpu1.dcache.SoftPFReq_hits::total 174561 # number of SoftPFReq hits 1688system.cpu1.dcache.WriteLineReq_hits::cpu1.data 162110 # number of WriteLineReq hits 1689system.cpu1.dcache.WriteLineReq_hits::total 162110 # number of WriteLineReq hits 1690system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1665176 # number of LoadLockedReq hits 1691system.cpu1.dcache.LoadLockedReq_hits::total 1665176 # number of LoadLockedReq hits 1692system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1621987 # number of StoreCondReq hits 1693system.cpu1.dcache.StoreCondReq_hits::total 1621987 # number of StoreCondReq hits 1694system.cpu1.dcache.demand_hits::cpu1.data 142401211 # number of demand (read+write) hits 1695system.cpu1.dcache.demand_hits::total 142401211 # number of demand (read+write) hits 1696system.cpu1.dcache.overall_hits::cpu1.data 142575772 # number of overall hits 1697system.cpu1.dcache.overall_hits::total 142575772 # number of overall hits 1698system.cpu1.dcache.ReadReq_misses::cpu1.data 2838030 # number of ReadReq misses 1699system.cpu1.dcache.ReadReq_misses::total 2838030 # number of ReadReq misses 1700system.cpu1.dcache.WriteReq_misses::cpu1.data 1310627 # number of WriteReq misses 1701system.cpu1.dcache.WriteReq_misses::total 1310627 # number of WriteReq misses 1702system.cpu1.dcache.SoftPFReq_misses::cpu1.data 624714 # number of SoftPFReq misses 1703system.cpu1.dcache.SoftPFReq_misses::total 624714 # number of SoftPFReq misses 1704system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447850 # number of WriteLineReq misses 1705system.cpu1.dcache.WriteLineReq_misses::total 447850 # number of WriteLineReq misses 1706system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162703 # number of LoadLockedReq misses 1707system.cpu1.dcache.LoadLockedReq_misses::total 162703 # number of LoadLockedReq misses 1708system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204676 # number of StoreCondReq misses 1709system.cpu1.dcache.StoreCondReq_misses::total 204676 # number of StoreCondReq misses 1710system.cpu1.dcache.demand_misses::cpu1.data 4596507 # number of demand (read+write) misses 1711system.cpu1.dcache.demand_misses::total 4596507 # number of demand (read+write) misses 1712system.cpu1.dcache.overall_misses::cpu1.data 5221221 # number of overall misses 1713system.cpu1.dcache.overall_misses::total 5221221 # number of overall misses 1714system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40862074000 # number of ReadReq miss cycles 1715system.cpu1.dcache.ReadReq_miss_latency::total 40862074000 # number of ReadReq miss cycles 1716system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24688918000 # number of WriteReq miss cycles 1717system.cpu1.dcache.WriteReq_miss_latency::total 24688918000 # number of WriteReq miss cycles 1718system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10778682000 # number of WriteLineReq miss cycles 1719system.cpu1.dcache.WriteLineReq_miss_latency::total 10778682000 # number of WriteLineReq miss cycles 1720system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2442456000 # number of LoadLockedReq miss cycles 1721system.cpu1.dcache.LoadLockedReq_miss_latency::total 2442456000 # number of LoadLockedReq miss cycles 1722system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5069864000 # number of StoreCondReq miss cycles 1723system.cpu1.dcache.StoreCondReq_miss_latency::total 5069864000 # number of StoreCondReq miss cycles 1724system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3108000 # number of StoreCondFailReq miss cycles 1725system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3108000 # number of StoreCondFailReq miss cycles 1726system.cpu1.dcache.demand_miss_latency::cpu1.data 76329674000 # number of demand (read+write) miss cycles 1727system.cpu1.dcache.demand_miss_latency::total 76329674000 # number of demand (read+write) miss cycles 1728system.cpu1.dcache.overall_miss_latency::cpu1.data 76329674000 # number of overall miss cycles 1729system.cpu1.dcache.overall_miss_latency::total 76329674000 # number of overall miss cycles 1730system.cpu1.dcache.ReadReq_accesses::cpu1.data 76591652 # number of ReadReq accesses(hits+misses) 1731system.cpu1.dcache.ReadReq_accesses::total 76591652 # number of ReadReq accesses(hits+misses) 1732system.cpu1.dcache.WriteReq_accesses::cpu1.data 69796106 # number of WriteReq accesses(hits+misses) 1733system.cpu1.dcache.WriteReq_accesses::total 69796106 # number of WriteReq accesses(hits+misses) 1734system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799275 # number of SoftPFReq accesses(hits+misses) 1735system.cpu1.dcache.SoftPFReq_accesses::total 799275 # number of SoftPFReq accesses(hits+misses) 1736system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 609960 # number of WriteLineReq accesses(hits+misses) 1737system.cpu1.dcache.WriteLineReq_accesses::total 609960 # number of WriteLineReq accesses(hits+misses) 1738system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1827879 # number of LoadLockedReq accesses(hits+misses) 1739system.cpu1.dcache.LoadLockedReq_accesses::total 1827879 # number of LoadLockedReq accesses(hits+misses) 1740system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1826663 # number of StoreCondReq accesses(hits+misses) 1741system.cpu1.dcache.StoreCondReq_accesses::total 1826663 # number of StoreCondReq accesses(hits+misses) 1742system.cpu1.dcache.demand_accesses::cpu1.data 146997718 # number of demand (read+write) accesses 1743system.cpu1.dcache.demand_accesses::total 146997718 # number of demand (read+write) accesses 1744system.cpu1.dcache.overall_accesses::cpu1.data 147796993 # number of overall (read+write) accesses 1745system.cpu1.dcache.overall_accesses::total 147796993 # number of overall (read+write) accesses 1746system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037054 # miss rate for ReadReq accesses 1747system.cpu1.dcache.ReadReq_miss_rate::total 0.037054 # miss rate for ReadReq accesses 1748system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018778 # miss rate for WriteReq accesses 1749system.cpu1.dcache.WriteReq_miss_rate::total 0.018778 # miss rate for WriteReq accesses 1750system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.781601 # miss rate for SoftPFReq accesses 1751system.cpu1.dcache.SoftPFReq_miss_rate::total 0.781601 # miss rate for SoftPFReq accesses 1752system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.734228 # miss rate for WriteLineReq accesses 1753system.cpu1.dcache.WriteLineReq_miss_rate::total 0.734228 # miss rate for WriteLineReq accesses 1754system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089012 # miss rate for LoadLockedReq accesses 1755system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089012 # miss rate for LoadLockedReq accesses 1756system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112049 # miss rate for StoreCondReq accesses 1757system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112049 # miss rate for StoreCondReq accesses 1758system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031269 # miss rate for demand accesses 1759system.cpu1.dcache.demand_miss_rate::total 0.031269 # miss rate for demand accesses 1760system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035327 # miss rate for overall accesses 1761system.cpu1.dcache.overall_miss_rate::total 0.035327 # miss rate for overall accesses 1762system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14398.041599 # average ReadReq miss latency 1763system.cpu1.dcache.ReadReq_avg_miss_latency::total 14398.041599 # average ReadReq miss latency 1764system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18837.486180 # average WriteReq miss latency 1765system.cpu1.dcache.WriteReq_avg_miss_latency::total 18837.486180 # average WriteReq miss latency 1766system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24067.616389 # average WriteLineReq miss latency 1767system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24067.616389 # average WriteLineReq miss latency 1768system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15011.745327 # average LoadLockedReq miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15011.745327 # average LoadLockedReq miss latency 1770system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24770.192890 # average StoreCondReq miss latency 1771system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24770.192890 # average StoreCondReq miss latency 1772system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1773system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1774system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16606.017134 # average overall miss latency 1775system.cpu1.dcache.demand_avg_miss_latency::total 16606.017134 # average overall miss latency 1776system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14619.123381 # average overall miss latency 1777system.cpu1.dcache.overall_avg_miss_latency::total 14619.123381 # average overall miss latency 1778system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1779system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1780system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1781system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1782system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1783system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1784system.cpu1.dcache.writebacks::writebacks 5018466 # number of writebacks 1785system.cpu1.dcache.writebacks::total 5018466 # number of writebacks 1786system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16365 # number of ReadReq MSHR hits 1787system.cpu1.dcache.ReadReq_mshr_hits::total 16365 # number of ReadReq MSHR hits 1788system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 405 # number of WriteReq MSHR hits 1789system.cpu1.dcache.WriteReq_mshr_hits::total 405 # number of WriteReq MSHR hits 1790system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42163 # number of LoadLockedReq MSHR hits 1791system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42163 # number of LoadLockedReq MSHR hits 1792system.cpu1.dcache.demand_mshr_hits::cpu1.data 16770 # number of demand (read+write) MSHR hits 1793system.cpu1.dcache.demand_mshr_hits::total 16770 # number of demand (read+write) MSHR hits 1794system.cpu1.dcache.overall_mshr_hits::cpu1.data 16770 # number of overall MSHR hits 1795system.cpu1.dcache.overall_mshr_hits::total 16770 # number of overall MSHR hits 1796system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2821665 # number of ReadReq MSHR misses 1797system.cpu1.dcache.ReadReq_mshr_misses::total 2821665 # number of ReadReq MSHR misses 1798system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1310222 # number of WriteReq MSHR misses 1799system.cpu1.dcache.WriteReq_mshr_misses::total 1310222 # number of WriteReq MSHR misses 1800system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 624714 # number of SoftPFReq MSHR misses 1801system.cpu1.dcache.SoftPFReq_mshr_misses::total 624714 # number of SoftPFReq MSHR misses 1802system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 447850 # number of WriteLineReq MSHR misses 1803system.cpu1.dcache.WriteLineReq_mshr_misses::total 447850 # number of WriteLineReq MSHR misses 1804system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses 1805system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses 1806system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204676 # number of StoreCondReq MSHR misses 1807system.cpu1.dcache.StoreCondReq_mshr_misses::total 204676 # number of StoreCondReq MSHR misses 1808system.cpu1.dcache.demand_mshr_misses::cpu1.data 4579737 # number of demand (read+write) MSHR misses 1809system.cpu1.dcache.demand_mshr_misses::total 4579737 # number of demand (read+write) MSHR misses 1810system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204451 # number of overall MSHR misses 1811system.cpu1.dcache.overall_mshr_misses::total 5204451 # number of overall MSHR misses 1812system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable 1813system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11035 # number of ReadReq MSHR uncacheable 1814system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable 1815system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable 1816system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses 1817system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22984 # number of overall MSHR uncacheable misses 1818system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37160053500 # number of ReadReq MSHR miss cycles 1819system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37160053500 # number of ReadReq MSHR miss cycles 1820system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23356658000 # number of WriteReq MSHR miss cycles 1821system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23356658000 # number of WriteReq MSHR miss cycles 1822system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12967475000 # number of SoftPFReq MSHR miss cycles 1823system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12967475000 # number of SoftPFReq MSHR miss cycles 1824system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10330832000 # number of WriteLineReq MSHR miss cycles 1825system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10330832000 # number of WriteLineReq MSHR miss cycles 1826system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654542500 # number of LoadLockedReq MSHR miss cycles 1827system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1654542500 # number of LoadLockedReq MSHR miss cycles 1828system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4865246000 # number of StoreCondReq MSHR miss cycles 1829system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4865246000 # number of StoreCondReq MSHR miss cycles 1830system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3050000 # number of StoreCondFailReq MSHR miss cycles 1831system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3050000 # number of StoreCondFailReq MSHR miss cycles 1832system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70847543500 # number of demand (read+write) MSHR miss cycles 1833system.cpu1.dcache.demand_mshr_miss_latency::total 70847543500 # number of demand (read+write) MSHR miss cycles 1834system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83815018500 # number of overall MSHR miss cycles 1835system.cpu1.dcache.overall_mshr_miss_latency::total 83815018500 # number of overall MSHR miss cycles 1836system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1894238000 # number of ReadReq MSHR uncacheable cycles 1837system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1894238000 # number of ReadReq MSHR uncacheable cycles 1838system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1894238000 # number of overall MSHR uncacheable cycles 1839system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1894238000 # number of overall MSHR uncacheable cycles 1840system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036840 # mshr miss rate for ReadReq accesses 1841system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036840 # mshr miss rate for ReadReq accesses 1842system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018772 # mshr miss rate for WriteReq accesses 1843system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018772 # mshr miss rate for WriteReq accesses 1844system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.781601 # mshr miss rate for SoftPFReq accesses 1845system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.781601 # mshr miss rate for SoftPFReq accesses 1846system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734228 # mshr miss rate for WriteLineReq accesses 1847system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734228 # mshr miss rate for WriteLineReq accesses 1848system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065945 # mshr miss rate for LoadLockedReq accesses 1849system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065945 # mshr miss rate for LoadLockedReq accesses 1850system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112049 # mshr miss rate for StoreCondReq accesses 1851system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112049 # mshr miss rate for StoreCondReq accesses 1852system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031155 # mshr miss rate for demand accesses 1853system.cpu1.dcache.demand_mshr_miss_rate::total 0.031155 # mshr miss rate for demand accesses 1854system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035214 # mshr miss rate for overall accesses 1855system.cpu1.dcache.overall_mshr_miss_rate::total 0.035214 # mshr miss rate for overall accesses 1856system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13169.548299 # average ReadReq mshr miss latency 1857system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13169.548299 # average ReadReq mshr miss latency 1858system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17826.488946 # average WriteReq mshr miss latency 1859system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17826.488946 # average WriteReq mshr miss latency 1860system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20757.458613 # average SoftPFReq mshr miss latency 1861system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20757.458613 # average SoftPFReq mshr miss latency 1862system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23067.616389 # average WriteLineReq mshr miss latency 1863system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23067.616389 # average WriteLineReq mshr miss latency 1864system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13726.086776 # average LoadLockedReq mshr miss latency 1865system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.086776 # average LoadLockedReq mshr miss latency 1866system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23770.476265 # average StoreCondReq mshr miss latency 1867system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23770.476265 # average StoreCondReq mshr miss latency 1868system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1869system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1870system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15469.784291 # average overall mshr miss latency 1871system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15469.784291 # average overall mshr miss latency 1872system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16104.487966 # average overall mshr miss latency 1873system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16104.487966 # average overall mshr miss latency 1874system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 # average ReadReq mshr uncacheable latency 1875system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency 1876system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency 1877system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency 1878system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1879system.cpu1.icache.tags.replacements 4797887 # number of replacements 1880system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use 1881system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. 1882system.cpu1.icache.tags.sampled_refs 4798399 # Sample count of references to valid blocks. 1883system.cpu1.icache.tags.avg_refs 86.714342 # Average number of references to valid blocks. 1884system.cpu1.icache.tags.warmup_cycle 8378704245000 # Cycle when the warmup percentage was hit. 1885system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.259979 # Average occupied blocks per requestor 1886system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969258 # Average percentage of cache occupancy 1887system.cpu1.icache.tags.occ_percent::total 0.969258 # Average percentage of cache occupancy 1888system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1889system.cpu1.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 1890system.cpu1.icache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id 1891system.cpu1.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id 1892system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 1893system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1894system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses 1895system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses 1896system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1897system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits 1898system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits 1899system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits 1900system.cpu1.icache.demand_hits::total 416090013 # number of demand (read+write) hits 1901system.cpu1.icache.overall_hits::cpu1.inst 416090013 # number of overall hits 1902system.cpu1.icache.overall_hits::total 416090013 # number of overall hits 1903system.cpu1.icache.ReadReq_misses::cpu1.inst 4798405 # number of ReadReq misses 1904system.cpu1.icache.ReadReq_misses::total 4798405 # number of ReadReq misses 1905system.cpu1.icache.demand_misses::cpu1.inst 4798405 # number of demand (read+write) misses 1906system.cpu1.icache.demand_misses::total 4798405 # number of demand (read+write) misses 1907system.cpu1.icache.overall_misses::cpu1.inst 4798405 # number of overall misses 1908system.cpu1.icache.overall_misses::total 4798405 # number of overall misses 1909system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50998473000 # number of ReadReq miss cycles 1910system.cpu1.icache.ReadReq_miss_latency::total 50998473000 # number of ReadReq miss cycles 1911system.cpu1.icache.demand_miss_latency::cpu1.inst 50998473000 # number of demand (read+write) miss cycles 1912system.cpu1.icache.demand_miss_latency::total 50998473000 # number of demand (read+write) miss cycles 1913system.cpu1.icache.overall_miss_latency::cpu1.inst 50998473000 # number of overall miss cycles 1914system.cpu1.icache.overall_miss_latency::total 50998473000 # number of overall miss cycles 1915system.cpu1.icache.ReadReq_accesses::cpu1.inst 420888418 # number of ReadReq accesses(hits+misses) 1916system.cpu1.icache.ReadReq_accesses::total 420888418 # number of ReadReq accesses(hits+misses) 1917system.cpu1.icache.demand_accesses::cpu1.inst 420888418 # number of demand (read+write) accesses 1918system.cpu1.icache.demand_accesses::total 420888418 # number of demand (read+write) accesses 1919system.cpu1.icache.overall_accesses::cpu1.inst 420888418 # number of overall (read+write) accesses 1920system.cpu1.icache.overall_accesses::total 420888418 # number of overall (read+write) accesses 1921system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011401 # miss rate for ReadReq accesses 1922system.cpu1.icache.ReadReq_miss_rate::total 0.011401 # miss rate for ReadReq accesses 1923system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011401 # miss rate for demand accesses 1924system.cpu1.icache.demand_miss_rate::total 0.011401 # miss rate for demand accesses 1925system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011401 # miss rate for overall accesses 1926system.cpu1.icache.overall_miss_rate::total 0.011401 # miss rate for overall accesses 1927system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10628.213542 # average ReadReq miss latency 1928system.cpu1.icache.ReadReq_avg_miss_latency::total 10628.213542 # average ReadReq miss latency 1929system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency 1930system.cpu1.icache.demand_avg_miss_latency::total 10628.213542 # average overall miss latency 1931system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10628.213542 # average overall miss latency 1932system.cpu1.icache.overall_avg_miss_latency::total 10628.213542 # average overall miss latency 1933system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1934system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1935system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1936system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1937system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1938system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1939system.cpu1.icache.writebacks::writebacks 4797887 # number of writebacks 1940system.cpu1.icache.writebacks::total 4797887 # number of writebacks 1941system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4798405 # number of ReadReq MSHR misses 1942system.cpu1.icache.ReadReq_mshr_misses::total 4798405 # number of ReadReq MSHR misses 1943system.cpu1.icache.demand_mshr_misses::cpu1.inst 4798405 # number of demand (read+write) MSHR misses 1944system.cpu1.icache.demand_mshr_misses::total 4798405 # number of demand (read+write) MSHR misses 1945system.cpu1.icache.overall_mshr_misses::cpu1.inst 4798405 # number of overall MSHR misses 1946system.cpu1.icache.overall_mshr_misses::total 4798405 # number of overall MSHR misses 1947system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1948system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1949system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1950system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1951system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48599271000 # number of ReadReq MSHR miss cycles 1952system.cpu1.icache.ReadReq_mshr_miss_latency::total 48599271000 # number of ReadReq MSHR miss cycles 1953system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48599271000 # number of demand (read+write) MSHR miss cycles 1954system.cpu1.icache.demand_mshr_miss_latency::total 48599271000 # number of demand (read+write) MSHR miss cycles 1955system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48599271000 # number of overall MSHR miss cycles 1956system.cpu1.icache.overall_mshr_miss_latency::total 48599271000 # number of overall MSHR miss cycles 1957system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226500 # number of ReadReq MSHR uncacheable cycles 1958system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226500 # number of ReadReq MSHR uncacheable cycles 1959system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226500 # number of overall MSHR uncacheable cycles 1960system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226500 # number of overall MSHR uncacheable cycles 1961system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for ReadReq accesses 1962system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011401 # mshr miss rate for ReadReq accesses 1963system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for demand accesses 1964system.cpu1.icache.demand_mshr_miss_rate::total 0.011401 # mshr miss rate for demand accesses 1965system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for overall accesses 1966system.cpu1.icache.overall_mshr_miss_rate::total 0.011401 # mshr miss rate for overall accesses 1967system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average ReadReq mshr miss latency 1968system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10128.213646 # average ReadReq mshr miss latency 1969system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1970system.cpu1.icache.demand_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1971system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10128.213646 # average overall mshr miss latency 1972system.cpu1.icache.overall_avg_mshr_miss_latency::total 10128.213646 # average overall mshr miss latency 1973system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average ReadReq mshr uncacheable latency 1974system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency 1975system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency 1976system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency 1977system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1978system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued 1979system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified 1980system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1981system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1982system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1983system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing 1984system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 1985system.cpu1.l2cache.tags.replacements 1970256 # number of replacements 1986system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use 1987system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. 1988system.cpu1.l2cache.tags.sampled_refs 1985806 # Sample count of references to valid blocks. 1989system.cpu1.l2cache.tags.avg_refs 7.166669 # Average number of references to valid blocks. 1990system.cpu1.l2cache.tags.warmup_cycle 10058718427000 # Cycle when the warmup percentage was hit. 1991system.cpu1.l2cache.tags.occ_blocks::writebacks 12287.437490 # Average occupied blocks per requestor 1992system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.190300 # Average occupied blocks per requestor 1993system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 64.411311 # Average occupied blocks per requestor 1994system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 905.409563 # Average occupied blocks per requestor 1995system.cpu1.l2cache.tags.occ_percent::writebacks 0.749966 # Average percentage of cache occupancy 1996system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002697 # Average percentage of cache occupancy 1997system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003931 # Average percentage of cache occupancy 1998system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055262 # Average percentage of cache occupancy 1999system.cpu1.l2cache.tags.occ_percent::total 0.811856 # Average percentage of cache occupancy 2000system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1582 # Occupied blocks per task id 2001system.cpu1.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 2002system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13889 # Occupied blocks per task id 2003system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id 2004system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id 2005system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id 2006system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id 2007system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 38 # Occupied blocks per task id 2008system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id 2009system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 2010system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 2011system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2519 # Occupied blocks per task id 2012system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5802 # Occupied blocks per task id 2013system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5375 # Occupied blocks per task id 2014system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.096558 # Percentage of cache occupancy per task id 2015system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 2016system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id 2017system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses 2018system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses 2019system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2020system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits 2021system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits 2022system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits 2023system.cpu1.l2cache.WritebackDirty_hits::writebacks 3174179 # number of WritebackDirty hits 2024system.cpu1.l2cache.WritebackDirty_hits::total 3174179 # number of WritebackDirty hits 2025system.cpu1.l2cache.WritebackClean_hits::writebacks 6641283 # number of WritebackClean hits 2026system.cpu1.l2cache.WritebackClean_hits::total 6641283 # number of WritebackClean hits 2027system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits 2028system.cpu1.l2cache.UpgradeReq_hits::total 549 # number of UpgradeReq hits 2029system.cpu1.l2cache.ReadExReq_hits::cpu1.data 848093 # number of ReadExReq hits 2030system.cpu1.l2cache.ReadExReq_hits::total 848093 # number of ReadExReq hits 2031system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4339488 # number of ReadCleanReq hits 2032system.cpu1.l2cache.ReadCleanReq_hits::total 4339488 # number of ReadCleanReq hits 2033system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2669176 # number of ReadSharedReq hits 2034system.cpu1.l2cache.ReadSharedReq_hits::total 2669176 # number of ReadSharedReq hits 2035system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 193952 # number of InvalidateReq hits 2036system.cpu1.l2cache.InvalidateReq_hits::total 193952 # number of InvalidateReq hits 2037system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 241732 # number of demand (read+write) hits 2038system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150683 # number of demand (read+write) hits 2039system.cpu1.l2cache.demand_hits::cpu1.inst 4339488 # number of demand (read+write) hits 2040system.cpu1.l2cache.demand_hits::cpu1.data 3517269 # number of demand (read+write) hits 2041system.cpu1.l2cache.demand_hits::total 8249172 # number of demand (read+write) hits 2042system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 241732 # number of overall hits 2043system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150683 # number of overall hits 2044system.cpu1.l2cache.overall_hits::cpu1.inst 4339488 # number of overall hits 2045system.cpu1.l2cache.overall_hits::cpu1.data 3517269 # number of overall hits 2046system.cpu1.l2cache.overall_hits::total 8249172 # number of overall hits 2047system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10752 # number of ReadReq misses 2048system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9335 # number of ReadReq misses 2049system.cpu1.l2cache.ReadReq_misses::total 20087 # number of ReadReq misses 2050system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 209731 # number of UpgradeReq misses 2051system.cpu1.l2cache.UpgradeReq_misses::total 209731 # number of UpgradeReq misses 2052system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 204666 # number of SCUpgradeReq misses 2053system.cpu1.l2cache.SCUpgradeReq_misses::total 204666 # number of SCUpgradeReq misses 2054system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # number of SCUpgradeFailReq misses 2055system.cpu1.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 2056system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253892 # number of ReadExReq misses 2057system.cpu1.l2cache.ReadExReq_misses::total 253892 # number of ReadExReq misses 2058system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458917 # number of ReadCleanReq misses 2059system.cpu1.l2cache.ReadCleanReq_misses::total 458917 # number of ReadCleanReq misses 2060system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 897743 # number of ReadSharedReq misses 2061system.cpu1.l2cache.ReadSharedReq_misses::total 897743 # number of ReadSharedReq misses 2062system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252003 # number of InvalidateReq misses 2063system.cpu1.l2cache.InvalidateReq_misses::total 252003 # number of InvalidateReq misses 2064system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10752 # number of demand (read+write) misses 2065system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9335 # number of demand (read+write) misses 2066system.cpu1.l2cache.demand_misses::cpu1.inst 458917 # number of demand (read+write) misses 2067system.cpu1.l2cache.demand_misses::cpu1.data 1151635 # number of demand (read+write) misses 2068system.cpu1.l2cache.demand_misses::total 1630639 # number of demand (read+write) misses 2069system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10752 # number of overall misses 2070system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9335 # number of overall misses 2071system.cpu1.l2cache.overall_misses::cpu1.inst 458917 # number of overall misses 2072system.cpu1.l2cache.overall_misses::cpu1.data 1151635 # number of overall misses 2073system.cpu1.l2cache.overall_misses::total 1630639 # number of overall misses 2074system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 421263500 # number of ReadReq miss cycles 2075system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 385353500 # number of ReadReq miss cycles 2076system.cpu1.l2cache.ReadReq_miss_latency::total 806617000 # number of ReadReq miss cycles 2077system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1909199500 # number of UpgradeReq miss cycles 2078system.cpu1.l2cache.UpgradeReq_miss_latency::total 1909199500 # number of UpgradeReq miss cycles 2079system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1509536500 # number of SCUpgradeReq miss cycles 2080system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1509536500 # number of SCUpgradeReq miss cycles 2081system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2962499 # number of SCUpgradeFailReq miss cycles 2082system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2962499 # number of SCUpgradeFailReq miss cycles 2083system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10235182000 # number of ReadExReq miss cycles 2084system.cpu1.l2cache.ReadExReq_miss_latency::total 10235182000 # number of ReadExReq miss cycles 2085system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15333921500 # number of ReadCleanReq miss cycles 2086system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15333921500 # number of ReadCleanReq miss cycles 2087system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29041295500 # number of ReadSharedReq miss cycles 2088system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29041295500 # number of ReadSharedReq miss cycles 2089system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 413814500 # number of InvalidateReq miss cycles 2090system.cpu1.l2cache.InvalidateReq_miss_latency::total 413814500 # number of InvalidateReq miss cycles 2091system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 421263500 # number of demand (read+write) miss cycles 2092system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 385353500 # number of demand (read+write) miss cycles 2093system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15333921500 # number of demand (read+write) miss cycles 2094system.cpu1.l2cache.demand_miss_latency::cpu1.data 39276477500 # number of demand (read+write) miss cycles 2095system.cpu1.l2cache.demand_miss_latency::total 55417016000 # number of demand (read+write) miss cycles 2096system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 421263500 # number of overall miss cycles 2097system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 385353500 # number of overall miss cycles 2098system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15333921500 # number of overall miss cycles 2099system.cpu1.l2cache.overall_miss_latency::cpu1.data 39276477500 # number of overall miss cycles 2100system.cpu1.l2cache.overall_miss_latency::total 55417016000 # number of overall miss cycles 2101system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 252484 # number of ReadReq accesses(hits+misses) 2102system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 160018 # number of ReadReq accesses(hits+misses) 2103system.cpu1.l2cache.ReadReq_accesses::total 412502 # number of ReadReq accesses(hits+misses) 2104system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3174179 # number of WritebackDirty accesses(hits+misses) 2105system.cpu1.l2cache.WritebackDirty_accesses::total 3174179 # number of WritebackDirty accesses(hits+misses) 2106system.cpu1.l2cache.WritebackClean_accesses::writebacks 6641283 # number of WritebackClean accesses(hits+misses) 2107system.cpu1.l2cache.WritebackClean_accesses::total 6641283 # number of WritebackClean accesses(hits+misses) 2108system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 210280 # number of UpgradeReq accesses(hits+misses) 2109system.cpu1.l2cache.UpgradeReq_accesses::total 210280 # number of UpgradeReq accesses(hits+misses) 2110system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 204666 # number of SCUpgradeReq accesses(hits+misses) 2111system.cpu1.l2cache.SCUpgradeReq_accesses::total 204666 # number of SCUpgradeReq accesses(hits+misses) 2112system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 2113system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 2114system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1101985 # number of ReadExReq accesses(hits+misses) 2115system.cpu1.l2cache.ReadExReq_accesses::total 1101985 # number of ReadExReq accesses(hits+misses) 2116system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4798405 # number of ReadCleanReq accesses(hits+misses) 2117system.cpu1.l2cache.ReadCleanReq_accesses::total 4798405 # number of ReadCleanReq accesses(hits+misses) 2118system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3566919 # number of ReadSharedReq accesses(hits+misses) 2119system.cpu1.l2cache.ReadSharedReq_accesses::total 3566919 # number of ReadSharedReq accesses(hits+misses) 2120system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 445955 # number of InvalidateReq accesses(hits+misses) 2121system.cpu1.l2cache.InvalidateReq_accesses::total 445955 # number of InvalidateReq accesses(hits+misses) 2122system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 252484 # number of demand (read+write) accesses 2123system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 160018 # number of demand (read+write) accesses 2124system.cpu1.l2cache.demand_accesses::cpu1.inst 4798405 # number of demand (read+write) accesses 2125system.cpu1.l2cache.demand_accesses::cpu1.data 4668904 # number of demand (read+write) accesses 2126system.cpu1.l2cache.demand_accesses::total 9879811 # number of demand (read+write) accesses 2127system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 252484 # number of overall (read+write) accesses 2128system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 160018 # number of overall (read+write) accesses 2129system.cpu1.l2cache.overall_accesses::cpu1.inst 4798405 # number of overall (read+write) accesses 2130system.cpu1.l2cache.overall_accesses::cpu1.data 4668904 # number of overall (read+write) accesses 2131system.cpu1.l2cache.overall_accesses::total 9879811 # number of overall (read+write) accesses 2132system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for ReadReq accesses 2133system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses 2134system.cpu1.l2cache.ReadReq_miss_rate::total 0.048696 # miss rate for ReadReq accesses 2135system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997389 # miss rate for UpgradeReq accesses 2136system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997389 # miss rate for UpgradeReq accesses 2137system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2138system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2139system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2140system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2141system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230395 # miss rate for ReadExReq accesses 2142system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230395 # miss rate for ReadExReq accesses 2143system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095639 # miss rate for ReadCleanReq accesses 2144system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095639 # miss rate for ReadCleanReq accesses 2145system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.251686 # miss rate for ReadSharedReq accesses 2146system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.251686 # miss rate for ReadSharedReq accesses 2147system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565086 # miss rate for InvalidateReq accesses 2148system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565086 # miss rate for InvalidateReq accesses 2149system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for demand accesses 2150system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses 2151system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095639 # miss rate for demand accesses 2152system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246661 # miss rate for demand accesses 2153system.cpu1.l2cache.demand_miss_rate::total 0.165048 # miss rate for demand accesses 2154system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.042585 # miss rate for overall accesses 2155system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses 2156system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095639 # miss rate for overall accesses 2157system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246661 # miss rate for overall accesses 2158system.cpu1.l2cache.overall_miss_rate::total 0.165048 # miss rate for overall accesses 2159system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average ReadReq miss latency 2160system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41280.503482 # average ReadReq miss latency 2161system.cpu1.l2cache.ReadReq_avg_miss_latency::total 40156.170658 # average ReadReq miss latency 2162system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9103.086811 # average UpgradeReq miss latency 2163system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9103.086811 # average UpgradeReq miss latency 2164system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7375.609530 # average SCUpgradeReq miss latency 2165system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7375.609530 # average SCUpgradeReq miss latency 2166system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 296249.900000 # average SCUpgradeFailReq miss latency 2167system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 296249.900000 # average SCUpgradeFailReq miss latency 2168system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40313.133143 # average ReadExReq miss latency 2169system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40313.133143 # average ReadExReq miss latency 2170system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33413.278436 # average ReadCleanReq miss latency 2171system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33413.278436 # average ReadCleanReq miss latency 2172system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32349.230793 # average ReadSharedReq miss latency 2173system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32349.230793 # average ReadSharedReq miss latency 2174system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1642.101483 # average InvalidateReq miss latency 2175system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1642.101483 # average InvalidateReq miss latency 2176system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average overall miss latency 2177system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41280.503482 # average overall miss latency 2178system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33413.278436 # average overall miss latency 2179system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34104.970325 # average overall miss latency 2180system.cpu1.l2cache.demand_avg_miss_latency::total 33984.846431 # average overall miss latency 2181system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39180.013021 # average overall miss latency 2182system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41280.503482 # average overall miss latency 2183system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33413.278436 # average overall miss latency 2184system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34104.970325 # average overall miss latency 2185system.cpu1.l2cache.overall_avg_miss_latency::total 33984.846431 # average overall miss latency 2186system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2187system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2188system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2189system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2190system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2191system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2192system.cpu1.l2cache.unused_prefetches 39843 # number of HardPF blocks evicted w/o reference 2193system.cpu1.l2cache.writebacks::writebacks 1100180 # number of writebacks 2194system.cpu1.l2cache.writebacks::total 1100180 # number of writebacks 2195system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4729 # number of ReadExReq MSHR hits 2196system.cpu1.l2cache.ReadExReq_mshr_hits::total 4729 # number of ReadExReq MSHR hits 2197system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 266 # number of ReadSharedReq MSHR hits 2198system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 266 # number of ReadSharedReq MSHR hits 2199system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits 2200system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits 2201system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4995 # number of demand (read+write) MSHR hits 2202system.cpu1.l2cache.demand_mshr_hits::total 4995 # number of demand (read+write) MSHR hits 2203system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4995 # number of overall MSHR hits 2204system.cpu1.l2cache.overall_mshr_hits::total 4995 # number of overall MSHR hits 2205system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10752 # number of ReadReq MSHR misses 2206system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9335 # number of ReadReq MSHR misses 2207system.cpu1.l2cache.ReadReq_mshr_misses::total 20087 # number of ReadReq MSHR misses 2208system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 687556 # number of HardPFReq MSHR misses 2209system.cpu1.l2cache.HardPFReq_mshr_misses::total 687556 # number of HardPFReq MSHR misses 2210system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 209731 # number of UpgradeReq MSHR misses 2211system.cpu1.l2cache.UpgradeReq_mshr_misses::total 209731 # number of UpgradeReq MSHR misses 2212system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 204666 # number of SCUpgradeReq MSHR misses 2213system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 204666 # number of SCUpgradeReq MSHR misses 2214system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 10 # number of SCUpgradeFailReq MSHR misses 2215system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 2216system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249163 # number of ReadExReq MSHR misses 2217system.cpu1.l2cache.ReadExReq_mshr_misses::total 249163 # number of ReadExReq MSHR misses 2218system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 458917 # number of ReadCleanReq MSHR misses 2219system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 458917 # number of ReadCleanReq MSHR misses 2220system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 897477 # number of ReadSharedReq MSHR misses 2221system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 897477 # number of ReadSharedReq MSHR misses 2222system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252001 # number of InvalidateReq MSHR misses 2223system.cpu1.l2cache.InvalidateReq_mshr_misses::total 252001 # number of InvalidateReq MSHR misses 2224system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10752 # number of demand (read+write) MSHR misses 2225system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9335 # number of demand (read+write) MSHR misses 2226system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 458917 # number of demand (read+write) MSHR misses 2227system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1146640 # number of demand (read+write) MSHR misses 2228system.cpu1.l2cache.demand_mshr_misses::total 1625644 # number of demand (read+write) MSHR misses 2229system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10752 # number of overall MSHR misses 2230system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9335 # number of overall MSHR misses 2231system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 458917 # number of overall MSHR misses 2232system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1146640 # number of overall MSHR misses 2233system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 687556 # number of overall MSHR misses 2234system.cpu1.l2cache.overall_mshr_misses::total 2313200 # number of overall MSHR misses 2235system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2236system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11035 # number of ReadReq MSHR uncacheable 2237system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11145 # number of ReadReq MSHR uncacheable 2238system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable 2239system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11949 # number of WriteReq MSHR uncacheable 2240system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2241system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22984 # number of overall MSHR uncacheable misses 2242system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23094 # number of overall MSHR uncacheable misses 2243system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of ReadReq MSHR miss cycles 2244system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 329343500 # number of ReadReq MSHR miss cycles 2245system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 686095000 # number of ReadReq MSHR miss cycles 2246system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of HardPFReq MSHR miss cycles 2247system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27876431726 # number of HardPFReq MSHR miss cycles 2248system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4396610500 # number of UpgradeReq MSHR miss cycles 2249system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4396610500 # number of UpgradeReq MSHR miss cycles 2250system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3329007000 # number of SCUpgradeReq MSHR miss cycles 2251system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3329007000 # number of SCUpgradeReq MSHR miss cycles 2252system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2614499 # number of SCUpgradeFailReq MSHR miss cycles 2253system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2614499 # number of SCUpgradeFailReq MSHR miss cycles 2254system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8260901500 # number of ReadExReq MSHR miss cycles 2255system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8260901500 # number of ReadExReq MSHR miss cycles 2256system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12580419500 # number of ReadCleanReq MSHR miss cycles 2257system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12580419500 # number of ReadCleanReq MSHR miss cycles 2258system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23624853500 # number of ReadSharedReq MSHR miss cycles 2259system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23624853500 # number of ReadSharedReq MSHR miss cycles 2260system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6839135500 # number of InvalidateReq MSHR miss cycles 2261system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6839135500 # number of InvalidateReq MSHR miss cycles 2262system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of demand (read+write) MSHR miss cycles 2263system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329343500 # number of demand (read+write) MSHR miss cycles 2264system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12580419500 # number of demand (read+write) MSHR miss cycles 2265system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31885755000 # number of demand (read+write) MSHR miss cycles 2266system.cpu1.l2cache.demand_mshr_miss_latency::total 45152269500 # number of demand (read+write) MSHR miss cycles 2267system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 356751500 # number of overall MSHR miss cycles 2268system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329343500 # number of overall MSHR miss cycles 2269system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12580419500 # number of overall MSHR miss cycles 2270system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31885755000 # number of overall MSHR miss cycles 2271system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27876431726 # number of overall MSHR miss cycles 2272system.cpu1.l2cache.overall_mshr_miss_latency::total 73028701226 # number of overall MSHR miss cycles 2273system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401500 # number of ReadReq MSHR uncacheable cycles 2274system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1805437500 # number of ReadReq MSHR uncacheable cycles 2275system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1814839000 # number of ReadReq MSHR uncacheable cycles 2276system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401500 # number of overall MSHR uncacheable cycles 2277system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1805437500 # number of overall MSHR uncacheable cycles 2278system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1814839000 # number of overall MSHR uncacheable cycles 2279system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for ReadReq accesses 2280system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for ReadReq accesses 2281system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048696 # mshr miss rate for ReadReq accesses 2282system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2283system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2284system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997389 # mshr miss rate for UpgradeReq accesses 2285system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997389 # mshr miss rate for UpgradeReq accesses 2286system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2287system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2288system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2289system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2290system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226104 # mshr miss rate for ReadExReq accesses 2291system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226104 # mshr miss rate for ReadExReq accesses 2292system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for ReadCleanReq accesses 2293system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095639 # mshr miss rate for ReadCleanReq accesses 2294system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251611 # mshr miss rate for ReadSharedReq accesses 2295system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251611 # mshr miss rate for ReadSharedReq accesses 2296system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565082 # mshr miss rate for InvalidateReq accesses 2297system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565082 # mshr miss rate for InvalidateReq accesses 2298system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for demand accesses 2299system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for demand accesses 2300system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for demand accesses 2301system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for demand accesses 2302system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164542 # mshr miss rate for demand accesses 2303system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042585 # mshr miss rate for overall accesses 2304system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058337 # mshr miss rate for overall accesses 2305system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095639 # mshr miss rate for overall accesses 2306system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245591 # mshr miss rate for overall accesses 2307system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2308system.cpu1.l2cache.overall_mshr_miss_rate::total 0.234134 # mshr miss rate for overall accesses 2309system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average ReadReq mshr miss latency 2310system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average ReadReq mshr miss latency 2311system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 34156.170658 # average ReadReq mshr miss latency 2312system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average HardPFReq mshr miss latency 2313system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40544.234544 # average HardPFReq mshr miss latency 2314system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20963.093200 # average UpgradeReq mshr miss latency 2315system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20963.093200 # average UpgradeReq mshr miss latency 2316system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16265.559497 # average SCUpgradeReq mshr miss latency 2317system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16265.559497 # average SCUpgradeReq mshr miss latency 2318system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261449.900000 # average SCUpgradeFailReq mshr miss latency 2319system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261449.900000 # average SCUpgradeFailReq mshr miss latency 2320system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33154.607626 # average ReadExReq mshr miss latency 2321system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33154.607626 # average ReadExReq mshr miss latency 2322system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average ReadCleanReq mshr miss latency 2323system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27413.278436 # average ReadCleanReq mshr miss latency 2324system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26323.631135 # average ReadSharedReq mshr miss latency 2325system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26323.631135 # average ReadSharedReq mshr miss latency 2326system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27139.318892 # average InvalidateReq mshr miss latency 2327system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27139.318892 # average InvalidateReq mshr miss latency 2328system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency 2329system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency 2330system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency 2331system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency 2332system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27775.004552 # average overall mshr miss latency 2333system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33180.013021 # average overall mshr miss latency 2334system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35280.503482 # average overall mshr miss latency 2335system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27413.278436 # average overall mshr miss latency 2336system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27807.991174 # average overall mshr miss latency 2337system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40544.234544 # average overall mshr miss latency 2338system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31570.422456 # average overall mshr miss latency 2339system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average ReadReq mshr uncacheable latency 2340system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163610.104214 # average ReadReq mshr uncacheable latency 2341system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162838.851503 # average ReadReq mshr uncacheable latency 2342system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85468.181818 # average overall mshr uncacheable latency 2343system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78551.927428 # average overall mshr uncacheable latency 2344system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78584.870529 # average overall mshr uncacheable latency 2345system.cpu1.toL2Bus.snoop_filter.tot_requests 20384822 # Total number of requests made to the snoop filter. 2346system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10471744 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2347system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2348system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. 2349system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2350system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2351system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2352system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution 2353system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution 2354system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution 2355system.cpu1.toL2Bus.trans_dist::WriteResp 11949 # Transaction distribution 2356system.cpu1.toL2Bus.trans_dist::WritebackDirty 4279928 # Transaction distribution 2357system.cpu1.toL2Bus.trans_dist::WritebackClean 6642170 # Transaction distribution 2358system.cpu1.toL2Bus.trans_dist::CleanEvict 2284917 # Transaction distribution 2359system.cpu1.toL2Bus.trans_dist::HardPFReq 836860 # Transaction distribution 2360system.cpu1.toL2Bus.trans_dist::UpgradeReq 390891 # Transaction distribution 2361system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 375101 # Transaction distribution 2362system.cpu1.toL2Bus.trans_dist::UpgradeResp 483493 # Transaction distribution 2363system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution 2364system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 2365system.cpu1.toL2Bus.trans_dist::ReadExReq 1131381 # Transaction distribution 2366system.cpu1.toL2Bus.trans_dist::ReadExResp 1109621 # Transaction distribution 2367system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4798405 # Transaction distribution 2368system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4426002 # Transaction distribution 2369system.cpu1.toL2Bus.trans_dist::InvalidateReq 496716 # Transaction distribution 2370system.cpu1.toL2Bus.trans_dist::InvalidateResp 445955 # Transaction distribution 2371system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14394916 # Packet count per connected master and slave (bytes) 2372system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16294669 # Packet count per connected master and slave (bytes) 2373system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 336160 # Packet count per connected master and slave (bytes) 2374system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 556294 # Packet count per connected master and slave (bytes) 2375system.cpu1.toL2Bus.pkt_count::total 31582039 # Packet count per connected master and slave (bytes) 2376system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614163064 # Cumulative packet size per connected master and slave (bytes) 2377system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 626579614 # Cumulative packet size per connected master and slave (bytes) 2378system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1280144 # Cumulative packet size per connected master and slave (bytes) 2379system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2019872 # Cumulative packet size per connected master and slave (bytes) 2380system.cpu1.toL2Bus.pkt_size::total 1244042694 # Cumulative packet size per connected master and slave (bytes) 2381system.cpu1.toL2Bus.snoops 5755928 # Total snoops (count) 2382system.cpu1.toL2Bus.snoop_fanout::samples 16349135 # Request fanout histogram 2383system.cpu1.toL2Bus.snoop_fanout::mean 0.122449 # Request fanout histogram 2384system.cpu1.toL2Bus.snoop_fanout::stdev 0.327837 # Request fanout histogram 2385system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2386system.cpu1.toL2Bus.snoop_fanout::0 14347367 87.76% 87.76% # Request fanout histogram 2387system.cpu1.toL2Bus.snoop_fanout::1 2001594 12.24% 100.00% # Request fanout histogram 2388system.cpu1.toL2Bus.snoop_fanout::2 174 0.00% 100.00% # Request fanout histogram 2389system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2390system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2391system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2392system.cpu1.toL2Bus.snoop_fanout::total 16349135 # Request fanout histogram 2393system.cpu1.toL2Bus.reqLayer0.occupancy 20146131499 # Layer occupancy (ticks) 2394system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2395system.cpu1.toL2Bus.snoopLayer0.occupancy 187574309 # Layer occupancy (ticks) 2396system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2397system.cpu1.toL2Bus.respLayer0.occupancy 7197716000 # Layer occupancy (ticks) 2398system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2399system.cpu1.toL2Bus.respLayer1.occupancy 7451139989 # Layer occupancy (ticks) 2400system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2401system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # Layer occupancy (ticks) 2402system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2403system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) 2404system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2405system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2406system.iobus.trans_dist::ReadReq 40346 # Transaction distribution 2407system.iobus.trans_dist::ReadResp 40346 # Transaction distribution 2408system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 2409system.iobus.trans_dist::WriteResp 136634 # Transaction distribution 2410system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47740 # Packet count per connected master and slave (bytes) 2411system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2412system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2413system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2414system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2415system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2416system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2417system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2418system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2419system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2420system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2421system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2422system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2423system.iobus.pkt_count_system.bridge.master::total 122674 # Packet count per connected master and slave (bytes) 2424system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) 2425system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) 2426system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2427system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2428system.iobus.pkt_count::total 353960 # Packet count per connected master and slave (bytes) 2429system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47760 # Cumulative packet size per connected master and slave (bytes) 2430system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2431system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2432system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2433system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2434system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2435system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2436system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2437system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2438system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2439system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2440system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2441system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2442system.iobus.pkt_size_system.bridge.master::total 155781 # Cumulative packet size per connected master and slave (bytes) 2443system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) 2444system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) 2445system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2446system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2447system.iobus.pkt_size::total 7496707 # Cumulative packet size per connected master and slave (bytes) 2448system.iobus.reqLayer0.occupancy 36949503 # Layer occupancy (ticks) 2449system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2450system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 2451system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2452system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 2453system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2454system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2455system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2456system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 2457system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2458system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2459system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2460system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2461system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2462system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 2463system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2464system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2465system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2466system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 2467system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2468system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) 2469system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2470system.iobus.reqLayer23.occupancy 26494000 # Layer occupancy (ticks) 2471system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2472system.iobus.reqLayer24.occupancy 37417500 # Layer occupancy (ticks) 2473system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2474system.iobus.reqLayer25.occupancy 569020926 # Layer occupancy (ticks) 2475system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2476system.iobus.respLayer0.occupancy 92771000 # Layer occupancy (ticks) 2477system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2478system.iobus.respLayer3.occupancy 147902000 # Layer occupancy (ticks) 2479system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2480system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2481system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2482system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2483system.iocache.tags.replacements 115585 # number of replacements 2484system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use 2485system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2486system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 2487system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2488system.iocache.tags.warmup_cycle 9095565849000 # Cycle when the warmup percentage was hit. 2489system.iocache.tags.occ_blocks::realview.ethernet 3.827817 # Average occupied blocks per requestor 2490system.iocache.tags.occ_blocks::realview.ide 7.416000 # Average occupied blocks per requestor 2491system.iocache.tags.occ_percent::realview.ethernet 0.239239 # Average percentage of cache occupancy 2492system.iocache.tags.occ_percent::realview.ide 0.463500 # Average percentage of cache occupancy 2493system.iocache.tags.occ_percent::total 0.702739 # Average percentage of cache occupancy 2494system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2495system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2496system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2497system.iocache.tags.tag_accesses 1040784 # Number of tag accesses 2498system.iocache.tags.data_accesses 1040784 # Number of data accesses 2499system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2500system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2501system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses 2502system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses 2503system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2504system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2505system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2506system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2507system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2508system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses 2509system.iocache.demand_misses::total 115643 # number of demand (read+write) misses 2510system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2511system.iocache.overall_misses::realview.ide 115603 # number of overall misses 2512system.iocache.overall_misses::total 115643 # number of overall misses 2513system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2514system.iocache.ReadReq_miss_latency::realview.ide 1623231612 # number of ReadReq miss cycles 2515system.iocache.ReadReq_miss_latency::total 1628431112 # number of ReadReq miss cycles 2516system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2517system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2518system.iocache.WriteLineReq_miss_latency::realview.ide 12905416814 # number of WriteLineReq miss cycles 2519system.iocache.WriteLineReq_miss_latency::total 12905416814 # number of WriteLineReq miss cycles 2520system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 2521system.iocache.demand_miss_latency::realview.ide 14528648426 # number of demand (read+write) miss cycles 2522system.iocache.demand_miss_latency::total 14534216926 # number of demand (read+write) miss cycles 2523system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 2524system.iocache.overall_miss_latency::realview.ide 14528648426 # number of overall miss cycles 2525system.iocache.overall_miss_latency::total 14534216926 # number of overall miss cycles 2526system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2527system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) 2528system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) 2529system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2530system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2531system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2532system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2533system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2534system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses 2535system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses 2536system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2537system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses 2538system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses 2539system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2540system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2541system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2542system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2543system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2544system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2545system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2546system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2547system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2548system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2549system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2550system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2551system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2552system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2553system.iocache.ReadReq_avg_miss_latency::realview.ide 182899.336563 # average ReadReq miss latency 2554system.iocache.ReadReq_avg_miss_latency::total 182723.419210 # average ReadReq miss latency 2555system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2556system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2557system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120918.754348 # average WriteLineReq miss latency 2558system.iocache.WriteLineReq_avg_miss_latency::total 120918.754348 # average WriteLineReq miss latency 2559system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2560system.iocache.demand_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency 2561system.iocache.demand_avg_miss_latency::total 125681.769982 # average overall miss latency 2562system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2563system.iocache.overall_avg_miss_latency::realview.ide 125677.088190 # average overall miss latency 2564system.iocache.overall_avg_miss_latency::total 125681.769982 # average overall miss latency 2565system.iocache.blocked_cycles::no_mshrs 31595 # number of cycles access was blocked 2566system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2567system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked 2568system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2569system.iocache.avg_blocked_cycles::no_mshrs 9.192610 # average number of cycles each access was blocked 2570system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2571system.iocache.writebacks::writebacks 106695 # number of writebacks 2572system.iocache.writebacks::total 106695 # number of writebacks 2573system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2574system.iocache.ReadReq_mshr_misses::realview.ide 8875 # number of ReadReq MSHR misses 2575system.iocache.ReadReq_mshr_misses::total 8912 # number of ReadReq MSHR misses 2576system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2577system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2578system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2579system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2580system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2581system.iocache.demand_mshr_misses::realview.ide 115603 # number of demand (read+write) MSHR misses 2582system.iocache.demand_mshr_misses::total 115643 # number of demand (read+write) MSHR misses 2583system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2584system.iocache.overall_mshr_misses::realview.ide 115603 # number of overall MSHR misses 2585system.iocache.overall_mshr_misses::total 115643 # number of overall MSHR misses 2586system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2587system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179481612 # number of ReadReq MSHR miss cycles 2588system.iocache.ReadReq_mshr_miss_latency::total 1182831112 # number of ReadReq MSHR miss cycles 2589system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2590system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2591system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7559977711 # number of WriteLineReq MSHR miss cycles 2592system.iocache.WriteLineReq_mshr_miss_latency::total 7559977711 # number of WriteLineReq MSHR miss cycles 2593system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 2594system.iocache.demand_mshr_miss_latency::realview.ide 8739459323 # number of demand (read+write) MSHR miss cycles 2595system.iocache.demand_mshr_miss_latency::total 8743027823 # number of demand (read+write) MSHR miss cycles 2596system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 2597system.iocache.overall_mshr_miss_latency::realview.ide 8739459323 # number of overall MSHR miss cycles 2598system.iocache.overall_mshr_miss_latency::total 8743027823 # number of overall MSHR miss cycles 2599system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2600system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2601system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2602system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2603system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2604system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2605system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2606system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2607system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2608system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2609system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2610system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2611system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2612system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2613system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132899.336563 # average ReadReq mshr miss latency 2614system.iocache.ReadReq_avg_mshr_miss_latency::total 132723.419210 # average ReadReq mshr miss latency 2615system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2616system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2617system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70834.061455 # average WriteLineReq mshr miss latency 2618system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70834.061455 # average WriteLineReq mshr miss latency 2619system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2620system.iocache.demand_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2621system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency 2622system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2623system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency 2624system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency 2625system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2626system.l2c.tags.replacements 1336257 # number of replacements 2627system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use 2628system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. 2629system.l2c.tags.sampled_refs 1394864 # Sample count of references to valid blocks. 2630system.l2c.tags.avg_refs 3.864457 # Average number of references to valid blocks. 2631system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. 2632system.l2c.tags.occ_blocks::writebacks 23096.089917 # Average occupied blocks per requestor 2633system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.068224 # Average occupied blocks per requestor 2634system.l2c.tags.occ_blocks::cpu0.itb.walker 220.083460 # Average occupied blocks per requestor 2635system.l2c.tags.occ_blocks::cpu0.inst 4065.866850 # Average occupied blocks per requestor 2636system.l2c.tags.occ_blocks::cpu0.data 8220.853874 # Average occupied blocks per requestor 2637system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.282047 # Average occupied blocks per requestor 2638system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.986041 # Average occupied blocks per requestor 2639system.l2c.tags.occ_blocks::cpu1.itb.walker 269.420690 # Average occupied blocks per requestor 2640system.l2c.tags.occ_blocks::cpu1.inst 2932.882407 # Average occupied blocks per requestor 2641system.l2c.tags.occ_blocks::cpu1.data 5116.369986 # Average occupied blocks per requestor 2642system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10693.582513 # Average occupied blocks per requestor 2643system.l2c.tags.occ_percent::writebacks 0.352418 # Average percentage of cache occupancy 2644system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002061 # Average percentage of cache occupancy 2645system.l2c.tags.occ_percent::cpu0.itb.walker 0.003358 # Average percentage of cache occupancy 2646system.l2c.tags.occ_percent::cpu0.inst 0.062040 # Average percentage of cache occupancy 2647system.l2c.tags.occ_percent::cpu0.data 0.125440 # Average percentage of cache occupancy 2648system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127034 # Average percentage of cache occupancy 2649system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002502 # Average percentage of cache occupancy 2650system.l2c.tags.occ_percent::cpu1.itb.walker 0.004111 # Average percentage of cache occupancy 2651system.l2c.tags.occ_percent::cpu1.inst 0.044752 # Average percentage of cache occupancy 2652system.l2c.tags.occ_percent::cpu1.data 0.078070 # Average percentage of cache occupancy 2653system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.163171 # Average percentage of cache occupancy 2654system.l2c.tags.occ_percent::total 0.964958 # Average percentage of cache occupancy 2655system.l2c.tags.occ_task_id_blocks::1022 10513 # Occupied blocks per task id 2656system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id 2657system.l2c.tags.occ_task_id_blocks::1024 47867 # Occupied blocks per task id 2658system.l2c.tags.age_task_id_blocks_1022::2 208 # Occupied blocks per task id 2659system.l2c.tags.age_task_id_blocks_1022::3 519 # Occupied blocks per task id 2660system.l2c.tags.age_task_id_blocks_1022::4 9786 # Occupied blocks per task id 2661system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id 2662system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 2663system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 2664system.l2c.tags.age_task_id_blocks_1024::2 1623 # Occupied blocks per task id 2665system.l2c.tags.age_task_id_blocks_1024::3 5220 # Occupied blocks per task id 2666system.l2c.tags.age_task_id_blocks_1024::4 40883 # Occupied blocks per task id 2667system.l2c.tags.occ_task_id_percent::1022 0.160416 # Percentage of cache occupancy per task id 2668system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id 2669system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id 2670system.l2c.tags.tag_accesses 69855982 # Number of tag accesses 2671system.l2c.tags.data_accesses 69855982 # Number of data accesses 2672system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 2673system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits 2674system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits 2675system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits 2676system.l2c.UpgradeReq_hits::cpu1.data 130434 # number of UpgradeReq hits 2677system.l2c.UpgradeReq_hits::total 288383 # number of UpgradeReq hits 2678system.l2c.SCUpgradeReq_hits::cpu0.data 36828 # number of SCUpgradeReq hits 2679system.l2c.SCUpgradeReq_hits::cpu1.data 37034 # number of SCUpgradeReq hits 2680system.l2c.SCUpgradeReq_hits::total 73862 # number of SCUpgradeReq hits 2681system.l2c.ReadExReq_hits::cpu0.data 45889 # number of ReadExReq hits 2682system.l2c.ReadExReq_hits::cpu1.data 57251 # number of ReadExReq hits 2683system.l2c.ReadExReq_hits::total 103140 # number of ReadExReq hits 2684system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4670 # number of ReadSharedReq hits 2685system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3337 # number of ReadSharedReq hits 2686system.l2c.ReadSharedReq_hits::cpu0.inst 411404 # number of ReadSharedReq hits 2687system.l2c.ReadSharedReq_hits::cpu0.data 536957 # number of ReadSharedReq hits 2688system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 268808 # number of ReadSharedReq hits 2689system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6004 # number of ReadSharedReq hits 2690system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5313 # number of ReadSharedReq hits 2691system.l2c.ReadSharedReq_hits::cpu1.inst 419752 # number of ReadSharedReq hits 2692system.l2c.ReadSharedReq_hits::cpu1.data 541221 # number of ReadSharedReq hits 2693system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283166 # number of ReadSharedReq hits 2694system.l2c.ReadSharedReq_hits::total 2480632 # number of ReadSharedReq hits 2695system.l2c.InvalidateReq_hits::cpu0.data 118921 # number of InvalidateReq hits 2696system.l2c.InvalidateReq_hits::cpu1.data 122409 # number of InvalidateReq hits 2697system.l2c.InvalidateReq_hits::total 241330 # number of InvalidateReq hits 2698system.l2c.demand_hits::cpu0.dtb.walker 4670 # number of demand (read+write) hits 2699system.l2c.demand_hits::cpu0.itb.walker 3337 # number of demand (read+write) hits 2700system.l2c.demand_hits::cpu0.inst 411404 # number of demand (read+write) hits 2701system.l2c.demand_hits::cpu0.data 582846 # number of demand (read+write) hits 2702system.l2c.demand_hits::cpu0.l2cache.prefetcher 268808 # number of demand (read+write) hits 2703system.l2c.demand_hits::cpu1.dtb.walker 6004 # number of demand (read+write) hits 2704system.l2c.demand_hits::cpu1.itb.walker 5313 # number of demand (read+write) hits 2705system.l2c.demand_hits::cpu1.inst 419752 # number of demand (read+write) hits 2706system.l2c.demand_hits::cpu1.data 598472 # number of demand (read+write) hits 2707system.l2c.demand_hits::cpu1.l2cache.prefetcher 283166 # number of demand (read+write) hits 2708system.l2c.demand_hits::total 2583772 # number of demand (read+write) hits 2709system.l2c.overall_hits::cpu0.dtb.walker 4670 # number of overall hits 2710system.l2c.overall_hits::cpu0.itb.walker 3337 # number of overall hits 2711system.l2c.overall_hits::cpu0.inst 411404 # number of overall hits 2712system.l2c.overall_hits::cpu0.data 582846 # number of overall hits 2713system.l2c.overall_hits::cpu0.l2cache.prefetcher 268808 # number of overall hits 2714system.l2c.overall_hits::cpu1.dtb.walker 6004 # number of overall hits 2715system.l2c.overall_hits::cpu1.itb.walker 5313 # number of overall hits 2716system.l2c.overall_hits::cpu1.inst 419752 # number of overall hits 2717system.l2c.overall_hits::cpu1.data 598472 # number of overall hits 2718system.l2c.overall_hits::cpu1.l2cache.prefetcher 283166 # number of overall hits 2719system.l2c.overall_hits::total 2583772 # number of overall hits 2720system.l2c.UpgradeReq_misses::cpu0.data 61222 # number of UpgradeReq misses 2721system.l2c.UpgradeReq_misses::cpu1.data 59774 # number of UpgradeReq misses 2722system.l2c.UpgradeReq_misses::total 120996 # number of UpgradeReq misses 2723system.l2c.SCUpgradeReq_misses::cpu0.data 13056 # number of SCUpgradeReq misses 2724system.l2c.SCUpgradeReq_misses::cpu1.data 12621 # number of SCUpgradeReq misses 2725system.l2c.SCUpgradeReq_misses::total 25677 # number of SCUpgradeReq misses 2726system.l2c.ReadExReq_misses::cpu0.data 80578 # number of ReadExReq misses 2727system.l2c.ReadExReq_misses::cpu1.data 52729 # number of ReadExReq misses 2728system.l2c.ReadExReq_misses::total 133307 # number of ReadExReq misses 2729system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1465 # number of ReadSharedReq misses 2730system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1507 # number of ReadSharedReq misses 2731system.l2c.ReadSharedReq_misses::cpu0.inst 49296 # number of ReadSharedReq misses 2732system.l2c.ReadSharedReq_misses::cpu0.data 137179 # number of ReadSharedReq misses 2733system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 229932 # number of ReadSharedReq misses 2734system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2146 # number of ReadSharedReq misses 2735system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2116 # number of ReadSharedReq misses 2736system.l2c.ReadSharedReq_misses::cpu1.inst 39165 # number of ReadSharedReq misses 2737system.l2c.ReadSharedReq_misses::cpu1.data 95585 # number of ReadSharedReq misses 2738system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 188965 # number of ReadSharedReq misses 2739system.l2c.ReadSharedReq_misses::total 747356 # number of ReadSharedReq misses 2740system.l2c.InvalidateReq_misses::cpu0.data 446352 # number of InvalidateReq misses 2741system.l2c.InvalidateReq_misses::cpu1.data 114497 # number of InvalidateReq misses 2742system.l2c.InvalidateReq_misses::total 560849 # number of InvalidateReq misses 2743system.l2c.demand_misses::cpu0.dtb.walker 1465 # number of demand (read+write) misses 2744system.l2c.demand_misses::cpu0.itb.walker 1507 # number of demand (read+write) misses 2745system.l2c.demand_misses::cpu0.inst 49296 # number of demand (read+write) misses 2746system.l2c.demand_misses::cpu0.data 217757 # number of demand (read+write) misses 2747system.l2c.demand_misses::cpu0.l2cache.prefetcher 229932 # number of demand (read+write) misses 2748system.l2c.demand_misses::cpu1.dtb.walker 2146 # number of demand (read+write) misses 2749system.l2c.demand_misses::cpu1.itb.walker 2116 # number of demand (read+write) misses 2750system.l2c.demand_misses::cpu1.inst 39165 # number of demand (read+write) misses 2751system.l2c.demand_misses::cpu1.data 148314 # number of demand (read+write) misses 2752system.l2c.demand_misses::cpu1.l2cache.prefetcher 188965 # number of demand (read+write) misses 2753system.l2c.demand_misses::total 880663 # number of demand (read+write) misses 2754system.l2c.overall_misses::cpu0.dtb.walker 1465 # number of overall misses 2755system.l2c.overall_misses::cpu0.itb.walker 1507 # number of overall misses 2756system.l2c.overall_misses::cpu0.inst 49296 # number of overall misses 2757system.l2c.overall_misses::cpu0.data 217757 # number of overall misses 2758system.l2c.overall_misses::cpu0.l2cache.prefetcher 229932 # number of overall misses 2759system.l2c.overall_misses::cpu1.dtb.walker 2146 # number of overall misses 2760system.l2c.overall_misses::cpu1.itb.walker 2116 # number of overall misses 2761system.l2c.overall_misses::cpu1.inst 39165 # number of overall misses 2762system.l2c.overall_misses::cpu1.data 148314 # number of overall misses 2763system.l2c.overall_misses::cpu1.l2cache.prefetcher 188965 # number of overall misses 2764system.l2c.overall_misses::total 880663 # number of overall misses 2765system.l2c.UpgradeReq_miss_latency::cpu0.data 367859500 # number of UpgradeReq miss cycles 2766system.l2c.UpgradeReq_miss_latency::cpu1.data 359764000 # number of UpgradeReq miss cycles 2767system.l2c.UpgradeReq_miss_latency::total 727623500 # number of UpgradeReq miss cycles 2768system.l2c.SCUpgradeReq_miss_latency::cpu0.data 70353500 # number of SCUpgradeReq miss cycles 2769system.l2c.SCUpgradeReq_miss_latency::cpu1.data 71619000 # number of SCUpgradeReq miss cycles 2770system.l2c.SCUpgradeReq_miss_latency::total 141972500 # number of SCUpgradeReq miss cycles 2771system.l2c.ReadExReq_miss_latency::cpu0.data 7055893500 # number of ReadExReq miss cycles 2772system.l2c.ReadExReq_miss_latency::cpu1.data 4403905000 # number of ReadExReq miss cycles 2773system.l2c.ReadExReq_miss_latency::total 11459798500 # number of ReadExReq miss cycles 2774system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 131430500 # number of ReadSharedReq miss cycles 2775system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 136636000 # number of ReadSharedReq miss cycles 2776system.l2c.ReadSharedReq_miss_latency::cpu0.inst 4206937000 # number of ReadSharedReq miss cycles 2777system.l2c.ReadSharedReq_miss_latency::cpu0.data 12205051500 # number of ReadSharedReq miss cycles 2778system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of ReadSharedReq miss cycles 2779system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 192694000 # number of ReadSharedReq miss cycles 2780system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 194855000 # number of ReadSharedReq miss cycles 2781system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3362110000 # number of ReadSharedReq miss cycles 2782system.l2c.ReadSharedReq_miss_latency::cpu1.data 8709641000 # number of ReadSharedReq miss cycles 2783system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of ReadSharedReq miss cycles 2784system.l2c.ReadSharedReq_miss_latency::total 79366262993 # number of ReadSharedReq miss cycles 2785system.l2c.InvalidateReq_miss_latency::cpu0.data 47144000 # number of InvalidateReq miss cycles 2786system.l2c.InvalidateReq_miss_latency::cpu1.data 45361000 # number of InvalidateReq miss cycles 2787system.l2c.InvalidateReq_miss_latency::total 92505000 # number of InvalidateReq miss cycles 2788system.l2c.demand_miss_latency::cpu0.dtb.walker 131430500 # number of demand (read+write) miss cycles 2789system.l2c.demand_miss_latency::cpu0.itb.walker 136636000 # number of demand (read+write) miss cycles 2790system.l2c.demand_miss_latency::cpu0.inst 4206937000 # number of demand (read+write) miss cycles 2791system.l2c.demand_miss_latency::cpu0.data 19260945000 # number of demand (read+write) miss cycles 2792system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of demand (read+write) miss cycles 2793system.l2c.demand_miss_latency::cpu1.dtb.walker 192694000 # number of demand (read+write) miss cycles 2794system.l2c.demand_miss_latency::cpu1.itb.walker 194855000 # number of demand (read+write) miss cycles 2795system.l2c.demand_miss_latency::cpu1.inst 3362110000 # number of demand (read+write) miss cycles 2796system.l2c.demand_miss_latency::cpu1.data 13113546000 # number of demand (read+write) miss cycles 2797system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of demand (read+write) miss cycles 2798system.l2c.demand_miss_latency::total 90826061493 # number of demand (read+write) miss cycles 2799system.l2c.overall_miss_latency::cpu0.dtb.walker 131430500 # number of overall miss cycles 2800system.l2c.overall_miss_latency::cpu0.itb.walker 136636000 # number of overall miss cycles 2801system.l2c.overall_miss_latency::cpu0.inst 4206937000 # number of overall miss cycles 2802system.l2c.overall_miss_latency::cpu0.data 19260945000 # number of overall miss cycles 2803system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27523923010 # number of overall miss cycles 2804system.l2c.overall_miss_latency::cpu1.dtb.walker 192694000 # number of overall miss cycles 2805system.l2c.overall_miss_latency::cpu1.itb.walker 194855000 # number of overall miss cycles 2806system.l2c.overall_miss_latency::cpu1.inst 3362110000 # number of overall miss cycles 2807system.l2c.overall_miss_latency::cpu1.data 13113546000 # number of overall miss cycles 2808system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22702984983 # number of overall miss cycles 2809system.l2c.overall_miss_latency::total 90826061493 # number of overall miss cycles 2810system.l2c.WritebackDirty_accesses::writebacks 2606701 # number of WritebackDirty accesses(hits+misses) 2811system.l2c.WritebackDirty_accesses::total 2606701 # number of WritebackDirty accesses(hits+misses) 2812system.l2c.UpgradeReq_accesses::cpu0.data 219171 # number of UpgradeReq accesses(hits+misses) 2813system.l2c.UpgradeReq_accesses::cpu1.data 190208 # number of UpgradeReq accesses(hits+misses) 2814system.l2c.UpgradeReq_accesses::total 409379 # number of UpgradeReq accesses(hits+misses) 2815system.l2c.SCUpgradeReq_accesses::cpu0.data 49884 # number of SCUpgradeReq accesses(hits+misses) 2816system.l2c.SCUpgradeReq_accesses::cpu1.data 49655 # number of SCUpgradeReq accesses(hits+misses) 2817system.l2c.SCUpgradeReq_accesses::total 99539 # number of SCUpgradeReq accesses(hits+misses) 2818system.l2c.ReadExReq_accesses::cpu0.data 126467 # number of ReadExReq accesses(hits+misses) 2819system.l2c.ReadExReq_accesses::cpu1.data 109980 # number of ReadExReq accesses(hits+misses) 2820system.l2c.ReadExReq_accesses::total 236447 # number of ReadExReq accesses(hits+misses) 2821system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6135 # number of ReadSharedReq accesses(hits+misses) 2822system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4844 # number of ReadSharedReq accesses(hits+misses) 2823system.l2c.ReadSharedReq_accesses::cpu0.inst 460700 # number of ReadSharedReq accesses(hits+misses) 2824system.l2c.ReadSharedReq_accesses::cpu0.data 674136 # number of ReadSharedReq accesses(hits+misses) 2825system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 498740 # number of ReadSharedReq accesses(hits+misses) 2826system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8150 # number of ReadSharedReq accesses(hits+misses) 2827system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7429 # number of ReadSharedReq accesses(hits+misses) 2828system.l2c.ReadSharedReq_accesses::cpu1.inst 458917 # number of ReadSharedReq accesses(hits+misses) 2829system.l2c.ReadSharedReq_accesses::cpu1.data 636806 # number of ReadSharedReq accesses(hits+misses) 2830system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 472131 # number of ReadSharedReq accesses(hits+misses) 2831system.l2c.ReadSharedReq_accesses::total 3227988 # number of ReadSharedReq accesses(hits+misses) 2832system.l2c.InvalidateReq_accesses::cpu0.data 565273 # number of InvalidateReq accesses(hits+misses) 2833system.l2c.InvalidateReq_accesses::cpu1.data 236906 # number of InvalidateReq accesses(hits+misses) 2834system.l2c.InvalidateReq_accesses::total 802179 # number of InvalidateReq accesses(hits+misses) 2835system.l2c.demand_accesses::cpu0.dtb.walker 6135 # number of demand (read+write) accesses 2836system.l2c.demand_accesses::cpu0.itb.walker 4844 # number of demand (read+write) accesses 2837system.l2c.demand_accesses::cpu0.inst 460700 # number of demand (read+write) accesses 2838system.l2c.demand_accesses::cpu0.data 800603 # number of demand (read+write) accesses 2839system.l2c.demand_accesses::cpu0.l2cache.prefetcher 498740 # number of demand (read+write) accesses 2840system.l2c.demand_accesses::cpu1.dtb.walker 8150 # number of demand (read+write) accesses 2841system.l2c.demand_accesses::cpu1.itb.walker 7429 # number of demand (read+write) accesses 2842system.l2c.demand_accesses::cpu1.inst 458917 # number of demand (read+write) accesses 2843system.l2c.demand_accesses::cpu1.data 746786 # number of demand (read+write) accesses 2844system.l2c.demand_accesses::cpu1.l2cache.prefetcher 472131 # number of demand (read+write) accesses 2845system.l2c.demand_accesses::total 3464435 # number of demand (read+write) accesses 2846system.l2c.overall_accesses::cpu0.dtb.walker 6135 # number of overall (read+write) accesses 2847system.l2c.overall_accesses::cpu0.itb.walker 4844 # number of overall (read+write) accesses 2848system.l2c.overall_accesses::cpu0.inst 460700 # number of overall (read+write) accesses 2849system.l2c.overall_accesses::cpu0.data 800603 # number of overall (read+write) accesses 2850system.l2c.overall_accesses::cpu0.l2cache.prefetcher 498740 # number of overall (read+write) accesses 2851system.l2c.overall_accesses::cpu1.dtb.walker 8150 # number of overall (read+write) accesses 2852system.l2c.overall_accesses::cpu1.itb.walker 7429 # number of overall (read+write) accesses 2853system.l2c.overall_accesses::cpu1.inst 458917 # number of overall (read+write) accesses 2854system.l2c.overall_accesses::cpu1.data 746786 # number of overall (read+write) accesses 2855system.l2c.overall_accesses::cpu1.l2cache.prefetcher 472131 # number of overall (read+write) accesses 2856system.l2c.overall_accesses::total 3464435 # number of overall (read+write) accesses 2857system.l2c.UpgradeReq_miss_rate::cpu0.data 0.279334 # miss rate for UpgradeReq accesses 2858system.l2c.UpgradeReq_miss_rate::cpu1.data 0.314256 # miss rate for UpgradeReq accesses 2859system.l2c.UpgradeReq_miss_rate::total 0.295560 # miss rate for UpgradeReq accesses 2860system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.261727 # miss rate for SCUpgradeReq accesses 2861system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.254174 # miss rate for SCUpgradeReq accesses 2862system.l2c.SCUpgradeReq_miss_rate::total 0.257959 # miss rate for SCUpgradeReq accesses 2863system.l2c.ReadExReq_miss_rate::cpu0.data 0.637146 # miss rate for ReadExReq accesses 2864system.l2c.ReadExReq_miss_rate::cpu1.data 0.479442 # miss rate for ReadExReq accesses 2865system.l2c.ReadExReq_miss_rate::total 0.563792 # miss rate for ReadExReq accesses 2866system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for ReadSharedReq accesses 2867system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311107 # miss rate for ReadSharedReq accesses 2868system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107002 # miss rate for ReadSharedReq accesses 2869system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.203489 # miss rate for ReadSharedReq accesses 2870system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for ReadSharedReq accesses 2871system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for ReadSharedReq accesses 2872system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.284830 # miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085342 # miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.150101 # miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_miss_rate::total 0.231524 # miss rate for ReadSharedReq accesses 2877system.l2c.InvalidateReq_miss_rate::cpu0.data 0.789622 # miss rate for InvalidateReq accesses 2878system.l2c.InvalidateReq_miss_rate::cpu1.data 0.483301 # miss rate for InvalidateReq accesses 2879system.l2c.InvalidateReq_miss_rate::total 0.699157 # miss rate for InvalidateReq accesses 2880system.l2c.demand_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for demand accesses 2881system.l2c.demand_miss_rate::cpu0.itb.walker 0.311107 # miss rate for demand accesses 2882system.l2c.demand_miss_rate::cpu0.inst 0.107002 # miss rate for demand accesses 2883system.l2c.demand_miss_rate::cpu0.data 0.271991 # miss rate for demand accesses 2884system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for demand accesses 2885system.l2c.demand_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for demand accesses 2886system.l2c.demand_miss_rate::cpu1.itb.walker 0.284830 # miss rate for demand accesses 2887system.l2c.demand_miss_rate::cpu1.inst 0.085342 # miss rate for demand accesses 2888system.l2c.demand_miss_rate::cpu1.data 0.198603 # miss rate for demand accesses 2889system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for demand accesses 2890system.l2c.demand_miss_rate::total 0.254201 # miss rate for demand accesses 2891system.l2c.overall_miss_rate::cpu0.dtb.walker 0.238794 # miss rate for overall accesses 2892system.l2c.overall_miss_rate::cpu0.itb.walker 0.311107 # miss rate for overall accesses 2893system.l2c.overall_miss_rate::cpu0.inst 0.107002 # miss rate for overall accesses 2894system.l2c.overall_miss_rate::cpu0.data 0.271991 # miss rate for overall accesses 2895system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461026 # miss rate for overall accesses 2896system.l2c.overall_miss_rate::cpu1.dtb.walker 0.263313 # miss rate for overall accesses 2897system.l2c.overall_miss_rate::cpu1.itb.walker 0.284830 # miss rate for overall accesses 2898system.l2c.overall_miss_rate::cpu1.inst 0.085342 # miss rate for overall accesses 2899system.l2c.overall_miss_rate::cpu1.data 0.198603 # miss rate for overall accesses 2900system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.400238 # miss rate for overall accesses 2901system.l2c.overall_miss_rate::total 0.254201 # miss rate for overall accesses 2902system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6008.616184 # average UpgradeReq miss latency 2903system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6018.737244 # average UpgradeReq miss latency 2904system.l2c.UpgradeReq_avg_miss_latency::total 6013.616153 # average UpgradeReq miss latency 2905system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5388.595282 # average SCUpgradeReq miss latency 2906system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5674.589969 # average SCUpgradeReq miss latency 2907system.l2c.SCUpgradeReq_avg_miss_latency::total 5529.170074 # average SCUpgradeReq miss latency 2908system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87566.004368 # average ReadExReq miss latency 2909system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83519.600220 # average ReadExReq miss latency 2910system.l2c.ReadExReq_avg_miss_latency::total 85965.466930 # average ReadExReq miss latency 2911system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average ReadSharedReq miss latency 2912system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90667.551427 # average ReadSharedReq miss latency 2913system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85340.331873 # average ReadSharedReq miss latency 2914system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88971.719432 # average ReadSharedReq miss latency 2915system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average ReadSharedReq miss latency 2916system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average ReadSharedReq miss latency 2917system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92086.483932 # average ReadSharedReq miss latency 2918system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85844.759351 # average ReadSharedReq miss latency 2919system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91119.328346 # average ReadSharedReq miss latency 2920system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average ReadSharedReq miss latency 2921system.l2c.ReadSharedReq_avg_miss_latency::total 106196.060503 # average ReadSharedReq miss latency 2922system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 105.620676 # average InvalidateReq miss latency 2923system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 396.176319 # average InvalidateReq miss latency 2924system.l2c.InvalidateReq_avg_miss_latency::total 164.937443 # average InvalidateReq miss latency 2925system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average overall miss latency 2926system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90667.551427 # average overall miss latency 2927system.l2c.demand_avg_miss_latency::cpu0.inst 85340.331873 # average overall miss latency 2928system.l2c.demand_avg_miss_latency::cpu0.data 88451.553796 # average overall miss latency 2929system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average overall miss latency 2930system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average overall miss latency 2931system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92086.483932 # average overall miss latency 2932system.l2c.demand_avg_miss_latency::cpu1.inst 85844.759351 # average overall miss latency 2933system.l2c.demand_avg_miss_latency::cpu1.data 88417.452162 # average overall miss latency 2934system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average overall miss latency 2935system.l2c.demand_avg_miss_latency::total 103133.731624 # average overall miss latency 2936system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89713.651877 # average overall miss latency 2937system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90667.551427 # average overall miss latency 2938system.l2c.overall_avg_miss_latency::cpu0.inst 85340.331873 # average overall miss latency 2939system.l2c.overall_avg_miss_latency::cpu0.data 88451.553796 # average overall miss latency 2940system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119704.621410 # average overall miss latency 2941system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89792.171482 # average overall miss latency 2942system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92086.483932 # average overall miss latency 2943system.l2c.overall_avg_miss_latency::cpu1.inst 85844.759351 # average overall miss latency 2944system.l2c.overall_avg_miss_latency::cpu1.data 88417.452162 # average overall miss latency 2945system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120143.862530 # average overall miss latency 2946system.l2c.overall_avg_miss_latency::total 103133.731624 # average overall miss latency 2947system.l2c.blocked_cycles::no_mshrs 237 # number of cycles access was blocked 2948system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2949system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked 2950system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2951system.l2c.avg_blocked_cycles::no_mshrs 237 # average number of cycles each access was blocked 2952system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2953system.l2c.writebacks::writebacks 1068644 # number of writebacks 2954system.l2c.writebacks::total 1068644 # number of writebacks 2955system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 42 # number of ReadSharedReq MSHR hits 2956system.l2c.ReadSharedReq_mshr_hits::cpu0.data 7 # number of ReadSharedReq MSHR hits 2957system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 109 # number of ReadSharedReq MSHR hits 2958system.l2c.ReadSharedReq_mshr_hits::cpu1.data 24 # number of ReadSharedReq MSHR hits 2959system.l2c.ReadSharedReq_mshr_hits::total 182 # number of ReadSharedReq MSHR hits 2960system.l2c.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits 2961system.l2c.demand_mshr_hits::cpu0.data 7 # number of demand (read+write) MSHR hits 2962system.l2c.demand_mshr_hits::cpu1.inst 109 # number of demand (read+write) MSHR hits 2963system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 2964system.l2c.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits 2965system.l2c.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits 2966system.l2c.overall_mshr_hits::cpu0.data 7 # number of overall MSHR hits 2967system.l2c.overall_mshr_hits::cpu1.inst 109 # number of overall MSHR hits 2968system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 2969system.l2c.overall_mshr_hits::total 182 # number of overall MSHR hits 2970system.l2c.CleanEvict_mshr_misses::writebacks 46836 # number of CleanEvict MSHR misses 2971system.l2c.CleanEvict_mshr_misses::total 46836 # number of CleanEvict MSHR misses 2972system.l2c.UpgradeReq_mshr_misses::cpu0.data 61222 # number of UpgradeReq MSHR misses 2973system.l2c.UpgradeReq_mshr_misses::cpu1.data 59774 # number of UpgradeReq MSHR misses 2974system.l2c.UpgradeReq_mshr_misses::total 120996 # number of UpgradeReq MSHR misses 2975system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13056 # number of SCUpgradeReq MSHR misses 2976system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12621 # number of SCUpgradeReq MSHR misses 2977system.l2c.SCUpgradeReq_mshr_misses::total 25677 # number of SCUpgradeReq MSHR misses 2978system.l2c.ReadExReq_mshr_misses::cpu0.data 80578 # number of ReadExReq MSHR misses 2979system.l2c.ReadExReq_mshr_misses::cpu1.data 52729 # number of ReadExReq MSHR misses 2980system.l2c.ReadExReq_mshr_misses::total 133307 # number of ReadExReq MSHR misses 2981system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1465 # number of ReadSharedReq MSHR misses 2982system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1507 # number of ReadSharedReq MSHR misses 2983system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 49254 # number of ReadSharedReq MSHR misses 2984system.l2c.ReadSharedReq_mshr_misses::cpu0.data 137172 # number of ReadSharedReq MSHR misses 2985system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 229932 # number of ReadSharedReq MSHR misses 2986system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2146 # number of ReadSharedReq MSHR misses 2987system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2116 # number of ReadSharedReq MSHR misses 2988system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39056 # number of ReadSharedReq MSHR misses 2989system.l2c.ReadSharedReq_mshr_misses::cpu1.data 95561 # number of ReadSharedReq MSHR misses 2990system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of ReadSharedReq MSHR misses 2991system.l2c.ReadSharedReq_mshr_misses::total 747174 # number of ReadSharedReq MSHR misses 2992system.l2c.InvalidateReq_mshr_misses::cpu0.data 446352 # number of InvalidateReq MSHR misses 2993system.l2c.InvalidateReq_mshr_misses::cpu1.data 114497 # number of InvalidateReq MSHR misses 2994system.l2c.InvalidateReq_mshr_misses::total 560849 # number of InvalidateReq MSHR misses 2995system.l2c.demand_mshr_misses::cpu0.dtb.walker 1465 # number of demand (read+write) MSHR misses 2996system.l2c.demand_mshr_misses::cpu0.itb.walker 1507 # number of demand (read+write) MSHR misses 2997system.l2c.demand_mshr_misses::cpu0.inst 49254 # number of demand (read+write) MSHR misses 2998system.l2c.demand_mshr_misses::cpu0.data 217750 # number of demand (read+write) MSHR misses 2999system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 229932 # number of demand (read+write) MSHR misses 3000system.l2c.demand_mshr_misses::cpu1.dtb.walker 2146 # number of demand (read+write) MSHR misses 3001system.l2c.demand_mshr_misses::cpu1.itb.walker 2116 # number of demand (read+write) MSHR misses 3002system.l2c.demand_mshr_misses::cpu1.inst 39056 # number of demand (read+write) MSHR misses 3003system.l2c.demand_mshr_misses::cpu1.data 148290 # number of demand (read+write) MSHR misses 3004system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of demand (read+write) MSHR misses 3005system.l2c.demand_mshr_misses::total 880481 # number of demand (read+write) MSHR misses 3006system.l2c.overall_mshr_misses::cpu0.dtb.walker 1465 # number of overall MSHR misses 3007system.l2c.overall_mshr_misses::cpu0.itb.walker 1507 # number of overall MSHR misses 3008system.l2c.overall_mshr_misses::cpu0.inst 49254 # number of overall MSHR misses 3009system.l2c.overall_mshr_misses::cpu0.data 217750 # number of overall MSHR misses 3010system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 229932 # number of overall MSHR misses 3011system.l2c.overall_mshr_misses::cpu1.dtb.walker 2146 # number of overall MSHR misses 3012system.l2c.overall_mshr_misses::cpu1.itb.walker 2116 # number of overall MSHR misses 3013system.l2c.overall_mshr_misses::cpu1.inst 39056 # number of overall MSHR misses 3014system.l2c.overall_mshr_misses::cpu1.data 148290 # number of overall MSHR misses 3015system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 188965 # number of overall MSHR misses 3016system.l2c.overall_mshr_misses::total 880481 # number of overall MSHR misses 3017system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 3018system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27617 # number of ReadReq MSHR uncacheable 3019system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 3020system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11033 # number of ReadReq MSHR uncacheable 3021system.l2c.ReadReq_mshr_uncacheable::total 81885 # number of ReadReq MSHR uncacheable 3022system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26565 # number of WriteReq MSHR uncacheable 3023system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11949 # number of WriteReq MSHR uncacheable 3024system.l2c.WriteReq_mshr_uncacheable::total 38514 # number of WriteReq MSHR uncacheable 3025system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 3026system.l2c.overall_mshr_uncacheable_misses::cpu0.data 54182 # number of overall MSHR uncacheable misses 3027system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 3028system.l2c.overall_mshr_uncacheable_misses::cpu1.data 22982 # number of overall MSHR uncacheable misses 3029system.l2c.overall_mshr_uncacheable_misses::total 120399 # number of overall MSHR uncacheable misses 3030system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1334926500 # number of UpgradeReq MSHR miss cycles 3031system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1302438000 # number of UpgradeReq MSHR miss cycles 3032system.l2c.UpgradeReq_mshr_miss_latency::total 2637364500 # number of UpgradeReq MSHR miss cycles 3033system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 323030000 # number of SCUpgradeReq MSHR miss cycles 3034system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 313272000 # number of SCUpgradeReq MSHR miss cycles 3035system.l2c.SCUpgradeReq_mshr_miss_latency::total 636302000 # number of SCUpgradeReq MSHR miss cycles 3036system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6250073584 # number of ReadExReq MSHR miss cycles 3037system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3876565100 # number of ReadExReq MSHR miss cycles 3038system.l2c.ReadExReq_mshr_miss_latency::total 10126638684 # number of ReadExReq MSHR miss cycles 3039system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of ReadSharedReq MSHR miss cycles 3040system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 121565002 # number of ReadSharedReq MSHR miss cycles 3041system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3711112036 # number of ReadSharedReq MSHR miss cycles 3042system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10832879176 # number of ReadSharedReq MSHR miss cycles 3043system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of ReadSharedReq MSHR miss cycles 3044system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of ReadSharedReq MSHR miss cycles 3045system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 173694002 # number of ReadSharedReq MSHR miss cycles 3046system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 2962814058 # number of ReadSharedReq MSHR miss cycles 3047system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 7752148763 # number of ReadSharedReq MSHR miss cycles 3048system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of ReadSharedReq MSHR miss cycles 3049system.l2c.ReadSharedReq_mshr_miss_latency::total 71879702509 # number of ReadSharedReq MSHR miss cycles 3050system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8910827500 # number of InvalidateReq MSHR miss cycles 3051system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2333318000 # number of InvalidateReq MSHR miss cycles 3052system.l2c.InvalidateReq_mshr_miss_latency::total 11244145500 # number of InvalidateReq MSHR miss cycles 3053system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of demand (read+write) MSHR miss cycles 3054system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 121565002 # number of demand (read+write) MSHR miss cycles 3055system.l2c.demand_mshr_miss_latency::cpu0.inst 3711112036 # number of demand (read+write) MSHR miss cycles 3056system.l2c.demand_mshr_miss_latency::cpu0.data 17082952760 # number of demand (read+write) MSHR miss cycles 3057system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of demand (read+write) MSHR miss cycles 3058system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of demand (read+write) MSHR miss cycles 3059system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173694002 # number of demand (read+write) MSHR miss cycles 3060system.l2c.demand_mshr_miss_latency::cpu1.inst 2962814058 # number of demand (read+write) MSHR miss cycles 3061system.l2c.demand_mshr_miss_latency::cpu1.data 11628713863 # number of demand (read+write) MSHR miss cycles 3062system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of demand (read+write) MSHR miss cycles 3063system.l2c.demand_mshr_miss_latency::total 82006341193 # number of demand (read+write) MSHR miss cycles 3064system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 116780001 # number of overall MSHR miss cycles 3065system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 121565002 # number of overall MSHR miss cycles 3066system.l2c.overall_mshr_miss_latency::cpu0.inst 3711112036 # number of overall MSHR miss cycles 3067system.l2c.overall_mshr_miss_latency::cpu0.data 17082952760 # number of overall MSHR miss cycles 3068system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25224418397 # number of overall MSHR miss cycles 3069system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171229509 # number of overall MSHR miss cycles 3070system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173694002 # number of overall MSHR miss cycles 3071system.l2c.overall_mshr_miss_latency::cpu1.inst 2962814058 # number of overall MSHR miss cycles 3072system.l2c.overall_mshr_miss_latency::cpu1.data 11628713863 # number of overall MSHR miss cycles 3073system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20813061565 # number of overall MSHR miss cycles 3074system.l2c.overall_mshr_miss_latency::total 82006341193 # number of overall MSHR miss cycles 3075system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles 3076system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4353667507 # number of ReadReq MSHR uncacheable cycles 3077system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7421000 # number of ReadReq MSHR uncacheable cycles 3078system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1606781004 # number of ReadReq MSHR uncacheable cycles 3079system.l2c.ReadReq_mshr_uncacheable_latency::total 8687651511 # number of ReadReq MSHR uncacheable cycles 3080system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles 3081system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4353667507 # number of overall MSHR uncacheable cycles 3082system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7421000 # number of overall MSHR uncacheable cycles 3083system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1606781004 # number of overall MSHR uncacheable cycles 3084system.l2c.overall_mshr_uncacheable_latency::total 8687651511 # number of overall MSHR uncacheable cycles 3085system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3086system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3087system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.279334 # mshr miss rate for UpgradeReq accesses 3088system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.314256 # mshr miss rate for UpgradeReq accesses 3089system.l2c.UpgradeReq_mshr_miss_rate::total 0.295560 # mshr miss rate for UpgradeReq accesses 3090system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.261727 # mshr miss rate for SCUpgradeReq accesses 3091system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.254174 # mshr miss rate for SCUpgradeReq accesses 3092system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.257959 # mshr miss rate for SCUpgradeReq accesses 3093system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.637146 # mshr miss rate for ReadExReq accesses 3094system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.479442 # mshr miss rate for ReadExReq accesses 3095system.l2c.ReadExReq_mshr_miss_rate::total 0.563792 # mshr miss rate for ReadExReq accesses 3096system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for ReadSharedReq accesses 3097system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for ReadSharedReq accesses 3098system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for ReadSharedReq accesses 3099system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.203478 # mshr miss rate for ReadSharedReq accesses 3100system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for ReadSharedReq accesses 3101system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for ReadSharedReq accesses 3102system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for ReadSharedReq accesses 3103system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for ReadSharedReq accesses 3104system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.150063 # mshr miss rate for ReadSharedReq accesses 3105system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for ReadSharedReq accesses 3106system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231467 # mshr miss rate for ReadSharedReq accesses 3107system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.789622 # mshr miss rate for InvalidateReq accesses 3108system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.483301 # mshr miss rate for InvalidateReq accesses 3109system.l2c.InvalidateReq_mshr_miss_rate::total 0.699157 # mshr miss rate for InvalidateReq accesses 3110system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for demand accesses 3111system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for demand accesses 3112system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for demand accesses 3113system.l2c.demand_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for demand accesses 3114system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for demand accesses 3115system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for demand accesses 3116system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for demand accesses 3117system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for demand accesses 3118system.l2c.demand_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for demand accesses 3119system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for demand accesses 3120system.l2c.demand_mshr_miss_rate::total 0.254149 # mshr miss rate for demand accesses 3121system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238794 # mshr miss rate for overall accesses 3122system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311107 # mshr miss rate for overall accesses 3123system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106911 # mshr miss rate for overall accesses 3124system.l2c.overall_mshr_miss_rate::cpu0.data 0.271982 # mshr miss rate for overall accesses 3125system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461026 # mshr miss rate for overall accesses 3126system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.263313 # mshr miss rate for overall accesses 3127system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.284830 # mshr miss rate for overall accesses 3128system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085105 # mshr miss rate for overall accesses 3129system.l2c.overall_mshr_miss_rate::cpu1.data 0.198571 # mshr miss rate for overall accesses 3130system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.400238 # mshr miss rate for overall accesses 3131system.l2c.overall_mshr_miss_rate::total 0.254149 # mshr miss rate for overall accesses 3132system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21804.686224 # average UpgradeReq mshr miss latency 3133system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21789.373306 # average UpgradeReq mshr miss latency 3134system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21797.121392 # average UpgradeReq mshr miss latency 3135system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24741.881127 # average SCUpgradeReq mshr miss latency 3136system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24821.487996 # average SCUpgradeReq mshr miss latency 3137system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24781.010243 # average SCUpgradeReq mshr miss latency 3138system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77565.508997 # average ReadExReq mshr miss latency 3139system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73518.653872 # average ReadExReq mshr miss latency 3140system.l2c.ReadExReq_avg_mshr_miss_latency::total 75964.793177 # average ReadExReq mshr miss latency 3141system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average ReadSharedReq mshr miss latency 3142system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average ReadSharedReq mshr miss latency 3143system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average ReadSharedReq mshr miss latency 3144system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78972.962237 # average ReadSharedReq mshr miss latency 3145system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average ReadSharedReq mshr miss latency 3146system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average ReadSharedReq mshr miss latency 3147system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average ReadSharedReq mshr miss latency 3148system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average ReadSharedReq mshr miss latency 3149system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81122.516121 # average ReadSharedReq mshr miss latency 3150system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average ReadSharedReq mshr miss latency 3151system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96202.092831 # average ReadSharedReq mshr miss latency 3152system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19963.677770 # average InvalidateReq mshr miss latency 3153system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20378.857088 # average InvalidateReq mshr miss latency 3154system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20048.436388 # average InvalidateReq mshr miss latency 3155system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency 3156system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency 3157system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency 3158system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency 3159system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency 3160system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency 3161system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency 3162system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency 3163system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency 3164system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency 3165system.l2c.demand_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency 3166system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79713.311263 # average overall mshr miss latency 3167system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80666.889184 # average overall mshr miss latency 3168system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75346.409144 # average overall mshr miss latency 3169system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78452.136670 # average overall mshr miss latency 3170system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109703.818507 # average overall mshr miss latency 3171system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79790.078751 # average overall mshr miss latency 3172system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82086.012287 # average overall mshr miss latency 3173system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75860.663099 # average overall mshr miss latency 3174system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78418.732639 # average overall mshr miss latency 3175system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110142.415606 # average overall mshr miss latency 3176system.l2c.overall_avg_mshr_miss_latency::total 93138.115636 # average overall mshr miss latency 3177system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency 3178system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157644.476482 # average ReadReq mshr uncacheable latency 3179system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average ReadReq mshr uncacheable latency 3180system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145634.098069 # average ReadReq mshr uncacheable latency 3181system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106095.762484 # average ReadReq mshr uncacheable latency 3182system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency 3183system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80352.654147 # average overall mshr uncacheable latency 3184system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67463.636364 # average overall mshr uncacheable latency 3185system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69914.759551 # average overall mshr uncacheable latency 3186system.l2c.overall_avg_mshr_uncacheable_latency::total 72157.173324 # average overall mshr uncacheable latency 3187system.membus.snoop_filter.tot_requests 3697678 # Total number of requests made to the snoop filter. 3188system.membus.snoop_filter.hit_single_requests 2246661 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3189system.membus.snoop_filter.hit_multi_requests 3188 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3190system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3191system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3192system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3193system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3194system.membus.trans_dist::ReadReq 81885 # Transaction distribution 3195system.membus.trans_dist::ReadResp 837971 # Transaction distribution 3196system.membus.trans_dist::WriteReq 38514 # Transaction distribution 3197system.membus.trans_dist::WriteResp 38514 # Transaction distribution 3198system.membus.trans_dist::WritebackDirty 1175339 # Transaction distribution 3199system.membus.trans_dist::CleanEvict 216465 # Transaction distribution 3200system.membus.trans_dist::UpgradeReq 402269 # Transaction distribution 3201system.membus.trans_dist::SCUpgradeReq 335845 # Transaction distribution 3202system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3203system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3204system.membus.trans_dist::ReadExReq 147056 # Transaction distribution 3205system.membus.trans_dist::ReadExResp 129063 # Transaction distribution 3206system.membus.trans_dist::ReadSharedReq 756086 # Transaction distribution 3207system.membus.trans_dist::InvalidateReq 664574 # Transaction distribution 3208system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122674 # Packet count per connected master and slave (bytes) 3209system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3210system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26434 # Packet count per connected master and slave (bytes) 3211system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4433526 # Packet count per connected master and slave (bytes) 3212system.membus.pkt_count_system.l2c.mem_side::total 4582726 # Packet count per connected master and slave (bytes) 3213system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237876 # Packet count per connected master and slave (bytes) 3214system.membus.pkt_count_system.iocache.mem_side::total 237876 # Packet count per connected master and slave (bytes) 3215system.membus.pkt_count::total 4820602 # Packet count per connected master and slave (bytes) 3216system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155781 # Cumulative packet size per connected master and slave (bytes) 3217system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3218system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52868 # Cumulative packet size per connected master and slave (bytes) 3219system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124620204 # Cumulative packet size per connected master and slave (bytes) 3220system.membus.pkt_size_system.l2c.mem_side::total 124829057 # Cumulative packet size per connected master and slave (bytes) 3221system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253952 # Cumulative packet size per connected master and slave (bytes) 3222system.membus.pkt_size_system.iocache.mem_side::total 7253952 # Cumulative packet size per connected master and slave (bytes) 3223system.membus.pkt_size::total 132083009 # Cumulative packet size per connected master and slave (bytes) 3224system.membus.snoops 605187 # Total snoops (count) 3225system.membus.snoop_fanout::samples 2426230 # Request fanout histogram 3226system.membus.snoop_fanout::mean 0.013777 # Request fanout histogram 3227system.membus.snoop_fanout::stdev 0.116566 # Request fanout histogram 3228system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3229system.membus.snoop_fanout::0 2392803 98.62% 98.62% # Request fanout histogram 3230system.membus.snoop_fanout::1 33427 1.38% 100.00% # Request fanout histogram 3231system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3232system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3233system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3234system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3235system.membus.snoop_fanout::total 2426230 # Request fanout histogram 3236system.membus.reqLayer0.occupancy 101268497 # Layer occupancy (ticks) 3237system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3238system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3239system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3240system.membus.reqLayer2.occupancy 21861496 # Layer occupancy (ticks) 3241system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3242system.membus.reqLayer5.occupancy 8209418227 # Layer occupancy (ticks) 3243system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3244system.membus.respLayer2.occupancy 4835085635 # Layer occupancy (ticks) 3245system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3246system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) 3247system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3248system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3249system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3250system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3251system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3252system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3253system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3254system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3255system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3256system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3257system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3258system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3259system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3260system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3261system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3262system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3263system.realview.ethernet.txBytes 966 # Bytes Transmitted 3264system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3265system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3266system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3267system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3268system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3269system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3270system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3271system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3272system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3273system.realview.ethernet.totPackets 3 # Total Packets 3274system.realview.ethernet.totBytes 966 # Total Bytes 3275system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3276system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3277system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3278system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3279system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3280system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3281system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3282system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3283system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3284system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3285system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3286system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3287system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3288system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3289system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3290system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3291system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3292system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3293system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3294system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3295system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3296system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3297system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3298system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3299system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3300system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3301system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3302system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3303system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3304system.realview.ethernet.droppedPackets 0 # number of packets dropped 3305system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3306system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3307system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3308system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3309system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3310system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3311system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3312system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3313system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3314system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3315system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3316system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3317system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3318system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3319system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3320system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3321system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3322system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3323system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3324system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3325system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3326system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3327system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3328system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. 3329system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3330system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3331system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. 3332system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3333system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3334system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states 3335system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution 3336system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution 3337system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution 3338system.toL2Bus.trans_dist::WriteResp 38514 # Transaction distribution 3339system.toL2Bus.trans_dist::WritebackDirty 3675345 # Transaction distribution 3340system.toL2Bus.trans_dist::CleanEvict 2314292 # Transaction distribution 3341system.toL2Bus.trans_dist::UpgradeReq 683405 # Transaction distribution 3342system.toL2Bus.trans_dist::SCUpgradeReq 409707 # Transaction distribution 3343system.toL2Bus.trans_dist::UpgradeResp 1093112 # Transaction distribution 3344system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution 3345system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution 3346system.toL2Bus.trans_dist::ReadExReq 292338 # Transaction distribution 3347system.toL2Bus.trans_dist::ReadExResp 292338 # Transaction distribution 3348system.toL2Bus.trans_dist::ReadSharedReq 4001459 # Transaction distribution 3349system.toL2Bus.trans_dist::InvalidateReq 832376 # Transaction distribution 3350system.toL2Bus.trans_dist::InvalidateResp 802179 # Transaction distribution 3351system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8623692 # Packet count per connected master and slave (bytes) 3352system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7234411 # Packet count per connected master and slave (bytes) 3353system.toL2Bus.pkt_count::total 15858103 # Packet count per connected master and slave (bytes) 3354system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 210145531 # Cumulative packet size per connected master and slave (bytes) 3355system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 178915910 # Cumulative packet size per connected master and slave (bytes) 3356system.toL2Bus.pkt_size::total 389061441 # Cumulative packet size per connected master and slave (bytes) 3357system.toL2Bus.snoops 2781791 # Total snoops (count) 3358system.toL2Bus.snoop_fanout::samples 7676067 # Request fanout histogram 3359system.toL2Bus.snoop_fanout::mean 0.360389 # Request fanout histogram 3360system.toL2Bus.snoop_fanout::stdev 0.483218 # Request fanout histogram 3361system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3362system.toL2Bus.snoop_fanout::0 4921172 64.11% 64.11% # Request fanout histogram 3363system.toL2Bus.snoop_fanout::1 2743418 35.74% 99.85% # Request fanout histogram 3364system.toL2Bus.snoop_fanout::2 11477 0.15% 100.00% # Request fanout histogram 3365system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3366system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3367system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3368system.toL2Bus.snoop_fanout::total 7676067 # Request fanout histogram 3369system.toL2Bus.reqLayer0.occupancy 8520913919 # Layer occupancy (ticks) 3370system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3371system.toL2Bus.snoopLayer0.occupancy 2554437 # Layer occupancy (ticks) 3372system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3373system.toL2Bus.respLayer0.occupancy 3920667694 # Layer occupancy (ticks) 3374system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3375system.toL2Bus.respLayer1.occupancy 3580148330 # Layer occupancy (ticks) 3376system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3377 3378---------- End Simulation Statistics ----------