1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.374315 # Number of seconds simulated
4sim_ticks 47374315410500 # Number of ticks simulated
5final_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 573964 # Simulator instruction rate (inst/s)
8host_op_rate 675116 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 30496109280 # Simulator tick rate (ticks/s)
10host_mem_usage 762100 # Number of bytes of host memory used
11host_seconds 1553.45 # Real time elapsed on the host
12sim_insts 891626325 # Number of instructions simulated
13sim_ops 1048762579 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory
26system.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory
27system.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory
28system.physmem.bytes_read::total 56553028 # Number of bytes read from this memory
29system.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory
31system.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory
32system.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35system.physmem.bytes_written::total 74853032 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 924162 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51system.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory
52system.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.readReqs 924162 # Number of read requests accepted
85system.physmem.writeReqs 1171831 # Number of write requests accepted
86system.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue
87system.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue
88system.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM
89system.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue
90system.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM
91system.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side
92system.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side
93system.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue
94system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96system.physmem.perBankRdBursts::0 54791 # Per bank write bursts
97system.physmem.perBankRdBursts::1 60963 # Per bank write bursts
98system.physmem.perBankRdBursts::2 51680 # Per bank write bursts
99system.physmem.perBankRdBursts::3 61600 # Per bank write bursts
100system.physmem.perBankRdBursts::4 56399 # Per bank write bursts
101system.physmem.perBankRdBursts::5 67623 # Per bank write bursts
102system.physmem.perBankRdBursts::6 62592 # Per bank write bursts
103system.physmem.perBankRdBursts::7 58195 # Per bank write bursts
104system.physmem.perBankRdBursts::8 51047 # Per bank write bursts
105system.physmem.perBankRdBursts::9 95684 # Per bank write bursts
106system.physmem.perBankRdBursts::10 47816 # Per bank write bursts
107system.physmem.perBankRdBursts::11 53141 # Per bank write bursts
108system.physmem.perBankRdBursts::12 48535 # Per bank write bursts
109system.physmem.perBankRdBursts::13 54663 # Per bank write bursts
110system.physmem.perBankRdBursts::14 49130 # Per bank write bursts
111system.physmem.perBankRdBursts::15 49949 # Per bank write bursts
112system.physmem.perBankWrBursts::0 71660 # Per bank write bursts
113system.physmem.perBankWrBursts::1 78743 # Per bank write bursts
114system.physmem.perBankWrBursts::2 71851 # Per bank write bursts
115system.physmem.perBankWrBursts::3 78616 # Per bank write bursts
116system.physmem.perBankWrBursts::4 73485 # Per bank write bursts
117system.physmem.perBankWrBursts::5 81529 # Per bank write bursts
118system.physmem.perBankWrBursts::6 75635 # Per bank write bursts
119system.physmem.perBankWrBursts::7 74455 # Per bank write bursts
120system.physmem.perBankWrBursts::8 70456 # Per bank write bursts
121system.physmem.perBankWrBursts::9 72917 # Per bank write bursts
122system.physmem.perBankWrBursts::10 67611 # Per bank write bursts
123system.physmem.perBankWrBursts::11 70918 # Per bank write bursts
124system.physmem.perBankWrBursts::12 67621 # Per bank write bursts
125system.physmem.perBankWrBursts::13 71486 # Per bank write bursts
126system.physmem.perBankWrBursts::14 70570 # Per bank write bursts
127system.physmem.perBankWrBursts::15 72018 # Per bank write bursts
128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129system.physmem.numWrRetry 85 # Number of times write queue was full causing retry
130system.physmem.totGap 47374312061000 # Total gap between requests
131system.physmem.readPktSize::0 0 # Read request sizes (log2)
132system.physmem.readPktSize::1 0 # Read request sizes (log2)
133system.physmem.readPktSize::2 43195 # Read request sizes (log2)
134system.physmem.readPktSize::3 25 # Read request sizes (log2)
135system.physmem.readPktSize::4 5 # Read request sizes (log2)
136system.physmem.readPktSize::5 0 # Read request sizes (log2)
137system.physmem.readPktSize::6 880937 # Read request sizes (log2)
138system.physmem.writePktSize::0 0 # Write request sizes (log2)
139system.physmem.writePktSize::1 0 # Write request sizes (log2)
140system.physmem.writePktSize::2 2 # Write request sizes (log2)
141system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142system.physmem.writePktSize::4 0 # Write request sizes (log2)
143system.physmem.writePktSize::5 0 # Write request sizes (log2)
144system.physmem.writePktSize::6 1169257 # Write request sizes (log2)
145system.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
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184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see
241system.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation
255system.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes
263system.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
305system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
306system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
307system.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads
308system.physmem.totQLat 30413749694 # Total ticks spent queuing
309system.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM
310system.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers
311system.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst
312system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
313system.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst
314system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
315system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
316system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
317system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
318system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
319system.physmem.busUtil 0.02 # Data bus utilization in percentage
320system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
321system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
322system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
323system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
324system.physmem.readRowHits 683627 # Number of row buffer hits during reads
325system.physmem.writeRowHits 482581 # Number of row buffer hits during writes
326system.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads
327system.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes
328system.physmem.avgGap 22602323.61 # Average gap between requests
329system.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined
330system.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ)
331system.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ)
332system.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ)
333system.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ)
334system.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ)
335system.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ)
336system.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ)
337system.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ)
338system.physmem_0.averagePower 668.688048 # Core power per rank (mW)
339system.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states
340system.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states
341system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
342system.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states
343system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
344system.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ)
345system.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ)
346system.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ)
347system.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ)
348system.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ)
349system.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ)
350system.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ)
351system.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ)
352system.physmem_1.averagePower 668.629051 # Core power per rank (mW)
353system.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states
354system.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states
355system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
356system.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states
357system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
358system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
359system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
360system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
361system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
362system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
363system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
364system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
365system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
366system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory

--- 10 unchanged lines hidden (view full) ---

377system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
378system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
379system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
380system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
381system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
382system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
383system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
384system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
385system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
386system.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
387system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
388system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
389system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
390system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
391system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
392system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
393system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
394system.cpu_clk_domain.clock 500 # Clock period in ticks
395system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

417system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
418system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
419system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
420system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
421system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
422system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
423system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
424system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
425system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
426system.cpu0.dtb.walker.walks 101108 # Table walker walks requested
427system.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors
428system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate
429system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate
430system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
431system.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency
454system.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution
455system.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution
456system.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution
457system.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution
458system.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution
460system.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated
461system.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated
462system.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated
463system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst
464system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
465system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst
466system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst
467system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
468system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst
469system.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst
470system.cpu0.dtb.inst_hits 0 # ITB inst hits
471system.cpu0.dtb.inst_misses 0 # ITB inst misses
472system.cpu0.dtb.read_hits 84046306 # DTB read hits
473system.cpu0.dtb.read_misses 73432 # DTB read misses
474system.cpu0.dtb.write_hits 77237834 # DTB write hits
475system.cpu0.dtb.write_misses 27676 # DTB write misses
476system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
477system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
478system.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
479system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
480system.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB
481system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
482system.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch
483system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
484system.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions
485system.cpu0.dtb.read_accesses 84119738 # DTB read accesses
486system.cpu0.dtb.write_accesses 77265510 # DTB write accesses
487system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
488system.cpu0.dtb.hits 161284140 # DTB hits
489system.cpu0.dtb.misses 101108 # DTB misses
490system.cpu0.dtb.accesses 161385248 # DTB accesses
491system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
492system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

513system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
514system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
515system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
516system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
517system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
518system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
519system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
520system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
521system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
522system.cpu0.itb.walker.walks 58460 # Table walker walks requested
523system.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors
524system.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate
525system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate
526system.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency
528system.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency
529system.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency
538system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency
539system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency
541system.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency
542system.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency
543system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
544system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
545system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
546system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
547system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
548system.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency
549system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution
550system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution
551system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution
552system.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated
553system.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated
554system.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated
555system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
556system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst
557system.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst
558system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
559system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst
560system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst
561system.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst
562system.cpu0.itb.inst_hits 449335815 # ITB inst hits
563system.cpu0.itb.inst_misses 58460 # ITB inst misses
564system.cpu0.itb.read_hits 0 # DTB read hits
565system.cpu0.itb.read_misses 0 # DTB read misses
566system.cpu0.itb.write_hits 0 # DTB write hits
567system.cpu0.itb.write_misses 0 # DTB write misses
568system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
569system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
570system.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
571system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
572system.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB
573system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
574system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
575system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
576system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
577system.cpu0.itb.read_accesses 0 # DTB read accesses
578system.cpu0.itb.write_accesses 0 # DTB write accesses
579system.cpu0.itb.inst_accesses 449394275 # ITB inst accesses
580system.cpu0.itb.hits 449335815 # DTB hits
581system.cpu0.itb.misses 58460 # DTB misses
582system.cpu0.itb.accesses 449394275 # DTB accesses
583system.cpu0.numPwrStateTransitions 8624 # Number of power state transitions
584system.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state
585system.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state
586system.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state
587system.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state
588system.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state
589system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state
590system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state
591system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state
592system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state
593system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state
594system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state
595system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state
596system.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state
597system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
598system.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state
599system.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state
600system.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states
601system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states
602system.cpu0.numCycles 94748630821 # number of cpu cycles simulated
603system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
604system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
605system.cpu0.kern.inst.arm 0 # number of arm instructions executed
606system.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed
607system.cpu0.committedInsts 449083110 # Number of instructions committed
608system.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed
609system.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses
610system.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses
611system.cpu0.num_func_calls 26866500 # number of times a function call or return occured
612system.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls
613system.cpu0.num_int_insts 485390643 # number of integer instructions
614system.cpu0.num_fp_insts 507449 # number of float instructions
615system.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read
616system.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written
617system.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read
618system.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written
619system.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read
620system.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written
621system.cpu0.num_mem_refs 161276211 # number of memory refs
622system.cpu0.num_load_insts 84042257 # Number of load instructions
623system.cpu0.num_store_insts 77233954 # Number of store instructions
624system.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles
625system.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles
626system.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles
627system.cpu0.idle_fraction 0.988242 # Percentage of idle cycles
628system.cpu0.Branches 100200450 # Number of branches fetched
629system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
630system.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction
631system.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction
632system.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction
633system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
634system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
635system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
636system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
637system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
638system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
639system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
640system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
641system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
642system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
643system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
644system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
645system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
646system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
647system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
648system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
649system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
650system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction
651system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
652system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction
653system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction
654system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
655system.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction
656system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction
657system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction
658system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction
659system.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction
660system.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction
661system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
662system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
663system.cpu0.op_class::total 528680248 # Class of executed instruction
664system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
665system.cpu0.dcache.tags.replacements 5566798 # number of replacements
666system.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use
667system.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks.
668system.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks.
669system.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks.
670system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit.
671system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor
672system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy
673system.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy
674system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
675system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
676system.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id
677system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id
678system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
679system.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses
680system.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses
681system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
682system.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits
683system.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits
684system.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits
685system.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits
686system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits
687system.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits
688system.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits
689system.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits
690system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # number of LoadLockedReq hits
691system.cpu0.dcache.LoadLockedReq_hits::total 1764306 # number of LoadLockedReq hits
692system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721538 # number of StoreCondReq hits
693system.cpu0.dcache.StoreCondReq_hits::total 1721538 # number of StoreCondReq hits
694system.cpu0.dcache.demand_hits::cpu0.data 151345791 # number of demand (read+write) hits
695system.cpu0.dcache.demand_hits::total 151345791 # number of demand (read+write) hits
696system.cpu0.dcache.overall_hits::cpu0.data 151545934 # number of overall hits
697system.cpu0.dcache.overall_hits::total 151545934 # number of overall hits
698system.cpu0.dcache.ReadReq_misses::cpu0.data 2974115 # number of ReadReq misses
699system.cpu0.dcache.ReadReq_misses::total 2974115 # number of ReadReq misses
700system.cpu0.dcache.WriteReq_misses::cpu0.data 1412109 # number of WriteReq misses
701system.cpu0.dcache.WriteReq_misses::total 1412109 # number of WriteReq misses
702system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649854 # number of SoftPFReq misses
703system.cpu0.dcache.SoftPFReq_misses::total 649854 # number of SoftPFReq misses
704system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801670 # number of WriteLineReq misses
705system.cpu0.dcache.WriteLineReq_misses::total 801670 # number of WriteLineReq misses
706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 161158 # number of LoadLockedReq misses
707system.cpu0.dcache.LoadLockedReq_misses::total 161158 # number of LoadLockedReq misses
708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202775 # number of StoreCondReq misses
709system.cpu0.dcache.StoreCondReq_misses::total 202775 # number of StoreCondReq misses
710system.cpu0.dcache.demand_misses::cpu0.data 5187894 # number of demand (read+write) misses
711system.cpu0.dcache.demand_misses::total 5187894 # number of demand (read+write) misses
712system.cpu0.dcache.overall_misses::cpu0.data 5837748 # number of overall misses
713system.cpu0.dcache.overall_misses::total 5837748 # number of overall misses
714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44497648000 # number of ReadReq miss cycles
715system.cpu0.dcache.ReadReq_miss_latency::total 44497648000 # number of ReadReq miss cycles
716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles
717system.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles
718system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles
719system.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles
720system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles
721system.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles
722system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles
723system.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles
724system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles
725system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles
726system.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles
727system.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles
728system.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles
729system.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles
730system.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses)
731system.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses)
732system.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses)
733system.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses)
734system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses)
735system.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses)
736system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses)
737system.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses)
738system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses)
739system.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses)
740system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses)
741system.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses)
742system.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses
743system.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses
744system.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses
745system.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses
746system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses
747system.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses
748system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses
749system.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses
750system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses
751system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses
752system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses
753system.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses
754system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses
755system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses
756system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses
757system.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses
758system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses
759system.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses
760system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses
761system.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses
762system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency
763system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency
764system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency
765system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency
766system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency
767system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency
768system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency
769system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency
770system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency
771system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency
772system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
773system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
774system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738 # average overall miss latency
775system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738 # average overall miss latency
776system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528 # average overall miss latency
777system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528 # average overall miss latency
778system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
779system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
780system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
781system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
782system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
783system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
784system.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks
785system.cpu0.dcache.writebacks::total 5566798 # number of writebacks
786system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits
787system.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits
788system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits
789system.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits
790system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # number of LoadLockedReq MSHR hits
791system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45711 # number of LoadLockedReq MSHR hits
792system.cpu0.dcache.demand_mshr_hits::cpu0.data 51151 # number of demand (read+write) MSHR hits
793system.cpu0.dcache.demand_mshr_hits::total 51151 # number of demand (read+write) MSHR hits
794system.cpu0.dcache.overall_mshr_hits::cpu0.data 51151 # number of overall MSHR hits
795system.cpu0.dcache.overall_mshr_hits::total 51151 # number of overall MSHR hits
796system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2944482 # number of ReadReq MSHR misses
797system.cpu0.dcache.ReadReq_mshr_misses::total 2944482 # number of ReadReq MSHR misses
798system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1390591 # number of WriteReq MSHR misses
799system.cpu0.dcache.WriteReq_mshr_misses::total 1390591 # number of WriteReq MSHR misses
800system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648168 # number of SoftPFReq MSHR misses
801system.cpu0.dcache.SoftPFReq_mshr_misses::total 648168 # number of SoftPFReq MSHR misses
802system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801670 # number of WriteLineReq MSHR misses
803system.cpu0.dcache.WriteLineReq_mshr_misses::total 801670 # number of WriteLineReq MSHR misses
804system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115447 # number of LoadLockedReq MSHR misses
805system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115447 # number of LoadLockedReq MSHR misses
806system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202775 # number of StoreCondReq MSHR misses
807system.cpu0.dcache.StoreCondReq_mshr_misses::total 202775 # number of StoreCondReq MSHR misses
808system.cpu0.dcache.demand_mshr_misses::cpu0.data 5136743 # number of demand (read+write) MSHR misses
809system.cpu0.dcache.demand_mshr_misses::total 5136743 # number of demand (read+write) MSHR misses
810system.cpu0.dcache.overall_mshr_misses::cpu0.data 5784911 # number of overall MSHR misses
811system.cpu0.dcache.overall_mshr_misses::total 5784911 # number of overall MSHR misses
812system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable
813system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21025 # number of ReadReq MSHR uncacheable
814system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable
815system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable
816system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses
817system.cpu0.dcache.overall_mshr_uncacheable_misses::total 43413 # number of overall MSHR uncacheable misses
818system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40085054500 # number of ReadReq MSHR miss cycles
819system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40085054500 # number of ReadReq MSHR miss cycles
820system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26946583500 # number of WriteReq MSHR miss cycles
821system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26946583500 # number of WriteReq MSHR miss cycles
822system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14957704500 # number of SoftPFReq MSHR miss cycles
823system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14957704500 # number of SoftPFReq MSHR miss cycles
824system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles
825system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles
826system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles
827system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles
828system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles
829system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles
830system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles
831system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles
832system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles
833system.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles
834system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles
835system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles
836system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles
837system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles
838system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles
839system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles
840system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses
841system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses
842system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses
843system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses
844system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses
845system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses
846system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses
847system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses
848system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses
849system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses
850system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses
851system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses
852system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses
853system.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses
854system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses
855system.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses
856system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency
857system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency
858system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency
859system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency
860system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency
861system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency
862system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency
863system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency
864system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency
865system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency
866system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency
867system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency
868system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
869system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
870system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency
871system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency
872system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency
873system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency
874system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency
875system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency
876system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency
877system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency
878system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
879system.cpu0.icache.tags.replacements 5174135 # number of replacements
880system.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use
881system.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks.
882system.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks.
883system.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks.
884system.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit.
885system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor
886system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy
887system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy
888system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
889system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
890system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
891system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id
892system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
893system.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses
894system.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses
895system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
896system.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits
897system.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits
898system.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits
899system.cpu0.icache.demand_hits::total 444161163 # number of demand (read+write) hits
900system.cpu0.icache.overall_hits::cpu0.inst 444161163 # number of overall hits
901system.cpu0.icache.overall_hits::total 444161163 # number of overall hits
902system.cpu0.icache.ReadReq_misses::cpu0.inst 5174652 # number of ReadReq misses
903system.cpu0.icache.ReadReq_misses::total 5174652 # number of ReadReq misses
904system.cpu0.icache.demand_misses::cpu0.inst 5174652 # number of demand (read+write) misses
905system.cpu0.icache.demand_misses::total 5174652 # number of demand (read+write) misses
906system.cpu0.icache.overall_misses::cpu0.inst 5174652 # number of overall misses
907system.cpu0.icache.overall_misses::total 5174652 # number of overall misses
908system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55704586500 # number of ReadReq miss cycles
909system.cpu0.icache.ReadReq_miss_latency::total 55704586500 # number of ReadReq miss cycles
910system.cpu0.icache.demand_miss_latency::cpu0.inst 55704586500 # number of demand (read+write) miss cycles
911system.cpu0.icache.demand_miss_latency::total 55704586500 # number of demand (read+write) miss cycles
912system.cpu0.icache.overall_miss_latency::cpu0.inst 55704586500 # number of overall miss cycles
913system.cpu0.icache.overall_miss_latency::total 55704586500 # number of overall miss cycles
914system.cpu0.icache.ReadReq_accesses::cpu0.inst 449335815 # number of ReadReq accesses(hits+misses)
915system.cpu0.icache.ReadReq_accesses::total 449335815 # number of ReadReq accesses(hits+misses)
916system.cpu0.icache.demand_accesses::cpu0.inst 449335815 # number of demand (read+write) accesses
917system.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses
918system.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses
919system.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses
920system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses
921system.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses
922system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # miss rate for demand accesses
923system.cpu0.icache.demand_miss_rate::total 0.011516 # miss rate for demand accesses
924system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011516 # miss rate for overall accesses
925system.cpu0.icache.overall_miss_rate::total 0.011516 # miss rate for overall accesses
926system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205 # average ReadReq miss latency
927system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205 # average ReadReq miss latency
928system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency
929system.cpu0.icache.demand_avg_miss_latency::total 10764.895205 # average overall miss latency
930system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency
931system.cpu0.icache.overall_avg_miss_latency::total 10764.895205 # average overall miss latency
932system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
933system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
934system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
935system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
936system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
937system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
938system.cpu0.icache.writebacks::writebacks 5174135 # number of writebacks
939system.cpu0.icache.writebacks::total 5174135 # number of writebacks
940system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5174652 # number of ReadReq MSHR misses
941system.cpu0.icache.ReadReq_mshr_misses::total 5174652 # number of ReadReq MSHR misses
942system.cpu0.icache.demand_mshr_misses::cpu0.inst 5174652 # number of demand (read+write) MSHR misses
943system.cpu0.icache.demand_mshr_misses::total 5174652 # number of demand (read+write) MSHR misses
944system.cpu0.icache.overall_mshr_misses::cpu0.inst 5174652 # number of overall MSHR misses
945system.cpu0.icache.overall_mshr_misses::total 5174652 # number of overall MSHR misses
946system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
947system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
948system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
949system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
950system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 53117260500 # number of ReadReq MSHR miss cycles
951system.cpu0.icache.ReadReq_mshr_miss_latency::total 53117260500 # number of ReadReq MSHR miss cycles
952system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 53117260500 # number of demand (read+write) MSHR miss cycles
953system.cpu0.icache.demand_mshr_miss_latency::total 53117260500 # number of demand (read+write) MSHR miss cycles
954system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 53117260500 # number of overall MSHR miss cycles
955system.cpu0.icache.overall_mshr_miss_latency::total 53117260500 # number of overall MSHR miss cycles
956system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles
957system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles
958system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles
959system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles
960system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for ReadReq accesses
961system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011516 # mshr miss rate for ReadReq accesses
962system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for demand accesses
963system.cpu0.icache.demand_mshr_miss_rate::total 0.011516 # mshr miss rate for demand accesses
964system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for overall accesses
965system.cpu0.icache.overall_mshr_miss_rate::total 0.011516 # mshr miss rate for overall accesses
966system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average ReadReq mshr miss latency
967system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205 # average ReadReq mshr miss latency
968system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency
969system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency
970system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency
971system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency
972system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency
973system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency
974system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency
975system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency
976system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
977system.cpu0.l2cache.prefetcher.num_hwpf_issued 7568346 # number of hwpf issued
978system.cpu0.l2cache.prefetcher.pfIdentified 7568354 # number of prefetch candidates identified
979system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
980system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
981system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
982system.cpu0.l2cache.prefetcher.pfSpanPage 981182 # number of prefetches not generated due to page crossing
983system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
984system.cpu0.l2cache.tags.replacements 2342884 # number of replacements
985system.cpu0.l2cache.tags.tagsinuse 15723.839714 # Cycle average of tags in use
986system.cpu0.l2cache.tags.total_refs 9135802 # Total number of references to valid blocks.
987system.cpu0.l2cache.tags.sampled_refs 2358598 # Sample count of references to valid blocks.
988system.cpu0.l2cache.tags.avg_refs 3.873404 # Average number of references to valid blocks.
989system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit.
990system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260 # Average occupied blocks per requestor
991system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.158261 # Average occupied blocks per requestor
992system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.135006 # Average occupied blocks per requestor
993system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 251.087187 # Average occupied blocks per requestor
994system.cpu0.l2cache.tags.occ_percent::writebacks 0.940397 # Average percentage of cache occupancy
995system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002329 # Average percentage of cache occupancy
996system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001656 # Average percentage of cache occupancy
997system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.015325 # Average percentage of cache occupancy
998system.cpu0.l2cache.tags.occ_percent::total 0.959707 # Average percentage of cache occupancy
999system.cpu0.l2cache.tags.occ_task_id_blocks::1022 345 # Occupied blocks per task id
1000system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
1001system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id
1002system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id
1003system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id
1004system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id
1005system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id
1006system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
1007system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id
1008system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id
1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
1010system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id
1011system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id
1012system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id
1013system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id
1014system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id
1015system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id
1016system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933655 # Percentage of cache occupancy per task id
1017system.cpu0.l2cache.tags.tag_accesses 370311903 # Number of tag accesses
1018system.cpu0.l2cache.tags.data_accesses 370311903 # Number of data accesses
1019system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1020system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 225709 # number of ReadReq hits
1021system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148168 # number of ReadReq hits
1022system.cpu0.l2cache.ReadReq_hits::total 373877 # number of ReadReq hits
1023system.cpu0.l2cache.WritebackDirty_hits::writebacks 3696575 # number of WritebackDirty hits
1024system.cpu0.l2cache.WritebackDirty_hits::total 3696575 # number of WritebackDirty hits
1025system.cpu0.l2cache.WritebackClean_hits::writebacks 7043197 # number of WritebackClean hits
1026system.cpu0.l2cache.WritebackClean_hits::total 7043197 # number of WritebackClean hits
1027system.cpu0.l2cache.ReadExReq_hits::cpu0.data 878685 # number of ReadExReq hits
1028system.cpu0.l2cache.ReadExReq_hits::total 878685 # number of ReadExReq hits
1029system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695575 # number of ReadCleanReq hits
1030system.cpu0.l2cache.ReadCleanReq_hits::total 4695575 # number of ReadCleanReq hits
1031system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2752703 # number of ReadSharedReq hits
1032system.cpu0.l2cache.ReadSharedReq_hits::total 2752703 # number of ReadSharedReq hits
1033system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216682 # number of InvalidateReq hits
1034system.cpu0.l2cache.InvalidateReq_hits::total 216682 # number of InvalidateReq hits
1035system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 225709 # number of demand (read+write) hits
1036system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148168 # number of demand (read+write) hits
1037system.cpu0.l2cache.demand_hits::cpu0.inst 4695575 # number of demand (read+write) hits
1038system.cpu0.l2cache.demand_hits::cpu0.data 3631388 # number of demand (read+write) hits
1039system.cpu0.l2cache.demand_hits::total 8700840 # number of demand (read+write) hits
1040system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 225709 # number of overall hits
1041system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148168 # number of overall hits
1042system.cpu0.l2cache.overall_hits::cpu0.inst 4695575 # number of overall hits
1043system.cpu0.l2cache.overall_hits::cpu0.data 3631388 # number of overall hits
1044system.cpu0.l2cache.overall_hits::total 8700840 # number of overall hits
1045system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 18676 # number of ReadReq misses
1046system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10607 # number of ReadReq misses
1047system.cpu0.l2cache.ReadReq_misses::total 29283 # number of ReadReq misses
1048system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 251664 # number of UpgradeReq misses
1049system.cpu0.l2cache.UpgradeReq_misses::total 251664 # number of UpgradeReq misses
1050system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202763 # number of SCUpgradeReq misses
1051system.cpu0.l2cache.SCUpgradeReq_misses::total 202763 # number of SCUpgradeReq misses
1052system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses
1053system.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses
1054system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278535 # number of ReadExReq misses
1055system.cpu0.l2cache.ReadExReq_misses::total 278535 # number of ReadExReq misses
1056system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 479077 # number of ReadCleanReq misses
1057system.cpu0.l2cache.ReadCleanReq_misses::total 479077 # number of ReadCleanReq misses
1058system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 955394 # number of ReadSharedReq misses
1059system.cpu0.l2cache.ReadSharedReq_misses::total 955394 # number of ReadSharedReq misses
1060system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582714 # number of InvalidateReq misses
1061system.cpu0.l2cache.InvalidateReq_misses::total 582714 # number of InvalidateReq misses
1062system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 18676 # number of demand (read+write) misses
1063system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10607 # number of demand (read+write) misses
1064system.cpu0.l2cache.demand_misses::cpu0.inst 479077 # number of demand (read+write) misses
1065system.cpu0.l2cache.demand_misses::cpu0.data 1233929 # number of demand (read+write) misses
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1103system.cpu0.l2cache.WritebackDirty_accesses::total 3696575 # number of WritebackDirty accesses(hits+misses)
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1105system.cpu0.l2cache.WritebackClean_accesses::total 7043197 # number of WritebackClean accesses(hits+misses)
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1134system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1135system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
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1142system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092581 # miss rate for ReadCleanReq accesses
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1144system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.257651 # miss rate for ReadSharedReq accesses
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1146system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728943 # miss rate for InvalidateReq accesses
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1154system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092581 # miss rate for overall accesses
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1158system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35066.465542 # average ReadReq miss latency
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1161system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3643.014098 # average UpgradeReq miss latency
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1163system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1587.747765 # average SCUpgradeReq miss latency
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1165system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190208.250000 # average SCUpgradeFailReq miss latency
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1167system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45331.606434 # average ReadExReq miss latency
1168system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35802.051653 # average ReadCleanReq miss latency
1169system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35802.051653 # average ReadCleanReq miss latency
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1171system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34667.740744 # average ReadSharedReq miss latency
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1173system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 685.155153 # average InvalidateReq miss latency
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1175system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35066.465542 # average overall miss latency
1176system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35802.051653 # average overall miss latency
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1180system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35066.465542 # average overall miss latency
1181system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35802.051653 # average overall miss latency
1182system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37074.896933 # average overall miss latency
1183system.cpu0.l2cache.overall_avg_miss_latency::total 36639.393349 # average overall miss latency
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1185system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1186system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1187system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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1189system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1190system.cpu0.l2cache.unused_prefetches 41508 # number of HardPF blocks evicted w/o reference
1191system.cpu0.l2cache.writebacks::writebacks 1560695 # number of writebacks
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1193system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5412 # number of ReadExReq MSHR hits
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1195system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 417 # number of ReadSharedReq MSHR hits
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1197system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5829 # number of demand (read+write) MSHR hits
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1199system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5829 # number of overall MSHR hits
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1232system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable
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1237system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses
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1255system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27353907000 # number of ReadSharedReq MSHR miss cycles
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1257system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18732640000 # number of InvalidateReq MSHR miss cycles
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1273system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3820807000 # number of overall MSHR uncacheable cycles
1274system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7316839500 # number of overall MSHR uncacheable cycles
1275system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for ReadReq accesses
1276system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for ReadReq accesses
1277system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.072634 # mshr miss rate for ReadReq accesses
1278system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1279system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1280system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1281system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1282system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1283system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1284system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1285system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1286system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses
1287system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses
1288system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses
1289system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses
1290system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses
1291system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses
1292system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses
1293system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses
1294system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses
1295system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses
1296system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses
1297system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses
1298system.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses
1299system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses
1300system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses
1301system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses
1302system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses
1303system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1304system.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses
1305system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency
1306system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency
1307system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency
1308system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency
1309system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency
1310system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency
1311system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency
1312system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency
1313system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency
1314system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency
1315system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency
1316system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency
1317system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency
1318system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency
1319system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency
1320system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency
1321system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency
1322system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency
1323system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency
1324system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency
1325system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency
1326system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency
1327system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency
1328system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency
1329system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency
1330system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency
1331system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency
1332system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency
1333system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency
1334system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency
1335system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency
1336system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency
1337system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency
1338system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency
1339system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency
1340system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency
1341system.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter.
1342system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1343system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1344system.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter.
1345system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1346system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1347system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1348system.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution
1349system.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution
1350system.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution
1351system.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution
1352system.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution
1353system.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution
1354system.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution
1355system.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution
1356system.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution
1357system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution
1358system.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution
1359system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
1360system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
1361system.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution
1362system.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution
1363system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution
1364system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution
1365system.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution
1366system.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution
1367system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes)
1368system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes)
1369system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes)
1370system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes)
1371system.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes)
1372system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes)
1373system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes)
1374system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes)
1375system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes)
1376system.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes)
1377system.cpu0.toL2Bus.snoops 5171785 # Total snoops (count)
1378system.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes)
1379system.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram
1380system.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram
1381system.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram
1382system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1383system.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram
1384system.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram
1385system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
1386system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1387system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1388system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1389system.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram
1390system.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks)
1391system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1392system.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks)
1393system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1394system.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks)
1395system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1396system.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks)
1397system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1398system.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks)
1399system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1400system.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks)
1401system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1402system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1403system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1404system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1405system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1406system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1407system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1408system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1409system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1410system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1424system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1425system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1426system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1427system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1428system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1429system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1430system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1431system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1432system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1433system.cpu1.dtb.walker.walks 113512 # Table walker walks requested
1434system.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors
1435system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate
1436system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate
1437system.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting
1438system.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency
1439system.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency
1440system.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency
1441system.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1442system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1443system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1444system.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency
1445system.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency
1446system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency
1447system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency
1448system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency
1449system.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency
1450system.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency
1451system.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency
1452system.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency
1453system.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency
1454system.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency
1455system.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency
1456system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency
1457system.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency
1458system.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency
1459system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1460system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
1461system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
1462system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1463system.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency
1464system.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution
1465system.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution
1466system.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution
1467system.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution
1468system.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution
1469system.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated
1470system.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated
1471system.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated
1472system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst
1473system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1474system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst
1475system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst
1476system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1477system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst
1478system.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst
1479system.cpu1.dtb.inst_hits 0 # ITB inst hits
1480system.cpu1.dtb.inst_misses 0 # ITB inst misses
1481system.cpu1.dtb.read_hits 83873503 # DTB read hits
1482system.cpu1.dtb.read_misses 85876 # DTB read misses
1483system.cpu1.dtb.write_hits 75393075 # DTB write hits
1484system.cpu1.dtb.write_misses 27636 # DTB write misses
1485system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1486system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1487system.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
1488system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
1489system.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB
1490system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1491system.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch
1492system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1493system.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions
1494system.cpu1.dtb.read_accesses 83959379 # DTB read accesses
1495system.cpu1.dtb.write_accesses 75420711 # DTB write accesses
1496system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1497system.cpu1.dtb.hits 159266578 # DTB hits
1498system.cpu1.dtb.misses 113512 # DTB misses
1499system.cpu1.dtb.accesses 159380090 # DTB accesses
1500system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1501system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1502system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1503system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1504system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1505system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1506system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1507system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1508system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1522system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1523system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1524system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1525system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1526system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1527system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1528system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1529system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1530system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1531system.cpu1.itb.walker.walks 59776 # Table walker walks requested
1532system.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors
1533system.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate
1534system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate
1535system.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency
1536system.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1537system.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency
1538system.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency
1539system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency
1540system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency
1541system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency
1542system.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency
1543system.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency
1544system.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency
1545system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency
1546system.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency
1547system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency
1548system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
1549system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1550system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1551system.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency
1552system.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution
1553system.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution
1554system.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution
1555system.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated
1556system.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated
1557system.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated
1558system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1559system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst
1560system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst
1561system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1562system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst
1563system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst
1564system.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst
1565system.cpu1.itb.inst_hits 442849873 # ITB inst hits
1566system.cpu1.itb.inst_misses 59776 # ITB inst misses
1567system.cpu1.itb.read_hits 0 # DTB read hits
1568system.cpu1.itb.read_misses 0 # DTB read misses
1569system.cpu1.itb.write_hits 0 # DTB write hits
1570system.cpu1.itb.write_misses 0 # DTB write misses
1571system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1572system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1573system.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID
1574system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
1575system.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB
1576system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1577system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1578system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1579system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1580system.cpu1.itb.read_accesses 0 # DTB read accesses
1581system.cpu1.itb.write_accesses 0 # DTB write accesses
1582system.cpu1.itb.inst_accesses 442909649 # ITB inst accesses
1583system.cpu1.itb.hits 442849873 # DTB hits
1584system.cpu1.itb.misses 59776 # DTB misses
1585system.cpu1.itb.accesses 442909649 # DTB accesses
1586system.cpu1.numPwrStateTransitions 28574 # Number of power state transitions
1587system.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state
1588system.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state
1589system.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state
1590system.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state
1591system.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state
1592system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state
1593system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state
1594system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state
1595system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state
1596system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state
1597system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state
1598system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1599system.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state
1600system.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state
1601system.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states
1602system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states
1603system.cpu1.numCycles 94748630821 # number of cpu cycles simulated
1604system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1605system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1606system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1607system.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed
1608system.cpu1.committedInsts 442543215 # Number of instructions committed
1609system.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed
1610system.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses
1611system.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses
1612system.cpu1.num_func_calls 26483096 # number of times a function call or return occured
1613system.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls
1614system.cpu1.num_int_insts 478315040 # number of integer instructions
1615system.cpu1.num_fp_insts 404780 # number of float instructions
1616system.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read
1617system.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written
1618system.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read
1619system.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written
1620system.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read
1621system.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written
1622system.cpu1.num_mem_refs 159256484 # number of memory refs
1623system.cpu1.num_load_insts 83870110 # Number of load instructions
1624system.cpu1.num_store_insts 75386374 # Number of store instructions
1625system.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles
1626system.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles
1627system.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles
1628system.cpu1.idle_fraction 0.988993 # Percentage of idle cycles
1629system.cpu1.Branches 98643380 # Number of branches fetched
1630system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
1631system.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction
1632system.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction
1633system.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction
1634system.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction
1635system.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction
1636system.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction
1637system.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction
1638system.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction
1639system.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction
1640system.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction
1641system.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction
1642system.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction
1643system.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction
1644system.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction
1645system.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction
1646system.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction
1647system.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction
1648system.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction
1649system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction
1650system.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction
1651system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction
1652system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction
1653system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction
1654system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction
1655system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction
1656system.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction
1657system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
1658system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
1659system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
1660system.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction
1661system.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction
1662system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1663system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1664system.cpu1.op_class::total 520684927 # Class of executed instruction
1665system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1666system.cpu1.dcache.tags.replacements 5203972 # number of replacements
1667system.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use
1668system.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks.
1669system.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks.
1670system.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks.
1671system.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit.
1672system.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor
1673system.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy
1674system.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy
1675system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1676system.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
1677system.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
1678system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
1679system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1680system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1681system.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses
1682system.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses
1683system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1684system.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits
1685system.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits
1686system.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits
1687system.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits
1688system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits
1689system.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits
1690system.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits
1691system.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits
1692system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits
1693system.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits
1694system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits
1695system.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits
1696system.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits
1697system.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits
1698system.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits
1699system.cpu1.dcache.overall_hits::total 149942310 # number of overall hits
1700system.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses
1701system.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses
1702system.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses
1703system.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses
1704system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses
1705system.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses
1706system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # number of WriteLineReq misses
1707system.cpu1.dcache.WriteLineReq_misses::total 446111 # number of WriteLineReq misses
1708system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170906 # number of LoadLockedReq misses
1709system.cpu1.dcache.LoadLockedReq_misses::total 170906 # number of LoadLockedReq misses
1710system.cpu1.dcache.StoreCondReq_misses::cpu1.data 205163 # number of StoreCondReq misses
1711system.cpu1.dcache.StoreCondReq_misses::total 205163 # number of StoreCondReq misses
1712system.cpu1.dcache.demand_misses::cpu1.data 4762027 # number of demand (read+write) misses
1713system.cpu1.dcache.demand_misses::total 4762027 # number of demand (read+write) misses
1714system.cpu1.dcache.overall_misses::cpu1.data 5392442 # number of overall misses
1715system.cpu1.dcache.overall_misses::total 5392442 # number of overall misses
1716system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43487315000 # number of ReadReq miss cycles
1717system.cpu1.dcache.ReadReq_miss_latency::total 43487315000 # number of ReadReq miss cycles
1718system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24009342500 # number of WriteReq miss cycles
1719system.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles
1720system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles
1721system.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles
1722system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles
1723system.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles
1724system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles
1725system.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles
1726system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles
1727system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles
1728system.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles
1729system.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles
1730system.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles
1731system.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles
1732system.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses)
1733system.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses)
1734system.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses)
1735system.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses)
1736system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses)
1737system.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses)
1738system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses)
1739system.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses)
1740system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses)
1741system.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses)
1742system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses)
1743system.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses)
1744system.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses
1745system.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses
1746system.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses
1747system.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses
1748system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses
1749system.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses
1750system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses
1751system.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses
1752system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses
1753system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses
1754system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses
1755system.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses
1756system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses
1757system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses
1758system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses
1759system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses
1760system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses
1761system.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses
1762system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses
1763system.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses
1764system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency
1765system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency
1766system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency
1767system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency
1768system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency
1769system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency
1770system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency
1771system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency
1772system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency
1773system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency
1774system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1775system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1776system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency
1777system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency
1778system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency
1779system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency
1780system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1781system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1782system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1783system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1784system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1785system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1786system.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks
1787system.cpu1.dcache.writebacks::total 5203972 # number of writebacks
1788system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits
1789system.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits
1790system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits
1791system.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits
1792system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits
1793system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits
1794system.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits
1795system.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits
1796system.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits
1797system.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits
1798system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses
1799system.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses
1800system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses
1801system.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses
1802system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses
1803system.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses
1804system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses
1805system.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses
1806system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses
1807system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses
1808system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses
1809system.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses
1810system.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses
1811system.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses
1812system.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses
1813system.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses
1814system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable
1815system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable
1816system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable
1817system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable
1818system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses
1819system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses
1820system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles
1821system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles
1822system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles
1823system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles
1824system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles
1825system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles
1826system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles
1827system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles
1828system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles
1829system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles
1830system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles
1831system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles
1832system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles
1833system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles
1834system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles
1835system.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles
1836system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles
1837system.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles
1838system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles
1839system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles
1840system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles
1841system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles
1842system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses
1843system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses
1844system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses
1845system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses
1846system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses
1847system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses
1848system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses
1849system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses
1850system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses
1851system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses
1852system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses
1853system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses
1854system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses
1855system.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses
1856system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses
1857system.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses
1858system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency
1859system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency
1860system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency
1861system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency
1862system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency
1863system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency
1864system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency
1865system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency
1866system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency
1867system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency
1868system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency
1869system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency
1870system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1871system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1872system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency
1873system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency
1874system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency
1875system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency
1876system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency
1877system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency
1878system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency
1879system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency
1880system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1881system.cpu1.icache.tags.replacements 4895837 # number of replacements
1882system.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use
1883system.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks.
1884system.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks.
1885system.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks.
1886system.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit.
1887system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor
1888system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy
1889system.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy
1890system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1891system.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
1892system.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
1893system.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
1894system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
1895system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1896system.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses
1897system.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses
1898system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1899system.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits
1900system.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits
1901system.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits
1902system.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits
1903system.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits
1904system.cpu1.icache.overall_hits::total 437953524 # number of overall hits
1905system.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # number of ReadReq misses
1906system.cpu1.icache.ReadReq_misses::total 4896349 # number of ReadReq misses
1907system.cpu1.icache.demand_misses::cpu1.inst 4896349 # number of demand (read+write) misses
1908system.cpu1.icache.demand_misses::total 4896349 # number of demand (read+write) misses
1909system.cpu1.icache.overall_misses::cpu1.inst 4896349 # number of overall misses
1910system.cpu1.icache.overall_misses::total 4896349 # number of overall misses
1911system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51444170000 # number of ReadReq miss cycles
1912system.cpu1.icache.ReadReq_miss_latency::total 51444170000 # number of ReadReq miss cycles
1913system.cpu1.icache.demand_miss_latency::cpu1.inst 51444170000 # number of demand (read+write) miss cycles
1914system.cpu1.icache.demand_miss_latency::total 51444170000 # number of demand (read+write) miss cycles
1915system.cpu1.icache.overall_miss_latency::cpu1.inst 51444170000 # number of overall miss cycles
1916system.cpu1.icache.overall_miss_latency::total 51444170000 # number of overall miss cycles
1917system.cpu1.icache.ReadReq_accesses::cpu1.inst 442849873 # number of ReadReq accesses(hits+misses)
1918system.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses)
1919system.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses
1920system.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses
1921system.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses
1922system.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses
1923system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses
1924system.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses
1925system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses
1926system.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses
1927system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses
1928system.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses
1929system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency
1930system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency
1931system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency
1932system.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency
1933system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency
1934system.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency
1935system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1936system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1937system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1938system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1939system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1940system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1941system.cpu1.icache.writebacks::writebacks 4895837 # number of writebacks
1942system.cpu1.icache.writebacks::total 4895837 # number of writebacks
1943system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4896349 # number of ReadReq MSHR misses
1944system.cpu1.icache.ReadReq_mshr_misses::total 4896349 # number of ReadReq MSHR misses
1945system.cpu1.icache.demand_mshr_misses::cpu1.inst 4896349 # number of demand (read+write) MSHR misses
1946system.cpu1.icache.demand_mshr_misses::total 4896349 # number of demand (read+write) MSHR misses
1947system.cpu1.icache.overall_mshr_misses::cpu1.inst 4896349 # number of overall MSHR misses
1948system.cpu1.icache.overall_mshr_misses::total 4896349 # number of overall MSHR misses
1949system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
1950system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
1951system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
1952system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
1953system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48995995500 # number of ReadReq MSHR miss cycles
1954system.cpu1.icache.ReadReq_mshr_miss_latency::total 48995995500 # number of ReadReq MSHR miss cycles
1955system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48995995500 # number of demand (read+write) MSHR miss cycles
1956system.cpu1.icache.demand_mshr_miss_latency::total 48995995500 # number of demand (read+write) MSHR miss cycles
1957system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48995995500 # number of overall MSHR miss cycles
1958system.cpu1.icache.overall_mshr_miss_latency::total 48995995500 # number of overall MSHR miss cycles
1959system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10402000 # number of ReadReq MSHR uncacheable cycles
1960system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10402000 # number of ReadReq MSHR uncacheable cycles
1961system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10402000 # number of overall MSHR uncacheable cycles
1962system.cpu1.icache.overall_mshr_uncacheable_latency::total 10402000 # number of overall MSHR uncacheable cycles
1963system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for ReadReq accesses
1964system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011056 # mshr miss rate for ReadReq accesses
1965system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for demand accesses
1966system.cpu1.icache.demand_mshr_miss_rate::total 0.011056 # mshr miss rate for demand accesses
1967system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for overall accesses
1968system.cpu1.icache.overall_mshr_miss_rate::total 0.011056 # mshr miss rate for overall accesses
1969system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average ReadReq mshr miss latency
1970system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722 # average ReadReq mshr miss latency
1971system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency
1972system.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency
1973system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency
1974system.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency
1975system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average ReadReq mshr uncacheable latency
1976system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364 # average ReadReq mshr uncacheable latency
1977system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average overall mshr uncacheable latency
1978system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364 # average overall mshr uncacheable latency
1979system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1980system.cpu1.l2cache.prefetcher.num_hwpf_issued 7252070 # number of hwpf issued
1981system.cpu1.l2cache.prefetcher.pfIdentified 7252079 # number of prefetch candidates identified
1982system.cpu1.l2cache.prefetcher.pfBufferHit 8 # number of redundant prefetches already in prefetch queue
1983system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1984system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1985system.cpu1.l2cache.prefetcher.pfSpanPage 909185 # number of prefetches not generated due to page crossing
1986system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
1987system.cpu1.l2cache.tags.replacements 1859788 # number of replacements
1988system.cpu1.l2cache.tags.tagsinuse 13078.836793 # Cycle average of tags in use
1989system.cpu1.l2cache.tags.total_refs 8983696 # Total number of references to valid blocks.
1990system.cpu1.l2cache.tags.sampled_refs 1875537 # Sample count of references to valid blocks.
1991system.cpu1.l2cache.tags.avg_refs 4.789933 # Average number of references to valid blocks.
1992system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1993system.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935 # Average occupied blocks per requestor
1994system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.493162 # Average occupied blocks per requestor
1995system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.479573 # Average occupied blocks per requestor
1996system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 226.246124 # Average occupied blocks per requestor
1997system.cpu1.l2cache.tags.occ_percent::writebacks 0.782692 # Average percentage of cache occupancy
1998system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001068 # Average percentage of cache occupancy
1999system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000701 # Average percentage of cache occupancy
2000system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013809 # Average percentage of cache occupancy
2001system.cpu1.l2cache.tags.occ_percent::total 0.798269 # Average percentage of cache occupancy
2002system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id
2003system.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id
2004system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15409 # Occupied blocks per task id
2005system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
2006system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 107 # Occupied blocks per task id
2007system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 144 # Occupied blocks per task id
2008system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 23 # Occupied blocks per task id
2009system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
2010system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id
2011system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
2012system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
2013system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 868 # Occupied blocks per task id
2014system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6435 # Occupied blocks per task id
2015system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7258 # Occupied blocks per task id
2016system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id
2017system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id
2018system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id
2019system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id
2020system.cpu1.l2cache.tags.tag_accesses 348956442 # Number of tag accesses
2021system.cpu1.l2cache.tags.data_accesses 348956442 # Number of data accesses
2022system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2023system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 258658 # number of ReadReq hits
2024system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151547 # number of ReadReq hits
2025system.cpu1.l2cache.ReadReq_hits::total 410205 # number of ReadReq hits
2026system.cpu1.l2cache.WritebackDirty_hits::writebacks 3266667 # number of WritebackDirty hits
2027system.cpu1.l2cache.WritebackDirty_hits::total 3266667 # number of WritebackDirty hits
2028system.cpu1.l2cache.WritebackClean_hits::writebacks 6832390 # number of WritebackClean hits
2029system.cpu1.l2cache.WritebackClean_hits::total 6832390 # number of WritebackClean hits
2030system.cpu1.l2cache.ReadExReq_hits::cpu1.data 881671 # number of ReadExReq hits
2031system.cpu1.l2cache.ReadExReq_hits::total 881671 # number of ReadExReq hits
2032system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4452144 # number of ReadCleanReq hits
2033system.cpu1.l2cache.ReadCleanReq_hits::total 4452144 # number of ReadCleanReq hits
2034system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2841120 # number of ReadSharedReq hits
2035system.cpu1.l2cache.ReadSharedReq_hits::total 2841120 # number of ReadSharedReq hits
2036system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 192152 # number of InvalidateReq hits
2037system.cpu1.l2cache.InvalidateReq_hits::total 192152 # number of InvalidateReq hits
2038system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 258658 # number of demand (read+write) hits
2039system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151547 # number of demand (read+write) hits
2040system.cpu1.l2cache.demand_hits::cpu1.inst 4452144 # number of demand (read+write) hits
2041system.cpu1.l2cache.demand_hits::cpu1.data 3722791 # number of demand (read+write) hits
2042system.cpu1.l2cache.demand_hits::total 8585140 # number of demand (read+write) hits
2043system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 258658 # number of overall hits
2044system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151547 # number of overall hits
2045system.cpu1.l2cache.overall_hits::cpu1.inst 4452144 # number of overall hits
2046system.cpu1.l2cache.overall_hits::cpu1.data 3722791 # number of overall hits
2047system.cpu1.l2cache.overall_hits::total 8585140 # number of overall hits
2048system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18381 # number of ReadReq misses
2049system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9249 # number of ReadReq misses
2050system.cpu1.l2cache.ReadReq_misses::total 27630 # number of ReadReq misses
2051system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207506 # number of UpgradeReq misses
2052system.cpu1.l2cache.UpgradeReq_misses::total 207506 # number of UpgradeReq misses
2053system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 205160 # number of SCUpgradeReq misses
2054system.cpu1.l2cache.SCUpgradeReq_misses::total 205160 # number of SCUpgradeReq misses
2055system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
2056system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
2057system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235234 # number of ReadExReq misses
2058system.cpu1.l2cache.ReadExReq_misses::total 235234 # number of ReadExReq misses
2059system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 444205 # number of ReadCleanReq misses
2060system.cpu1.l2cache.ReadCleanReq_misses::total 444205 # number of ReadCleanReq misses
2061system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 895209 # number of ReadSharedReq misses
2062system.cpu1.l2cache.ReadSharedReq_misses::total 895209 # number of ReadSharedReq misses
2063system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 252043 # number of InvalidateReq misses
2064system.cpu1.l2cache.InvalidateReq_misses::total 252043 # number of InvalidateReq misses
2065system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18381 # number of demand (read+write) misses
2066system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9249 # number of demand (read+write) misses
2067system.cpu1.l2cache.demand_misses::cpu1.inst 444205 # number of demand (read+write) misses
2068system.cpu1.l2cache.demand_misses::cpu1.data 1130443 # number of demand (read+write) misses
2069system.cpu1.l2cache.demand_misses::total 1602278 # number of demand (read+write) misses
2070system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18381 # number of overall misses
2071system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9249 # number of overall misses
2072system.cpu1.l2cache.overall_misses::cpu1.inst 444205 # number of overall misses
2073system.cpu1.l2cache.overall_misses::cpu1.data 1130443 # number of overall misses
2074system.cpu1.l2cache.overall_misses::total 1602278 # number of overall misses
2075system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 560546000 # number of ReadReq miss cycles
2076system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 349476500 # number of ReadReq miss cycles
2077system.cpu1.l2cache.ReadReq_miss_latency::total 910022500 # number of ReadReq miss cycles
2078system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 940760500 # number of UpgradeReq miss cycles
2079system.cpu1.l2cache.UpgradeReq_miss_latency::total 940760500 # number of UpgradeReq miss cycles
2080system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 308144500 # number of SCUpgradeReq miss cycles
2081system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 308144500 # number of SCUpgradeReq miss cycles
2082system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2058000 # number of SCUpgradeFailReq miss cycles
2083system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2058000 # number of SCUpgradeFailReq miss cycles
2084system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9879714999 # number of ReadExReq miss cycles
2085system.cpu1.l2cache.ReadExReq_miss_latency::total 9879714999 # number of ReadExReq miss cycles
2086system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 14896666000 # number of ReadCleanReq miss cycles
2087system.cpu1.l2cache.ReadCleanReq_miss_latency::total 14896666000 # number of ReadCleanReq miss cycles
2088system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29710253000 # number of ReadSharedReq miss cycles
2089system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29710253000 # number of ReadSharedReq miss cycles
2090system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 322403500 # number of InvalidateReq miss cycles
2091system.cpu1.l2cache.InvalidateReq_miss_latency::total 322403500 # number of InvalidateReq miss cycles
2092system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 560546000 # number of demand (read+write) miss cycles
2093system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 349476500 # number of demand (read+write) miss cycles
2094system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14896666000 # number of demand (read+write) miss cycles
2095system.cpu1.l2cache.demand_miss_latency::cpu1.data 39589967999 # number of demand (read+write) miss cycles
2096system.cpu1.l2cache.demand_miss_latency::total 55396656499 # number of demand (read+write) miss cycles
2097system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 560546000 # number of overall miss cycles
2098system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 349476500 # number of overall miss cycles
2099system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14896666000 # number of overall miss cycles
2100system.cpu1.l2cache.overall_miss_latency::cpu1.data 39589967999 # number of overall miss cycles
2101system.cpu1.l2cache.overall_miss_latency::total 55396656499 # number of overall miss cycles
2102system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 277039 # number of ReadReq accesses(hits+misses)
2103system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 160796 # number of ReadReq accesses(hits+misses)
2104system.cpu1.l2cache.ReadReq_accesses::total 437835 # number of ReadReq accesses(hits+misses)
2105system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3266667 # number of WritebackDirty accesses(hits+misses)
2106system.cpu1.l2cache.WritebackDirty_accesses::total 3266667 # number of WritebackDirty accesses(hits+misses)
2107system.cpu1.l2cache.WritebackClean_accesses::writebacks 6832390 # number of WritebackClean accesses(hits+misses)
2108system.cpu1.l2cache.WritebackClean_accesses::total 6832390 # number of WritebackClean accesses(hits+misses)
2109system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207506 # number of UpgradeReq accesses(hits+misses)
2110system.cpu1.l2cache.UpgradeReq_accesses::total 207506 # number of UpgradeReq accesses(hits+misses)
2111system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 205160 # number of SCUpgradeReq accesses(hits+misses)
2112system.cpu1.l2cache.SCUpgradeReq_accesses::total 205160 # number of SCUpgradeReq accesses(hits+misses)
2113system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
2114system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
2115system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1116905 # number of ReadExReq accesses(hits+misses)
2116system.cpu1.l2cache.ReadExReq_accesses::total 1116905 # number of ReadExReq accesses(hits+misses)
2117system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4896349 # number of ReadCleanReq accesses(hits+misses)
2118system.cpu1.l2cache.ReadCleanReq_accesses::total 4896349 # number of ReadCleanReq accesses(hits+misses)
2119system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3736329 # number of ReadSharedReq accesses(hits+misses)
2120system.cpu1.l2cache.ReadSharedReq_accesses::total 3736329 # number of ReadSharedReq accesses(hits+misses)
2121system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 444195 # number of InvalidateReq accesses(hits+misses)
2122system.cpu1.l2cache.InvalidateReq_accesses::total 444195 # number of InvalidateReq accesses(hits+misses)
2123system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 277039 # number of demand (read+write) accesses
2124system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 160796 # number of demand (read+write) accesses
2125system.cpu1.l2cache.demand_accesses::cpu1.inst 4896349 # number of demand (read+write) accesses
2126system.cpu1.l2cache.demand_accesses::cpu1.data 4853234 # number of demand (read+write) accesses
2127system.cpu1.l2cache.demand_accesses::total 10187418 # number of demand (read+write) accesses
2128system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 277039 # number of overall (read+write) accesses
2129system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 160796 # number of overall (read+write) accesses
2130system.cpu1.l2cache.overall_accesses::cpu1.inst 4896349 # number of overall (read+write) accesses
2131system.cpu1.l2cache.overall_accesses::cpu1.data 4853234 # number of overall (read+write) accesses
2132system.cpu1.l2cache.overall_accesses::total 10187418 # number of overall (read+write) accesses
2133system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for ReadReq accesses
2134system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057520 # miss rate for ReadReq accesses
2135system.cpu1.l2cache.ReadReq_miss_rate::total 0.063106 # miss rate for ReadReq accesses
2136system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2137system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2138system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2139system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2140system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2141system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2142system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210612 # miss rate for ReadExReq accesses
2143system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210612 # miss rate for ReadExReq accesses
2144system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090722 # miss rate for ReadCleanReq accesses
2145system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090722 # miss rate for ReadCleanReq accesses
2146system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.239596 # miss rate for ReadSharedReq accesses
2147system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.239596 # miss rate for ReadSharedReq accesses
2148system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.567415 # miss rate for InvalidateReq accesses
2149system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.567415 # miss rate for InvalidateReq accesses
2150system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for demand accesses
2151system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057520 # miss rate for demand accesses
2152system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090722 # miss rate for demand accesses
2153system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.232926 # miss rate for demand accesses
2154system.cpu1.l2cache.demand_miss_rate::total 0.157280 # miss rate for demand accesses
2155system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.066348 # miss rate for overall accesses
2156system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057520 # miss rate for overall accesses
2157system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090722 # miss rate for overall accesses
2158system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.232926 # miss rate for overall accesses
2159system.cpu1.l2cache.overall_miss_rate::total 0.157280 # miss rate for overall accesses
2160system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average ReadReq miss latency
2161system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37785.328144 # average ReadReq miss latency
2162system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32936.029678 # average ReadReq miss latency
2163system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4533.654449 # average UpgradeReq miss latency
2164system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4533.654449 # average UpgradeReq miss latency
2165system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1501.971632 # average SCUpgradeReq miss latency
2166system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1501.971632 # average SCUpgradeReq miss latency
2167system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 686000 # average SCUpgradeFailReq miss latency
2168system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 686000 # average SCUpgradeFailReq miss latency
2169system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41999.519623 # average ReadExReq miss latency
2170system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41999.519623 # average ReadExReq miss latency
2171system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 33535.565786 # average ReadCleanReq miss latency
2172system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 33535.565786 # average ReadCleanReq miss latency
2173system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33188.063346 # average ReadSharedReq miss latency
2174system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33188.063346 # average ReadSharedReq miss latency
2175system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1279.160699 # average InvalidateReq miss latency
2176system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1279.160699 # average InvalidateReq miss latency
2177system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average overall miss latency
2178system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37785.328144 # average overall miss latency
2179system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 33535.565786 # average overall miss latency
2180system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35021.640188 # average overall miss latency
2181system.cpu1.l2cache.demand_avg_miss_latency::total 34573.686026 # average overall miss latency
2182system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30495.946902 # average overall miss latency
2183system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37785.328144 # average overall miss latency
2184system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 33535.565786 # average overall miss latency
2185system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35021.640188 # average overall miss latency
2186system.cpu1.l2cache.overall_avg_miss_latency::total 34573.686026 # average overall miss latency
2187system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2188system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2189system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2190system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2191system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2192system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2193system.cpu1.l2cache.unused_prefetches 39888 # number of HardPF blocks evicted w/o reference
2194system.cpu1.l2cache.writebacks::writebacks 1080406 # number of writebacks
2195system.cpu1.l2cache.writebacks::total 1080406 # number of writebacks
2196system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5355 # number of ReadExReq MSHR hits
2197system.cpu1.l2cache.ReadExReq_mshr_hits::total 5355 # number of ReadExReq MSHR hits
2198system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 314 # number of ReadSharedReq MSHR hits
2199system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 314 # number of ReadSharedReq MSHR hits
2200system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
2201system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
2202system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5669 # number of demand (read+write) MSHR hits
2203system.cpu1.l2cache.demand_mshr_hits::total 5669 # number of demand (read+write) MSHR hits
2204system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5669 # number of overall MSHR hits
2205system.cpu1.l2cache.overall_mshr_hits::total 5669 # number of overall MSHR hits
2206system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18381 # number of ReadReq MSHR misses
2207system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9249 # number of ReadReq MSHR misses
2208system.cpu1.l2cache.ReadReq_mshr_misses::total 27630 # number of ReadReq MSHR misses
2209system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 700284 # number of HardPFReq MSHR misses
2210system.cpu1.l2cache.HardPFReq_mshr_misses::total 700284 # number of HardPFReq MSHR misses
2211system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207506 # number of UpgradeReq MSHR misses
2212system.cpu1.l2cache.UpgradeReq_mshr_misses::total 207506 # number of UpgradeReq MSHR misses
2213system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 205160 # number of SCUpgradeReq MSHR misses
2214system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 205160 # number of SCUpgradeReq MSHR misses
2215system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2216system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2217system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229879 # number of ReadExReq MSHR misses
2218system.cpu1.l2cache.ReadExReq_mshr_misses::total 229879 # number of ReadExReq MSHR misses
2219system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 444205 # number of ReadCleanReq MSHR misses
2220system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 444205 # number of ReadCleanReq MSHR misses
2221system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 894895 # number of ReadSharedReq MSHR misses
2222system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 894895 # number of ReadSharedReq MSHR misses
2223system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 252041 # number of InvalidateReq MSHR misses
2224system.cpu1.l2cache.InvalidateReq_mshr_misses::total 252041 # number of InvalidateReq MSHR misses
2225system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18381 # number of demand (read+write) MSHR misses
2226system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9249 # number of demand (read+write) MSHR misses
2227system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 444205 # number of demand (read+write) MSHR misses
2228system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1124774 # number of demand (read+write) MSHR misses
2229system.cpu1.l2cache.demand_mshr_misses::total 1596609 # number of demand (read+write) MSHR misses
2230system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18381 # number of overall MSHR misses
2231system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9249 # number of overall MSHR misses
2232system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 444205 # number of overall MSHR misses
2233system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1124774 # number of overall MSHR misses
2234system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 700284 # number of overall MSHR misses
2235system.cpu1.l2cache.overall_mshr_misses::total 2296893 # number of overall MSHR misses
2236system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2237system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable
2238system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17687 # number of ReadReq MSHR uncacheable
2239system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable
2240system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable
2241system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2242system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses
2243system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 33812 # number of overall MSHR uncacheable misses
2244system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of ReadReq MSHR miss cycles
2245system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 293982500 # number of ReadReq MSHR miss cycles
2246system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 744242500 # number of ReadReq MSHR miss cycles
2247system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29274832519 # number of HardPFReq MSHR miss cycles
2248system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29274832519 # number of HardPFReq MSHR miss cycles
2249system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3856981999 # number of UpgradeReq MSHR miss cycles
2250system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3856981999 # number of UpgradeReq MSHR miss cycles
2251system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3119783996 # number of SCUpgradeReq MSHR miss cycles
2252system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3119783996 # number of SCUpgradeReq MSHR miss cycles
2253system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1764000 # number of SCUpgradeFailReq MSHR miss cycles
2254system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1764000 # number of SCUpgradeFailReq MSHR miss cycles
2255system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7964098999 # number of ReadExReq MSHR miss cycles
2256system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7964098999 # number of ReadExReq MSHR miss cycles
2257system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12231436000 # number of ReadCleanReq MSHR miss cycles
2258system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12231436000 # number of ReadCleanReq MSHR miss cycles
2259system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24307582500 # number of ReadSharedReq MSHR miss cycles
2260system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24307582500 # number of ReadSharedReq MSHR miss cycles
2261system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6863337500 # number of InvalidateReq MSHR miss cycles
2262system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6863337500 # number of InvalidateReq MSHR miss cycles
2263system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of demand (read+write) MSHR miss cycles
2264system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 293982500 # number of demand (read+write) MSHR miss cycles
2265system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12231436000 # number of demand (read+write) MSHR miss cycles
2266system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32271681499 # number of demand (read+write) MSHR miss cycles
2267system.cpu1.l2cache.demand_mshr_miss_latency::total 45247359999 # number of demand (read+write) MSHR miss cycles
2268system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 450260000 # number of overall MSHR miss cycles
2269system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 293982500 # number of overall MSHR miss cycles
2270system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12231436000 # number of overall MSHR miss cycles
2271system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32271681499 # number of overall MSHR miss cycles
2272system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29274832519 # number of overall MSHR miss cycles
2273system.cpu1.l2cache.overall_mshr_miss_latency::total 74522192518 # number of overall MSHR miss cycles
2274system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9577000 # number of ReadReq MSHR uncacheable cycles
2275system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2837977500 # number of ReadReq MSHR uncacheable cycles
2276system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2847554500 # number of ReadReq MSHR uncacheable cycles
2277system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9577000 # number of overall MSHR uncacheable cycles
2278system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2837977500 # number of overall MSHR uncacheable cycles
2279system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2847554500 # number of overall MSHR uncacheable cycles
2280system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for ReadReq accesses
2281system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for ReadReq accesses
2282system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063106 # mshr miss rate for ReadReq accesses
2283system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2284system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2285system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2286system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2287system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2288system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2289system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2290system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2291system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.205818 # mshr miss rate for ReadExReq accesses
2292system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.205818 # mshr miss rate for ReadExReq accesses
2293system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for ReadCleanReq accesses
2294system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090722 # mshr miss rate for ReadCleanReq accesses
2295system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.239512 # mshr miss rate for ReadSharedReq accesses
2296system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239512 # mshr miss rate for ReadSharedReq accesses
2297system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.567411 # mshr miss rate for InvalidateReq accesses
2298system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.567411 # mshr miss rate for InvalidateReq accesses
2299system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for demand accesses
2300system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for demand accesses
2301system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for demand accesses
2302system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for demand accesses
2303system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156724 # mshr miss rate for demand accesses
2304system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for overall accesses
2305system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for overall accesses
2306system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for overall accesses
2307system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for overall accesses
2308system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2309system.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses
2310system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency
2311system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency
2312system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency
2313system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency
2314system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency
2315system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency
2316system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency
2317system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency
2318system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency
2319system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency
2320system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency
2321system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency
2322system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency
2323system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency
2324system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency
2325system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency
2326system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency
2327system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency
2328system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency
2329system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency
2330system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency
2331system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency
2332system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency
2333system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency
2334system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency
2335system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency
2336system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency
2337system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency
2338system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency
2339system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency
2340system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency
2341system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency
2342system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency
2343system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency
2344system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency
2345system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency
2346system.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter.
2347system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2348system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2349system.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter.
2350system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2351system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2352system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2353system.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution
2354system.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution
2355system.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution
2356system.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution
2357system.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution
2358system.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution
2359system.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution
2360system.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution
2361system.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution
2362system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution
2363system.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution
2364system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution
2365system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
2366system.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution
2367system.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution
2368system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution
2369system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution
2370system.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution
2371system.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution
2372system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes)
2373system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes)
2374system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes)
2375system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes)
2376system.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes)
2377system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes)
2378system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes)
2379system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes)
2380system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes)
2381system.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes)
2382system.cpu1.toL2Bus.snoops 4601099 # Total snoops (count)
2383system.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes)
2384system.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram
2385system.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram
2386system.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram
2387system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2388system.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram
2389system.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram
2390system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2391system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2392system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2393system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2394system.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram
2395system.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks)
2396system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2397system.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks)
2398system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2399system.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks)
2400system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2401system.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks)
2402system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2403system.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks)
2404system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2405system.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks)
2406system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2407system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2408system.iobus.trans_dist::ReadReq 40399 # Transaction distribution
2409system.iobus.trans_dist::ReadResp 40399 # Transaction distribution
2410system.iobus.trans_dist::WriteReq 136980 # Transaction distribution
2411system.iobus.trans_dist::WriteResp 136980 # Transaction distribution
2412system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes)
2413system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2414system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2415system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2416system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2417system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2418system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2419system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2420system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2421system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2422system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2423system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
2424system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2425system.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes)
2426system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes)
2427system.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes)
2428system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2429system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2430system.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes)
2431system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes)
2432system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2433system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2434system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2435system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2436system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2437system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2438system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2439system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2440system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2441system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2442system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
2443system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2444system.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes)
2445system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes)
2446system.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes)
2447system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2448system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2449system.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes)
2450system.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks)
2451system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2452system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
2453system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2454system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks)
2455system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2456system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
2457system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2458system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
2459system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2460system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2461system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2462system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2463system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2464system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2465system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2466system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2467system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2468system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2469system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2470system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2471system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2472system.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks)
2473system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2474system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks)
2475system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2476system.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks)
2477system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2478system.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks)
2479system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2480system.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks)
2481system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2482system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2483system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2484system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2485system.iocache.tags.replacements 115853 # number of replacements
2486system.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use
2487system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2488system.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks.
2489system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2490system.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit.
2491system.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor
2492system.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor
2493system.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy
2494system.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy
2495system.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy
2496system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2497system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2498system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2499system.iocache.tags.tag_accesses 1043178 # Number of tag accesses
2500system.iocache.tags.data_accesses 1043178 # Number of data accesses
2501system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2502system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2503system.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses
2504system.iocache.ReadReq_misses::total 8922 # number of ReadReq misses
2505system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2506system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2507system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
2508system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2509system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2510system.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses
2511system.iocache.demand_misses::total 115909 # number of demand (read+write) misses
2512system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2513system.iocache.overall_misses::realview.ide 115869 # number of overall misses
2514system.iocache.overall_misses::total 115909 # number of overall misses
2515system.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles
2516system.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles
2517system.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles
2518system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2519system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2520system.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles
2521system.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles
2522system.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles
2523system.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles
2524system.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles
2525system.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles
2526system.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles
2527system.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles
2528system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2529system.iocache.ReadReq_accesses::realview.ide 8885 # number of ReadReq accesses(hits+misses)
2530system.iocache.ReadReq_accesses::total 8922 # number of ReadReq accesses(hits+misses)
2531system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2532system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2533system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
2534system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2535system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2536system.iocache.demand_accesses::realview.ide 115869 # number of demand (read+write) accesses
2537system.iocache.demand_accesses::total 115909 # number of demand (read+write) accesses
2538system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2539system.iocache.overall_accesses::realview.ide 115869 # number of overall (read+write) accesses
2540system.iocache.overall_accesses::total 115909 # number of overall (read+write) accesses
2541system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2542system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2543system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2544system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2545system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2546system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2547system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2548system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2549system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2550system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2551system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2552system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2553system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2554system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency
2555system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency
2556system.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency
2557system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2558system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2559system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency
2560system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency
2561system.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency
2562system.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency
2563system.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency
2564system.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency
2565system.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency
2566system.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency
2567system.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked
2568system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2569system.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked
2570system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2571system.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked
2572system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2573system.iocache.writebacks::writebacks 106953 # number of writebacks
2574system.iocache.writebacks::total 106953 # number of writebacks
2575system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2576system.iocache.ReadReq_mshr_misses::realview.ide 8885 # number of ReadReq MSHR misses
2577system.iocache.ReadReq_mshr_misses::total 8922 # number of ReadReq MSHR misses
2578system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2579system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2580system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
2581system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2582system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2583system.iocache.demand_mshr_misses::realview.ide 115869 # number of demand (read+write) MSHR misses
2584system.iocache.demand_mshr_misses::total 115909 # number of demand (read+write) MSHR misses
2585system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2586system.iocache.overall_mshr_misses::realview.ide 115869 # number of overall MSHR misses
2587system.iocache.overall_mshr_misses::total 115909 # number of overall MSHR misses
2588system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3428000 # number of ReadReq MSHR miss cycles
2589system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189343087 # number of ReadReq MSHR miss cycles
2590system.iocache.ReadReq_mshr_miss_latency::total 1192771087 # number of ReadReq MSHR miss cycles
2591system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2592system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2593system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7553188799 # number of WriteLineReq MSHR miss cycles
2594system.iocache.WriteLineReq_mshr_miss_latency::total 7553188799 # number of WriteLineReq MSHR miss cycles
2595system.iocache.demand_mshr_miss_latency::realview.ethernet 3647000 # number of demand (read+write) MSHR miss cycles
2596system.iocache.demand_mshr_miss_latency::realview.ide 8742531886 # number of demand (read+write) MSHR miss cycles
2597system.iocache.demand_mshr_miss_latency::total 8746178886 # number of demand (read+write) MSHR miss cycles
2598system.iocache.overall_mshr_miss_latency::realview.ethernet 3647000 # number of overall MSHR miss cycles
2599system.iocache.overall_mshr_miss_latency::realview.ide 8742531886 # number of overall MSHR miss cycles
2600system.iocache.overall_mshr_miss_latency::total 8746178886 # number of overall MSHR miss cycles
2601system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2602system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2603system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2604system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2605system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2606system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2607system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2608system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2609system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2610system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2611system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2612system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2613system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2614system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency
2615system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency
2616system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency
2617system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2618system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2619system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698 # average WriteLineReq mshr miss latency
2620system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698 # average WriteLineReq mshr miss latency
2621system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency
2622system.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency
2623system.iocache.demand_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency
2624system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency
2625system.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency
2626system.iocache.overall_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency
2627system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2628system.l2c.tags.replacements 1378015 # number of replacements
2629system.l2c.tags.tagsinuse 64998.786153 # Cycle average of tags in use
2630system.l2c.tags.total_refs 6107230 # Total number of references to valid blocks.
2631system.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks.
2632system.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks.
2633system.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit.
2634system.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor
2635system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor
2636system.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor
2637system.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor
2638system.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor
2639system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor
2640system.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor
2641system.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor
2642system.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor
2643system.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor
2644system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor
2645system.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy
2646system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy
2647system.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy
2648system.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy
2649system.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy
2650system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy
2651system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy
2652system.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy
2653system.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy
2654system.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy
2655system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy
2656system.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy
2657system.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id
2658system.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id
2659system.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id
2660system.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id
2661system.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id
2662system.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id
2663system.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id
2664system.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id
2665system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
2666system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
2667system.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id
2668system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
2669system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
2670system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id
2671system.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id
2672system.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id
2673system.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id
2674system.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id
2675system.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id
2676system.l2c.tags.tag_accesses 69629880 # Number of tag accesses
2677system.l2c.tags.data_accesses 69629880 # Number of data accesses
2678system.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
2679system.l2c.WritebackDirty_hits::writebacks 2641101 # number of WritebackDirty hits
2680system.l2c.WritebackDirty_hits::total 2641101 # number of WritebackDirty hits
2681system.l2c.UpgradeReq_hits::cpu0.data 213424 # number of UpgradeReq hits
2682system.l2c.UpgradeReq_hits::cpu1.data 155298 # number of UpgradeReq hits
2683system.l2c.UpgradeReq_hits::total 368722 # number of UpgradeReq hits
2684system.l2c.SCUpgradeReq_hits::cpu0.data 50511 # number of SCUpgradeReq hits
2685system.l2c.SCUpgradeReq_hits::cpu1.data 50527 # number of SCUpgradeReq hits
2686system.l2c.SCUpgradeReq_hits::total 101038 # number of SCUpgradeReq hits
2687system.l2c.ReadExReq_hits::cpu0.data 63650 # number of ReadExReq hits
2688system.l2c.ReadExReq_hits::cpu1.data 48993 # number of ReadExReq hits
2689system.l2c.ReadExReq_hits::total 112643 # number of ReadExReq hits
2690system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 10681 # number of ReadSharedReq hits
2691system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5935 # number of ReadSharedReq hits
2692system.l2c.ReadSharedReq_hits::cpu0.inst 422841 # number of ReadSharedReq hits
2693system.l2c.ReadSharedReq_hits::cpu0.data 567260 # number of ReadSharedReq hits
2694system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276728 # number of ReadSharedReq hits
2695system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 9775 # number of ReadSharedReq hits
2696system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4116 # number of ReadSharedReq hits
2697system.l2c.ReadSharedReq_hits::cpu1.inst 406188 # number of ReadSharedReq hits
2698system.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits
2699system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits
2700system.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits
2701system.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits
2702system.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits
2703system.l2c.InvalidateReq_hits::total 256882 # number of InvalidateReq hits
2704system.l2c.demand_hits::cpu0.dtb.walker 10681 # number of demand (read+write) hits
2705system.l2c.demand_hits::cpu0.itb.walker 5935 # number of demand (read+write) hits
2706system.l2c.demand_hits::cpu0.inst 422841 # number of demand (read+write) hits
2707system.l2c.demand_hits::cpu0.data 630910 # number of demand (read+write) hits
2708system.l2c.demand_hits::cpu0.l2cache.prefetcher 276728 # number of demand (read+write) hits
2709system.l2c.demand_hits::cpu1.dtb.walker 9775 # number of demand (read+write) hits
2710system.l2c.demand_hits::cpu1.itb.walker 4116 # number of demand (read+write) hits
2711system.l2c.demand_hits::cpu1.inst 406188 # number of demand (read+write) hits
2712system.l2c.demand_hits::cpu1.data 561391 # number of demand (read+write) hits
2713system.l2c.demand_hits::cpu1.l2cache.prefetcher 278781 # number of demand (read+write) hits
2714system.l2c.demand_hits::total 2607346 # number of demand (read+write) hits
2715system.l2c.overall_hits::cpu0.dtb.walker 10681 # number of overall hits
2716system.l2c.overall_hits::cpu0.itb.walker 5935 # number of overall hits
2717system.l2c.overall_hits::cpu0.inst 422841 # number of overall hits
2718system.l2c.overall_hits::cpu0.data 630910 # number of overall hits
2719system.l2c.overall_hits::cpu0.l2cache.prefetcher 276728 # number of overall hits
2720system.l2c.overall_hits::cpu1.dtb.walker 9775 # number of overall hits
2721system.l2c.overall_hits::cpu1.itb.walker 4116 # number of overall hits
2722system.l2c.overall_hits::cpu1.inst 406188 # number of overall hits
2723system.l2c.overall_hits::cpu1.data 561391 # number of overall hits
2724system.l2c.overall_hits::cpu1.l2cache.prefetcher 278781 # number of overall hits
2725system.l2c.overall_hits::total 2607346 # number of overall hits
2726system.l2c.UpgradeReq_misses::cpu0.data 24497 # number of UpgradeReq misses
2727system.l2c.UpgradeReq_misses::cpu1.data 25507 # number of UpgradeReq misses
2728system.l2c.UpgradeReq_misses::total 50004 # number of UpgradeReq misses
2729system.l2c.SCUpgradeReq_misses::cpu0.data 796 # number of SCUpgradeReq misses
2730system.l2c.SCUpgradeReq_misses::cpu1.data 825 # number of SCUpgradeReq misses
2731system.l2c.SCUpgradeReq_misses::total 1621 # number of SCUpgradeReq misses
2732system.l2c.ReadExReq_misses::cpu0.data 72583 # number of ReadExReq misses
2733system.l2c.ReadExReq_misses::cpu1.data 52296 # number of ReadExReq misses
2734system.l2c.ReadExReq_misses::total 124879 # number of ReadExReq misses
2735system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1676 # number of ReadSharedReq misses
2736system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1611 # number of ReadSharedReq misses
2737system.l2c.ReadSharedReq_misses::cpu0.inst 56236 # number of ReadSharedReq misses
2738system.l2c.ReadSharedReq_misses::cpu0.data 130395 # number of ReadSharedReq misses
2739system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 210895 # number of ReadSharedReq misses
2740system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1750 # number of ReadSharedReq misses
2741system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1829 # number of ReadSharedReq misses
2742system.l2c.ReadSharedReq_misses::cpu1.inst 38017 # number of ReadSharedReq misses
2743system.l2c.ReadSharedReq_misses::cpu1.data 107679 # number of ReadSharedReq misses
2744system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 200910 # number of ReadSharedReq misses
2745system.l2c.ReadSharedReq_misses::total 750998 # number of ReadSharedReq misses
2746system.l2c.InvalidateReq_misses::cpu0.data 430773 # number of InvalidateReq misses
2747system.l2c.InvalidateReq_misses::cpu1.data 119101 # number of InvalidateReq misses
2748system.l2c.InvalidateReq_misses::total 549874 # number of InvalidateReq misses
2749system.l2c.demand_misses::cpu0.dtb.walker 1676 # number of demand (read+write) misses
2750system.l2c.demand_misses::cpu0.itb.walker 1611 # number of demand (read+write) misses
2751system.l2c.demand_misses::cpu0.inst 56236 # number of demand (read+write) misses
2752system.l2c.demand_misses::cpu0.data 202978 # number of demand (read+write) misses
2753system.l2c.demand_misses::cpu0.l2cache.prefetcher 210895 # number of demand (read+write) misses
2754system.l2c.demand_misses::cpu1.dtb.walker 1750 # number of demand (read+write) misses
2755system.l2c.demand_misses::cpu1.itb.walker 1829 # number of demand (read+write) misses
2756system.l2c.demand_misses::cpu1.inst 38017 # number of demand (read+write) misses
2757system.l2c.demand_misses::cpu1.data 159975 # number of demand (read+write) misses
2758system.l2c.demand_misses::cpu1.l2cache.prefetcher 200910 # number of demand (read+write) misses
2759system.l2c.demand_misses::total 875877 # number of demand (read+write) misses
2760system.l2c.overall_misses::cpu0.dtb.walker 1676 # number of overall misses
2761system.l2c.overall_misses::cpu0.itb.walker 1611 # number of overall misses
2762system.l2c.overall_misses::cpu0.inst 56236 # number of overall misses
2763system.l2c.overall_misses::cpu0.data 202978 # number of overall misses
2764system.l2c.overall_misses::cpu0.l2cache.prefetcher 210895 # number of overall misses
2765system.l2c.overall_misses::cpu1.dtb.walker 1750 # number of overall misses
2766system.l2c.overall_misses::cpu1.itb.walker 1829 # number of overall misses
2767system.l2c.overall_misses::cpu1.inst 38017 # number of overall misses
2768system.l2c.overall_misses::cpu1.data 159975 # number of overall misses
2769system.l2c.overall_misses::cpu1.l2cache.prefetcher 200910 # number of overall misses
2770system.l2c.overall_misses::total 875877 # number of overall misses
2771system.l2c.UpgradeReq_miss_latency::cpu0.data 177641500 # number of UpgradeReq miss cycles
2772system.l2c.UpgradeReq_miss_latency::cpu1.data 151031500 # number of UpgradeReq miss cycles
2773system.l2c.UpgradeReq_miss_latency::total 328673000 # number of UpgradeReq miss cycles
2774system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8353500 # number of SCUpgradeReq miss cycles
2775system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8021500 # number of SCUpgradeReq miss cycles
2776system.l2c.SCUpgradeReq_miss_latency::total 16375000 # number of SCUpgradeReq miss cycles
2777system.l2c.ReadExReq_miss_latency::cpu0.data 6466021500 # number of ReadExReq miss cycles
2778system.l2c.ReadExReq_miss_latency::cpu1.data 4532203999 # number of ReadExReq miss cycles
2779system.l2c.ReadExReq_miss_latency::total 10998225499 # number of ReadExReq miss cycles
2780system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 151916500 # number of ReadSharedReq miss cycles
2781system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 149670500 # number of ReadSharedReq miss cycles
2782system.l2c.ReadSharedReq_miss_latency::cpu0.inst 4848581000 # number of ReadSharedReq miss cycles
2783system.l2c.ReadSharedReq_miss_latency::cpu0.data 11828995999 # number of ReadSharedReq miss cycles
2784system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of ReadSharedReq miss cycles
2785system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157377000 # number of ReadSharedReq miss cycles
2786system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 162435000 # number of ReadSharedReq miss cycles
2787system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3283945500 # number of ReadSharedReq miss cycles
2788system.l2c.ReadSharedReq_miss_latency::cpu1.data 9698473500 # number of ReadSharedReq miss cycles
2789system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of ReadSharedReq miss cycles
2790system.l2c.ReadSharedReq_miss_latency::total 80853175921 # number of ReadSharedReq miss cycles
2791system.l2c.InvalidateReq_miss_latency::cpu0.data 43381500 # number of InvalidateReq miss cycles
2792system.l2c.InvalidateReq_miss_latency::cpu1.data 30876500 # number of InvalidateReq miss cycles
2793system.l2c.InvalidateReq_miss_latency::total 74258000 # number of InvalidateReq miss cycles
2794system.l2c.demand_miss_latency::cpu0.dtb.walker 151916500 # number of demand (read+write) miss cycles
2795system.l2c.demand_miss_latency::cpu0.itb.walker 149670500 # number of demand (read+write) miss cycles
2796system.l2c.demand_miss_latency::cpu0.inst 4848581000 # number of demand (read+write) miss cycles
2797system.l2c.demand_miss_latency::cpu0.data 18295017499 # number of demand (read+write) miss cycles
2798system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of demand (read+write) miss cycles
2799system.l2c.demand_miss_latency::cpu1.dtb.walker 157377000 # number of demand (read+write) miss cycles
2800system.l2c.demand_miss_latency::cpu1.itb.walker 162435000 # number of demand (read+write) miss cycles
2801system.l2c.demand_miss_latency::cpu1.inst 3283945500 # number of demand (read+write) miss cycles
2802system.l2c.demand_miss_latency::cpu1.data 14230677499 # number of demand (read+write) miss cycles
2803system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of demand (read+write) miss cycles
2804system.l2c.demand_miss_latency::total 91851401420 # number of demand (read+write) miss cycles
2805system.l2c.overall_miss_latency::cpu0.dtb.walker 151916500 # number of overall miss cycles
2806system.l2c.overall_miss_latency::cpu0.itb.walker 149670500 # number of overall miss cycles
2807system.l2c.overall_miss_latency::cpu0.inst 4848581000 # number of overall miss cycles
2808system.l2c.overall_miss_latency::cpu0.data 18295017499 # number of overall miss cycles
2809system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 26350487356 # number of overall miss cycles
2810system.l2c.overall_miss_latency::cpu1.dtb.walker 157377000 # number of overall miss cycles
2811system.l2c.overall_miss_latency::cpu1.itb.walker 162435000 # number of overall miss cycles
2812system.l2c.overall_miss_latency::cpu1.inst 3283945500 # number of overall miss cycles
2813system.l2c.overall_miss_latency::cpu1.data 14230677499 # number of overall miss cycles
2814system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24221293566 # number of overall miss cycles
2815system.l2c.overall_miss_latency::total 91851401420 # number of overall miss cycles
2816system.l2c.WritebackDirty_accesses::writebacks 2641101 # number of WritebackDirty accesses(hits+misses)
2817system.l2c.WritebackDirty_accesses::total 2641101 # number of WritebackDirty accesses(hits+misses)
2818system.l2c.UpgradeReq_accesses::cpu0.data 237921 # number of UpgradeReq accesses(hits+misses)
2819system.l2c.UpgradeReq_accesses::cpu1.data 180805 # number of UpgradeReq accesses(hits+misses)
2820system.l2c.UpgradeReq_accesses::total 418726 # number of UpgradeReq accesses(hits+misses)
2821system.l2c.SCUpgradeReq_accesses::cpu0.data 51307 # number of SCUpgradeReq accesses(hits+misses)
2822system.l2c.SCUpgradeReq_accesses::cpu1.data 51352 # number of SCUpgradeReq accesses(hits+misses)
2823system.l2c.SCUpgradeReq_accesses::total 102659 # number of SCUpgradeReq accesses(hits+misses)
2824system.l2c.ReadExReq_accesses::cpu0.data 136233 # number of ReadExReq accesses(hits+misses)
2825system.l2c.ReadExReq_accesses::cpu1.data 101289 # number of ReadExReq accesses(hits+misses)
2826system.l2c.ReadExReq_accesses::total 237522 # number of ReadExReq accesses(hits+misses)
2827system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 12357 # number of ReadSharedReq accesses(hits+misses)
2828system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7546 # number of ReadSharedReq accesses(hits+misses)
2829system.l2c.ReadSharedReq_accesses::cpu0.inst 479077 # number of ReadSharedReq accesses(hits+misses)
2830system.l2c.ReadSharedReq_accesses::cpu0.data 697655 # number of ReadSharedReq accesses(hits+misses)
2831system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 487623 # number of ReadSharedReq accesses(hits+misses)
2832system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 11525 # number of ReadSharedReq accesses(hits+misses)
2833system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5945 # number of ReadSharedReq accesses(hits+misses)
2834system.l2c.ReadSharedReq_accesses::cpu1.inst 444205 # number of ReadSharedReq accesses(hits+misses)
2835system.l2c.ReadSharedReq_accesses::cpu1.data 620077 # number of ReadSharedReq accesses(hits+misses)
2836system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 479691 # number of ReadSharedReq accesses(hits+misses)
2837system.l2c.ReadSharedReq_accesses::total 3245701 # number of ReadSharedReq accesses(hits+misses)
2838system.l2c.InvalidateReq_accesses::cpu0.data 567330 # number of InvalidateReq accesses(hits+misses)
2839system.l2c.InvalidateReq_accesses::cpu1.data 239426 # number of InvalidateReq accesses(hits+misses)
2840system.l2c.InvalidateReq_accesses::total 806756 # number of InvalidateReq accesses(hits+misses)
2841system.l2c.demand_accesses::cpu0.dtb.walker 12357 # number of demand (read+write) accesses
2842system.l2c.demand_accesses::cpu0.itb.walker 7546 # number of demand (read+write) accesses
2843system.l2c.demand_accesses::cpu0.inst 479077 # number of demand (read+write) accesses
2844system.l2c.demand_accesses::cpu0.data 833888 # number of demand (read+write) accesses
2845system.l2c.demand_accesses::cpu0.l2cache.prefetcher 487623 # number of demand (read+write) accesses
2846system.l2c.demand_accesses::cpu1.dtb.walker 11525 # number of demand (read+write) accesses
2847system.l2c.demand_accesses::cpu1.itb.walker 5945 # number of demand (read+write) accesses
2848system.l2c.demand_accesses::cpu1.inst 444205 # number of demand (read+write) accesses
2849system.l2c.demand_accesses::cpu1.data 721366 # number of demand (read+write) accesses
2850system.l2c.demand_accesses::cpu1.l2cache.prefetcher 479691 # number of demand (read+write) accesses
2851system.l2c.demand_accesses::total 3483223 # number of demand (read+write) accesses
2852system.l2c.overall_accesses::cpu0.dtb.walker 12357 # number of overall (read+write) accesses
2853system.l2c.overall_accesses::cpu0.itb.walker 7546 # number of overall (read+write) accesses
2854system.l2c.overall_accesses::cpu0.inst 479077 # number of overall (read+write) accesses
2855system.l2c.overall_accesses::cpu0.data 833888 # number of overall (read+write) accesses
2856system.l2c.overall_accesses::cpu0.l2cache.prefetcher 487623 # number of overall (read+write) accesses
2857system.l2c.overall_accesses::cpu1.dtb.walker 11525 # number of overall (read+write) accesses
2858system.l2c.overall_accesses::cpu1.itb.walker 5945 # number of overall (read+write) accesses
2859system.l2c.overall_accesses::cpu1.inst 444205 # number of overall (read+write) accesses
2860system.l2c.overall_accesses::cpu1.data 721366 # number of overall (read+write) accesses
2861system.l2c.overall_accesses::cpu1.l2cache.prefetcher 479691 # number of overall (read+write) accesses
2862system.l2c.overall_accesses::total 3483223 # number of overall (read+write) accesses
2863system.l2c.UpgradeReq_miss_rate::cpu0.data 0.102963 # miss rate for UpgradeReq accesses
2864system.l2c.UpgradeReq_miss_rate::cpu1.data 0.141075 # miss rate for UpgradeReq accesses
2865system.l2c.UpgradeReq_miss_rate::total 0.119419 # miss rate for UpgradeReq accesses
2866system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.015514 # miss rate for SCUpgradeReq accesses
2867system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016066 # miss rate for SCUpgradeReq accesses
2868system.l2c.SCUpgradeReq_miss_rate::total 0.015790 # miss rate for SCUpgradeReq accesses
2869system.l2c.ReadExReq_miss_rate::cpu0.data 0.532786 # miss rate for ReadExReq accesses
2870system.l2c.ReadExReq_miss_rate::cpu1.data 0.516305 # miss rate for ReadExReq accesses
2871system.l2c.ReadExReq_miss_rate::total 0.525758 # miss rate for ReadExReq accesses
2872system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for ReadSharedReq accesses
2873system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.213491 # miss rate for ReadSharedReq accesses
2874system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117384 # miss rate for ReadSharedReq accesses
2875system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.186905 # miss rate for ReadSharedReq accesses
2876system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for ReadSharedReq accesses
2877system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for ReadSharedReq accesses
2878system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.307653 # miss rate for ReadSharedReq accesses
2879system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085584 # miss rate for ReadSharedReq accesses
2880system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173654 # miss rate for ReadSharedReq accesses
2881system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for ReadSharedReq accesses
2882system.l2c.ReadSharedReq_miss_rate::total 0.231382 # miss rate for ReadSharedReq accesses
2883system.l2c.InvalidateReq_miss_rate::cpu0.data 0.759299 # miss rate for InvalidateReq accesses
2884system.l2c.InvalidateReq_miss_rate::cpu1.data 0.497444 # miss rate for InvalidateReq accesses
2885system.l2c.InvalidateReq_miss_rate::total 0.681587 # miss rate for InvalidateReq accesses
2886system.l2c.demand_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for demand accesses
2887system.l2c.demand_miss_rate::cpu0.itb.walker 0.213491 # miss rate for demand accesses
2888system.l2c.demand_miss_rate::cpu0.inst 0.117384 # miss rate for demand accesses
2889system.l2c.demand_miss_rate::cpu0.data 0.243412 # miss rate for demand accesses
2890system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for demand accesses
2891system.l2c.demand_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for demand accesses
2892system.l2c.demand_miss_rate::cpu1.itb.walker 0.307653 # miss rate for demand accesses
2893system.l2c.demand_miss_rate::cpu1.inst 0.085584 # miss rate for demand accesses
2894system.l2c.demand_miss_rate::cpu1.data 0.221767 # miss rate for demand accesses
2895system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for demand accesses
2896system.l2c.demand_miss_rate::total 0.251456 # miss rate for demand accesses
2897system.l2c.overall_miss_rate::cpu0.dtb.walker 0.135632 # miss rate for overall accesses
2898system.l2c.overall_miss_rate::cpu0.itb.walker 0.213491 # miss rate for overall accesses
2899system.l2c.overall_miss_rate::cpu0.inst 0.117384 # miss rate for overall accesses
2900system.l2c.overall_miss_rate::cpu0.data 0.243412 # miss rate for overall accesses
2901system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.432496 # miss rate for overall accesses
2902system.l2c.overall_miss_rate::cpu1.dtb.walker 0.151844 # miss rate for overall accesses
2903system.l2c.overall_miss_rate::cpu1.itb.walker 0.307653 # miss rate for overall accesses
2904system.l2c.overall_miss_rate::cpu1.inst 0.085584 # miss rate for overall accesses
2905system.l2c.overall_miss_rate::cpu1.data 0.221767 # miss rate for overall accesses
2906system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.418832 # miss rate for overall accesses
2907system.l2c.overall_miss_rate::total 0.251456 # miss rate for overall accesses
2908system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7251.561416 # average UpgradeReq miss latency
2909system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5921.178500 # average UpgradeReq miss latency
2910system.l2c.UpgradeReq_avg_miss_latency::total 6572.934165 # average UpgradeReq miss latency
2911system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10494.346734 # average SCUpgradeReq miss latency
2912system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9723.030303 # average SCUpgradeReq miss latency
2913system.l2c.SCUpgradeReq_avg_miss_latency::total 10101.789019 # average SCUpgradeReq miss latency
2914system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89084.517036 # average ReadExReq miss latency
2915system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86664.448505 # average ReadExReq miss latency
2916system.l2c.ReadExReq_avg_miss_latency::total 88071.056775 # average ReadExReq miss latency
2917system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90642.303103 # average ReadSharedReq miss latency
2918system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92905.338299 # average ReadSharedReq miss latency
2919system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86218.454371 # average ReadSharedReq miss latency
2920system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90716.637900 # average ReadSharedReq miss latency
2921system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average ReadSharedReq miss latency
2922system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average ReadSharedReq miss latency
2923system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 88810.825588 # average ReadSharedReq miss latency
2924system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86380.974301 # average ReadSharedReq miss latency
2925system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90068.383807 # average ReadSharedReq miss latency
2926system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average ReadSharedReq miss latency
2927system.l2c.ReadSharedReq_avg_miss_latency::total 107660.973692 # average ReadSharedReq miss latency
2928system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 100.706172 # average InvalidateReq miss latency
2929system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 259.246354 # average InvalidateReq miss latency
2930system.l2c.InvalidateReq_avg_miss_latency::total 135.045483 # average InvalidateReq miss latency
2931system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90642.303103 # average overall miss latency
2932system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92905.338299 # average overall miss latency
2933system.l2c.demand_avg_miss_latency::cpu0.inst 86218.454371 # average overall miss latency
2934system.l2c.demand_avg_miss_latency::cpu0.data 90133.007020 # average overall miss latency
2935system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average overall miss latency
2936system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average overall miss latency
2937system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88810.825588 # average overall miss latency
2938system.l2c.demand_avg_miss_latency::cpu1.inst 86380.974301 # average overall miss latency
2939system.l2c.demand_avg_miss_latency::cpu1.data 88955.633687 # average overall miss latency
2940system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average overall miss latency
2941system.l2c.demand_avg_miss_latency::total 104867.922574 # average overall miss latency
2942system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90642.303103 # average overall miss latency
2943system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92905.338299 # average overall miss latency
2944system.l2c.overall_avg_miss_latency::cpu0.inst 86218.454371 # average overall miss latency
2945system.l2c.overall_avg_miss_latency::cpu0.data 90133.007020 # average overall miss latency
2946system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124946.003253 # average overall miss latency
2947system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89929.714286 # average overall miss latency
2948system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88810.825588 # average overall miss latency
2949system.l2c.overall_avg_miss_latency::cpu1.inst 86380.974301 # average overall miss latency
2950system.l2c.overall_avg_miss_latency::cpu1.data 88955.633687 # average overall miss latency
2951system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120557.929252 # average overall miss latency
2952system.l2c.overall_avg_miss_latency::total 104867.922574 # average overall miss latency
2953system.l2c.blocked_cycles::no_mshrs 424 # number of cycles access was blocked
2954system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2955system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
2956system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2957system.l2c.avg_blocked_cycles::no_mshrs 84.800000 # average number of cycles each access was blocked
2958system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2959system.l2c.writebacks::writebacks 1062304 # number of writebacks
2960system.l2c.writebacks::total 1062304 # number of writebacks
2961system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 133 # number of ReadSharedReq MSHR hits
2962system.l2c.ReadSharedReq_mshr_hits::cpu0.data 64 # number of ReadSharedReq MSHR hits
2963system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 89 # number of ReadSharedReq MSHR hits
2964system.l2c.ReadSharedReq_mshr_hits::cpu1.data 16 # number of ReadSharedReq MSHR hits
2965system.l2c.ReadSharedReq_mshr_hits::total 302 # number of ReadSharedReq MSHR hits
2966system.l2c.demand_mshr_hits::cpu0.inst 133 # number of demand (read+write) MSHR hits
2967system.l2c.demand_mshr_hits::cpu0.data 64 # number of demand (read+write) MSHR hits
2968system.l2c.demand_mshr_hits::cpu1.inst 89 # number of demand (read+write) MSHR hits
2969system.l2c.demand_mshr_hits::cpu1.data 16 # number of demand (read+write) MSHR hits
2970system.l2c.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits
2971system.l2c.overall_mshr_hits::cpu0.inst 133 # number of overall MSHR hits
2972system.l2c.overall_mshr_hits::cpu0.data 64 # number of overall MSHR hits
2973system.l2c.overall_mshr_hits::cpu1.inst 89 # number of overall MSHR hits
2974system.l2c.overall_mshr_hits::cpu1.data 16 # number of overall MSHR hits
2975system.l2c.overall_mshr_hits::total 302 # number of overall MSHR hits
2976system.l2c.CleanEvict_mshr_misses::writebacks 54771 # number of CleanEvict MSHR misses
2977system.l2c.CleanEvict_mshr_misses::total 54771 # number of CleanEvict MSHR misses
2978system.l2c.UpgradeReq_mshr_misses::cpu0.data 24497 # number of UpgradeReq MSHR misses
2979system.l2c.UpgradeReq_mshr_misses::cpu1.data 25507 # number of UpgradeReq MSHR misses
2980system.l2c.UpgradeReq_mshr_misses::total 50004 # number of UpgradeReq MSHR misses
2981system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 796 # number of SCUpgradeReq MSHR misses
2982system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 825 # number of SCUpgradeReq MSHR misses
2983system.l2c.SCUpgradeReq_mshr_misses::total 1621 # number of SCUpgradeReq MSHR misses
2984system.l2c.ReadExReq_mshr_misses::cpu0.data 72583 # number of ReadExReq MSHR misses
2985system.l2c.ReadExReq_mshr_misses::cpu1.data 52296 # number of ReadExReq MSHR misses
2986system.l2c.ReadExReq_mshr_misses::total 124879 # number of ReadExReq MSHR misses
2987system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1676 # number of ReadSharedReq MSHR misses
2988system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1611 # number of ReadSharedReq MSHR misses
2989system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 56103 # number of ReadSharedReq MSHR misses
2990system.l2c.ReadSharedReq_mshr_misses::cpu0.data 130331 # number of ReadSharedReq MSHR misses
2991system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 210895 # number of ReadSharedReq MSHR misses
2992system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1750 # number of ReadSharedReq MSHR misses
2993system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1829 # number of ReadSharedReq MSHR misses
2994system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 37928 # number of ReadSharedReq MSHR misses
2995system.l2c.ReadSharedReq_mshr_misses::cpu1.data 107663 # number of ReadSharedReq MSHR misses
2996system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 200910 # number of ReadSharedReq MSHR misses
2997system.l2c.ReadSharedReq_mshr_misses::total 750696 # number of ReadSharedReq MSHR misses
2998system.l2c.InvalidateReq_mshr_misses::cpu0.data 430773 # number of InvalidateReq MSHR misses
2999system.l2c.InvalidateReq_mshr_misses::cpu1.data 119101 # number of InvalidateReq MSHR misses
3000system.l2c.InvalidateReq_mshr_misses::total 549874 # number of InvalidateReq MSHR misses
3001system.l2c.demand_mshr_misses::cpu0.dtb.walker 1676 # number of demand (read+write) MSHR misses
3002system.l2c.demand_mshr_misses::cpu0.itb.walker 1611 # number of demand (read+write) MSHR misses
3003system.l2c.demand_mshr_misses::cpu0.inst 56103 # number of demand (read+write) MSHR misses
3004system.l2c.demand_mshr_misses::cpu0.data 202914 # number of demand (read+write) MSHR misses
3005system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 210895 # number of demand (read+write) MSHR misses
3006system.l2c.demand_mshr_misses::cpu1.dtb.walker 1750 # number of demand (read+write) MSHR misses
3007system.l2c.demand_mshr_misses::cpu1.itb.walker 1829 # number of demand (read+write) MSHR misses
3008system.l2c.demand_mshr_misses::cpu1.inst 37928 # number of demand (read+write) MSHR misses
3009system.l2c.demand_mshr_misses::cpu1.data 159959 # number of demand (read+write) MSHR misses
3010system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 200910 # number of demand (read+write) MSHR misses
3011system.l2c.demand_mshr_misses::total 875575 # number of demand (read+write) MSHR misses
3012system.l2c.overall_mshr_misses::cpu0.dtb.walker 1676 # number of overall MSHR misses
3013system.l2c.overall_mshr_misses::cpu0.itb.walker 1611 # number of overall MSHR misses
3014system.l2c.overall_mshr_misses::cpu0.inst 56103 # number of overall MSHR misses
3015system.l2c.overall_mshr_misses::cpu0.data 202914 # number of overall MSHR misses
3016system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 210895 # number of overall MSHR misses
3017system.l2c.overall_mshr_misses::cpu1.dtb.walker 1750 # number of overall MSHR misses
3018system.l2c.overall_mshr_misses::cpu1.itb.walker 1829 # number of overall MSHR misses
3019system.l2c.overall_mshr_misses::cpu1.inst 37928 # number of overall MSHR misses
3020system.l2c.overall_mshr_misses::cpu1.data 159959 # number of overall MSHR misses
3021system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 200910 # number of overall MSHR misses
3022system.l2c.overall_mshr_misses::total 875575 # number of overall MSHR misses
3023system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
3024system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable
3025system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
3026system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17575 # number of ReadReq MSHR uncacheable
3027system.l2c.ReadReq_mshr_uncacheable::total 81835 # number of ReadReq MSHR uncacheable
3028system.l2c.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable
3029system.l2c.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable
3030system.l2c.WriteReq_mshr_uncacheable::total 38513 # number of WriteReq MSHR uncacheable
3031system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
3032system.l2c.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses
3033system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
3034system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33700 # number of overall MSHR uncacheable misses
3035system.l2c.overall_mshr_uncacheable_misses::total 120348 # number of overall MSHR uncacheable misses
3036system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 503126000 # number of UpgradeReq MSHR miss cycles
3037system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 519991500 # number of UpgradeReq MSHR miss cycles
3038system.l2c.UpgradeReq_mshr_miss_latency::total 1023117500 # number of UpgradeReq MSHR miss cycles
3039system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 19775000 # number of SCUpgradeReq MSHR miss cycles
3040system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20085500 # number of SCUpgradeReq MSHR miss cycles
3041system.l2c.SCUpgradeReq_mshr_miss_latency::total 39860500 # number of SCUpgradeReq MSHR miss cycles
3042system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5740155074 # number of ReadExReq MSHR miss cycles
3043system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4009215058 # number of ReadExReq MSHR miss cycles
3044system.l2c.ReadExReq_mshr_miss_latency::total 9749370132 # number of ReadExReq MSHR miss cycles
3045system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 135154504 # number of ReadSharedReq MSHR miss cycles
3046system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 133557506 # number of ReadSharedReq MSHR miss cycles
3047system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4277568054 # number of ReadSharedReq MSHR miss cycles
3048system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10520997188 # number of ReadSharedReq MSHR miss cycles
3049system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 24241323314 # number of ReadSharedReq MSHR miss cycles
3050system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 139876501 # number of ReadSharedReq MSHR miss cycles
3051system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 144145000 # number of ReadSharedReq MSHR miss cycles
3052system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 2898586521 # number of ReadSharedReq MSHR miss cycles
3053system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8620097178 # number of ReadSharedReq MSHR miss cycles
3054system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 22212057363 # number of ReadSharedReq MSHR miss cycles
3055system.l2c.ReadSharedReq_mshr_miss_latency::total 73323363129 # number of ReadSharedReq MSHR miss cycles
3056system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8575090000 # number of InvalidateReq MSHR miss cycles
3057system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2366625500 # number of InvalidateReq MSHR miss cycles
3058system.l2c.InvalidateReq_mshr_miss_latency::total 10941715500 # number of InvalidateReq MSHR miss cycles
3059system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 135154504 # number of demand (read+write) MSHR miss cycles
3060system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133557506 # number of demand (read+write) MSHR miss cycles
3061system.l2c.demand_mshr_miss_latency::cpu0.inst 4277568054 # number of demand (read+write) MSHR miss cycles
3062system.l2c.demand_mshr_miss_latency::cpu0.data 16261152262 # number of demand (read+write) MSHR miss cycles
3063system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 24241323314 # number of demand (read+write) MSHR miss cycles
3064system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 139876501 # number of demand (read+write) MSHR miss cycles
3065system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 144145000 # number of demand (read+write) MSHR miss cycles
3066system.l2c.demand_mshr_miss_latency::cpu1.inst 2898586521 # number of demand (read+write) MSHR miss cycles
3067system.l2c.demand_mshr_miss_latency::cpu1.data 12629312236 # number of demand (read+write) MSHR miss cycles
3068system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 22212057363 # number of demand (read+write) MSHR miss cycles
3069system.l2c.demand_mshr_miss_latency::total 83072733261 # number of demand (read+write) MSHR miss cycles
3070system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 135154504 # number of overall MSHR miss cycles
3071system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133557506 # number of overall MSHR miss cycles
3072system.l2c.overall_mshr_miss_latency::cpu0.inst 4277568054 # number of overall MSHR miss cycles
3073system.l2c.overall_mshr_miss_latency::cpu0.data 16261152262 # number of overall MSHR miss cycles
3074system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 24241323314 # number of overall MSHR miss cycles
3075system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 139876501 # number of overall MSHR miss cycles
3076system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 144145000 # number of overall MSHR miss cycles
3077system.l2c.overall_mshr_miss_latency::cpu1.inst 2898586521 # number of overall MSHR miss cycles
3078system.l2c.overall_mshr_miss_latency::cpu1.data 12629312236 # number of overall MSHR miss cycles
3079system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 22212057363 # number of overall MSHR miss cycles
3080system.l2c.overall_mshr_miss_latency::total 83072733261 # number of overall MSHR miss cycles
3081system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles
3082system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3442200004 # number of ReadReq MSHR uncacheable cycles
3083system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7595500 # number of ReadReq MSHR uncacheable cycles
3084system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2521551501 # number of ReadReq MSHR uncacheable cycles
3085system.l2c.ReadReq_mshr_uncacheable_latency::total 8691129005 # number of ReadReq MSHR uncacheable cycles
3086system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles
3087system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3442200004 # number of overall MSHR uncacheable cycles
3088system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7595500 # number of overall MSHR uncacheable cycles
3089system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2521551501 # number of overall MSHR uncacheable cycles
3090system.l2c.overall_mshr_uncacheable_latency::total 8691129005 # number of overall MSHR uncacheable cycles
3091system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3092system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3093system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.102963 # mshr miss rate for UpgradeReq accesses
3094system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.141075 # mshr miss rate for UpgradeReq accesses
3095system.l2c.UpgradeReq_mshr_miss_rate::total 0.119419 # mshr miss rate for UpgradeReq accesses
3096system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.015514 # mshr miss rate for SCUpgradeReq accesses
3097system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016066 # mshr miss rate for SCUpgradeReq accesses
3098system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015790 # mshr miss rate for SCUpgradeReq accesses
3099system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.532786 # mshr miss rate for ReadExReq accesses
3100system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.516305 # mshr miss rate for ReadExReq accesses
3101system.l2c.ReadExReq_mshr_miss_rate::total 0.525758 # mshr miss rate for ReadExReq accesses
3102system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for ReadSharedReq accesses
3103system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for ReadSharedReq accesses
3104system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for ReadSharedReq accesses
3105system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186813 # mshr miss rate for ReadSharedReq accesses
3106system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for ReadSharedReq accesses
3107system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for ReadSharedReq accesses
3108system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for ReadSharedReq accesses
3109system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for ReadSharedReq accesses
3110system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173628 # mshr miss rate for ReadSharedReq accesses
3111system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for ReadSharedReq accesses
3112system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231289 # mshr miss rate for ReadSharedReq accesses
3113system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.759299 # mshr miss rate for InvalidateReq accesses
3114system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.497444 # mshr miss rate for InvalidateReq accesses
3115system.l2c.InvalidateReq_mshr_miss_rate::total 0.681587 # mshr miss rate for InvalidateReq accesses
3116system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for demand accesses
3117system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for demand accesses
3118system.l2c.demand_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for demand accesses
3119system.l2c.demand_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for demand accesses
3120system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for demand accesses
3121system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for demand accesses
3122system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for demand accesses
3123system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for demand accesses
3124system.l2c.demand_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for demand accesses
3125system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for demand accesses
3126system.l2c.demand_mshr_miss_rate::total 0.251369 # mshr miss rate for demand accesses
3127system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for overall accesses
3128system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for overall accesses
3129system.l2c.overall_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for overall accesses
3130system.l2c.overall_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for overall accesses
3131system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for overall accesses
3132system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for overall accesses
3133system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for overall accesses
3134system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for overall accesses
3135system.l2c.overall_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for overall accesses
3136system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for overall accesses
3137system.l2c.overall_mshr_miss_rate::total 0.251369 # mshr miss rate for overall accesses
3138system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20538.269992 # average UpgradeReq mshr miss latency
3139system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20386.227310 # average UpgradeReq mshr miss latency
3140system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20460.713143 # average UpgradeReq mshr miss latency
3141system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24842.964824 # average SCUpgradeReq mshr miss latency
3142system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24346.060606 # average SCUpgradeReq mshr miss latency
3143system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.067859 # average SCUpgradeReq mshr miss latency
3144system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79084.015183 # average ReadExReq mshr miss latency
3145system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097 # average ReadExReq mshr miss latency
3146system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332 # average ReadExReq mshr miss latency
3147system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average ReadSharedReq mshr miss latency
3148system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average ReadSharedReq mshr miss latency
3149system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average ReadSharedReq mshr miss latency
3150system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799 # average ReadSharedReq mshr miss latency
3151system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average ReadSharedReq mshr miss latency
3152system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average ReadSharedReq mshr miss latency
3153system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average ReadSharedReq mshr miss latency
3154system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average ReadSharedReq mshr miss latency
3155system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency
3156system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency
3157system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency
3158system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency
3159system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency
3160system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency
3161system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency
3162system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency
3163system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency
3164system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency
3165system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency
3166system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency
3167system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency
3168system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency
3169system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency
3170system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency
3171system.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency
3172system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency
3173system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency
3174system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency
3175system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency
3176system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency
3177system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency
3178system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency
3179system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency
3180system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency
3181system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency
3182system.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency
3183system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency
3184system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency
3185system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency
3186system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency
3187system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency
3188system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency
3189system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency
3190system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency
3191system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency
3192system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency
3193system.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter.
3194system.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3195system.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3196system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3197system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3198system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3199system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3200system.membus.trans_dist::ReadReq 81835 # Transaction distribution
3201system.membus.trans_dist::ReadResp 841453 # Transaction distribution
3202system.membus.trans_dist::WriteReq 38513 # Transaction distribution
3203system.membus.trans_dist::WriteResp 38513 # Transaction distribution
3204system.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution
3205system.membus.trans_dist::CleanEvict 224172 # Transaction distribution
3206system.membus.trans_dist::UpgradeReq 330190 # Transaction distribution
3207system.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution
3208system.membus.trans_dist::UpgradeResp 21 # Transaction distribution
3209system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
3210system.membus.trans_dist::ReadExReq 142313 # Transaction distribution
3211system.membus.trans_dist::ReadExResp 124217 # Transaction distribution
3212system.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution
3213system.membus.trans_dist::InvalidateReq 654423 # Transaction distribution
3214system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes)
3215system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3216system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes)
3217system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes)
3218system.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes)
3219system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes)
3220system.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes)
3221system.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes)
3222system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes)
3223system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3224system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes)
3225system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes)
3226system.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes)
3227system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes)
3228system.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes)
3229system.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes)
3230system.membus.snoops 603280 # Total snoops (count)
3231system.membus.snoopTraffic 185472 # Total snoop traffic (bytes)
3232system.membus.snoop_fanout::samples 2313692 # Request fanout histogram
3233system.membus.snoop_fanout::mean 0.013382 # Request fanout histogram
3234system.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram
3235system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3236system.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram
3237system.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram
3238system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3239system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3240system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3241system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3242system.membus.snoop_fanout::total 2313692 # Request fanout histogram
3243system.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks)
3244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3245system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3246system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3247system.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks)
3248system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3249system.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks)
3250system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3251system.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks)
3252system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3253system.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks)
3254system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3255system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3256system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3257system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3258system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3259system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3260system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3261system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3262system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3263system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3264system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3265system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3266system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3267system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3268system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3269system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3270system.realview.ethernet.txBytes 966 # Bytes Transmitted
3271system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3272system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3273system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3274system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3275system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3276system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3277system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

--- 26 unchanged lines hidden (view full) ---

3304system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3305system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3306system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3307system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3308system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3309system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3310system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3311system.realview.ethernet.droppedPackets 0 # number of packets dropped
3312system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3313system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3314system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3315system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3316system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3317system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3318system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3319system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3320system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3321system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3322system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3323system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3324system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3325system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3326system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3327system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3328system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3329system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3330system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3331system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3332system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3333system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3334system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3335system.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter.
3336system.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3337system.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3338system.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter.
3339system.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3340system.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3341system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states
3342system.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution
3343system.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution
3344system.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution
3345system.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution
3346system.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution
3347system.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution
3348system.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution
3349system.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution
3350system.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution
3351system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution
3352system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
3353system.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution
3354system.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution
3355system.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution
3356system.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution
3357system.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution
3358system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes)
3359system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes)
3360system.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes)
3361system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes)
3362system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes)
3363system.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes)
3364system.toL2Bus.snoops 2839573 # Total snoops (count)
3365system.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes)
3366system.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram
3367system.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram
3368system.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram
3369system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3370system.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram
3371system.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram
3372system.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram
3373system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3374system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3375system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3376system.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram
3377system.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks)
3378system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3379system.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks)
3380system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3381system.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks)
3382system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3383system.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks)
3384system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3385
3386---------- End Simulation Statistics ----------