1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.403575 # Number of seconds simulated
4sim_ticks 47403574916500 # Number of ticks simulated
5final_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 473223 # Simulator instruction rate (inst/s)
8host_op_rate 556671 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 25492174892 # Simulator tick rate (ticks/s)
10host_mem_usage 749540 # Number of bytes of host memory used
11host_seconds 1859.53 # Real time elapsed on the host
12sim_insts 879974755 # Number of instructions simulated
13sim_ops 1035148021 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory
26system.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory
27system.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory
28system.physmem.bytes_read::total 56576516 # Number of bytes read from this memory
29system.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory
31system.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory
32system.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35system.physmem.bytes_written::total 75204968 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 924529 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51system.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory
52system.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.readReqs 924529 # Number of read requests accepted
85system.physmem.writeReqs 1177330 # Number of write requests accepted
86system.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue
87system.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue
88system.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM
89system.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue
90system.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM
91system.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side
92system.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side
93system.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue
94system.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one
95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96system.physmem.perBankRdBursts::0 51848 # Per bank write bursts
97system.physmem.perBankRdBursts::1 60547 # Per bank write bursts
98system.physmem.perBankRdBursts::2 52943 # Per bank write bursts
99system.physmem.perBankRdBursts::3 59873 # Per bank write bursts
100system.physmem.perBankRdBursts::4 53995 # Per bank write bursts
101system.physmem.perBankRdBursts::5 59394 # Per bank write bursts
102system.physmem.perBankRdBursts::6 55656 # Per bank write bursts
103system.physmem.perBankRdBursts::7 56350 # Per bank write bursts
104system.physmem.perBankRdBursts::8 47470 # Per bank write bursts
105system.physmem.perBankRdBursts::9 98045 # Per bank write bursts
106system.physmem.perBankRdBursts::10 51346 # Per bank write bursts
107system.physmem.perBankRdBursts::11 58216 # Per bank write bursts
108system.physmem.perBankRdBursts::12 52575 # Per bank write bursts
109system.physmem.perBankRdBursts::13 60842 # Per bank write bursts
110system.physmem.perBankRdBursts::14 50185 # Per bank write bursts
111system.physmem.perBankRdBursts::15 54822 # Per bank write bursts
112system.physmem.perBankWrBursts::0 69717 # Per bank write bursts
113system.physmem.perBankWrBursts::1 76530 # Per bank write bursts
114system.physmem.perBankWrBursts::2 71410 # Per bank write bursts
115system.physmem.perBankWrBursts::3 77292 # Per bank write bursts
116system.physmem.perBankWrBursts::4 71372 # Per bank write bursts
117system.physmem.perBankWrBursts::5 75019 # Per bank write bursts
118system.physmem.perBankWrBursts::6 75211 # Per bank write bursts
119system.physmem.perBankWrBursts::7 75617 # Per bank write bursts
120system.physmem.perBankWrBursts::8 67898 # Per bank write bursts
121system.physmem.perBankWrBursts::9 76939 # Per bank write bursts
122system.physmem.perBankWrBursts::10 70016 # Per bank write bursts
123system.physmem.perBankWrBursts::11 75357 # Per bank write bursts
124system.physmem.perBankWrBursts::12 71664 # Per bank write bursts
125system.physmem.perBankWrBursts::13 78615 # Per bank write bursts
126system.physmem.perBankWrBursts::14 70257 # Per bank write bursts
127system.physmem.perBankWrBursts::15 72133 # Per bank write bursts
128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129system.physmem.numWrRetry 33 # Number of times write queue was full causing retry
130system.physmem.totGap 47403571626000 # Total gap between requests
131system.physmem.readPktSize::0 0 # Read request sizes (log2)
132system.physmem.readPktSize::1 0 # Read request sizes (log2)
133system.physmem.readPktSize::2 43195 # Read request sizes (log2)
134system.physmem.readPktSize::3 25 # Read request sizes (log2)
135system.physmem.readPktSize::4 5 # Read request sizes (log2)
136system.physmem.readPktSize::5 0 # Read request sizes (log2)
137system.physmem.readPktSize::6 881304 # Read request sizes (log2)
138system.physmem.writePktSize::0 0 # Write request sizes (log2)
139system.physmem.writePktSize::1 0 # Write request sizes (log2)
140system.physmem.writePktSize::2 2 # Write request sizes (log2)
141system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142system.physmem.writePktSize::4 0 # Write request sizes (log2)
143system.physmem.writePktSize::5 0 # Write request sizes (log2)
144system.physmem.writePktSize::6 1174756 # Write request sizes (log2)
145system.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::29 77885 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::30 70974 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::31 65826 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::32 63695 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::34 1650 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::35 1244 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::36 937 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::37 692 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::38 576 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::39 555 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::40 407 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::41 403 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see
241system.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation
255system.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes
263system.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads
304system.physmem.totQLat 29056215697 # Total ticks spent queuing
305system.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM
306system.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers
307system.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst
308system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
309system.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst
310system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s
311system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s
312system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
313system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s
314system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
315system.physmem.busUtil 0.02 # Data bus utilization in percentage
316system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
317system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
318system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
319system.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing
320system.physmem.readRowHits 688543 # Number of row buffer hits during reads
321system.physmem.writeRowHits 439987 # Number of row buffer hits during writes
322system.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads
323system.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes
324system.physmem.avgGap 22553164.43 # Average gap between requests
325system.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined
326system.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ)
327system.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ)
328system.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ)
329system.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ)
330system.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ)
331system.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ)
332system.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ)
333system.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ)
334system.physmem_0.averagePower 668.669411 # Core power per rank (mW)
335system.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states
336system.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states
337system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
338system.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states
339system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
340system.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ)
341system.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ)
342system.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ)
343system.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ)
344system.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ)
345system.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ)
346system.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ)
347system.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ)
348system.physmem_1.averagePower 668.683580 # Core power per rank (mW)
349system.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states
350system.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states
351system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
352system.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states
353system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
354system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
355system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
359system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
360system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
361system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
362system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory

--- 10 unchanged lines hidden (view full) ---

373system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
374system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
375system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
376system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
377system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
378system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
380system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
381system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
382system.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
383system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
384system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
385system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
386system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
387system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
388system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
389system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
390system.cpu_clk_domain.clock 500 # Clock period in ticks
391system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

413system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
414system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
415system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
416system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
417system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
418system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
419system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
420system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
421system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
422system.cpu0.dtb.walker.walks 114038 # Table walker walks requested
423system.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors
424system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate
425system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate
426system.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting
427system.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution
454system.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution
455system.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution
456system.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution
457system.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution
458system.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated
459system.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated
460system.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated
461system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst
462system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
463system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst
464system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst
465system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
466system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst
467system.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst
468system.cpu0.dtb.inst_hits 0 # ITB inst hits
469system.cpu0.dtb.inst_misses 0 # ITB inst misses
470system.cpu0.dtb.read_hits 86092375 # DTB read hits
471system.cpu0.dtb.read_misses 87013 # DTB read misses
472system.cpu0.dtb.write_hits 77928513 # DTB write hits
473system.cpu0.dtb.write_misses 27025 # DTB write misses
474system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
475system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
476system.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
477system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
478system.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB
479system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
480system.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch
481system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
482system.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions
483system.cpu0.dtb.read_accesses 86179388 # DTB read accesses
484system.cpu0.dtb.write_accesses 77955538 # DTB write accesses
485system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
486system.cpu0.dtb.hits 164020888 # DTB hits
487system.cpu0.dtb.misses 114038 # DTB misses
488system.cpu0.dtb.accesses 164134926 # DTB accesses
489system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
490system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

511system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
512system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
513system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
514system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
515system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
516system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
517system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
518system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
519system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
520system.cpu0.itb.walker.walks 57747 # Table walker walks requested
521system.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors
522system.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate
523system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate
524system.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency
525system.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency
538system.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency
539system.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency
541system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency
542system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency
543system.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency
544system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
545system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
546system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
547system.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency
548system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution
549system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution
550system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution
551system.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated
552system.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated
553system.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated
554system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
555system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst
556system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst
557system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
558system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst
559system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst
560system.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst
561system.cpu0.itb.inst_hits 458544228 # ITB inst hits
562system.cpu0.itb.inst_misses 57747 # ITB inst misses
563system.cpu0.itb.read_hits 0 # DTB read hits
564system.cpu0.itb.read_misses 0 # DTB read misses
565system.cpu0.itb.write_hits 0 # DTB write hits
566system.cpu0.itb.write_misses 0 # DTB write misses
567system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
568system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
569system.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
570system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
571system.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB
572system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
573system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
574system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
575system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
576system.cpu0.itb.read_accesses 0 # DTB read accesses
577system.cpu0.itb.write_accesses 0 # DTB write accesses
578system.cpu0.itb.inst_accesses 458601975 # ITB inst accesses
579system.cpu0.itb.hits 458544228 # DTB hits
580system.cpu0.itb.misses 57747 # DTB misses
581system.cpu0.itb.accesses 458601975 # DTB accesses
582system.cpu0.numPwrStateTransitions 27516 # Number of power state transitions
583system.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state
584system.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state
585system.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state
586system.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state
587system.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state
588system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state
589system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
590system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
591system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state
592system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state
593system.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state
594system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
595system.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state
596system.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state
597system.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states
598system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states
599system.cpu0.numCycles 94807149833 # number of cpu cycles simulated
600system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
601system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
602system.cpu0.kern.inst.arm 0 # number of arm instructions executed
603system.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed
604system.cpu0.committedInsts 458270897 # Number of instructions committed
605system.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed
606system.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses
607system.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses
608system.cpu0.num_func_calls 27507374 # number of times a function call or return occured
609system.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls
610system.cpu0.num_int_insts 494447989 # number of integer instructions
611system.cpu0.num_fp_insts 420942 # number of float instructions
612system.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read
613system.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written
614system.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read
615system.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written
616system.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read
617system.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written
618system.cpu0.num_mem_refs 164010919 # number of memory refs
619system.cpu0.num_load_insts 86087147 # Number of load instructions
620system.cpu0.num_store_insts 77923772 # Number of store instructions
621system.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles
622system.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles
623system.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles
624system.cpu0.idle_fraction 0.988082 # Percentage of idle cycles
625system.cpu0.Branches 102213618 # Number of branches fetched
626system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
627system.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction
628system.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction
629system.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction
630system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction
631system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction
632system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction
633system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction
634system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction
635system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction
636system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction
637system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction
638system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction
639system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction
640system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction
641system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction
642system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction
643system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction
644system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction
645system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction
646system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction
647system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction
648system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction
649system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction
650system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction
651system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction
652system.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction
653system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction
654system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction
655system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction
656system.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction
657system.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction
658system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
659system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
660system.cpu0.op_class::total 538410126 # Class of executed instruction
661system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
662system.cpu0.dcache.tags.replacements 5755741 # number of replacements
663system.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use
664system.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks.
665system.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks.
666system.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks.
667system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit.
668system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor
669system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy
670system.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy
671system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
672system.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
673system.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id
674system.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
675system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
676system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
677system.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses
678system.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses
679system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
680system.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits
681system.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits
682system.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits
683system.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits
684system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits
685system.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits
686system.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits
687system.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits
688system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits
689system.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits
690system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits
691system.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits
692system.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits
693system.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits
694system.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits
695system.cpu0.dcache.overall_hits::total 153968410 # number of overall hits
696system.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses
697system.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses
698system.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses
699system.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses
700system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses
701system.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses
702system.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses
703system.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses
704system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses
705system.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses
706system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses
707system.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses
708system.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses
709system.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses
710system.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses
711system.cpu0.dcache.overall_misses::total 5993812 # number of overall misses
712system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles
713system.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles
714system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles
715system.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles
716system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles
717system.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles
718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles
719system.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles
720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles
721system.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles
722system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles
723system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles
724system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles
725system.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles
726system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles
727system.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles
728system.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses)
729system.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses)
730system.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses)
731system.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses)
732system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses)
733system.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses)
734system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses)
735system.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses)
736system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses)
737system.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses)
738system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses)
739system.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses)
740system.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses
741system.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses
742system.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses
743system.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses
744system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses
745system.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses
746system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses
747system.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses
748system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses
749system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses
750system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses
751system.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses
752system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses
753system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses
754system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses
755system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # miss rate for StoreCondReq accesses
756system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033537 # miss rate for demand accesses
757system.cpu0.dcache.demand_miss_rate::total 0.033537 # miss rate for demand accesses
758system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037470 # miss rate for overall accesses
759system.cpu0.dcache.overall_miss_rate::total 0.037470 # miss rate for overall accesses
760system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306 # average ReadReq miss latency
761system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306 # average ReadReq miss latency
762system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948 # average WriteReq miss latency
763system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948 # average WriteReq miss latency
764system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922 # average WriteLineReq miss latency
765system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922 # average WriteLineReq miss latency
766system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270 # average LoadLockedReq miss latency
767system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency
768system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency
769system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency
770system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
771system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
772system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency
773system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency
774system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency
775system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency
776system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
777system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
778system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
779system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
780system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
781system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
782system.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks
783system.cpu0.dcache.writebacks::total 5755741 # number of writebacks
784system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits
785system.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits
786system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits
787system.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits
788system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits
789system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits
790system.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits
791system.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits
792system.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits
793system.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits
794system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses
795system.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses
796system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses
797system.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses
798system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses
799system.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses
800system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses
801system.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses
802system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses
803system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses
804system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses
805system.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses
806system.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses
807system.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses
808system.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses
809system.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses
810system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable
811system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable
812system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable
813system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable
814system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses
815system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses
816system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles
817system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles
818system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles
819system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles
820system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles
821system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles
822system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles
823system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles
824system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles
825system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles
826system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles
827system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles
828system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles
829system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles
830system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles
831system.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles
832system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles
833system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles
834system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles
835system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles
836system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles
837system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles
838system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses
839system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses
840system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses
841system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses
842system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses
843system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses
844system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses
845system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses
846system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses
847system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses
848system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses
849system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses
850system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses
851system.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses
852system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses
853system.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses
854system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency
855system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency
856system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency
857system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency
858system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency
859system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency
860system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency
861system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency
862system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency
863system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency
864system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency
865system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency
866system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
867system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
868system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency
869system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency
870system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency
871system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency
872system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency
873system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency
874system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency
875system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency
876system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
877system.cpu0.icache.tags.replacements 4916262 # number of replacements
878system.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use
879system.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks.
880system.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks.
881system.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks.
882system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit.
883system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor
884system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy
885system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy
886system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
887system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
888system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
889system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
890system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
891system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
892system.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses
893system.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses
894system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
895system.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits
896system.cpu0.icache.ReadReq_hits::total 453627454 # number of ReadReq hits
897system.cpu0.icache.demand_hits::cpu0.inst 453627454 # number of demand (read+write) hits
898system.cpu0.icache.demand_hits::total 453627454 # number of demand (read+write) hits
899system.cpu0.icache.overall_hits::cpu0.inst 453627454 # number of overall hits
900system.cpu0.icache.overall_hits::total 453627454 # number of overall hits
901system.cpu0.icache.ReadReq_misses::cpu0.inst 4916774 # number of ReadReq misses
902system.cpu0.icache.ReadReq_misses::total 4916774 # number of ReadReq misses
903system.cpu0.icache.demand_misses::cpu0.inst 4916774 # number of demand (read+write) misses
904system.cpu0.icache.demand_misses::total 4916774 # number of demand (read+write) misses
905system.cpu0.icache.overall_misses::cpu0.inst 4916774 # number of overall misses
906system.cpu0.icache.overall_misses::total 4916774 # number of overall misses
907system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52276659500 # number of ReadReq miss cycles
908system.cpu0.icache.ReadReq_miss_latency::total 52276659500 # number of ReadReq miss cycles
909system.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles
910system.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles
911system.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles
912system.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles
913system.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses)
914system.cpu0.icache.ReadReq_accesses::total 458544228 # number of ReadReq accesses(hits+misses)
915system.cpu0.icache.demand_accesses::cpu0.inst 458544228 # number of demand (read+write) accesses
916system.cpu0.icache.demand_accesses::total 458544228 # number of demand (read+write) accesses
917system.cpu0.icache.overall_accesses::cpu0.inst 458544228 # number of overall (read+write) accesses
918system.cpu0.icache.overall_accesses::total 458544228 # number of overall (read+write) accesses
919system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010723 # miss rate for ReadReq accesses
920system.cpu0.icache.ReadReq_miss_rate::total 0.010723 # miss rate for ReadReq accesses
921system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010723 # miss rate for demand accesses
922system.cpu0.icache.demand_miss_rate::total 0.010723 # miss rate for demand accesses
923system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010723 # miss rate for overall accesses
924system.cpu0.icache.overall_miss_rate::total 0.010723 # miss rate for overall accesses
925system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807 # average ReadReq miss latency
926system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807 # average ReadReq miss latency
927system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency
928system.cpu0.icache.demand_avg_miss_latency::total 10632.308807 # average overall miss latency
929system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency
930system.cpu0.icache.overall_avg_miss_latency::total 10632.308807 # average overall miss latency
931system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
932system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
933system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
934system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
935system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
936system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
937system.cpu0.icache.writebacks::writebacks 4916262 # number of writebacks
938system.cpu0.icache.writebacks::total 4916262 # number of writebacks
939system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4916774 # number of ReadReq MSHR misses
940system.cpu0.icache.ReadReq_mshr_misses::total 4916774 # number of ReadReq MSHR misses
941system.cpu0.icache.demand_mshr_misses::cpu0.inst 4916774 # number of demand (read+write) MSHR misses
942system.cpu0.icache.demand_mshr_misses::total 4916774 # number of demand (read+write) MSHR misses
943system.cpu0.icache.overall_mshr_misses::cpu0.inst 4916774 # number of overall MSHR misses
944system.cpu0.icache.overall_mshr_misses::total 4916774 # number of overall MSHR misses
945system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
946system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
947system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
948system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
949system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 49818272500 # number of ReadReq MSHR miss cycles
950system.cpu0.icache.ReadReq_mshr_miss_latency::total 49818272500 # number of ReadReq MSHR miss cycles
951system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 49818272500 # number of demand (read+write) MSHR miss cycles
952system.cpu0.icache.demand_mshr_miss_latency::total 49818272500 # number of demand (read+write) MSHR miss cycles
953system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 49818272500 # number of overall MSHR miss cycles
954system.cpu0.icache.overall_mshr_miss_latency::total 49818272500 # number of overall MSHR miss cycles
955system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles
956system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles
957system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles
958system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles
959system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for ReadReq accesses
960system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010723 # mshr miss rate for ReadReq accesses
961system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for demand accesses
962system.cpu0.icache.demand_mshr_miss_rate::total 0.010723 # mshr miss rate for demand accesses
963system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for overall accesses
964system.cpu0.icache.overall_mshr_miss_rate::total 0.010723 # mshr miss rate for overall accesses
965system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average ReadReq mshr miss latency
966system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10132.308807 # average ReadReq mshr miss latency
967system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency
968system.cpu0.icache.demand_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency
969system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10132.308807 # average overall mshr miss latency
970system.cpu0.icache.overall_avg_mshr_miss_latency::total 10132.308807 # average overall mshr miss latency
971system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency
972system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency
973system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency
974system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency
975system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
976system.cpu0.l2cache.prefetcher.num_hwpf_issued 7829609 # number of hwpf issued
977system.cpu0.l2cache.prefetcher.pfIdentified 7829625 # number of prefetch candidates identified
978system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
979system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
980system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
981system.cpu0.l2cache.prefetcher.pfSpanPage 1043159 # number of prefetches not generated due to page crossing
982system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
983system.cpu0.l2cache.tags.replacements 2362641 # number of replacements
984system.cpu0.l2cache.tags.tagsinuse 16162.227513 # Cycle average of tags in use
985system.cpu0.l2cache.tags.total_refs 14986861 # Total number of references to valid blocks.
986system.cpu0.l2cache.tags.sampled_refs 2378231 # Sample count of references to valid blocks.
987system.cpu0.l2cache.tags.avg_refs 6.301684 # Average number of references to valid blocks.
988system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit.
989system.cpu0.l2cache.tags.occ_blocks::writebacks 15129.176557 # Average occupied blocks per requestor
990system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.599278 # Average occupied blocks per requestor
991system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 80.860024 # Average occupied blocks per requestor
992system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 896.591654 # Average occupied blocks per requestor
993system.cpu0.l2cache.tags.occ_percent::writebacks 0.923412 # Average percentage of cache occupancy
994system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003394 # Average percentage of cache occupancy
995system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004935 # Average percentage of cache occupancy
996system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054724 # Average percentage of cache occupancy
997system.cpu0.l2cache.tags.occ_percent::total 0.986464 # Average percentage of cache occupancy
998system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1593 # Occupied blocks per task id
999system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
1000system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13925 # Occupied blocks per task id
1001system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 258 # Occupied blocks per task id
1002system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 732 # Occupied blocks per task id
1003system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 603 # Occupied blocks per task id
1004system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
1005system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id
1006system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2612 # Occupied blocks per task id
1010system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5888 # Occupied blocks per task id
1011system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5210 # Occupied blocks per task id
1012system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097229 # Percentage of cache occupancy per task id
1013system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id
1014system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.849915 # Percentage of cache occupancy per task id
1015system.cpu0.l2cache.tags.tag_accesses 362405390 # Number of tag accesses
1016system.cpu0.l2cache.tags.data_accesses 362405390 # Number of data accesses
1017system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1018system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 268274 # number of ReadReq hits
1019system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147126 # number of ReadReq hits
1020system.cpu0.l2cache.ReadReq_hits::total 415400 # number of ReadReq hits
1021system.cpu0.l2cache.WritebackDirty_hits::writebacks 3821588 # number of WritebackDirty hits
1022system.cpu0.l2cache.WritebackDirty_hits::total 3821588 # number of WritebackDirty hits
1023system.cpu0.l2cache.WritebackClean_hits::writebacks 6849535 # number of WritebackClean hits
1024system.cpu0.l2cache.WritebackClean_hits::total 6849535 # number of WritebackClean hits
1025system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 548 # number of UpgradeReq hits
1026system.cpu0.l2cache.UpgradeReq_hits::total 548 # number of UpgradeReq hits
1027system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933451 # number of ReadExReq hits
1028system.cpu0.l2cache.ReadExReq_hits::total 933451 # number of ReadExReq hits
1029system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4462897 # number of ReadCleanReq hits
1030system.cpu0.l2cache.ReadCleanReq_hits::total 4462897 # number of ReadCleanReq hits
1031system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2959469 # number of ReadSharedReq hits
1032system.cpu0.l2cache.ReadSharedReq_hits::total 2959469 # number of ReadSharedReq hits
1033system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 207284 # number of InvalidateReq hits
1034system.cpu0.l2cache.InvalidateReq_hits::total 207284 # number of InvalidateReq hits
1035system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 268274 # number of demand (read+write) hits
1036system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147126 # number of demand (read+write) hits
1037system.cpu0.l2cache.demand_hits::cpu0.inst 4462897 # number of demand (read+write) hits
1038system.cpu0.l2cache.demand_hits::cpu0.data 3892920 # number of demand (read+write) hits
1039system.cpu0.l2cache.demand_hits::total 8771217 # number of demand (read+write) hits
1040system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 268274 # number of overall hits
1041system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147126 # number of overall hits
1042system.cpu0.l2cache.overall_hits::cpu0.inst 4462897 # number of overall hits
1043system.cpu0.l2cache.overall_hits::cpu0.data 3892920 # number of overall hits
1044system.cpu0.l2cache.overall_hits::total 8771217 # number of overall hits
1045system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10042 # number of ReadReq misses
1046system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8210 # number of ReadReq misses
1047system.cpu0.l2cache.ReadReq_misses::total 18252 # number of ReadReq misses
1048system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 241773 # number of UpgradeReq misses
1049system.cpu0.l2cache.UpgradeReq_misses::total 241773 # number of UpgradeReq misses
1050system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190127 # number of SCUpgradeReq misses
1051system.cpu0.l2cache.SCUpgradeReq_misses::total 190127 # number of SCUpgradeReq misses
1052system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses
1053system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
1054system.cpu0.l2cache.ReadExReq_misses::cpu0.data 253021 # number of ReadExReq misses
1055system.cpu0.l2cache.ReadExReq_misses::total 253021 # number of ReadExReq misses
1056system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 453877 # number of ReadCleanReq misses
1057system.cpu0.l2cache.ReadCleanReq_misses::total 453877 # number of ReadCleanReq misses
1058system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 922445 # number of ReadSharedReq misses
1059system.cpu0.l2cache.ReadSharedReq_misses::total 922445 # number of ReadSharedReq misses
1060system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 574180 # number of InvalidateReq misses
1061system.cpu0.l2cache.InvalidateReq_misses::total 574180 # number of InvalidateReq misses
1062system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10042 # number of demand (read+write) misses
1063system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8210 # number of demand (read+write) misses
1064system.cpu0.l2cache.demand_misses::cpu0.inst 453877 # number of demand (read+write) misses
1065system.cpu0.l2cache.demand_misses::cpu0.data 1175466 # number of demand (read+write) misses
1066system.cpu0.l2cache.demand_misses::total 1647595 # number of demand (read+write) misses
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1076system.cpu0.l2cache.UpgradeReq_miss_latency::total 1915432500 # number of UpgradeReq miss cycles
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1080system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2680500 # number of SCUpgradeFailReq miss cycles
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1084system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15633345500 # number of ReadCleanReq miss cycles
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1086system.cpu0.l2cache.ReadSharedReq_miss_latency::total 32366023500 # number of ReadSharedReq miss cycles
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1088system.cpu0.l2cache.InvalidateReq_miss_latency::total 286150500 # number of InvalidateReq miss cycles
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1101system.cpu0.l2cache.ReadReq_accesses::total 433652 # number of ReadReq accesses(hits+misses)
1102system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3821588 # number of WritebackDirty accesses(hits+misses)
1103system.cpu0.l2cache.WritebackDirty_accesses::total 3821588 # number of WritebackDirty accesses(hits+misses)
1104system.cpu0.l2cache.WritebackClean_accesses::writebacks 6849535 # number of WritebackClean accesses(hits+misses)
1105system.cpu0.l2cache.WritebackClean_accesses::total 6849535 # number of WritebackClean accesses(hits+misses)
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1107system.cpu0.l2cache.UpgradeReq_accesses::total 242321 # number of UpgradeReq accesses(hits+misses)
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1111system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
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1119system.cpu0.l2cache.InvalidateReq_accesses::total 781464 # number of InvalidateReq accesses(hits+misses)
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1126system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155336 # number of overall (read+write) accesses
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1131system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052853 # miss rate for ReadReq accesses
1132system.cpu0.l2cache.ReadReq_miss_rate::total 0.042089 # miss rate for ReadReq accesses
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1134system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997739 # miss rate for UpgradeReq accesses
1135system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1136system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1137system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1138system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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1140system.cpu0.l2cache.ReadExReq_miss_rate::total 0.213255 # miss rate for ReadExReq accesses
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1142system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092312 # miss rate for ReadCleanReq accesses
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1144system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.237626 # miss rate for ReadSharedReq accesses
1145system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734749 # miss rate for InvalidateReq accesses
1146system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734749 # miss rate for InvalidateReq accesses
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1148system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052853 # miss rate for demand accesses
1149system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092312 # miss rate for demand accesses
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1153system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052853 # miss rate for overall accesses
1154system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092312 # miss rate for overall accesses
1155system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.231921 # miss rate for overall accesses
1156system.cpu0.l2cache.overall_miss_rate::total 0.158137 # miss rate for overall accesses
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1158system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41399.573691 # average ReadReq miss latency
1159system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39277.010739 # average ReadReq miss latency
1160system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7922.441712 # average UpgradeReq miss latency
1161system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7922.441712 # average UpgradeReq miss latency
1162system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 8317.061753 # average SCUpgradeReq miss latency
1163system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 8317.061753 # average SCUpgradeReq miss latency
1164system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 382928.571429 # average SCUpgradeFailReq miss latency
1165system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382928.571429 # average SCUpgradeFailReq miss latency
1166system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50360.452291 # average ReadExReq miss latency
1167system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50360.452291 # average ReadExReq miss latency
1168system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34444.013466 # average ReadCleanReq miss latency
1169system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34444.013466 # average ReadCleanReq miss latency
1170system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35087.212246 # average ReadSharedReq miss latency
1171system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35087.212246 # average ReadSharedReq miss latency
1172system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 498.363754 # average InvalidateReq miss latency
1173system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 498.363754 # average InvalidateReq miss latency
1174system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average overall miss latency
1175system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41399.573691 # average overall miss latency
1176system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34444.013466 # average overall miss latency
1177system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38374.802418 # average overall miss latency
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1179system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37541.674965 # average overall miss latency
1180system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41399.573691 # average overall miss latency
1181system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34444.013466 # average overall miss latency
1182system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38374.802418 # average overall miss latency
1183system.cpu0.l2cache.overall_avg_miss_latency::total 37301.949204 # average overall miss latency
1184system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1185system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1186system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1187system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1188system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1189system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1190system.cpu0.l2cache.unused_prefetches 39736 # number of HardPF blocks evicted w/o reference
1191system.cpu0.l2cache.writebacks::writebacks 1527732 # number of writebacks
1192system.cpu0.l2cache.writebacks::total 1527732 # number of writebacks
1193system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5839 # number of ReadExReq MSHR hits
1194system.cpu0.l2cache.ReadExReq_mshr_hits::total 5839 # number of ReadExReq MSHR hits
1195system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 307 # number of ReadSharedReq MSHR hits
1196system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 307 # number of ReadSharedReq MSHR hits
1197system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6146 # number of demand (read+write) MSHR hits
1198system.cpu0.l2cache.demand_mshr_hits::total 6146 # number of demand (read+write) MSHR hits
1199system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6146 # number of overall MSHR hits
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1207system.cpu0.l2cache.UpgradeReq_mshr_misses::total 241773 # number of UpgradeReq MSHR misses
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1217system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 922138 # number of ReadSharedReq MSHR misses
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1219system.cpu0.l2cache.InvalidateReq_mshr_misses::total 574180 # number of InvalidateReq MSHR misses
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1223system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1169320 # number of demand (read+write) MSHR misses
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1226system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8210 # number of overall MSHR misses
1227system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 453877 # number of overall MSHR misses
1228system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1169320 # number of overall MSHR misses
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1230system.cpu0.l2cache.overall_mshr_misses::total 2389464 # number of overall MSHR misses
1231system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
1232system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable
1233system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 70700 # number of ReadReq MSHR uncacheable
1234system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable
1235system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable
1236system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
1237system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses
1238system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 97240 # number of overall MSHR uncacheable misses
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1243system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33693542276 # number of HardPFReq MSHR miss cycles
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1245system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5018820000 # number of UpgradeReq MSHR miss cycles
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1247system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3123659500 # number of SCUpgradeReq MSHR miss cycles
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1249system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2368500 # number of SCUpgradeFailReq MSHR miss cycles
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1251system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10716539999 # number of ReadExReq MSHR miss cycles
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1253system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 12910083500 # number of ReadCleanReq MSHR miss cycles
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1255system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 26808700000 # number of ReadSharedReq MSHR miss cycles
1256system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18844533500 # number of InvalidateReq MSHR miss cycles
1257system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18844533500 # number of InvalidateReq MSHR miss cycles
1258system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 316741500 # number of demand (read+write) MSHR miss cycles
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1264system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290630500 # number of overall MSHR miss cycles
1265system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12910083500 # number of overall MSHR miss cycles
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1268system.cpu0.l2cache.overall_mshr_miss_latency::total 84736237775 # number of overall MSHR miss cycles
1269system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles
1270system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850748500 # number of ReadReq MSHR uncacheable cycles
1271system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles
1272system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles
1273system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles
1274system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # number of overall MSHR uncacheable cycles
1275system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for ReadReq accesses
1276system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for ReadReq accesses
1277system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042089 # mshr miss rate for ReadReq accesses
1278system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1279system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1280system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997739 # mshr miss rate for UpgradeReq accesses
1281system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997739 # mshr miss rate for UpgradeReq accesses
1282system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1283system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1284system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1285system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1286system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses
1287system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses
1288system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses
1289system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses
1290system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses
1291system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses
1292system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses
1293system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses
1294system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses
1295system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses
1296system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses
1297system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses
1298system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses
1299system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses
1300system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses
1301system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses
1302system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses
1303system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1304system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses
1305system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency
1306system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency
1307system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency
1308system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency
1309system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency
1310system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency
1311system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency
1312system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency
1313system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency
1314system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency
1315system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency
1316system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency
1317system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency
1318system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency
1319system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency
1320system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency
1321system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency
1322system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency
1323system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency
1324system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency
1325system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency
1326system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency
1327system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency
1328system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency
1329system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency
1330system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency
1331system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency
1332system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency
1333system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency
1334system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency
1335system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency
1336system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency
1337system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency
1338system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency
1339system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency
1340system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency
1341system.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter.
1342system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1343system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1344system.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter.
1345system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1346system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1347system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1348system.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution
1349system.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution
1350system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1351system.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution
1352system.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution
1353system.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution
1354system.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution
1355system.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution
1356system.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution
1357system.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution
1358system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution
1359system.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution
1360system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
1361system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution
1362system.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution
1363system.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution
1364system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution
1365system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution
1366system.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution
1367system.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution
1368system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes)
1369system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes)
1370system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes)
1371system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes)
1372system.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes)
1373system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes)
1374system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes)
1375system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes)
1376system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes)
1377system.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes)
1378system.cpu0.toL2Bus.snoops 6259200 # Total snoops (count)
1379system.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes)
1380system.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram
1381system.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram
1382system.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram
1383system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1384system.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram
1385system.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram
1386system.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram
1387system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1388system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1389system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1390system.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram
1391system.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks)
1392system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1393system.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks)
1394system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1395system.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks)
1396system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1397system.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks)
1398system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1399system.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks)
1400system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1401system.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks)
1402system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1403system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1404system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1405system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1406system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1407system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1408system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1409system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1410system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1411system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1425system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1426system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1427system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1428system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1429system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1430system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1431system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1432system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1433system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1434system.cpu1.dtb.walker.walks 102344 # Table walker walks requested
1435system.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors
1436system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate
1437system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate
1438system.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting
1439system.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency
1440system.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency
1441system.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency
1442system.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1443system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1444system.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency
1445system.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency
1446system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency
1447system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency
1448system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency
1449system.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency
1450system.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency
1451system.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency
1452system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency
1453system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency
1454system.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
1455system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1456system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1457system.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency
1458system.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution
1459system.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution
1460system.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution
1461system.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution
1462system.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution
1463system.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution
1464system.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated
1465system.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated
1466system.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated
1467system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst
1468system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1469system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst
1470system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst
1471system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1472system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst
1473system.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst
1474system.cpu1.dtb.inst_hits 0 # ITB inst hits
1475system.cpu1.dtb.inst_misses 0 # ITB inst misses
1476system.cpu1.dtb.read_hits 79660508 # DTB read hits
1477system.cpu1.dtb.read_misses 74735 # DTB read misses
1478system.cpu1.dtb.write_hits 72705787 # DTB write hits
1479system.cpu1.dtb.write_misses 27609 # DTB write misses
1480system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1481system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1482system.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
1483system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1484system.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB
1485system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1486system.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch
1487system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1488system.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions
1489system.cpu1.dtb.read_accesses 79735243 # DTB read accesses
1490system.cpu1.dtb.write_accesses 72733396 # DTB write accesses
1491system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1492system.cpu1.dtb.hits 152366295 # DTB hits
1493system.cpu1.dtb.misses 102344 # DTB misses
1494system.cpu1.dtb.accesses 152468639 # DTB accesses
1495system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1496system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1497system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1498system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1499system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1500system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1501system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1502system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1503system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1517system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1518system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1519system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1520system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1521system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1522system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1523system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1524system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1525system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1526system.cpu1.itb.walker.walks 58593 # Table walker walks requested
1527system.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors
1528system.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate
1529system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate
1530system.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency
1531system.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1532system.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency
1533system.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency
1534system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency
1535system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency
1536system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency
1537system.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency
1538system.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency
1539system.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency
1540system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency
1541system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency
1542system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency
1543system.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency
1544system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency
1545system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency
1546system.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency
1547system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
1548system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
1549system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1550system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1551system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1552system.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency
1553system.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution
1554system.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution
1555system.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution
1556system.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated
1557system.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated
1558system.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated
1559system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1560system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst
1561system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst
1562system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1563system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst
1564system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst
1565system.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst
1566system.cpu1.itb.inst_hits 421982441 # ITB inst hits
1567system.cpu1.itb.inst_misses 58593 # ITB inst misses
1568system.cpu1.itb.read_hits 0 # DTB read hits
1569system.cpu1.itb.read_misses 0 # DTB read misses
1570system.cpu1.itb.write_hits 0 # DTB write hits
1571system.cpu1.itb.write_misses 0 # DTB write misses
1572system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1573system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1574system.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID
1575system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
1576system.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB
1577system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1578system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1579system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1580system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1581system.cpu1.itb.read_accesses 0 # DTB read accesses
1582system.cpu1.itb.write_accesses 0 # DTB write accesses
1583system.cpu1.itb.inst_accesses 422041034 # ITB inst accesses
1584system.cpu1.itb.hits 421982441 # DTB hits
1585system.cpu1.itb.misses 58593 # DTB misses
1586system.cpu1.itb.accesses 422041034 # DTB accesses
1587system.cpu1.numPwrStateTransitions 9904 # Number of power state transitions
1588system.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state
1589system.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state
1590system.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state
1591system.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state
1592system.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state
1593system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state
1594system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state
1595system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state
1596system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state
1597system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state
1598system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state
1599system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state
1600system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state
1601system.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state
1602system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1603system.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state
1604system.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state
1605system.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states
1606system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states
1607system.cpu1.numCycles 94807149833 # number of cpu cycles simulated
1608system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1609system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1610system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1611system.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed
1612system.cpu1.committedInsts 421703858 # Number of instructions committed
1613system.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed
1614system.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses
1615system.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses
1616system.cpu1.num_func_calls 25188507 # number of times a function call or return occured
1617system.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls
1618system.cpu1.num_int_insts 456781482 # number of integer instructions
1619system.cpu1.num_fp_insts 475663 # number of float instructions
1620system.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read
1621system.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written
1622system.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read
1623system.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written
1624system.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read
1625system.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written
1626system.cpu1.num_mem_refs 152358964 # number of memory refs
1627system.cpu1.num_load_insts 79658830 # Number of load instructions
1628system.cpu1.num_store_insts 72700134 # Number of store instructions
1629system.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles
1630system.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles
1631system.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles
1632system.cpu1.idle_fraction 0.989420 # Percentage of idle cycles
1633system.cpu1.Branches 94064671 # Number of branches fetched
1634system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
1635system.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction
1636system.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction
1637system.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction
1638system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction
1639system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction
1640system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction
1641system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction
1642system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction
1643system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction
1644system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction
1645system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction
1646system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction
1647system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction
1648system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction
1649system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction
1650system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction
1651system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction
1652system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction
1653system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction
1654system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction
1655system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction
1656system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction
1657system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction
1658system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction
1659system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction
1660system.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction
1661system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction
1662system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction
1663system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction
1664system.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction
1665system.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction
1666system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1667system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1668system.cpu1.op_class::total 497333042 # Class of executed instruction
1669system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1670system.cpu1.dcache.tags.replacements 5003393 # number of replacements
1671system.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use
1672system.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks.
1673system.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks.
1674system.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks.
1675system.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit.
1676system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor
1677system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy
1678system.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy
1679system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1680system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
1681system.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id
1682system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
1683system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1684system.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses
1685system.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses
1686system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1687system.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits
1688system.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits
1689system.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits
1690system.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits
1691system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits
1692system.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits
1693system.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits
1694system.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits
1695system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits
1696system.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits
1697system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits
1698system.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits
1699system.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits
1700system.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits
1701system.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits
1702system.cpu1.dcache.overall_hits::total 143489600 # number of overall hits
1703system.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses
1704system.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses
1705system.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses
1706system.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses
1707system.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses
1708system.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses
1709system.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses
1710system.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses
1711system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses
1712system.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses
1713system.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses
1714system.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses
1715system.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses
1716system.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses
1717system.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses
1718system.cpu1.dcache.overall_misses::total 5199606 # number of overall misses
1719system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles
1720system.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles
1721system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles
1722system.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles
1723system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles
1724system.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles
1725system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles
1726system.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles
1727system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles
1728system.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles
1729system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles
1730system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles
1731system.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles
1732system.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles
1733system.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles
1734system.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles
1735system.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses)
1736system.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses)
1737system.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses)
1738system.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses)
1739system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses)
1740system.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses)
1741system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses)
1742system.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses)
1743system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses)
1744system.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses)
1745system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses)
1746system.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses)
1747system.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses
1748system.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses
1749system.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses
1750system.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses
1751system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses
1752system.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses
1753system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses
1754system.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses
1755system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses
1756system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses
1757system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses
1758system.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses
1759system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses
1760system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses
1761system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses
1762system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses
1763system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses
1764system.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses
1765system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses
1766system.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses
1767system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency
1768system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency
1769system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency
1770system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency
1771system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency
1772system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency
1773system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency
1774system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency
1775system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency
1776system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency
1777system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1778system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1779system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency
1780system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency
1781system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency
1782system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency
1783system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1784system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1785system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1786system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1787system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1788system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1789system.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks
1790system.cpu1.dcache.writebacks::total 5003393 # number of writebacks
1791system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits
1792system.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits
1793system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits
1794system.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits
1795system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits
1796system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits
1797system.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits
1798system.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits
1799system.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits
1800system.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits
1801system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses
1802system.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses
1803system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses
1804system.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses
1805system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses
1806system.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses
1807system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses
1808system.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses
1809system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses
1810system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses
1811system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses
1812system.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses
1813system.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses
1814system.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses
1815system.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses
1816system.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses
1817system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable
1818system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable
1819system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable
1820system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable
1821system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses
1822system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses
1823system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles
1824system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles
1825system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles
1826system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles
1827system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles
1828system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles
1829system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles
1830system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles
1831system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles
1832system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles
1833system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles
1834system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles
1835system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles
1836system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles
1837system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles
1838system.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles
1839system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles
1840system.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles
1841system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles
1842system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles
1843system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles
1844system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles
1845system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses
1846system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses
1847system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses
1848system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses
1849system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses
1850system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses
1851system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses
1852system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses
1853system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses
1854system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses
1855system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses
1856system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses
1857system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses
1858system.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses
1859system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses
1860system.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses
1861system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency
1862system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency
1863system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency
1864system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency
1865system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency
1866system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency
1867system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency
1868system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency
1869system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency
1870system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency
1871system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency
1872system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency
1873system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1874system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1875system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency
1876system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency
1877system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency
1878system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency
1879system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency
1880system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency
1881system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency
1882system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency
1883system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1884system.cpu1.icache.tags.replacements 5018955 # number of replacements
1885system.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use
1886system.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks.
1887system.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks.
1888system.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks.
1889system.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit.
1890system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor
1891system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy
1892system.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy
1893system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1894system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
1895system.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
1896system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
1897system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1898system.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses
1899system.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses
1900system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1901system.cpu1.icache.ReadReq_hits::cpu1.inst 416962969 # number of ReadReq hits
1902system.cpu1.icache.ReadReq_hits::total 416962969 # number of ReadReq hits
1903system.cpu1.icache.demand_hits::cpu1.inst 416962969 # number of demand (read+write) hits
1904system.cpu1.icache.demand_hits::total 416962969 # number of demand (read+write) hits
1905system.cpu1.icache.overall_hits::cpu1.inst 416962969 # number of overall hits
1906system.cpu1.icache.overall_hits::total 416962969 # number of overall hits
1907system.cpu1.icache.ReadReq_misses::cpu1.inst 5019472 # number of ReadReq misses
1908system.cpu1.icache.ReadReq_misses::total 5019472 # number of ReadReq misses
1909system.cpu1.icache.demand_misses::cpu1.inst 5019472 # number of demand (read+write) misses
1910system.cpu1.icache.demand_misses::total 5019472 # number of demand (read+write) misses
1911system.cpu1.icache.overall_misses::cpu1.inst 5019472 # number of overall misses
1912system.cpu1.icache.overall_misses::total 5019472 # number of overall misses
1913system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53186343000 # number of ReadReq miss cycles
1914system.cpu1.icache.ReadReq_miss_latency::total 53186343000 # number of ReadReq miss cycles
1915system.cpu1.icache.demand_miss_latency::cpu1.inst 53186343000 # number of demand (read+write) miss cycles
1916system.cpu1.icache.demand_miss_latency::total 53186343000 # number of demand (read+write) miss cycles
1917system.cpu1.icache.overall_miss_latency::cpu1.inst 53186343000 # number of overall miss cycles
1918system.cpu1.icache.overall_miss_latency::total 53186343000 # number of overall miss cycles
1919system.cpu1.icache.ReadReq_accesses::cpu1.inst 421982441 # number of ReadReq accesses(hits+misses)
1920system.cpu1.icache.ReadReq_accesses::total 421982441 # number of ReadReq accesses(hits+misses)
1921system.cpu1.icache.demand_accesses::cpu1.inst 421982441 # number of demand (read+write) accesses
1922system.cpu1.icache.demand_accesses::total 421982441 # number of demand (read+write) accesses
1923system.cpu1.icache.overall_accesses::cpu1.inst 421982441 # number of overall (read+write) accesses
1924system.cpu1.icache.overall_accesses::total 421982441 # number of overall (read+write) accesses
1925system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011895 # miss rate for ReadReq accesses
1926system.cpu1.icache.ReadReq_miss_rate::total 0.011895 # miss rate for ReadReq accesses
1927system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011895 # miss rate for demand accesses
1928system.cpu1.icache.demand_miss_rate::total 0.011895 # miss rate for demand accesses
1929system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011895 # miss rate for overall accesses
1930system.cpu1.icache.overall_miss_rate::total 0.011895 # miss rate for overall accesses
1931system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524 # average ReadReq miss latency
1932system.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524 # average ReadReq miss latency
1933system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency
1934system.cpu1.icache.demand_avg_miss_latency::total 10596.003524 # average overall miss latency
1935system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency
1936system.cpu1.icache.overall_avg_miss_latency::total 10596.003524 # average overall miss latency
1937system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1938system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1939system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1940system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1941system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1942system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1943system.cpu1.icache.writebacks::writebacks 5018955 # number of writebacks
1944system.cpu1.icache.writebacks::total 5018955 # number of writebacks
1945system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5019472 # number of ReadReq MSHR misses
1946system.cpu1.icache.ReadReq_mshr_misses::total 5019472 # number of ReadReq MSHR misses
1947system.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses
1948system.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses
1949system.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses
1950system.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses
1951system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
1952system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
1953system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
1954system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
1955system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles
1956system.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles
1957system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles
1958system.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles
1959system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles
1960system.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles
1961system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles
1962system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles
1963system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles
1964system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles
1965system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses
1966system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses
1967system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses
1968system.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses
1969system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses
1970system.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses
1971system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency
1972system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency
1973system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency
1974system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency
1975system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency
1976system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency
1977system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency
1978system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency
1979system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency
1980system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency
1981system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1982system.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued
1983system.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified
1984system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue
1985system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1986system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1987system.cpu1.l2cache.prefetcher.pfSpanPage 855832 # number of prefetches not generated due to page crossing
1988system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
1989system.cpu1.l2cache.tags.replacements 1952199 # number of replacements
1990system.cpu1.l2cache.tags.tagsinuse 13310.052713 # Cycle average of tags in use
1991system.cpu1.l2cache.tags.total_refs 14647404 # Total number of references to valid blocks.
1992system.cpu1.l2cache.tags.sampled_refs 1968271 # Sample count of references to valid blocks.
1993system.cpu1.l2cache.tags.avg_refs 7.441762 # Average number of references to valid blocks.
1994system.cpu1.l2cache.tags.warmup_cycle 9691338413500 # Cycle when the warmup percentage was hit.
1995system.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537 # Average occupied blocks per requestor
1996system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.710351 # Average occupied blocks per requestor
1997system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 42.105943 # Average occupied blocks per requestor
1998system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 846.327882 # Average occupied blocks per requestor
1999system.cpu1.l2cache.tags.occ_percent::writebacks 0.755304 # Average percentage of cache occupancy
2000system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002851 # Average percentage of cache occupancy
2001system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002570 # Average percentage of cache occupancy
2002system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051656 # Average percentage of cache occupancy
2003system.cpu1.l2cache.tags.occ_percent::total 0.812381 # Average percentage of cache occupancy
2004system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1315 # Occupied blocks per task id
2005system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id
2006system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id
2007system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 28 # Occupied blocks per task id
2008system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 206 # Occupied blocks per task id
2009system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 560 # Occupied blocks per task id
2010system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id
2011system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id
2012system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
2013system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
2014system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
2015system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 976 # Occupied blocks per task id
2016system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4506 # Occupied blocks per task id
2017system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5198 # Occupied blocks per task id
2018system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3947 # Occupied blocks per task id
2019system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080261 # Percentage of cache occupancy per task id
2020system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id
2021system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id
2022system.cpu1.l2cache.tags.tag_accesses 339868675 # Number of tag accesses
2023system.cpu1.l2cache.tags.data_accesses 339868675 # Number of data accesses
2024system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2025system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 236019 # number of ReadReq hits
2026system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150274 # number of ReadReq hits
2027system.cpu1.l2cache.ReadReq_hits::total 386293 # number of ReadReq hits
2028system.cpu1.l2cache.WritebackDirty_hits::writebacks 3171050 # number of WritebackDirty hits
2029system.cpu1.l2cache.WritebackDirty_hits::total 3171050 # number of WritebackDirty hits
2030system.cpu1.l2cache.WritebackClean_hits::writebacks 6850339 # number of WritebackClean hits
2031system.cpu1.l2cache.WritebackClean_hits::total 6850339 # number of WritebackClean hits
2032system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 404 # number of UpgradeReq hits
2033system.cpu1.l2cache.UpgradeReq_hits::total 404 # number of UpgradeReq hits
2034system.cpu1.l2cache.ReadExReq_hits::cpu1.data 839001 # number of ReadExReq hits
2035system.cpu1.l2cache.ReadExReq_hits::total 839001 # number of ReadExReq hits
2036system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4555671 # number of ReadCleanReq hits
2037system.cpu1.l2cache.ReadCleanReq_hits::total 4555671 # number of ReadCleanReq hits
2038system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2665864 # number of ReadSharedReq hits
2039system.cpu1.l2cache.ReadSharedReq_hits::total 2665864 # number of ReadSharedReq hits
2040system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 201941 # number of InvalidateReq hits
2041system.cpu1.l2cache.InvalidateReq_hits::total 201941 # number of InvalidateReq hits
2042system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 236019 # number of demand (read+write) hits
2043system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150274 # number of demand (read+write) hits
2044system.cpu1.l2cache.demand_hits::cpu1.inst 4555671 # number of demand (read+write) hits
2045system.cpu1.l2cache.demand_hits::cpu1.data 3504865 # number of demand (read+write) hits
2046system.cpu1.l2cache.demand_hits::total 8446829 # number of demand (read+write) hits
2047system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 236019 # number of overall hits
2048system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150274 # number of overall hits
2049system.cpu1.l2cache.overall_hits::cpu1.inst 4555671 # number of overall hits
2050system.cpu1.l2cache.overall_hits::cpu1.data 3504865 # number of overall hits
2051system.cpu1.l2cache.overall_hits::total 8446829 # number of overall hits
2052system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10494 # number of ReadReq misses
2053system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9148 # number of ReadReq misses
2054system.cpu1.l2cache.ReadReq_misses::total 19642 # number of ReadReq misses
2055system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207236 # number of UpgradeReq misses
2056system.cpu1.l2cache.UpgradeReq_misses::total 207236 # number of UpgradeReq misses
2057system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 191347 # number of SCUpgradeReq misses
2058system.cpu1.l2cache.SCUpgradeReq_misses::total 191347 # number of SCUpgradeReq misses
2059system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
2060system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
2061system.cpu1.l2cache.ReadExReq_misses::cpu1.data 252464 # number of ReadExReq misses
2062system.cpu1.l2cache.ReadExReq_misses::total 252464 # number of ReadExReq misses
2063system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463801 # number of ReadCleanReq misses
2064system.cpu1.l2cache.ReadCleanReq_misses::total 463801 # number of ReadCleanReq misses
2065system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 876385 # number of ReadSharedReq misses
2066system.cpu1.l2cache.ReadSharedReq_misses::total 876385 # number of ReadSharedReq misses
2067system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256334 # number of InvalidateReq misses
2068system.cpu1.l2cache.InvalidateReq_misses::total 256334 # number of InvalidateReq misses
2069system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10494 # number of demand (read+write) misses
2070system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9148 # number of demand (read+write) misses
2071system.cpu1.l2cache.demand_misses::cpu1.inst 463801 # number of demand (read+write) misses
2072system.cpu1.l2cache.demand_misses::cpu1.data 1128849 # number of demand (read+write) misses
2073system.cpu1.l2cache.demand_misses::total 1612292 # number of demand (read+write) misses
2074system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10494 # number of overall misses
2075system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9148 # number of overall misses
2076system.cpu1.l2cache.overall_misses::cpu1.inst 463801 # number of overall misses
2077system.cpu1.l2cache.overall_misses::cpu1.data 1128849 # number of overall misses
2078system.cpu1.l2cache.overall_misses::total 1612292 # number of overall misses
2079system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 383427500 # number of ReadReq miss cycles
2080system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 341472000 # number of ReadReq miss cycles
2081system.cpu1.l2cache.ReadReq_miss_latency::total 724899500 # number of ReadReq miss cycles
2082system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1893664000 # number of UpgradeReq miss cycles
2083system.cpu1.l2cache.UpgradeReq_miss_latency::total 1893664000 # number of UpgradeReq miss cycles
2084system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1540982500 # number of SCUpgradeReq miss cycles
2085system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1540982500 # number of SCUpgradeReq miss cycles
2086system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2848499 # number of SCUpgradeFailReq miss cycles
2087system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2848499 # number of SCUpgradeFailReq miss cycles
2088system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10062122499 # number of ReadExReq miss cycles
2089system.cpu1.l2cache.ReadExReq_miss_latency::total 10062122499 # number of ReadExReq miss cycles
2090system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 15777836000 # number of ReadCleanReq miss cycles
2091system.cpu1.l2cache.ReadCleanReq_miss_latency::total 15777836000 # number of ReadCleanReq miss cycles
2092system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28794953500 # number of ReadSharedReq miss cycles
2093system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28794953500 # number of ReadSharedReq miss cycles
2094system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 441282000 # number of InvalidateReq miss cycles
2095system.cpu1.l2cache.InvalidateReq_miss_latency::total 441282000 # number of InvalidateReq miss cycles
2096system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 383427500 # number of demand (read+write) miss cycles
2097system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 341472000 # number of demand (read+write) miss cycles
2098system.cpu1.l2cache.demand_miss_latency::cpu1.inst 15777836000 # number of demand (read+write) miss cycles
2099system.cpu1.l2cache.demand_miss_latency::cpu1.data 38857075999 # number of demand (read+write) miss cycles
2100system.cpu1.l2cache.demand_miss_latency::total 55359811499 # number of demand (read+write) miss cycles
2101system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 383427500 # number of overall miss cycles
2102system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 341472000 # number of overall miss cycles
2103system.cpu1.l2cache.overall_miss_latency::cpu1.inst 15777836000 # number of overall miss cycles
2104system.cpu1.l2cache.overall_miss_latency::cpu1.data 38857075999 # number of overall miss cycles
2105system.cpu1.l2cache.overall_miss_latency::total 55359811499 # number of overall miss cycles
2106system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 246513 # number of ReadReq accesses(hits+misses)
2107system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159422 # number of ReadReq accesses(hits+misses)
2108system.cpu1.l2cache.ReadReq_accesses::total 405935 # number of ReadReq accesses(hits+misses)
2109system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3171050 # number of WritebackDirty accesses(hits+misses)
2110system.cpu1.l2cache.WritebackDirty_accesses::total 3171050 # number of WritebackDirty accesses(hits+misses)
2111system.cpu1.l2cache.WritebackClean_accesses::writebacks 6850339 # number of WritebackClean accesses(hits+misses)
2112system.cpu1.l2cache.WritebackClean_accesses::total 6850339 # number of WritebackClean accesses(hits+misses)
2113system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207640 # number of UpgradeReq accesses(hits+misses)
2114system.cpu1.l2cache.UpgradeReq_accesses::total 207640 # number of UpgradeReq accesses(hits+misses)
2115system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 191347 # number of SCUpgradeReq accesses(hits+misses)
2116system.cpu1.l2cache.SCUpgradeReq_accesses::total 191347 # number of SCUpgradeReq accesses(hits+misses)
2117system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
2118system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
2119system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1091465 # number of ReadExReq accesses(hits+misses)
2120system.cpu1.l2cache.ReadExReq_accesses::total 1091465 # number of ReadExReq accesses(hits+misses)
2121system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5019472 # number of ReadCleanReq accesses(hits+misses)
2122system.cpu1.l2cache.ReadCleanReq_accesses::total 5019472 # number of ReadCleanReq accesses(hits+misses)
2123system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3542249 # number of ReadSharedReq accesses(hits+misses)
2124system.cpu1.l2cache.ReadSharedReq_accesses::total 3542249 # number of ReadSharedReq accesses(hits+misses)
2125system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 458275 # number of InvalidateReq accesses(hits+misses)
2126system.cpu1.l2cache.InvalidateReq_accesses::total 458275 # number of InvalidateReq accesses(hits+misses)
2127system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 246513 # number of demand (read+write) accesses
2128system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159422 # number of demand (read+write) accesses
2129system.cpu1.l2cache.demand_accesses::cpu1.inst 5019472 # number of demand (read+write) accesses
2130system.cpu1.l2cache.demand_accesses::cpu1.data 4633714 # number of demand (read+write) accesses
2131system.cpu1.l2cache.demand_accesses::total 10059121 # number of demand (read+write) accesses
2132system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 246513 # number of overall (read+write) accesses
2133system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159422 # number of overall (read+write) accesses
2134system.cpu1.l2cache.overall_accesses::cpu1.inst 5019472 # number of overall (read+write) accesses
2135system.cpu1.l2cache.overall_accesses::cpu1.data 4633714 # number of overall (read+write) accesses
2136system.cpu1.l2cache.overall_accesses::total 10059121 # number of overall (read+write) accesses
2137system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for ReadReq accesses
2138system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057382 # miss rate for ReadReq accesses
2139system.cpu1.l2cache.ReadReq_miss_rate::total 0.048387 # miss rate for ReadReq accesses
2140system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998054 # miss rate for UpgradeReq accesses
2141system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998054 # miss rate for UpgradeReq accesses
2142system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2143system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2144system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2145system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2146system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231307 # miss rate for ReadExReq accesses
2147system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231307 # miss rate for ReadExReq accesses
2148system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092400 # miss rate for ReadCleanReq accesses
2149system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092400 # miss rate for ReadCleanReq accesses
2150system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.247409 # miss rate for ReadSharedReq accesses
2151system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.247409 # miss rate for ReadSharedReq accesses
2152system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.559345 # miss rate for InvalidateReq accesses
2153system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.559345 # miss rate for InvalidateReq accesses
2154system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for demand accesses
2155system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057382 # miss rate for demand accesses
2156system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092400 # miss rate for demand accesses
2157system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243616 # miss rate for demand accesses
2158system.cpu1.l2cache.demand_miss_rate::total 0.160282 # miss rate for demand accesses
2159system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for overall accesses
2160system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057382 # miss rate for overall accesses
2161system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092400 # miss rate for overall accesses
2162system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243616 # miss rate for overall accesses
2163system.cpu1.l2cache.overall_miss_rate::total 0.160282 # miss rate for overall accesses
2164system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average ReadReq miss latency
2165system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37327.503279 # average ReadReq miss latency
2166system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36905.584971 # average ReadReq miss latency
2167system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 9137.717385 # average UpgradeReq miss latency
2168system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 9137.717385 # average UpgradeReq miss latency
2169system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 8053.340267 # average SCUpgradeReq miss latency
2170system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 8053.340267 # average SCUpgradeReq miss latency
2171system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 406928.428571 # average SCUpgradeFailReq miss latency
2172system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 406928.428571 # average SCUpgradeFailReq miss latency
2173system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39855.672488 # average ReadExReq miss latency
2174system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39855.672488 # average ReadExReq miss latency
2175system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34018.546747 # average ReadCleanReq miss latency
2176system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34018.546747 # average ReadCleanReq miss latency
2177system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32856.511122 # average ReadSharedReq miss latency
2178system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32856.511122 # average ReadSharedReq miss latency
2179system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1721.511778 # average InvalidateReq miss latency
2180system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1721.511778 # average InvalidateReq miss latency
2181system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average overall miss latency
2182system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37327.503279 # average overall miss latency
2183system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34018.546747 # average overall miss latency
2184system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34421.854472 # average overall miss latency
2185system.cpu1.l2cache.demand_avg_miss_latency::total 34336.095136 # average overall miss latency
2186system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36537.783495 # average overall miss latency
2187system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37327.503279 # average overall miss latency
2188system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34018.546747 # average overall miss latency
2189system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34421.854472 # average overall miss latency
2190system.cpu1.l2cache.overall_avg_miss_latency::total 34336.095136 # average overall miss latency
2191system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2192system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2193system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2194system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2195system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2196system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2197system.cpu1.l2cache.unused_prefetches 40910 # number of HardPF blocks evicted w/o reference
2198system.cpu1.l2cache.writebacks::writebacks 1077285 # number of writebacks
2199system.cpu1.l2cache.writebacks::total 1077285 # number of writebacks
2200system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4355 # number of ReadExReq MSHR hits
2201system.cpu1.l2cache.ReadExReq_mshr_hits::total 4355 # number of ReadExReq MSHR hits
2202system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 371 # number of ReadSharedReq MSHR hits
2203system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 371 # number of ReadSharedReq MSHR hits
2204system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4726 # number of demand (read+write) MSHR hits
2205system.cpu1.l2cache.demand_mshr_hits::total 4726 # number of demand (read+write) MSHR hits
2206system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4726 # number of overall MSHR hits
2207system.cpu1.l2cache.overall_mshr_hits::total 4726 # number of overall MSHR hits
2208system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10494 # number of ReadReq MSHR misses
2209system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9148 # number of ReadReq MSHR misses
2210system.cpu1.l2cache.ReadReq_mshr_misses::total 19642 # number of ReadReq MSHR misses
2211system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 670250 # number of HardPFReq MSHR misses
2212system.cpu1.l2cache.HardPFReq_mshr_misses::total 670250 # number of HardPFReq MSHR misses
2213system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207236 # number of UpgradeReq MSHR misses
2214system.cpu1.l2cache.UpgradeReq_mshr_misses::total 207236 # number of UpgradeReq MSHR misses
2215system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 191347 # number of SCUpgradeReq MSHR misses
2216system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 191347 # number of SCUpgradeReq MSHR misses
2217system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
2218system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
2219system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248109 # number of ReadExReq MSHR misses
2220system.cpu1.l2cache.ReadExReq_mshr_misses::total 248109 # number of ReadExReq MSHR misses
2221system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463801 # number of ReadCleanReq MSHR misses
2222system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463801 # number of ReadCleanReq MSHR misses
2223system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 876014 # number of ReadSharedReq MSHR misses
2224system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 876014 # number of ReadSharedReq MSHR misses
2225system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256334 # number of InvalidateReq MSHR misses
2226system.cpu1.l2cache.InvalidateReq_mshr_misses::total 256334 # number of InvalidateReq MSHR misses
2227system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10494 # number of demand (read+write) MSHR misses
2228system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9148 # number of demand (read+write) MSHR misses
2229system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463801 # number of demand (read+write) MSHR misses
2230system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1124123 # number of demand (read+write) MSHR misses
2231system.cpu1.l2cache.demand_mshr_misses::total 1607566 # number of demand (read+write) MSHR misses
2232system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10494 # number of overall MSHR misses
2233system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9148 # number of overall MSHR misses
2234system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463801 # number of overall MSHR misses
2235system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1124123 # number of overall MSHR misses
2236system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 670250 # number of overall MSHR misses
2237system.cpu1.l2cache.overall_mshr_misses::total 2277816 # number of overall MSHR misses
2238system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2239system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable
2240system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 11131 # number of ReadReq MSHR uncacheable
2241system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable
2242system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable
2243system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2244system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses
2245system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 23055 # number of overall MSHR uncacheable misses
2246system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of ReadReq MSHR miss cycles
2247system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 286584000 # number of ReadReq MSHR miss cycles
2248system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 607047500 # number of ReadReq MSHR miss cycles
2249system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of HardPFReq MSHR miss cycles
2250system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26432385766 # number of HardPFReq MSHR miss cycles
2251system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4355093500 # number of UpgradeReq MSHR miss cycles
2252system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4355093500 # number of UpgradeReq MSHR miss cycles
2253system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3151504000 # number of SCUpgradeReq MSHR miss cycles
2254system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3151504000 # number of SCUpgradeReq MSHR miss cycles
2255system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2506499 # number of SCUpgradeFailReq MSHR miss cycles
2256system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2506499 # number of SCUpgradeFailReq MSHR miss cycles
2257system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8136910999 # number of ReadExReq MSHR miss cycles
2258system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8136910999 # number of ReadExReq MSHR miss cycles
2259system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 12995030000 # number of ReadCleanReq MSHR miss cycles
2260system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 12995030000 # number of ReadCleanReq MSHR miss cycles
2261system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23494652500 # number of ReadSharedReq MSHR miss cycles
2262system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23494652500 # number of ReadSharedReq MSHR miss cycles
2263system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6984949000 # number of InvalidateReq MSHR miss cycles
2264system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6984949000 # number of InvalidateReq MSHR miss cycles
2265system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of demand (read+write) MSHR miss cycles
2266system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286584000 # number of demand (read+write) MSHR miss cycles
2267system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12995030000 # number of demand (read+write) MSHR miss cycles
2268system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31631563499 # number of demand (read+write) MSHR miss cycles
2269system.cpu1.l2cache.demand_mshr_miss_latency::total 45233640999 # number of demand (read+write) MSHR miss cycles
2270system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 320463500 # number of overall MSHR miss cycles
2271system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286584000 # number of overall MSHR miss cycles
2272system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12995030000 # number of overall MSHR miss cycles
2273system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31631563499 # number of overall MSHR miss cycles
2274system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26432385766 # number of overall MSHR miss cycles
2275system.cpu1.l2cache.overall_mshr_miss_latency::total 71666026765 # number of overall MSHR miss cycles
2276system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9401000 # number of ReadReq MSHR uncacheable cycles
2277system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1799706000 # number of ReadReq MSHR uncacheable cycles
2278system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1809107000 # number of ReadReq MSHR uncacheable cycles
2279system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9401000 # number of overall MSHR uncacheable cycles
2280system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1799706000 # number of overall MSHR uncacheable cycles
2281system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1809107000 # number of overall MSHR uncacheable cycles
2282system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for ReadReq accesses
2283system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for ReadReq accesses
2284system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048387 # mshr miss rate for ReadReq accesses
2285system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2286system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2287system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998054 # mshr miss rate for UpgradeReq accesses
2288system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998054 # mshr miss rate for UpgradeReq accesses
2289system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2290system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2291system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2292system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2293system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.227317 # mshr miss rate for ReadExReq accesses
2294system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.227317 # mshr miss rate for ReadExReq accesses
2295system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for ReadCleanReq accesses
2296system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092400 # mshr miss rate for ReadCleanReq accesses
2297system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.247304 # mshr miss rate for ReadSharedReq accesses
2298system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247304 # mshr miss rate for ReadSharedReq accesses
2299system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.559345 # mshr miss rate for InvalidateReq accesses
2300system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.559345 # mshr miss rate for InvalidateReq accesses
2301system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for demand accesses
2302system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for demand accesses
2303system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for demand accesses
2304system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for demand accesses
2305system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159812 # mshr miss rate for demand accesses
2306system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.042570 # mshr miss rate for overall accesses
2307system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057382 # mshr miss rate for overall accesses
2308system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092400 # mshr miss rate for overall accesses
2309system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242597 # mshr miss rate for overall accesses
2310system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2311system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226443 # mshr miss rate for overall accesses
2312system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average ReadReq mshr miss latency
2313system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average ReadReq mshr miss latency
2314system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971 # average ReadReq mshr miss latency
2315system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average HardPFReq mshr miss latency
2316system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887 # average HardPFReq mshr miss latency
2317system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744 # average UpgradeReq mshr miss latency
2318system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744 # average UpgradeReq mshr miss latency
2319system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826 # average SCUpgradeReq mshr miss latency
2320system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826 # average SCUpgradeReq mshr miss latency
2321system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714 # average SCUpgradeFailReq mshr miss latency
2322system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714 # average SCUpgradeFailReq mshr miss latency
2323system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752 # average ReadExReq mshr miss latency
2324system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752 # average ReadExReq mshr miss latency
2325system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average ReadCleanReq mshr miss latency
2326system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747 # average ReadCleanReq mshr miss latency
2327system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937 # average ReadSharedReq mshr miss latency
2328system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937 # average ReadSharedReq mshr miss latency
2329system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency
2330system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency
2331system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency
2332system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency
2333system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency
2334system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency
2335system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency
2336system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency
2337system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency
2338system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency
2339system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency
2340system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency
2341system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency
2342system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency
2343system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency
2344system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency
2345system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency
2346system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency
2347system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency
2348system.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter.
2349system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2350system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2351system.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter.
2352system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2353system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2354system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2355system.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution
2356system.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution
2357system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2358system.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution
2359system.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution
2360system.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution
2361system.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution
2362system.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution
2363system.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution
2364system.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution
2365system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution
2366system.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution
2367system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution
2368system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution
2369system.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution
2370system.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution
2371system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution
2372system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution
2373system.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution
2374system.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution
2375system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes)
2376system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes)
2377system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes)
2378system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes)
2379system.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes)
2380system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes)
2381system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes)
2382system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes)
2383system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes)
2384system.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes)
2385system.cpu1.toL2Bus.snoops 5663025 # Total snoops (count)
2386system.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes)
2387system.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram
2388system.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram
2389system.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram
2390system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2391system.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram
2392system.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram
2393system.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram
2394system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2395system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2396system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2397system.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram
2398system.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks)
2399system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2400system.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks)
2401system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2402system.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks)
2403system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2404system.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks)
2405system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2406system.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks)
2407system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2408system.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks)
2409system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2410system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2411system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
2412system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
2413system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
2414system.iobus.trans_dist::WriteResp 136621 # Transaction distribution
2415system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes)
2416system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2417system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2418system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2419system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2420system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2421system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2422system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2423system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2424system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2425system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2426system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2427system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2428system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes)
2429system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes)
2430system.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes)
2431system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2432system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2433system.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes)
2434system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes)
2435system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2436system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2437system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2438system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2439system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2440system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2441system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2442system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2443system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2444system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2445system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2446system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2447system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes)
2448system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes)
2449system.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes)
2450system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2451system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2452system.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes)
2453system.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks)
2454system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2455system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks)
2456system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2457system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
2458system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2459system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
2460system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2461system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
2462system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2463system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2464system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2465system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2466system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2467system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2468system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2469system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2470system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2471system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2472system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2473system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2474system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2475system.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks)
2476system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2477system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks)
2478system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2479system.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks)
2480system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2481system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks)
2482system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2483system.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks)
2484system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2485system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2486system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2487system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2488system.iocache.tags.replacements 115616 # number of replacements
2489system.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use
2490system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2491system.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks.
2492system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2493system.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit.
2494system.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor
2495system.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor
2496system.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy
2497system.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy
2498system.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy
2499system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2500system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2501system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2502system.iocache.tags.tag_accesses 1040928 # Number of tag accesses
2503system.iocache.tags.data_accesses 1040928 # Number of data accesses
2504system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2505system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2506system.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses
2507system.iocache.ReadReq_misses::total 8928 # number of ReadReq misses
2508system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2509system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2510system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2511system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2512system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2513system.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses
2514system.iocache.demand_misses::total 115659 # number of demand (read+write) misses
2515system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2516system.iocache.overall_misses::realview.ide 115619 # number of overall misses
2517system.iocache.overall_misses::total 115659 # number of overall misses
2518system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
2519system.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles
2520system.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles
2521system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2522system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2523system.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles
2524system.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles
2525system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
2526system.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles
2527system.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles
2528system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
2529system.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles
2530system.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles
2531system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2532system.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses)
2533system.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses)
2534system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2535system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2536system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2537system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2538system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2539system.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses
2540system.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses
2541system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2542system.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses
2543system.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses
2544system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2545system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2546system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2547system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2548system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2549system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2550system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2551system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2552system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2553system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2554system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2555system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2556system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2557system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
2558system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency
2559system.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency
2560system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2561system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2562system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency
2563system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency
2564system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
2565system.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency
2566system.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency
2567system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
2568system.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency
2569system.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency
2570system.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked
2571system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2572system.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked
2573system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2574system.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked
2575system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2576system.iocache.writebacks::writebacks 106695 # number of writebacks
2577system.iocache.writebacks::total 106695 # number of writebacks
2578system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2579system.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses
2580system.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses
2581system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2582system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2583system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2584system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2585system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2586system.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses
2587system.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses
2588system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2589system.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses
2590system.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses
2591system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
2592system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles
2593system.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles
2594system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2595system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2596system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles
2597system.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles
2598system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
2599system.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles
2600system.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles
2601system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
2602system.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles
2603system.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles
2604system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2605system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2606system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2607system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2608system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2609system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2610system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2611system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2612system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2613system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2614system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2615system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2616system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2617system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
2618system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency
2619system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency
2620system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2621system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2622system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency
2623system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency
2624system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
2625system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency
2626system.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency
2627system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
2628system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency
2629system.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency
2630system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2631system.l2c.tags.replacements 1334376 # number of replacements
2632system.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use
2633system.l2c.tags.total_refs 5390543 # Total number of references to valid blocks.
2634system.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks.
2635system.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks.
2636system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit.
2637system.l2c.tags.occ_blocks::writebacks 22223.163606 # Average occupied blocks per requestor
2638system.l2c.tags.occ_blocks::cpu0.dtb.walker 261.500257 # Average occupied blocks per requestor
2639system.l2c.tags.occ_blocks::cpu0.itb.walker 456.360455 # Average occupied blocks per requestor
2640system.l2c.tags.occ_blocks::cpu0.inst 3501.846073 # Average occupied blocks per requestor
2641system.l2c.tags.occ_blocks::cpu0.data 10429.068271 # Average occupied blocks per requestor
2642system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383 # Average occupied blocks per requestor
2643system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.820782 # Average occupied blocks per requestor
2644system.l2c.tags.occ_blocks::cpu1.itb.walker 49.581814 # Average occupied blocks per requestor
2645system.l2c.tags.occ_blocks::cpu1.inst 3191.520948 # Average occupied blocks per requestor
2646system.l2c.tags.occ_blocks::cpu1.data 3798.713740 # Average occupied blocks per requestor
2647system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor
2648system.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy
2649system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy
2650system.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy
2651system.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy
2652system.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy
2653system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy
2654system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy
2655system.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy
2656system.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy
2657system.l2c.tags.occ_percent::cpu1.data 0.057964 # Average percentage of cache occupancy
2658system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.039963 # Average percentage of cache occupancy
2659system.l2c.tags.occ_percent::total 0.965797 # Average percentage of cache occupancy
2660system.l2c.tags.occ_task_id_blocks::1022 10362 # Occupied blocks per task id
2661system.l2c.tags.occ_task_id_blocks::1023 274 # Occupied blocks per task id
2662system.l2c.tags.occ_task_id_blocks::1024 48360 # Occupied blocks per task id
2663system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
2664system.l2c.tags.age_task_id_blocks_1022::2 240 # Occupied blocks per task id
2665system.l2c.tags.age_task_id_blocks_1022::3 245 # Occupied blocks per task id
2666system.l2c.tags.age_task_id_blocks_1022::4 9869 # Occupied blocks per task id
2667system.l2c.tags.age_task_id_blocks_1023::4 274 # Occupied blocks per task id
2668system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
2669system.l2c.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
2670system.l2c.tags.age_task_id_blocks_1024::2 1630 # Occupied blocks per task id
2671system.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id
2672system.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id
2673system.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id
2674system.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id
2675system.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id
2676system.l2c.tags.tag_accesses 69824789 # Number of tag accesses
2677system.l2c.tags.data_accesses 69824789 # Number of data accesses
2678system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
2679system.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits
2680system.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits
2681system.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits
2682system.l2c.UpgradeReq_hits::cpu1.data 131498 # number of UpgradeReq hits
2683system.l2c.UpgradeReq_hits::total 288738 # number of UpgradeReq hits
2684system.l2c.SCUpgradeReq_hits::cpu0.data 36551 # number of SCUpgradeReq hits
2685system.l2c.SCUpgradeReq_hits::cpu1.data 35663 # number of SCUpgradeReq hits
2686system.l2c.SCUpgradeReq_hits::total 72214 # number of SCUpgradeReq hits
2687system.l2c.ReadExReq_hits::cpu0.data 46670 # number of ReadExReq hits
2688system.l2c.ReadExReq_hits::cpu1.data 57995 # number of ReadExReq hits
2689system.l2c.ReadExReq_hits::total 104665 # number of ReadExReq hits
2690system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4832 # number of ReadSharedReq hits
2691system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3674 # number of ReadSharedReq hits
2692system.l2c.ReadSharedReq_hits::cpu0.inst 408343 # number of ReadSharedReq hits
2693system.l2c.ReadSharedReq_hits::cpu0.data 539971 # number of ReadSharedReq hits
2694system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 281420 # number of ReadSharedReq hits
2695system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5997 # number of ReadSharedReq hits
2696system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5496 # number of ReadSharedReq hits
2697system.l2c.ReadSharedReq_hits::cpu1.inst 419901 # number of ReadSharedReq hits
2698system.l2c.ReadSharedReq_hits::cpu1.data 530515 # number of ReadSharedReq hits
2699system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 275271 # number of ReadSharedReq hits
2700system.l2c.ReadSharedReq_hits::total 2475420 # number of ReadSharedReq hits
2701system.l2c.InvalidateReq_hits::cpu0.data 117433 # number of InvalidateReq hits
2702system.l2c.InvalidateReq_hits::cpu1.data 122622 # number of InvalidateReq hits
2703system.l2c.InvalidateReq_hits::total 240055 # number of InvalidateReq hits
2704system.l2c.demand_hits::cpu0.dtb.walker 4832 # number of demand (read+write) hits
2705system.l2c.demand_hits::cpu0.itb.walker 3674 # number of demand (read+write) hits
2706system.l2c.demand_hits::cpu0.inst 408343 # number of demand (read+write) hits
2707system.l2c.demand_hits::cpu0.data 586641 # number of demand (read+write) hits
2708system.l2c.demand_hits::cpu0.l2cache.prefetcher 281420 # number of demand (read+write) hits
2709system.l2c.demand_hits::cpu1.dtb.walker 5997 # number of demand (read+write) hits
2710system.l2c.demand_hits::cpu1.itb.walker 5496 # number of demand (read+write) hits
2711system.l2c.demand_hits::cpu1.inst 419901 # number of demand (read+write) hits
2712system.l2c.demand_hits::cpu1.data 588510 # number of demand (read+write) hits
2713system.l2c.demand_hits::cpu1.l2cache.prefetcher 275271 # number of demand (read+write) hits
2714system.l2c.demand_hits::total 2580085 # number of demand (read+write) hits
2715system.l2c.overall_hits::cpu0.dtb.walker 4832 # number of overall hits
2716system.l2c.overall_hits::cpu0.itb.walker 3674 # number of overall hits
2717system.l2c.overall_hits::cpu0.inst 408343 # number of overall hits
2718system.l2c.overall_hits::cpu0.data 586641 # number of overall hits
2719system.l2c.overall_hits::cpu0.l2cache.prefetcher 281420 # number of overall hits
2720system.l2c.overall_hits::cpu1.dtb.walker 5997 # number of overall hits
2721system.l2c.overall_hits::cpu1.itb.walker 5496 # number of overall hits
2722system.l2c.overall_hits::cpu1.inst 419901 # number of overall hits
2723system.l2c.overall_hits::cpu1.data 588510 # number of overall hits
2724system.l2c.overall_hits::cpu1.l2cache.prefetcher 275271 # number of overall hits
2725system.l2c.overall_hits::total 2580085 # number of overall hits
2726system.l2c.UpgradeReq_misses::cpu0.data 61532 # number of UpgradeReq misses
2727system.l2c.UpgradeReq_misses::cpu1.data 60685 # number of UpgradeReq misses
2728system.l2c.UpgradeReq_misses::total 122217 # number of UpgradeReq misses
2729system.l2c.SCUpgradeReq_misses::cpu0.data 12602 # number of SCUpgradeReq misses
2730system.l2c.SCUpgradeReq_misses::cpu1.data 13049 # number of SCUpgradeReq misses
2731system.l2c.SCUpgradeReq_misses::total 25651 # number of SCUpgradeReq misses
2732system.l2c.ReadExReq_misses::cpu0.data 81623 # number of ReadExReq misses
2733system.l2c.ReadExReq_misses::cpu1.data 50736 # number of ReadExReq misses
2734system.l2c.ReadExReq_misses::total 132359 # number of ReadExReq misses
2735system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq misses
2736system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1980 # number of ReadSharedReq misses
2737system.l2c.ReadSharedReq_misses::cpu0.inst 45534 # number of ReadSharedReq misses
2738system.l2c.ReadSharedReq_misses::cpu0.data 135010 # number of ReadSharedReq misses
2739system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq misses
2740system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq misses
2741system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1646 # number of ReadSharedReq misses
2742system.l2c.ReadSharedReq_misses::cpu1.inst 43900 # number of ReadSharedReq misses
2743system.l2c.ReadSharedReq_misses::cpu1.data 98157 # number of ReadSharedReq misses
2744system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq misses
2745system.l2c.ReadSharedReq_misses::total 747537 # number of ReadSharedReq misses
2746system.l2c.InvalidateReq_misses::cpu0.data 445868 # number of InvalidateReq misses
2747system.l2c.InvalidateReq_misses::cpu1.data 117477 # number of InvalidateReq misses
2748system.l2c.InvalidateReq_misses::total 563345 # number of InvalidateReq misses
2749system.l2c.demand_misses::cpu0.dtb.walker 1903 # number of demand (read+write) misses
2750system.l2c.demand_misses::cpu0.itb.walker 1980 # number of demand (read+write) misses
2751system.l2c.demand_misses::cpu0.inst 45534 # number of demand (read+write) misses
2752system.l2c.demand_misses::cpu0.data 216633 # number of demand (read+write) misses
2753system.l2c.demand_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) misses
2754system.l2c.demand_misses::cpu1.dtb.walker 1748 # number of demand (read+write) misses
2755system.l2c.demand_misses::cpu1.itb.walker 1646 # number of demand (read+write) misses
2756system.l2c.demand_misses::cpu1.inst 43900 # number of demand (read+write) misses
2757system.l2c.demand_misses::cpu1.data 148893 # number of demand (read+write) misses
2758system.l2c.demand_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) misses
2759system.l2c.demand_misses::total 879896 # number of demand (read+write) misses
2760system.l2c.overall_misses::cpu0.dtb.walker 1903 # number of overall misses
2761system.l2c.overall_misses::cpu0.itb.walker 1980 # number of overall misses
2762system.l2c.overall_misses::cpu0.inst 45534 # number of overall misses
2763system.l2c.overall_misses::cpu0.data 216633 # number of overall misses
2764system.l2c.overall_misses::cpu0.l2cache.prefetcher 240877 # number of overall misses
2765system.l2c.overall_misses::cpu1.dtb.walker 1748 # number of overall misses
2766system.l2c.overall_misses::cpu1.itb.walker 1646 # number of overall misses
2767system.l2c.overall_misses::cpu1.inst 43900 # number of overall misses
2768system.l2c.overall_misses::cpu1.data 148893 # number of overall misses
2769system.l2c.overall_misses::cpu1.l2cache.prefetcher 176782 # number of overall misses
2770system.l2c.overall_misses::total 879896 # number of overall misses
2771system.l2c.UpgradeReq_miss_latency::cpu0.data 390440000 # number of UpgradeReq miss cycles
2772system.l2c.UpgradeReq_miss_latency::cpu1.data 373608000 # number of UpgradeReq miss cycles
2773system.l2c.UpgradeReq_miss_latency::total 764048000 # number of UpgradeReq miss cycles
2774system.l2c.SCUpgradeReq_miss_latency::cpu0.data 65654000 # number of SCUpgradeReq miss cycles
2775system.l2c.SCUpgradeReq_miss_latency::cpu1.data 76676500 # number of SCUpgradeReq miss cycles
2776system.l2c.SCUpgradeReq_miss_latency::total 142330500 # number of SCUpgradeReq miss cycles
2777system.l2c.ReadExReq_miss_latency::cpu0.data 7135565500 # number of ReadExReq miss cycles
2778system.l2c.ReadExReq_miss_latency::cpu1.data 4240679000 # number of ReadExReq miss cycles
2779system.l2c.ReadExReq_miss_latency::total 11376244500 # number of ReadExReq miss cycles
2780system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 166331500 # number of ReadSharedReq miss cycles
2781system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 176995000 # number of ReadSharedReq miss cycles
2782system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3903055500 # number of ReadSharedReq miss cycles
2783system.l2c.ReadSharedReq_miss_latency::cpu0.data 11953058500 # number of ReadSharedReq miss cycles
2784system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of ReadSharedReq miss cycles
2785system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157717000 # number of ReadSharedReq miss cycles
2786system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 151093000 # number of ReadSharedReq miss cycles
2787system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3757434500 # number of ReadSharedReq miss cycles
2788system.l2c.ReadSharedReq_miss_latency::cpu1.data 9007178500 # number of ReadSharedReq miss cycles
2789system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of ReadSharedReq miss cycles
2790system.l2c.ReadSharedReq_miss_latency::total 79243121431 # number of ReadSharedReq miss cycles
2791system.l2c.InvalidateReq_miss_latency::cpu0.data 55722000 # number of InvalidateReq miss cycles
2792system.l2c.InvalidateReq_miss_latency::cpu1.data 43983500 # number of InvalidateReq miss cycles
2793system.l2c.InvalidateReq_miss_latency::total 99705500 # number of InvalidateReq miss cycles
2794system.l2c.demand_miss_latency::cpu0.dtb.walker 166331500 # number of demand (read+write) miss cycles
2795system.l2c.demand_miss_latency::cpu0.itb.walker 176995000 # number of demand (read+write) miss cycles
2796system.l2c.demand_miss_latency::cpu0.inst 3903055500 # number of demand (read+write) miss cycles
2797system.l2c.demand_miss_latency::cpu0.data 19088624000 # number of demand (read+write) miss cycles
2798system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of demand (read+write) miss cycles
2799system.l2c.demand_miss_latency::cpu1.dtb.walker 157717000 # number of demand (read+write) miss cycles
2800system.l2c.demand_miss_latency::cpu1.itb.walker 151093000 # number of demand (read+write) miss cycles
2801system.l2c.demand_miss_latency::cpu1.inst 3757434500 # number of demand (read+write) miss cycles
2802system.l2c.demand_miss_latency::cpu1.data 13247857500 # number of demand (read+write) miss cycles
2803system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of demand (read+write) miss cycles
2804system.l2c.demand_miss_latency::total 90619365931 # number of demand (read+write) miss cycles
2805system.l2c.overall_miss_latency::cpu0.dtb.walker 166331500 # number of overall miss cycles
2806system.l2c.overall_miss_latency::cpu0.itb.walker 176995000 # number of overall miss cycles
2807system.l2c.overall_miss_latency::cpu0.inst 3903055500 # number of overall miss cycles
2808system.l2c.overall_miss_latency::cpu0.data 19088624000 # number of overall miss cycles
2809system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of overall miss cycles
2810system.l2c.overall_miss_latency::cpu1.dtb.walker 157717000 # number of overall miss cycles
2811system.l2c.overall_miss_latency::cpu1.itb.walker 151093000 # number of overall miss cycles
2812system.l2c.overall_miss_latency::cpu1.inst 3757434500 # number of overall miss cycles
2813system.l2c.overall_miss_latency::cpu1.data 13247857500 # number of overall miss cycles
2814system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of overall miss cycles
2815system.l2c.overall_miss_latency::total 90619365931 # number of overall miss cycles
2816system.l2c.WritebackDirty_accesses::writebacks 2605015 # number of WritebackDirty accesses(hits+misses)
2817system.l2c.WritebackDirty_accesses::total 2605015 # number of WritebackDirty accesses(hits+misses)
2818system.l2c.UpgradeReq_accesses::cpu0.data 218772 # number of UpgradeReq accesses(hits+misses)
2819system.l2c.UpgradeReq_accesses::cpu1.data 192183 # number of UpgradeReq accesses(hits+misses)
2820system.l2c.UpgradeReq_accesses::total 410955 # number of UpgradeReq accesses(hits+misses)
2821system.l2c.SCUpgradeReq_accesses::cpu0.data 49153 # number of SCUpgradeReq accesses(hits+misses)
2822system.l2c.SCUpgradeReq_accesses::cpu1.data 48712 # number of SCUpgradeReq accesses(hits+misses)
2823system.l2c.SCUpgradeReq_accesses::total 97865 # number of SCUpgradeReq accesses(hits+misses)
2824system.l2c.ReadExReq_accesses::cpu0.data 128293 # number of ReadExReq accesses(hits+misses)
2825system.l2c.ReadExReq_accesses::cpu1.data 108731 # number of ReadExReq accesses(hits+misses)
2826system.l2c.ReadExReq_accesses::total 237024 # number of ReadExReq accesses(hits+misses)
2827system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6735 # number of ReadSharedReq accesses(hits+misses)
2828system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5654 # number of ReadSharedReq accesses(hits+misses)
2829system.l2c.ReadSharedReq_accesses::cpu0.inst 453877 # number of ReadSharedReq accesses(hits+misses)
2830system.l2c.ReadSharedReq_accesses::cpu0.data 674981 # number of ReadSharedReq accesses(hits+misses)
2831system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 522297 # number of ReadSharedReq accesses(hits+misses)
2832system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7745 # number of ReadSharedReq accesses(hits+misses)
2833system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7142 # number of ReadSharedReq accesses(hits+misses)
2834system.l2c.ReadSharedReq_accesses::cpu1.inst 463801 # number of ReadSharedReq accesses(hits+misses)
2835system.l2c.ReadSharedReq_accesses::cpu1.data 628672 # number of ReadSharedReq accesses(hits+misses)
2836system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 452053 # number of ReadSharedReq accesses(hits+misses)
2837system.l2c.ReadSharedReq_accesses::total 3222957 # number of ReadSharedReq accesses(hits+misses)
2838system.l2c.InvalidateReq_accesses::cpu0.data 563301 # number of InvalidateReq accesses(hits+misses)
2839system.l2c.InvalidateReq_accesses::cpu1.data 240099 # number of InvalidateReq accesses(hits+misses)
2840system.l2c.InvalidateReq_accesses::total 803400 # number of InvalidateReq accesses(hits+misses)
2841system.l2c.demand_accesses::cpu0.dtb.walker 6735 # number of demand (read+write) accesses
2842system.l2c.demand_accesses::cpu0.itb.walker 5654 # number of demand (read+write) accesses
2843system.l2c.demand_accesses::cpu0.inst 453877 # number of demand (read+write) accesses
2844system.l2c.demand_accesses::cpu0.data 803274 # number of demand (read+write) accesses
2845system.l2c.demand_accesses::cpu0.l2cache.prefetcher 522297 # number of demand (read+write) accesses
2846system.l2c.demand_accesses::cpu1.dtb.walker 7745 # number of demand (read+write) accesses
2847system.l2c.demand_accesses::cpu1.itb.walker 7142 # number of demand (read+write) accesses
2848system.l2c.demand_accesses::cpu1.inst 463801 # number of demand (read+write) accesses
2849system.l2c.demand_accesses::cpu1.data 737403 # number of demand (read+write) accesses
2850system.l2c.demand_accesses::cpu1.l2cache.prefetcher 452053 # number of demand (read+write) accesses
2851system.l2c.demand_accesses::total 3459981 # number of demand (read+write) accesses
2852system.l2c.overall_accesses::cpu0.dtb.walker 6735 # number of overall (read+write) accesses
2853system.l2c.overall_accesses::cpu0.itb.walker 5654 # number of overall (read+write) accesses
2854system.l2c.overall_accesses::cpu0.inst 453877 # number of overall (read+write) accesses
2855system.l2c.overall_accesses::cpu0.data 803274 # number of overall (read+write) accesses
2856system.l2c.overall_accesses::cpu0.l2cache.prefetcher 522297 # number of overall (read+write) accesses
2857system.l2c.overall_accesses::cpu1.dtb.walker 7745 # number of overall (read+write) accesses
2858system.l2c.overall_accesses::cpu1.itb.walker 7142 # number of overall (read+write) accesses
2859system.l2c.overall_accesses::cpu1.inst 463801 # number of overall (read+write) accesses
2860system.l2c.overall_accesses::cpu1.data 737403 # number of overall (read+write) accesses
2861system.l2c.overall_accesses::cpu1.l2cache.prefetcher 452053 # number of overall (read+write) accesses
2862system.l2c.overall_accesses::total 3459981 # number of overall (read+write) accesses
2863system.l2c.UpgradeReq_miss_rate::cpu0.data 0.281261 # miss rate for UpgradeReq accesses
2864system.l2c.UpgradeReq_miss_rate::cpu1.data 0.315767 # miss rate for UpgradeReq accesses
2865system.l2c.UpgradeReq_miss_rate::total 0.297398 # miss rate for UpgradeReq accesses
2866system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.256383 # miss rate for SCUpgradeReq accesses
2867system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.267881 # miss rate for SCUpgradeReq accesses
2868system.l2c.SCUpgradeReq_miss_rate::total 0.262106 # miss rate for SCUpgradeReq accesses
2869system.l2c.ReadExReq_miss_rate::cpu0.data 0.636223 # miss rate for ReadExReq accesses
2870system.l2c.ReadExReq_miss_rate::cpu1.data 0.466619 # miss rate for ReadExReq accesses
2871system.l2c.ReadExReq_miss_rate::total 0.558420 # miss rate for ReadExReq accesses
2872system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for ReadSharedReq accesses
2873system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.350195 # miss rate for ReadSharedReq accesses
2874system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100322 # miss rate for ReadSharedReq accesses
2875system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200020 # miss rate for ReadSharedReq accesses
2876system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for ReadSharedReq accesses
2877system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for ReadSharedReq accesses
2878system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230468 # miss rate for ReadSharedReq accesses
2879system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.094653 # miss rate for ReadSharedReq accesses
2880system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.156134 # miss rate for ReadSharedReq accesses
2881system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for ReadSharedReq accesses
2882system.l2c.ReadSharedReq_miss_rate::total 0.231941 # miss rate for ReadSharedReq accesses
2883system.l2c.InvalidateReq_miss_rate::cpu0.data 0.791527 # miss rate for InvalidateReq accesses
2884system.l2c.InvalidateReq_miss_rate::cpu1.data 0.489286 # miss rate for InvalidateReq accesses
2885system.l2c.InvalidateReq_miss_rate::total 0.701201 # miss rate for InvalidateReq accesses
2886system.l2c.demand_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for demand accesses
2887system.l2c.demand_miss_rate::cpu0.itb.walker 0.350195 # miss rate for demand accesses
2888system.l2c.demand_miss_rate::cpu0.inst 0.100322 # miss rate for demand accesses
2889system.l2c.demand_miss_rate::cpu0.data 0.269688 # miss rate for demand accesses
2890system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for demand accesses
2891system.l2c.demand_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for demand accesses
2892system.l2c.demand_miss_rate::cpu1.itb.walker 0.230468 # miss rate for demand accesses
2893system.l2c.demand_miss_rate::cpu1.inst 0.094653 # miss rate for demand accesses
2894system.l2c.demand_miss_rate::cpu1.data 0.201915 # miss rate for demand accesses
2895system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for demand accesses
2896system.l2c.demand_miss_rate::total 0.254307 # miss rate for demand accesses
2897system.l2c.overall_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for overall accesses
2898system.l2c.overall_miss_rate::cpu0.itb.walker 0.350195 # miss rate for overall accesses
2899system.l2c.overall_miss_rate::cpu0.inst 0.100322 # miss rate for overall accesses
2900system.l2c.overall_miss_rate::cpu0.data 0.269688 # miss rate for overall accesses
2901system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for overall accesses
2902system.l2c.overall_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for overall accesses
2903system.l2c.overall_miss_rate::cpu1.itb.walker 0.230468 # miss rate for overall accesses
2904system.l2c.overall_miss_rate::cpu1.inst 0.094653 # miss rate for overall accesses
2905system.l2c.overall_miss_rate::cpu1.data 0.201915 # miss rate for overall accesses
2906system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for overall accesses
2907system.l2c.overall_miss_rate::total 0.254307 # miss rate for overall accesses
2908system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6345.316258 # average UpgradeReq miss latency
2909system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6156.513142 # average UpgradeReq miss latency
2910system.l2c.UpgradeReq_avg_miss_latency::total 6251.568931 # average UpgradeReq miss latency
2911system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5209.807967 # average SCUpgradeReq miss latency
2912system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5876.044141 # average SCUpgradeReq miss latency
2913system.l2c.SCUpgradeReq_avg_miss_latency::total 5548.731044 # average SCUpgradeReq miss latency
2914system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87421.014910 # average ReadExReq miss latency
2915system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83583.234784 # average ReadExReq miss latency
2916system.l2c.ReadExReq_avg_miss_latency::total 85949.912737 # average ReadExReq miss latency
2917system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average ReadSharedReq miss latency
2918system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89391.414141 # average ReadSharedReq miss latency
2919system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85717.387008 # average ReadSharedReq miss latency
2920system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88534.615954 # average ReadSharedReq miss latency
2921system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average ReadSharedReq miss latency
2922system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average ReadSharedReq miss latency
2923system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 91794.046173 # average ReadSharedReq miss latency
2924system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85590.763098 # average ReadSharedReq miss latency
2925system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91762.976660 # average ReadSharedReq miss latency
2926system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average ReadSharedReq miss latency
2927system.l2c.ReadSharedReq_avg_miss_latency::total 106005.617690 # average ReadSharedReq miss latency
2928system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 124.974208 # average InvalidateReq miss latency
2929system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 374.400947 # average InvalidateReq miss latency
2930system.l2c.InvalidateReq_avg_miss_latency::total 176.988346 # average InvalidateReq miss latency
2931system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average overall miss latency
2932system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89391.414141 # average overall miss latency
2933system.l2c.demand_avg_miss_latency::cpu0.inst 85717.387008 # average overall miss latency
2934system.l2c.demand_avg_miss_latency::cpu0.data 88115.033259 # average overall miss latency
2935system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average overall miss latency
2936system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average overall miss latency
2937system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91794.046173 # average overall miss latency
2938system.l2c.demand_avg_miss_latency::cpu1.inst 85590.763098 # average overall miss latency
2939system.l2c.demand_avg_miss_latency::cpu1.data 88975.690597 # average overall miss latency
2940system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average overall miss latency
2941system.l2c.demand_avg_miss_latency::total 102988.723589 # average overall miss latency
2942system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87404.887020 # average overall miss latency
2943system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89391.414141 # average overall miss latency
2944system.l2c.overall_avg_miss_latency::cpu0.inst 85717.387008 # average overall miss latency
2945system.l2c.overall_avg_miss_latency::cpu0.data 88115.033259 # average overall miss latency
2946system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 118649.787252 # average overall miss latency
2947system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90227.116705 # average overall miss latency
2948system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91794.046173 # average overall miss latency
2949system.l2c.overall_avg_miss_latency::cpu1.inst 85590.763098 # average overall miss latency
2950system.l2c.overall_avg_miss_latency::cpu1.data 88975.690597 # average overall miss latency
2951system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120997.913402 # average overall miss latency
2952system.l2c.overall_avg_miss_latency::total 102988.723589 # average overall miss latency
2953system.l2c.blocked_cycles::no_mshrs 494 # number of cycles access was blocked
2954system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2955system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2956system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2957system.l2c.avg_blocked_cycles::no_mshrs 54.888889 # average number of cycles each access was blocked
2958system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2959system.l2c.writebacks::writebacks 1068061 # number of writebacks
2960system.l2c.writebacks::total 1068061 # number of writebacks
2961system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 54 # number of ReadSharedReq MSHR hits
2962system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits
2963system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 49 # number of ReadSharedReq MSHR hits
2964system.l2c.ReadSharedReq_mshr_hits::cpu1.data 43 # number of ReadSharedReq MSHR hits
2965system.l2c.ReadSharedReq_mshr_hits::total 165 # number of ReadSharedReq MSHR hits
2966system.l2c.demand_mshr_hits::cpu0.inst 54 # number of demand (read+write) MSHR hits
2967system.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits
2968system.l2c.demand_mshr_hits::cpu1.inst 49 # number of demand (read+write) MSHR hits
2969system.l2c.demand_mshr_hits::cpu1.data 43 # number of demand (read+write) MSHR hits
2970system.l2c.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
2971system.l2c.overall_mshr_hits::cpu0.inst 54 # number of overall MSHR hits
2972system.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits
2973system.l2c.overall_mshr_hits::cpu1.inst 49 # number of overall MSHR hits
2974system.l2c.overall_mshr_hits::cpu1.data 43 # number of overall MSHR hits
2975system.l2c.overall_mshr_hits::total 165 # number of overall MSHR hits
2976system.l2c.CleanEvict_mshr_misses::writebacks 48108 # number of CleanEvict MSHR misses
2977system.l2c.CleanEvict_mshr_misses::total 48108 # number of CleanEvict MSHR misses
2978system.l2c.UpgradeReq_mshr_misses::cpu0.data 61532 # number of UpgradeReq MSHR misses
2979system.l2c.UpgradeReq_mshr_misses::cpu1.data 60685 # number of UpgradeReq MSHR misses
2980system.l2c.UpgradeReq_mshr_misses::total 122217 # number of UpgradeReq MSHR misses
2981system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12602 # number of SCUpgradeReq MSHR misses
2982system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 13049 # number of SCUpgradeReq MSHR misses
2983system.l2c.SCUpgradeReq_mshr_misses::total 25651 # number of SCUpgradeReq MSHR misses
2984system.l2c.ReadExReq_mshr_misses::cpu0.data 81623 # number of ReadExReq MSHR misses
2985system.l2c.ReadExReq_mshr_misses::cpu1.data 50736 # number of ReadExReq MSHR misses
2986system.l2c.ReadExReq_mshr_misses::total 132359 # number of ReadExReq MSHR misses
2987system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq MSHR misses
2988system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1980 # number of ReadSharedReq MSHR misses
2989system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45480 # number of ReadSharedReq MSHR misses
2990system.l2c.ReadSharedReq_mshr_misses::cpu0.data 134991 # number of ReadSharedReq MSHR misses
2991system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq MSHR misses
2992system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq MSHR misses
2993system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1646 # number of ReadSharedReq MSHR misses
2994system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 43851 # number of ReadSharedReq MSHR misses
2995system.l2c.ReadSharedReq_mshr_misses::cpu1.data 98114 # number of ReadSharedReq MSHR misses
2996system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq MSHR misses
2997system.l2c.ReadSharedReq_mshr_misses::total 747372 # number of ReadSharedReq MSHR misses
2998system.l2c.InvalidateReq_mshr_misses::cpu0.data 445868 # number of InvalidateReq MSHR misses
2999system.l2c.InvalidateReq_mshr_misses::cpu1.data 117477 # number of InvalidateReq MSHR misses
3000system.l2c.InvalidateReq_mshr_misses::total 563345 # number of InvalidateReq MSHR misses
3001system.l2c.demand_mshr_misses::cpu0.dtb.walker 1903 # number of demand (read+write) MSHR misses
3002system.l2c.demand_mshr_misses::cpu0.itb.walker 1980 # number of demand (read+write) MSHR misses
3003system.l2c.demand_mshr_misses::cpu0.inst 45480 # number of demand (read+write) MSHR misses
3004system.l2c.demand_mshr_misses::cpu0.data 216614 # number of demand (read+write) MSHR misses
3005system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) MSHR misses
3006system.l2c.demand_mshr_misses::cpu1.dtb.walker 1748 # number of demand (read+write) MSHR misses
3007system.l2c.demand_mshr_misses::cpu1.itb.walker 1646 # number of demand (read+write) MSHR misses
3008system.l2c.demand_mshr_misses::cpu1.inst 43851 # number of demand (read+write) MSHR misses
3009system.l2c.demand_mshr_misses::cpu1.data 148850 # number of demand (read+write) MSHR misses
3010system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) MSHR misses
3011system.l2c.demand_mshr_misses::total 879731 # number of demand (read+write) MSHR misses
3012system.l2c.overall_mshr_misses::cpu0.dtb.walker 1903 # number of overall MSHR misses
3013system.l2c.overall_mshr_misses::cpu0.itb.walker 1980 # number of overall MSHR misses
3014system.l2c.overall_mshr_misses::cpu0.inst 45480 # number of overall MSHR misses
3015system.l2c.overall_mshr_misses::cpu0.data 216614 # number of overall MSHR misses
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3017system.l2c.overall_mshr_misses::cpu1.dtb.walker 1748 # number of overall MSHR misses
3018system.l2c.overall_mshr_misses::cpu1.itb.walker 1646 # number of overall MSHR misses
3019system.l2c.overall_mshr_misses::cpu1.inst 43851 # number of overall MSHR misses
3020system.l2c.overall_mshr_misses::cpu1.data 148850 # number of overall MSHR misses
3021system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 176782 # number of overall MSHR misses
3022system.l2c.overall_mshr_misses::total 879731 # number of overall MSHR misses
3023system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
3024system.l2c.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable
3025system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
3026system.l2c.ReadReq_mshr_uncacheable::cpu1.data 11019 # number of ReadReq MSHR uncacheable
3027system.l2c.ReadReq_mshr_uncacheable::total 81829 # number of ReadReq MSHR uncacheable
3028system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable
3029system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable
3030system.l2c.WriteReq_mshr_uncacheable::total 38464 # number of WriteReq MSHR uncacheable
3031system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
3032system.l2c.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses
3033system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
3034system.l2c.overall_mshr_uncacheable_misses::cpu1.data 22943 # number of overall MSHR uncacheable misses
3035system.l2c.overall_mshr_uncacheable_misses::total 120293 # number of overall MSHR uncacheable misses
3036system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1338948000 # number of UpgradeReq MSHR miss cycles
3037system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1324584000 # number of UpgradeReq MSHR miss cycles
3038system.l2c.UpgradeReq_mshr_miss_latency::total 2663532000 # number of UpgradeReq MSHR miss cycles
3039system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 312012000 # number of SCUpgradeReq MSHR miss cycles
3040system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 323877000 # number of SCUpgradeReq MSHR miss cycles
3041system.l2c.SCUpgradeReq_mshr_miss_latency::total 635889000 # number of SCUpgradeReq MSHR miss cycles
3042system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6319298576 # number of ReadExReq MSHR miss cycles
3043system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3733266108 # number of ReadExReq MSHR miss cycles
3044system.l2c.ReadExReq_mshr_miss_latency::total 10052564684 # number of ReadExReq MSHR miss cycles
3045system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of ReadSharedReq MSHR miss cycles
3046system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 157194002 # number of ReadSharedReq MSHR miss cycles
3047system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 3443824526 # number of ReadSharedReq MSHR miss cycles
3048system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10601706692 # number of ReadSharedReq MSHR miss cycles
3049system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of ReadSharedReq MSHR miss cycles
3050system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of ReadSharedReq MSHR miss cycles
3051system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 134631004 # number of ReadSharedReq MSHR miss cycles
3052system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3315499572 # number of ReadSharedReq MSHR miss cycles
3053system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8022481292 # number of ReadSharedReq MSHR miss cycles
3054system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of ReadSharedReq MSHR miss cycles
3055system.l2c.ReadSharedReq_mshr_miss_latency::total 71756096476 # number of ReadSharedReq MSHR miss cycles
3056system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8904054000 # number of InvalidateReq MSHR miss cycles
3057system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2392104000 # number of InvalidateReq MSHR miss cycles
3058system.l2c.InvalidateReq_mshr_miss_latency::total 11296158000 # number of InvalidateReq MSHR miss cycles
3059system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of demand (read+write) MSHR miss cycles
3060system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 157194002 # number of demand (read+write) MSHR miss cycles
3061system.l2c.demand_mshr_miss_latency::cpu0.inst 3443824526 # number of demand (read+write) MSHR miss cycles
3062system.l2c.demand_mshr_miss_latency::cpu0.data 16921005268 # number of demand (read+write) MSHR miss cycles
3063system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of demand (read+write) MSHR miss cycles
3064system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of demand (read+write) MSHR miss cycles
3065system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 134631004 # number of demand (read+write) MSHR miss cycles
3066system.l2c.demand_mshr_miss_latency::cpu1.inst 3315499572 # number of demand (read+write) MSHR miss cycles
3067system.l2c.demand_mshr_miss_latency::cpu1.data 11755747400 # number of demand (read+write) MSHR miss cycles
3068system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of demand (read+write) MSHR miss cycles
3069system.l2c.demand_mshr_miss_latency::total 81808661160 # number of demand (read+write) MSHR miss cycles
3070system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 147301500 # number of overall MSHR miss cycles
3071system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 157194002 # number of overall MSHR miss cycles
3072system.l2c.overall_mshr_miss_latency::cpu0.inst 3443824526 # number of overall MSHR miss cycles
3073system.l2c.overall_mshr_miss_latency::cpu0.data 16921005268 # number of overall MSHR miss cycles
3074system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26171043713 # number of overall MSHR miss cycles
3075system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 140235503 # number of overall MSHR miss cycles
3076system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 134631004 # number of overall MSHR miss cycles
3077system.l2c.overall_mshr_miss_latency::cpu1.inst 3315499572 # number of overall MSHR miss cycles
3078system.l2c.overall_mshr_miss_latency::cpu1.data 11755747400 # number of overall MSHR miss cycles
3079system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19622178672 # number of overall MSHR miss cycles
3080system.l2c.overall_mshr_miss_latency::total 81808661160 # number of overall MSHR miss cycles
3081system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of ReadReq MSHR uncacheable cycles
3082system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4354335503 # number of ReadReq MSHR uncacheable cycles
3083system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7420500 # number of ReadReq MSHR uncacheable cycles
3084system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1601314002 # number of ReadReq MSHR uncacheable cycles
3085system.l2c.ReadReq_mshr_uncacheable_latency::total 8682852005 # number of ReadReq MSHR uncacheable cycles
3086system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2719782000 # number of overall MSHR uncacheable cycles
3087system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4354335503 # number of overall MSHR uncacheable cycles
3088system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7420500 # number of overall MSHR uncacheable cycles
3089system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1601314002 # number of overall MSHR uncacheable cycles
3090system.l2c.overall_mshr_uncacheable_latency::total 8682852005 # number of overall MSHR uncacheable cycles
3091system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3092system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3093system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.281261 # mshr miss rate for UpgradeReq accesses
3094system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315767 # mshr miss rate for UpgradeReq accesses
3095system.l2c.UpgradeReq_mshr_miss_rate::total 0.297398 # mshr miss rate for UpgradeReq accesses
3096system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.256383 # mshr miss rate for SCUpgradeReq accesses
3097system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.267881 # mshr miss rate for SCUpgradeReq accesses
3098system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.262106 # mshr miss rate for SCUpgradeReq accesses
3099system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.636223 # mshr miss rate for ReadExReq accesses
3100system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466619 # mshr miss rate for ReadExReq accesses
3101system.l2c.ReadExReq_mshr_miss_rate::total 0.558420 # mshr miss rate for ReadExReq accesses
3102system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for ReadSharedReq accesses
3103system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for ReadSharedReq accesses
3104system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for ReadSharedReq accesses
3105system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199992 # mshr miss rate for ReadSharedReq accesses
3106system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for ReadSharedReq accesses
3107system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for ReadSharedReq accesses
3108system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for ReadSharedReq accesses
3109system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for ReadSharedReq accesses
3110system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.156065 # mshr miss rate for ReadSharedReq accesses
3111system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for ReadSharedReq accesses
3112system.l2c.ReadSharedReq_mshr_miss_rate::total 0.231890 # mshr miss rate for ReadSharedReq accesses
3113system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.791527 # mshr miss rate for InvalidateReq accesses
3114system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489286 # mshr miss rate for InvalidateReq accesses
3115system.l2c.InvalidateReq_mshr_miss_rate::total 0.701201 # mshr miss rate for InvalidateReq accesses
3116system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for demand accesses
3117system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for demand accesses
3118system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for demand accesses
3119system.l2c.demand_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for demand accesses
3120system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for demand accesses
3121system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for demand accesses
3122system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for demand accesses
3123system.l2c.demand_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for demand accesses
3124system.l2c.demand_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for demand accesses
3125system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for demand accesses
3126system.l2c.demand_mshr_miss_rate::total 0.254259 # mshr miss rate for demand accesses
3127system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.282554 # mshr miss rate for overall accesses
3128system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.350195 # mshr miss rate for overall accesses
3129system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100203 # mshr miss rate for overall accesses
3130system.l2c.overall_mshr_miss_rate::cpu0.data 0.269664 # mshr miss rate for overall accesses
3131system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.461188 # mshr miss rate for overall accesses
3132system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.225694 # mshr miss rate for overall accesses
3133system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230468 # mshr miss rate for overall accesses
3134system.l2c.overall_mshr_miss_rate::cpu1.inst 0.094547 # mshr miss rate for overall accesses
3135system.l2c.overall_mshr_miss_rate::cpu1.data 0.201857 # mshr miss rate for overall accesses
3136system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.391065 # mshr miss rate for overall accesses
3137system.l2c.overall_mshr_miss_rate::total 0.254259 # mshr miss rate for overall accesses
3138system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21760.189820 # average UpgradeReq mshr miss latency
3139system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21827.206064 # average UpgradeReq mshr miss latency
3140system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21793.465721 # average UpgradeReq mshr miss latency
3141system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24758.927154 # average SCUpgradeReq mshr miss latency
3142system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24820.062840 # average SCUpgradeReq mshr miss latency
3143system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24790.027679 # average SCUpgradeReq mshr miss latency
3144system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77420.562538 # average ReadExReq mshr miss latency
3145system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73582.192289 # average ReadExReq mshr miss latency
3146system.l2c.ReadExReq_avg_mshr_miss_latency::total 75949.234159 # average ReadExReq mshr miss latency
3147system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average ReadSharedReq mshr miss latency
3148system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average ReadSharedReq mshr miss latency
3149system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average ReadSharedReq mshr miss latency
3150system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78536.396441 # average ReadSharedReq mshr miss latency
3151system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average ReadSharedReq mshr miss latency
3152system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average ReadSharedReq mshr miss latency
3153system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average ReadSharedReq mshr miss latency
3154system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average ReadSharedReq mshr miss latency
3155system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81766.937359 # average ReadSharedReq mshr miss latency
3156system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average ReadSharedReq mshr miss latency
3157system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96011.218611 # average ReadSharedReq mshr miss latency
3158system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19970.157087 # average InvalidateReq mshr miss latency
3159system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20362.317730 # average InvalidateReq mshr miss latency
3160system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20051.936203 # average InvalidateReq mshr miss latency
3161system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency
3162system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency
3163system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency
3164system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency
3165system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency
3166system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency
3167system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency
3168system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency
3169system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency
3170system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency
3171system.l2c.demand_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency
3172system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77404.887020 # average overall mshr miss latency
3173system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79390.910101 # average overall mshr miss latency
3174system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75721.735400 # average overall mshr miss latency
3175system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78115.935572 # average overall mshr miss latency
3176system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 108648.993939 # average overall mshr miss latency
3177system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80226.260297 # average overall mshr miss latency
3178system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81792.833536 # average overall mshr miss latency
3179system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75608.300198 # average overall mshr miss latency
3180system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78977.140746 # average overall mshr miss latency
3181system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110996.474030 # average overall mshr miss latency
3182system.l2c.overall_avg_mshr_miss_latency::total 92992.813894 # average overall mshr miss latency
3183system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency
3184system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency
3185system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency
3186system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency
3187system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency
3188system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency
3189system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency
3190system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency
3191system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency
3192system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency
3193system.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter.
3194system.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3195system.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3196system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3197system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3198system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3199system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3200system.membus.trans_dist::ReadReq 81829 # Transaction distribution
3201system.membus.trans_dist::ReadResp 838129 # Transaction distribution
3202system.membus.trans_dist::WriteReq 38464 # Transaction distribution
3203system.membus.trans_dist::WriteResp 38464 # Transaction distribution
3204system.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution
3205system.membus.trans_dist::CleanEvict 216961 # Transaction distribution
3206system.membus.trans_dist::UpgradeReq 398327 # Transaction distribution
3207system.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution
3208system.membus.trans_dist::UpgradeResp 22 # Transaction distribution
3209system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
3210system.membus.trans_dist::ReadExReq 145872 # Transaction distribution
3211system.membus.trans_dist::ReadExResp 127949 # Transaction distribution
3212system.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution
3213system.membus.trans_dist::InvalidateReq 666856 # Transaction distribution
3214system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes)
3215system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3216system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes)
3217system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes)
3218system.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes)
3219system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes)
3220system.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes)
3221system.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes)
3222system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes)
3223system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3224system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes)
3225system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes)
3226system.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes)
3227system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes)
3228system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes)
3229system.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes)
3230system.membus.snoops 572885 # Total snoops (count)
3231system.membus.snoopTraffic 188480 # Total snoop traffic (bytes)
3232system.membus.snoop_fanout::samples 2396814 # Request fanout histogram
3233system.membus.snoop_fanout::mean 0.013654 # Request fanout histogram
3234system.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram
3235system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3236system.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram
3237system.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram
3238system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3239system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3240system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3241system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3242system.membus.snoop_fanout::total 2396814 # Request fanout histogram
3243system.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks)
3244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3245system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3246system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3247system.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks)
3248system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3249system.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks)
3250system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3251system.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks)
3252system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3253system.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks)
3254system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3255system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3256system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3257system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3258system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3259system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3260system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3261system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3262system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3263system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3264system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3265system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3266system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3267system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3268system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3269system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3270system.realview.ethernet.txBytes 966 # Bytes Transmitted
3271system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3272system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3273system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3274system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3275system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3276system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3277system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

--- 26 unchanged lines hidden (view full) ---

3304system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3305system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3306system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3307system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3308system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3309system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3310system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3311system.realview.ethernet.droppedPackets 0 # number of packets dropped
3312system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3313system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3314system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3315system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3316system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3317system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3318system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3319system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3320system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3321system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3322system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3323system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3324system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3325system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3326system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3327system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3328system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3329system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3330system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3331system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3332system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3333system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3334system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3335system.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter.
3336system.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3337system.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3338system.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter.
3339system.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3340system.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3341system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states
3342system.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution
3343system.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution
3344system.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution
3345system.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution
3346system.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution
3347system.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution
3348system.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution
3349system.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution
3350system.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution
3351system.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution
3352system.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution
3353system.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution
3354system.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution
3355system.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution
3356system.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution
3357system.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution
3358system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes)
3359system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes)
3360system.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes)
3361system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes)
3362system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes)
3363system.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes)
3364system.toL2Bus.snoops 2716758 # Total snoops (count)
3365system.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes)
3366system.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram
3367system.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram
3368system.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram
3369system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3370system.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram
3371system.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram
3372system.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram
3373system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3374system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3375system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3376system.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram
3377system.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks)
3378system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3379system.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks)
3380system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3381system.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks)
3382system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3383system.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks)
3384system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3385
3386---------- End Simulation Statistics ----------