1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.367818 # Number of seconds simulated
4sim_ticks 47367817574000 # Number of ticks simulated
5final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 678056 # Simulator instruction rate (inst/s)
8host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
10host_mem_usage 751768 # Number of bytes of host memory used
11host_seconds 1245.10 # Real time elapsed on the host
12sim_insts 844246943 # Number of instructions simulated
13sim_ops 993804803 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory
27system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 684685 # Number of read requests accepted
84system.physmem.writeReqs 1596629 # Number of write requests accepted
85system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue
89system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 42136 # Per bank write bursts
96system.physmem.perBankRdBursts::1 44080 # Per bank write bursts
97system.physmem.perBankRdBursts::2 34958 # Per bank write bursts
98system.physmem.perBankRdBursts::3 41288 # Per bank write bursts
99system.physmem.perBankRdBursts::4 39326 # Per bank write bursts
100system.physmem.perBankRdBursts::5 49165 # Per bank write bursts
101system.physmem.perBankRdBursts::6 40428 # Per bank write bursts
102system.physmem.perBankRdBursts::7 47118 # Per bank write bursts
103system.physmem.perBankRdBursts::8 36254 # Per bank write bursts
104system.physmem.perBankRdBursts::9 81044 # Per bank write bursts
105system.physmem.perBankRdBursts::10 36070 # Per bank write bursts
106system.physmem.perBankRdBursts::11 40557 # Per bank write bursts
107system.physmem.perBankRdBursts::12 34453 # Per bank write bursts
108system.physmem.perBankRdBursts::13 38158 # Per bank write bursts
109system.physmem.perBankRdBursts::14 37145 # Per bank write bursts
110system.physmem.perBankRdBursts::15 42231 # Per bank write bursts
111system.physmem.perBankWrBursts::0 97165 # Per bank write bursts
112system.physmem.perBankWrBursts::1 99476 # Per bank write bursts
113system.physmem.perBankWrBursts::2 95543 # Per bank write bursts
114system.physmem.perBankWrBursts::3 98326 # Per bank write bursts
115system.physmem.perBankWrBursts::4 92692 # Per bank write bursts
116system.physmem.perBankWrBursts::5 102230 # Per bank write bursts
117system.physmem.perBankWrBursts::6 96747 # Per bank write bursts
118system.physmem.perBankWrBursts::7 98806 # Per bank write bursts
119system.physmem.perBankWrBursts::8 93672 # Per bank write bursts
120system.physmem.perBankWrBursts::9 100275 # Per bank write bursts
121system.physmem.perBankWrBursts::10 92352 # Per bank write bursts
122system.physmem.perBankWrBursts::11 96579 # Per bank write bursts
123system.physmem.perBankWrBursts::12 94667 # Per bank write bursts
124system.physmem.perBankWrBursts::13 97213 # Per bank write bursts
125system.physmem.perBankWrBursts::14 92658 # Per bank write bursts
126system.physmem.perBankWrBursts::15 99164 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 352 # Number of times write queue was full causing retry
129system.physmem.totGap 47367814519500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 43195 # Read request sizes (log2)
133system.physmem.readPktSize::3 37 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 641448 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2601 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1594026 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see

--- 9 unchanged lines hidden (view full) ---

183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
305system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads
306system.physmem.totQLat 20326500723 # Total ticks spent queuing
307system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
308system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
309system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
310system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
311system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
312system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
313system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
314system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
315system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
316system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
317system.physmem.busUtil 0.02 # Data bus utilization in percentage
318system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
319system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
320system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
321system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
322system.physmem.readRowHits 509481 # Number of row buffer hits during reads
323system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
324system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
325system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
326system.physmem.avgGap 20763390.98 # Average gap between requests
327system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
328system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
329system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
330system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
331system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
332system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
333system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
334system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
335system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
336system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
337system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
338system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
339system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
340system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
341system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
342system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
343system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
344system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
345system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
346system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
347system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
348system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
349system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
350system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
351system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
352system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
353system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
354system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
355system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
356system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
359system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
360system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
361system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
362system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory

--- 47 unchanged lines hidden (view full) ---

410system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
411system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
412system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
413system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
414system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
415system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
416system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
417system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
418system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
419system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
420system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
421system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
422system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
423system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
449system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
450system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
451system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.inst_hits 0 # ITB inst hits
459system.cpu0.dtb.inst_misses 0 # ITB inst misses
460system.cpu0.dtb.read_hits 81219280 # DTB read hits
461system.cpu0.dtb.read_misses 71070 # DTB read misses
462system.cpu0.dtb.write_hits 73504932 # DTB write hits
463system.cpu0.dtb.write_misses 24397 # DTB write misses
464system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
465system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
466system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
467system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
468system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
469system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
470system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
471system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
472system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
473system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
474system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
475system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
476system.cpu0.dtb.hits 154724212 # DTB hits
477system.cpu0.dtb.misses 95467 # DTB misses
478system.cpu0.dtb.accesses 154819679 # DTB accesses
479system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

500system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
501system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
502system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
503system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
504system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
505system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
506system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
507system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
508system.cpu0.itb.walker.walks 56383 # Table walker walks requested
509system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
510system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
511system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
512system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
513system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
516system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
517system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution
534system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution
535system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution
536system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
537system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
538system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
539system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
540system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
541system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
542system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
543system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
544system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
545system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
546system.cpu0.itb.inst_hits 434853798 # ITB inst hits
547system.cpu0.itb.inst_misses 56383 # ITB inst misses
548system.cpu0.itb.read_hits 0 # DTB read hits
549system.cpu0.itb.read_misses 0 # DTB read misses
550system.cpu0.itb.write_hits 0 # DTB write hits
551system.cpu0.itb.write_misses 0 # DTB write misses
552system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
553system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
554system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
555system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
556system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
557system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
558system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
559system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
560system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
561system.cpu0.itb.read_accesses 0 # DTB read accesses
562system.cpu0.itb.write_accesses 0 # DTB write accesses
563system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
564system.cpu0.itb.hits 434853798 # DTB hits
565system.cpu0.itb.misses 56383 # DTB misses
566system.cpu0.itb.accesses 434910181 # DTB accesses
567system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
568system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
569system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
570system.cpu0.committedInsts 434594659 # Number of instructions committed
571system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
572system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
573system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
574system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
575system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
576system.cpu0.num_int_insts 468245604 # number of integer instructions
577system.cpu0.num_fp_insts 368958 # number of float instructions
578system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
579system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
580system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
581system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
582system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
583system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
584system.cpu0.num_mem_refs 154715442 # number of memory refs
585system.cpu0.num_load_insts 81215665 # Number of load instructions
586system.cpu0.num_store_insts 73499777 # Number of store instructions
587system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
588system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
589system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
590system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
591system.cpu0.Branches 96525602 # Number of branches fetched
592system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
593system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
594system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
595system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
596system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
597system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
598system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
599system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
600system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
601system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
602system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
603system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
604system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
605system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
606system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
607system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
608system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
609system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
610system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
611system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
612system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
613system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
614system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
615system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
616system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
617system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
618system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
619system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
620system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
621system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
622system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
623system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
624system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
625system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
626system.cpu0.op_class::total 510121531 # Class of executed instruction
627system.cpu0.kern.inst.arm 0 # number of arm instructions executed
628system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
629system.cpu0.dcache.tags.replacements 5284481 # number of replacements
630system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
631system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
632system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
633system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
634system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
635system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
636system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
637system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
638system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
639system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
640system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
641system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
642system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
643system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
644system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
645system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
646system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
647system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits
648system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits
649system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits
650system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits
651system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits
652system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
653system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
654system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
655system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits
656system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
657system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits
658system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits
659system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits
660system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits
661system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses
662system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses
663system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses
664system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses
665system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses
666system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses
667system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses
668system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses
669system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses
670system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses
671system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses
672system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses
673system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses
674system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses
675system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses
676system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses
677system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles
678system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles
679system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles
680system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles
681system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles
682system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles
683system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles
684system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles
685system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles
686system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles
687system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles
688system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles
689system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles
690system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles
691system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles
692system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles
693system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses)
694system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses)
695system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses)
696system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses)
697system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses)
698system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses)
699system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses)
700system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses)
701system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses)
702system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses)
703system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses)
704system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses)
705system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses
706system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses
707system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses
708system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses
709system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses
710system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses
711system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses
712system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses
713system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses
714system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses
715system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses
716system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses
717system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses
718system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses
719system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses
720system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses
721system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses
722system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses
723system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
724system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
725system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency
726system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency
727system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency
728system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency
729system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency
730system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency
731system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency
732system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency
733system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency
734system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency
735system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
736system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
737system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency
738system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency
739system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency
740system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency
741system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
742system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
743system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
744system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
745system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
746system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
747system.cpu0.dcache.fast_writes 0 # number of fast writes performed
748system.cpu0.dcache.cache_copies 0 # number of cache copies performed
749system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks
750system.cpu0.dcache.writebacks::total 3634622 # number of writebacks
751system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits
752system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits
753system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits
754system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits
755system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits
756system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits
757system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits
758system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits
759system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits
760system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits
761system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses
762system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses
763system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses
764system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses
765system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses
766system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses
767system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses
768system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses
769system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses
770system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses
771system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses
772system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses
773system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses
774system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses
775system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses
776system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses
777system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles
778system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles
779system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles
780system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles
781system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles
782system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles
783system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles
784system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles
785system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles
786system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles
787system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles
788system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles
789system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles
790system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles
791system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles
792system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles
793system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles
794system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles
795system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles
796system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles
797system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles
798system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles
799system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles
800system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles
801system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses
802system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses
803system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses
804system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses
805system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses
806system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses
807system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses
808system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses
809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses
810system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses
811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses
812system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses
813system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses
814system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses
815system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses
816system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses
817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency
818system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency
819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency
820system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency
821system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency
822system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency
823system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency
824system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency
825system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency
826system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency
827system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency
828system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency
829system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
830system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
831system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency
832system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency
833system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency
834system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency
835system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
836system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
837system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
838system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
839system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
840system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
841system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
842system.cpu0.icache.tags.replacements 4499955 # number of replacements
843system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use
844system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks.
845system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks.
846system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks.
847system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit.
848system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor
849system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy
850system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
851system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
852system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
853system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
854system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id
855system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
856system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses
857system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses
858system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits
859system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits
860system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits
861system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits
862system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits
863system.cpu0.icache.overall_hits::total 430353331 # number of overall hits
864system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses
865system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses
866system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses
867system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses
868system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses
869system.cpu0.icache.overall_misses::total 4500467 # number of overall misses
870system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles
871system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles
872system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles
873system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles
874system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles
875system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles
876system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses)
877system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses)
878system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses
879system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses
880system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses
881system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses
882system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses
883system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses
884system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses
885system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses
886system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses
887system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses
888system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency
889system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency
890system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
891system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency
892system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
893system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency
894system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
895system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
896system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
897system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
898system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
899system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
900system.cpu0.icache.fast_writes 0 # number of fast writes performed
901system.cpu0.icache.cache_copies 0 # number of cache copies performed
902system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses
903system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses
904system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses
905system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses
906system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses
907system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses
908system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles
909system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles
910system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles
911system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles
912system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles
913system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles
914system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles
915system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles
916system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles
917system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles
918system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses
919system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses
920system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses
921system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses
922system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses
923system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses
924system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency
925system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency
926system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency
927system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency
928system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency
929system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency
930system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
931system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
932system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
933system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
934system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
935system.cpu0.l2cache.prefetcher.num_hwpf_issued 7625512 # number of hwpf issued
936system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified
937system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
938system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
939system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
940system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing
941system.cpu0.l2cache.tags.replacements 2276475 # number of replacements
942system.cpu0.l2cache.tags.tagsinuse 16164.000425 # Cycle average of tags in use
943system.cpu0.l2cache.tags.total_refs 9930056 # Total number of references to valid blocks.
944system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks.
945system.cpu0.l2cache.tags.avg_refs 4.331391 # Average number of references to valid blocks.
946system.cpu0.l2cache.tags.warmup_cycle 5342662500 # Cycle when the warmup percentage was hit.
947system.cpu0.l2cache.tags.occ_blocks::writebacks 7643.384526 # Average occupied blocks per requestor
948system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.376858 # Average occupied blocks per requestor
949system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.669060 # Average occupied blocks per requestor
950system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor
951system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor
952system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1070.606892 # Average occupied blocks per requestor
953system.cpu0.l2cache.tags.occ_percent::writebacks 0.466515 # Average percentage of cache occupancy
954system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003502 # Average percentage of cache occupancy
955system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004618 # Average percentage of cache occupancy
956system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226984 # Average percentage of cache occupancy
957system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219608 # Average percentage of cache occupancy
958system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065345 # Average percentage of cache occupancy
959system.cpu0.l2cache.tags.occ_percent::total 0.986572 # Average percentage of cache occupancy
960system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1394 # Occupied blocks per task id
961system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
962system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id
963system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id
964system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id
965system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id
966system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id
967system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id
968system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id
969system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
970system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
971system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id
972system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id
973system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id
974system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id
975system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085083 # Percentage of cache occupancy per task id
976system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
977system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id
978system.cpu0.l2cache.tags.tag_accesses 232158629 # Number of tag accesses
979system.cpu0.l2cache.tags.data_accesses 232158629 # Number of data accesses
980system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 184213 # number of ReadReq hits
981system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122134 # number of ReadReq hits
982system.cpu0.l2cache.ReadReq_hits::cpu0.inst 3989528 # number of ReadReq hits
983system.cpu0.l2cache.ReadReq_hits::cpu0.data 2659243 # number of ReadReq hits
984system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits
985system.cpu0.l2cache.Writeback_hits::writebacks 3634621 # number of Writeback hits
986system.cpu0.l2cache.Writeback_hits::total 3634621 # number of Writeback hits
987system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 174040 # number of WriteInvalidateReq hits
988system.cpu0.l2cache.WriteInvalidateReq_hits::total 174040 # number of WriteInvalidateReq hits
989system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 97614 # number of UpgradeReq hits
990system.cpu0.l2cache.UpgradeReq_hits::total 97614 # number of UpgradeReq hits
991system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30602 # number of SCUpgradeReq hits
992system.cpu0.l2cache.SCUpgradeReq_hits::total 30602 # number of SCUpgradeReq hits
993system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869323 # number of ReadExReq hits
994system.cpu0.l2cache.ReadExReq_hits::total 869323 # number of ReadExReq hits
995system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 184213 # number of demand (read+write) hits
996system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122134 # number of demand (read+write) hits
997system.cpu0.l2cache.demand_hits::cpu0.inst 3989528 # number of demand (read+write) hits
998system.cpu0.l2cache.demand_hits::cpu0.data 3528566 # number of demand (read+write) hits
999system.cpu0.l2cache.demand_hits::total 7824441 # number of demand (read+write) hits
1000system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 184213 # number of overall hits
1001system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122134 # number of overall hits
1002system.cpu0.l2cache.overall_hits::cpu0.inst 3989528 # number of overall hits
1003system.cpu0.l2cache.overall_hits::cpu0.data 3528566 # number of overall hits
1004system.cpu0.l2cache.overall_hits::total 7824441 # number of overall hits
1005system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8450 # number of ReadReq misses
1006system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6821 # number of ReadReq misses
1007system.cpu0.l2cache.ReadReq_misses::cpu0.inst 510939 # number of ReadReq misses
1008system.cpu0.l2cache.ReadReq_misses::cpu0.data 880615 # number of ReadReq misses
1009system.cpu0.l2cache.ReadReq_misses::total 1406825 # number of ReadReq misses
1010system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
1011system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
1012system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570673 # number of WriteInvalidateReq misses
1013system.cpu0.l2cache.WriteInvalidateReq_misses::total 570673 # number of WriteInvalidateReq misses
1014system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121192 # number of UpgradeReq misses
1015system.cpu0.l2cache.UpgradeReq_misses::total 121192 # number of UpgradeReq misses
1016system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 152342 # number of SCUpgradeReq misses
1017system.cpu0.l2cache.SCUpgradeReq_misses::total 152342 # number of SCUpgradeReq misses
1018system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses
1019system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
1020system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228613 # number of ReadExReq misses
1021system.cpu0.l2cache.ReadExReq_misses::total 228613 # number of ReadExReq misses
1022system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8450 # number of demand (read+write) misses
1023system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6821 # number of demand (read+write) misses
1024system.cpu0.l2cache.demand_misses::cpu0.inst 510939 # number of demand (read+write) misses
1025system.cpu0.l2cache.demand_misses::cpu0.data 1109228 # number of demand (read+write) misses
1026system.cpu0.l2cache.demand_misses::total 1635438 # number of demand (read+write) misses
1027system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8450 # number of overall misses
1028system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6821 # number of overall misses
1029system.cpu0.l2cache.overall_misses::cpu0.inst 510939 # number of overall misses
1030system.cpu0.l2cache.overall_misses::cpu0.data 1109228 # number of overall misses
1031system.cpu0.l2cache.overall_misses::total 1635438 # number of overall misses
1032system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 233396250 # number of ReadReq miss cycles
1033system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 201613986 # number of ReadReq miss cycles
1034system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15055870276 # number of ReadReq miss cycles
1035system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 27344253636 # number of ReadReq miss cycles
1036system.cpu0.l2cache.ReadReq_miss_latency::total 42835134148 # number of ReadReq miss cycles
1037system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214216390 # number of WriteInvalidateReq miss cycles
1038system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214216390 # number of WriteInvalidateReq miss cycles
1039system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2669808389 # number of UpgradeReq miss cycles
1040system.cpu0.l2cache.UpgradeReq_miss_latency::total 2669808389 # number of UpgradeReq miss cycles
1041system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3193098671 # number of SCUpgradeReq miss cycles
1042system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3193098671 # number of SCUpgradeReq miss cycles
1043system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1181000 # number of SCUpgradeFailReq miss cycles
1044system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1181000 # number of SCUpgradeFailReq miss cycles
1045system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10520875436 # number of ReadExReq miss cycles
1046system.cpu0.l2cache.ReadExReq_miss_latency::total 10520875436 # number of ReadExReq miss cycles
1047system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 233396250 # number of demand (read+write) miss cycles
1048system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 201613986 # number of demand (read+write) miss cycles
1049system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15055870276 # number of demand (read+write) miss cycles
1050system.cpu0.l2cache.demand_miss_latency::cpu0.data 37865129072 # number of demand (read+write) miss cycles
1051system.cpu0.l2cache.demand_miss_latency::total 53356009584 # number of demand (read+write) miss cycles
1052system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 233396250 # number of overall miss cycles
1053system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 201613986 # number of overall miss cycles
1054system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15055870276 # number of overall miss cycles
1055system.cpu0.l2cache.overall_miss_latency::cpu0.data 37865129072 # number of overall miss cycles
1056system.cpu0.l2cache.overall_miss_latency::total 53356009584 # number of overall miss cycles
1057system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 192663 # number of ReadReq accesses(hits+misses)
1058system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 128955 # number of ReadReq accesses(hits+misses)
1059system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4500467 # number of ReadReq accesses(hits+misses)
1060system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3539858 # number of ReadReq accesses(hits+misses)
1061system.cpu0.l2cache.ReadReq_accesses::total 8361943 # number of ReadReq accesses(hits+misses)
1062system.cpu0.l2cache.Writeback_accesses::writebacks 3634622 # number of Writeback accesses(hits+misses)
1063system.cpu0.l2cache.Writeback_accesses::total 3634622 # number of Writeback accesses(hits+misses)
1064system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 744713 # number of WriteInvalidateReq accesses(hits+misses)
1065system.cpu0.l2cache.WriteInvalidateReq_accesses::total 744713 # number of WriteInvalidateReq accesses(hits+misses)
1066system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218806 # number of UpgradeReq accesses(hits+misses)
1067system.cpu0.l2cache.UpgradeReq_accesses::total 218806 # number of UpgradeReq accesses(hits+misses)
1068system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 182944 # number of SCUpgradeReq accesses(hits+misses)
1069system.cpu0.l2cache.SCUpgradeReq_accesses::total 182944 # number of SCUpgradeReq accesses(hits+misses)
1070system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
1071system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
1072system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1097936 # number of ReadExReq accesses(hits+misses)
1073system.cpu0.l2cache.ReadExReq_accesses::total 1097936 # number of ReadExReq accesses(hits+misses)
1074system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 192663 # number of demand (read+write) accesses
1075system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 128955 # number of demand (read+write) accesses
1076system.cpu0.l2cache.demand_accesses::cpu0.inst 4500467 # number of demand (read+write) accesses
1077system.cpu0.l2cache.demand_accesses::cpu0.data 4637794 # number of demand (read+write) accesses
1078system.cpu0.l2cache.demand_accesses::total 9459879 # number of demand (read+write) accesses
1079system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 192663 # number of overall (read+write) accesses
1080system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 128955 # number of overall (read+write) accesses
1081system.cpu0.l2cache.overall_accesses::cpu0.inst 4500467 # number of overall (read+write) accesses
1082system.cpu0.l2cache.overall_accesses::cpu0.data 4637794 # number of overall (read+write) accesses
1083system.cpu0.l2cache.overall_accesses::total 9459879 # number of overall (read+write) accesses
1084system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for ReadReq accesses
1085system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052894 # miss rate for ReadReq accesses
1086system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.113530 # miss rate for ReadReq accesses
1087system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.248771 # miss rate for ReadReq accesses
1088system.cpu0.l2cache.ReadReq_miss_rate::total 0.168241 # miss rate for ReadReq accesses
1089system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
1090system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
1091system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.766299 # miss rate for WriteInvalidateReq accesses
1092system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.766299 # miss rate for WriteInvalidateReq accesses
1093system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.553879 # miss rate for UpgradeReq accesses
1094system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.553879 # miss rate for UpgradeReq accesses
1095system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832725 # miss rate for SCUpgradeReq accesses
1096system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832725 # miss rate for SCUpgradeReq accesses
1097system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1098system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1099system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.208221 # miss rate for ReadExReq accesses
1100system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208221 # miss rate for ReadExReq accesses
1101system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for demand accesses
1102system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052894 # miss rate for demand accesses
1103system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.113530 # miss rate for demand accesses
1104system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.239171 # miss rate for demand accesses
1105system.cpu0.l2cache.demand_miss_rate::total 0.172881 # miss rate for demand accesses
1106system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for overall accesses
1107system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052894 # miss rate for overall accesses
1108system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.113530 # miss rate for overall accesses
1109system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.239171 # miss rate for overall accesses
1110system.cpu0.l2cache.overall_miss_rate::total 0.172881 # miss rate for overall accesses
1111system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average ReadReq miss latency
1112system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 29557.834042 # average ReadReq miss latency
1113system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29467.060209 # average ReadReq miss latency
1114system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31051.314861 # average ReadReq miss latency
1115system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30448.089953 # average ReadReq miss latency
1116system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.375022 # average WriteInvalidateReq miss latency
1117system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.375022 # average WriteInvalidateReq miss latency
1118system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22029.576119 # average UpgradeReq miss latency
1119system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22029.576119 # average UpgradeReq miss latency
1120system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20960.067946 # average SCUpgradeReq miss latency
1121system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20960.067946 # average SCUpgradeReq miss latency
1122system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 393666.666667 # average SCUpgradeFailReq miss latency
1123system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 393666.666667 # average SCUpgradeFailReq miss latency
1124system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46020.460061 # average ReadExReq miss latency
1125system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46020.460061 # average ReadExReq miss latency
1126system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency
1127system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency
1128system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency
1129system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency
1130system.cpu0.l2cache.demand_avg_miss_latency::total 32624.905123 # average overall miss latency
1131system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency
1132system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency
1133system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency
1134system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency
1135system.cpu0.l2cache.overall_avg_miss_latency::total 32624.905123 # average overall miss latency
1136system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1137system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1138system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1139system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1140system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1141system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1142system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1143system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1144system.cpu0.l2cache.writebacks::writebacks 1283433 # number of writebacks
1145system.cpu0.l2cache.writebacks::total 1283433 # number of writebacks
1146system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 443 # number of ReadReq MSHR hits
1147system.cpu0.l2cache.ReadReq_mshr_hits::total 443 # number of ReadReq MSHR hits
1148system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3351 # number of ReadExReq MSHR hits
1149system.cpu0.l2cache.ReadExReq_mshr_hits::total 3351 # number of ReadExReq MSHR hits
1150system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3794 # number of demand (read+write) MSHR hits
1151system.cpu0.l2cache.demand_mshr_hits::total 3794 # number of demand (read+write) MSHR hits
1152system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3794 # number of overall MSHR hits
1153system.cpu0.l2cache.overall_mshr_hits::total 3794 # number of overall MSHR hits
1154system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8450 # number of ReadReq MSHR misses
1155system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6821 # number of ReadReq MSHR misses
1156system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 510939 # number of ReadReq MSHR misses
1157system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 880172 # number of ReadReq MSHR misses
1158system.cpu0.l2cache.ReadReq_mshr_misses::total 1406382 # number of ReadReq MSHR misses
1159system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
1160system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
1161system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of HardPFReq MSHR misses
1162system.cpu0.l2cache.HardPFReq_mshr_misses::total 635942 # number of HardPFReq MSHR misses
1163system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570673 # number of WriteInvalidateReq MSHR misses
1164system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570673 # number of WriteInvalidateReq MSHR misses
1165system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121192 # number of UpgradeReq MSHR misses
1166system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121192 # number of UpgradeReq MSHR misses
1167system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 152342 # number of SCUpgradeReq MSHR misses
1168system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 152342 # number of SCUpgradeReq MSHR misses
1169system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses
1170system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
1171system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 225262 # number of ReadExReq MSHR misses
1172system.cpu0.l2cache.ReadExReq_mshr_misses::total 225262 # number of ReadExReq MSHR misses
1173system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8450 # number of demand (read+write) MSHR misses
1174system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6821 # number of demand (read+write) MSHR misses
1175system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 510939 # number of demand (read+write) MSHR misses
1176system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1105434 # number of demand (read+write) MSHR misses
1177system.cpu0.l2cache.demand_mshr_misses::total 1631644 # number of demand (read+write) MSHR misses
1178system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8450 # number of overall MSHR misses
1179system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6821 # number of overall MSHR misses
1180system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 510939 # number of overall MSHR misses
1181system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1105434 # number of overall MSHR misses
1182system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of overall MSHR misses
1183system.cpu0.l2cache.overall_mshr_misses::total 2267586 # number of overall MSHR misses
1184system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of ReadReq MSHR miss cycles
1185system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 157112514 # number of ReadReq MSHR miss cycles
1186system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11720586224 # number of ReadReq MSHR miss cycles
1187system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 21558629277 # number of ReadReq MSHR miss cycles
1188system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33614638265 # number of ReadReq MSHR miss cycles
1189system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of HardPFReq MSHR miss cycles
1190system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 23030840367 # number of HardPFReq MSHR miss cycles
1191system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24220184845 # number of WriteInvalidateReq MSHR miss cycles
1192system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24220184845 # number of WriteInvalidateReq MSHR miss cycles
1193system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529730528 # number of UpgradeReq MSHR miss cycles
1194system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529730528 # number of UpgradeReq MSHR miss cycles
1195system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2304861456 # number of SCUpgradeReq MSHR miss cycles
1196system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304861456 # number of SCUpgradeReq MSHR miss cycles
1197system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1005500 # number of SCUpgradeFailReq MSHR miss cycles
1198system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1005500 # number of SCUpgradeFailReq MSHR miss cycles
1199system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8691962659 # number of ReadExReq MSHR miss cycles
1200system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8691962659 # number of ReadExReq MSHR miss cycles
1201system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of demand (read+write) MSHR miss cycles
1202system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles
1203system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles
1204system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles
1205system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles
1206system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles
1207system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles
1208system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles
1209system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles
1210system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles
1211system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles
1212system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles
1213system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles
1214system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles
1215system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles
1216system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles
1217system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles
1218system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles
1219system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles
1220system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses
1221system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses
1222system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses
1223system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses
1224system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses
1225system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
1226system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
1227system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1228system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1229system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses
1230system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses
1231system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses
1232system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses
1233system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses
1234system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses
1235system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1236system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1237system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses
1238system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses
1239system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses
1240system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses
1241system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses
1242system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses
1243system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses
1244system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses
1245system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses
1246system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses
1247system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses
1248system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1249system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses
1250system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency
1251system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency
1252system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency
1253system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency
1254system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency
1255system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency
1256system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency
1257system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency
1258system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency
1259system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency
1260system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency
1261system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency
1262system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency
1263system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency
1264system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency
1265system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency
1266system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency
1267system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
1268system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
1269system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
1270system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
1271system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency
1272system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
1273system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
1274system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
1275system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
1276system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency
1277system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency
1278system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1279system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1280system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1281system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1282system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1283system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1284system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1285system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1286system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1287system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
1288system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
1289system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
1290system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
1291system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
1292system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
1293system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
1294system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
1295system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
1296system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
1297system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
1298system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
1299system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
1300system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
1301system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
1302system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
1303system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
1304system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
1305system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
1306system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
1307system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
1308system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
1309system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
1310system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
1311system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
1312system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
1313system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
1314system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
1315system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
1316system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1317system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1318system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1319system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1320system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
1321system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
1322system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1323system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1324system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1325system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
1326system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
1327system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1328system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
1329system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1330system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
1331system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1332system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
1333system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1334system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
1335system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1336system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
1337system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1342system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1343system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1344system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

1359system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1360system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1361system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1362system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1363system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1364system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1365system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1366system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1367system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
1368system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
1369system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
1370system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
1371system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
1372system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
1373system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
1374system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
1375system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1376system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1377system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
1378system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
1379system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
1380system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
1381system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
1382system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
1383system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
1384system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
1385system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
1386system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
1387system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
1388system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1389system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1390system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
1391system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
1392system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
1393system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
1394system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
1395system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
1396system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
1397system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
1398system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
1399system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
1400system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
1401system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1402system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
1403system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
1404system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1405system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
1406system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
1407system.cpu1.dtb.inst_hits 0 # ITB inst hits
1408system.cpu1.dtb.inst_misses 0 # ITB inst misses
1409system.cpu1.dtb.read_hits 78277454 # DTB read hits
1410system.cpu1.dtb.read_misses 68245 # DTB read misses
1411system.cpu1.dtb.write_hits 71517077 # DTB write hits
1412system.cpu1.dtb.write_misses 24264 # DTB write misses
1413system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1414system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1415system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
1416system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
1417system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
1418system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1419system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
1420system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1421system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
1422system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
1423system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
1424system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1425system.cpu1.dtb.hits 149794531 # DTB hits
1426system.cpu1.dtb.misses 92509 # DTB misses
1427system.cpu1.dtb.accesses 149887040 # DTB accesses
1428system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1429system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1430system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1431system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1432system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1433system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1434system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1435system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1449system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1450system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1451system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1452system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1453system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1454system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1455system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1456system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1457system.cpu1.itb.walker.walks 60524 # Table walker walks requested
1458system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
1459system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
1460system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
1461system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
1462system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1463system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
1464system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
1465system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
1466system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
1467system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
1468system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
1469system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
1470system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
1471system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
1472system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
1473system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
1474system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
1475system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
1476system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
1477system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
1478system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
1479system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
1480system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
1481system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1482system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
1483system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
1484system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
1485system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
1486system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
1487system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
1488system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
1489system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
1490system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1491system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
1492system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
1493system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1494system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
1495system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
1496system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
1497system.cpu1.itb.inst_hits 409921957 # ITB inst hits
1498system.cpu1.itb.inst_misses 60524 # ITB inst misses
1499system.cpu1.itb.read_hits 0 # DTB read hits
1500system.cpu1.itb.read_misses 0 # DTB read misses
1501system.cpu1.itb.write_hits 0 # DTB write hits
1502system.cpu1.itb.write_misses 0 # DTB write misses
1503system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1504system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1505system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
1506system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
1507system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
1508system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1509system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1510system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1511system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1512system.cpu1.itb.read_accesses 0 # DTB read accesses
1513system.cpu1.itb.write_accesses 0 # DTB write accesses
1514system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
1515system.cpu1.itb.hits 409921957 # DTB hits
1516system.cpu1.itb.misses 60524 # DTB misses
1517system.cpu1.itb.accesses 409982481 # DTB accesses
1518system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
1519system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1520system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1521system.cpu1.committedInsts 409652284 # Number of instructions committed
1522system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
1523system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
1524system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
1525system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
1526system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
1527system.cpu1.num_int_insts 446181756 # number of integer instructions
1528system.cpu1.num_fp_insts 565626 # number of float instructions
1529system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
1530system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
1531system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
1532system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
1533system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
1534system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
1535system.cpu1.num_mem_refs 149782083 # number of memory refs
1536system.cpu1.num_load_insts 78271508 # Number of load instructions
1537system.cpu1.num_store_insts 71510575 # Number of store instructions
1538system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
1539system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
1540system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
1541system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
1542system.cpu1.Branches 91673037 # Number of branches fetched
1543system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
1544system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
1545system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
1546system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
1547system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
1548system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
1549system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
1550system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
1551system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
1552system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
1553system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
1554system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
1555system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
1556system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
1557system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
1558system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
1559system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
1560system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
1561system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
1562system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
1563system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
1564system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
1565system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
1566system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
1567system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
1568system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
1569system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
1570system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
1571system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
1572system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
1573system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
1574system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
1575system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1576system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1577system.cpu1.op_class::total 484255317 # Class of executed instruction
1578system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1579system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed
1580system.cpu1.dcache.tags.replacements 4752540 # number of replacements
1581system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use
1582system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks.
1583system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks.
1584system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks.
1585system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit.
1586system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor
1587system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy
1588system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy
1589system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1590system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
1591system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
1592system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
1593system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
1594system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1595system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses
1596system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses
1597system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits
1598system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits
1599system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits
1600system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits
1601system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits
1602system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits
1603system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits
1604system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits
1605system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits
1606system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits
1607system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits
1608system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits
1609system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits
1610system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits
1611system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits
1612system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits
1613system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses
1614system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses
1615system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses
1616system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses
1617system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses
1618system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses
1619system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses
1620system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses
1621system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses
1622system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses
1623system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses
1624system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses
1625system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses
1626system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses
1627system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses
1628system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses
1629system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles
1630system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles
1631system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles
1632system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles
1633system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles
1634system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles
1635system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles
1636system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles
1637system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles
1638system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles
1639system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles
1640system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles
1641system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles
1642system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles
1643system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles
1644system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles
1645system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses)
1646system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses)
1647system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses)
1648system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses)
1649system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses)
1650system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses)
1651system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses)
1652system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses)
1653system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses)
1654system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses)
1655system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses)
1656system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses)
1657system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses
1658system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses
1659system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses
1660system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses
1661system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses
1662system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses
1663system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses
1664system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses
1665system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses
1666system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses
1667system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses
1668system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses
1669system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses
1670system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses
1671system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses
1672system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses
1673system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses
1674system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses
1675system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses
1676system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses
1677system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency
1678system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency
1679system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency
1680system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency
1681system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency
1682system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency
1683system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency
1684system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency
1685system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency
1686system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency
1687system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1688system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1689system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency
1690system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
1691system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency
1692system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
1693system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1694system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1695system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1696system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1697system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1698system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1699system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1700system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1701system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks
1702system.cpu1.dcache.writebacks::total 3063492 # number of writebacks
1703system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits
1704system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits
1705system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits
1706system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits
1707system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits
1708system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits
1709system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits
1710system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits
1711system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits
1712system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits
1713system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses
1714system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses
1715system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses
1716system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses
1717system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses
1718system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses
1719system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses
1720system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses
1721system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses
1722system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses
1723system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses
1724system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses
1725system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses
1726system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses
1727system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses
1728system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses
1729system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles
1730system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles
1731system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles
1732system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles
1733system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles
1734system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles
1735system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles
1736system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles
1737system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles
1738system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles
1739system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles
1740system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles
1741system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles
1742system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles
1743system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles
1744system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles
1745system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles
1746system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles
1747system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles
1748system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles
1749system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles
1750system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles
1751system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles
1752system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles
1753system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses
1754system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses
1755system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses
1756system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses
1757system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses
1758system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses
1759system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses
1760system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses
1761system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses
1762system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses
1763system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses
1764system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses
1765system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses
1766system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses
1767system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses
1768system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses
1769system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency
1770system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency
1771system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency
1772system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency
1773system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency
1774system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency
1775system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency
1776system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency
1777system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency
1778system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency
1779system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency
1780system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency
1781system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1782system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1783system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency
1784system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency
1785system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency
1786system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency
1787system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1788system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1789system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1790system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1791system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1792system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1793system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1794system.cpu1.icache.tags.replacements 5523110 # number of replacements
1795system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use
1796system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks.
1797system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks.
1798system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks.
1799system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit.
1800system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor
1801system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy
1802system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy
1803system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1804system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
1805system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
1806system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
1807system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
1808system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1809system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses
1810system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses
1811system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits
1812system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits
1813system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits
1814system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits
1815system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits
1816system.cpu1.icache.overall_hits::total 404398330 # number of overall hits
1817system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses
1818system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses
1819system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses
1820system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses
1821system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses
1822system.cpu1.icache.overall_misses::total 5523627 # number of overall misses
1823system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles
1824system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles
1825system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles
1826system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles
1827system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles
1828system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles
1829system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses)
1830system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses)
1831system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses
1832system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses
1833system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses
1834system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses
1835system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses
1836system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses
1837system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses
1838system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses
1839system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses
1840system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses
1841system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency
1842system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency
1843system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
1844system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency
1845system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
1846system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency
1847system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1848system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1849system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1850system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1851system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1852system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1853system.cpu1.icache.fast_writes 0 # number of fast writes performed
1854system.cpu1.icache.cache_copies 0 # number of cache copies performed
1855system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5523627 # number of ReadReq MSHR misses
1856system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses
1857system.cpu1.icache.demand_mshr_misses::cpu1.inst 5523627 # number of demand (read+write) MSHR misses
1858system.cpu1.icache.demand_mshr_misses::total 5523627 # number of demand (read+write) MSHR misses
1859system.cpu1.icache.overall_mshr_misses::cpu1.inst 5523627 # number of overall MSHR misses
1860system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses
1861system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles
1862system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles
1863system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles
1864system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles
1865system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles
1866system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles
1867system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles
1868system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles
1869system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles
1870system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles
1871system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses
1872system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses
1873system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses
1874system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses
1875system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses
1876system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses
1877system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency
1878system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency
1879system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
1880system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
1881system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
1882system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
1883system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1884system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1885system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1886system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1887system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1888system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued
1889system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified
1890system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue
1891system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1892system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1893system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing
1894system.cpu1.l2cache.tags.replacements 1638473 # number of replacements
1895system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use
1896system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks.
1897system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks.
1898system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks.
1899system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit.
1900system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor
1901system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor
1902system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor
1903system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor
1904system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor
1905system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor
1906system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy
1907system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy
1908system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy
1909system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy
1910system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy
1911system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy
1912system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy
1913system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1616 # Occupied blocks per task id
1914system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
1915system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id
1916system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id
1917system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id
1918system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id
1919system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
1920system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
1921system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id
1922system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
1923system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
1924system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
1925system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id
1926system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id
1927system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id
1928system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id
1929system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
1930system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id
1931system.cpu1.l2cache.tags.tag_accesses 229858181 # Number of tag accesses
1932system.cpu1.l2cache.tags.data_accesses 229858181 # Number of data accesses
1933system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 196843 # number of ReadReq hits
1934system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 146711 # number of ReadReq hits
1935system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5082589 # number of ReadReq hits
1936system.cpu1.l2cache.ReadReq_hits::cpu1.data 2590406 # number of ReadReq hits
1937system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits
1938system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # number of Writeback hits
1939system.cpu1.l2cache.Writeback_hits::total 3063492 # number of Writeback hits
1940system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 265137 # number of WriteInvalidateReq hits
1941system.cpu1.l2cache.WriteInvalidateReq_hits::total 265137 # number of WriteInvalidateReq hits
1942system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 50742 # number of UpgradeReq hits
1943system.cpu1.l2cache.UpgradeReq_hits::total 50742 # number of UpgradeReq hits
1944system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 28295 # number of SCUpgradeReq hits
1945system.cpu1.l2cache.SCUpgradeReq_hits::total 28295 # number of SCUpgradeReq hits
1946system.cpu1.l2cache.ReadExReq_hits::cpu1.data 777406 # number of ReadExReq hits
1947system.cpu1.l2cache.ReadExReq_hits::total 777406 # number of ReadExReq hits
1948system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 196843 # number of demand (read+write) hits
1949system.cpu1.l2cache.demand_hits::cpu1.itb.walker 146711 # number of demand (read+write) hits
1950system.cpu1.l2cache.demand_hits::cpu1.inst 5082589 # number of demand (read+write) hits
1951system.cpu1.l2cache.demand_hits::cpu1.data 3367812 # number of demand (read+write) hits
1952system.cpu1.l2cache.demand_hits::total 8793955 # number of demand (read+write) hits
1953system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 196843 # number of overall hits
1954system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits
1955system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits
1956system.cpu1.l2cache.overall_hits::cpu1.data 3367812 # number of overall hits
1957system.cpu1.l2cache.overall_hits::total 8793955 # number of overall hits
1958system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9130 # number of ReadReq misses
1959system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7601 # number of ReadReq misses
1960system.cpu1.l2cache.ReadReq_misses::cpu1.inst 441038 # number of ReadReq misses
1961system.cpu1.l2cache.ReadReq_misses::cpu1.data 776098 # number of ReadReq misses
1962system.cpu1.l2cache.ReadReq_misses::total 1233867 # number of ReadReq misses
1963system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 229595 # number of WriteInvalidateReq misses
1964system.cpu1.l2cache.WriteInvalidateReq_misses::total 229595 # number of WriteInvalidateReq misses
1965system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120541 # number of UpgradeReq misses
1966system.cpu1.l2cache.UpgradeReq_misses::total 120541 # number of UpgradeReq misses
1967system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 147968 # number of SCUpgradeReq misses
1968system.cpu1.l2cache.SCUpgradeReq_misses::total 147968 # number of SCUpgradeReq misses
1969system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
1970system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
1971system.cpu1.l2cache.ReadExReq_misses::cpu1.data 207551 # number of ReadExReq misses
1972system.cpu1.l2cache.ReadExReq_misses::total 207551 # number of ReadExReq misses
1973system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9130 # number of demand (read+write) misses
1974system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7601 # number of demand (read+write) misses
1975system.cpu1.l2cache.demand_misses::cpu1.inst 441038 # number of demand (read+write) misses
1976system.cpu1.l2cache.demand_misses::cpu1.data 983649 # number of demand (read+write) misses
1977system.cpu1.l2cache.demand_misses::total 1441418 # number of demand (read+write) misses
1978system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9130 # number of overall misses
1979system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7601 # number of overall misses
1980system.cpu1.l2cache.overall_misses::cpu1.inst 441038 # number of overall misses
1981system.cpu1.l2cache.overall_misses::cpu1.data 983649 # number of overall misses
1982system.cpu1.l2cache.overall_misses::total 1441418 # number of overall misses
1983system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 287537248 # number of ReadReq miss cycles
1984system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 274641499 # number of ReadReq miss cycles
1985system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 13255864672 # number of ReadReq miss cycles
1986system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 23821498253 # number of ReadReq miss cycles
1987system.cpu1.l2cache.ReadReq_miss_latency::total 37639541672 # number of ReadReq miss cycles
1988system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 209637116 # number of WriteInvalidateReq miss cycles
1989system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 209637116 # number of WriteInvalidateReq miss cycles
1990system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2569493734 # number of UpgradeReq miss cycles
1991system.cpu1.l2cache.UpgradeReq_miss_latency::total 2569493734 # number of UpgradeReq miss cycles
1992system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3076594441 # number of SCUpgradeReq miss cycles
1993system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3076594441 # number of SCUpgradeReq miss cycles
1994system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1773498 # number of SCUpgradeFailReq miss cycles
1995system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1773498 # number of SCUpgradeFailReq miss cycles
1996system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8057830380 # number of ReadExReq miss cycles
1997system.cpu1.l2cache.ReadExReq_miss_latency::total 8057830380 # number of ReadExReq miss cycles
1998system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 287537248 # number of demand (read+write) miss cycles
1999system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 274641499 # number of demand (read+write) miss cycles
2000system.cpu1.l2cache.demand_miss_latency::cpu1.inst 13255864672 # number of demand (read+write) miss cycles
2001system.cpu1.l2cache.demand_miss_latency::cpu1.data 31879328633 # number of demand (read+write) miss cycles
2002system.cpu1.l2cache.demand_miss_latency::total 45697372052 # number of demand (read+write) miss cycles
2003system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 287537248 # number of overall miss cycles
2004system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 274641499 # number of overall miss cycles
2005system.cpu1.l2cache.overall_miss_latency::cpu1.inst 13255864672 # number of overall miss cycles
2006system.cpu1.l2cache.overall_miss_latency::cpu1.data 31879328633 # number of overall miss cycles
2007system.cpu1.l2cache.overall_miss_latency::total 45697372052 # number of overall miss cycles
2008system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 205973 # number of ReadReq accesses(hits+misses)
2009system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 154312 # number of ReadReq accesses(hits+misses)
2010system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5523627 # number of ReadReq accesses(hits+misses)
2011system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3366504 # number of ReadReq accesses(hits+misses)
2012system.cpu1.l2cache.ReadReq_accesses::total 9250416 # number of ReadReq accesses(hits+misses)
2013system.cpu1.l2cache.Writeback_accesses::writebacks 3063492 # number of Writeback accesses(hits+misses)
2014system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses)
2015system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 494732 # number of WriteInvalidateReq accesses(hits+misses)
2016system.cpu1.l2cache.WriteInvalidateReq_accesses::total 494732 # number of WriteInvalidateReq accesses(hits+misses)
2017system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 171283 # number of UpgradeReq accesses(hits+misses)
2018system.cpu1.l2cache.UpgradeReq_accesses::total 171283 # number of UpgradeReq accesses(hits+misses)
2019system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 176263 # number of SCUpgradeReq accesses(hits+misses)
2020system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses)
2021system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
2022system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
2023system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 984957 # number of ReadExReq accesses(hits+misses)
2024system.cpu1.l2cache.ReadExReq_accesses::total 984957 # number of ReadExReq accesses(hits+misses)
2025system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 205973 # number of demand (read+write) accesses
2026system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 154312 # number of demand (read+write) accesses
2027system.cpu1.l2cache.demand_accesses::cpu1.inst 5523627 # number of demand (read+write) accesses
2028system.cpu1.l2cache.demand_accesses::cpu1.data 4351461 # number of demand (read+write) accesses
2029system.cpu1.l2cache.demand_accesses::total 10235373 # number of demand (read+write) accesses
2030system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 205973 # number of overall (read+write) accesses
2031system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 154312 # number of overall (read+write) accesses
2032system.cpu1.l2cache.overall_accesses::cpu1.inst 5523627 # number of overall (read+write) accesses
2033system.cpu1.l2cache.overall_accesses::cpu1.data 4351461 # number of overall (read+write) accesses
2034system.cpu1.l2cache.overall_accesses::total 10235373 # number of overall (read+write) accesses
2035system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for ReadReq accesses
2036system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049257 # miss rate for ReadReq accesses
2037system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079846 # miss rate for ReadReq accesses
2038system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.230535 # miss rate for ReadReq accesses
2039system.cpu1.l2cache.ReadReq_miss_rate::total 0.133385 # miss rate for ReadReq accesses
2040system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.464080 # miss rate for WriteInvalidateReq accesses
2041system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.464080 # miss rate for WriteInvalidateReq accesses
2042system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.703753 # miss rate for UpgradeReq accesses
2043system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.703753 # miss rate for UpgradeReq accesses
2044system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.839473 # miss rate for SCUpgradeReq accesses
2045system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.839473 # miss rate for SCUpgradeReq accesses
2046system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2047system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2048system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210721 # miss rate for ReadExReq accesses
2049system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210721 # miss rate for ReadExReq accesses
2050system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for demand accesses
2051system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049257 # miss rate for demand accesses
2052system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079846 # miss rate for demand accesses
2053system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.226050 # miss rate for demand accesses
2054system.cpu1.l2cache.demand_miss_rate::total 0.140827 # miss rate for demand accesses
2055system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for overall accesses
2056system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049257 # miss rate for overall accesses
2057system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079846 # miss rate for overall accesses
2058system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.226050 # miss rate for overall accesses
2059system.cpu1.l2cache.overall_miss_rate::total 0.140827 # miss rate for overall accesses
2060system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average ReadReq miss latency
2061system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36132.285094 # average ReadReq miss latency
2062system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30056.060185 # average ReadReq miss latency
2063system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency
2064system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30505.347555 # average ReadReq miss latency
2065system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 913.073525 # average WriteInvalidateReq miss latency
2066system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 913.073525 # average WriteInvalidateReq miss latency
2067system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21316.346587 # average UpgradeReq miss latency
2068system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21316.346587 # average UpgradeReq miss latency
2069system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20792.295909 # average SCUpgradeReq miss latency
2070system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20792.295909 # average SCUpgradeReq miss latency
2071system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354699.600000 # average SCUpgradeFailReq miss latency
2072system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354699.600000 # average SCUpgradeFailReq miss latency
2073system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38823.375363 # average ReadExReq miss latency
2074system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38823.375363 # average ReadExReq miss latency
2075system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency
2076system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency
2077system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency
2078system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency
2079system.cpu1.l2cache.demand_avg_miss_latency::total 31703.067432 # average overall miss latency
2080system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency
2081system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency
2082system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency
2083system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency
2084system.cpu1.l2cache.overall_avg_miss_latency::total 31703.067432 # average overall miss latency
2085system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2086system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2087system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2088system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2089system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2090system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2091system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2092system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2093system.cpu1.l2cache.writebacks::writebacks 764216 # number of writebacks
2094system.cpu1.l2cache.writebacks::total 764216 # number of writebacks
2095system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits
2096system.cpu1.l2cache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits
2097system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2534 # number of ReadExReq MSHR hits
2098system.cpu1.l2cache.ReadExReq_mshr_hits::total 2534 # number of ReadExReq MSHR hits
2099system.cpu1.l2cache.demand_mshr_hits::cpu1.data 2857 # number of demand (read+write) MSHR hits
2100system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits
2101system.cpu1.l2cache.overall_mshr_hits::cpu1.data 2857 # number of overall MSHR hits
2102system.cpu1.l2cache.overall_mshr_hits::total 2857 # number of overall MSHR hits
2103system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9130 # number of ReadReq MSHR misses
2104system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7601 # number of ReadReq MSHR misses
2105system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 441038 # number of ReadReq MSHR misses
2106system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 775775 # number of ReadReq MSHR misses
2107system.cpu1.l2cache.ReadReq_mshr_misses::total 1233544 # number of ReadReq MSHR misses
2108system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of HardPFReq MSHR misses
2109system.cpu1.l2cache.HardPFReq_mshr_misses::total 524912 # number of HardPFReq MSHR misses
2110system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 229595 # number of WriteInvalidateReq MSHR misses
2111system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 229595 # number of WriteInvalidateReq MSHR misses
2112system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120541 # number of UpgradeReq MSHR misses
2113system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120541 # number of UpgradeReq MSHR misses
2114system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 147968 # number of SCUpgradeReq MSHR misses
2115system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147968 # number of SCUpgradeReq MSHR misses
2116system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
2117system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
2118system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 205017 # number of ReadExReq MSHR misses
2119system.cpu1.l2cache.ReadExReq_mshr_misses::total 205017 # number of ReadExReq MSHR misses
2120system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9130 # number of demand (read+write) MSHR misses
2121system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7601 # number of demand (read+write) MSHR misses
2122system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 441038 # number of demand (read+write) MSHR misses
2123system.cpu1.l2cache.demand_mshr_misses::cpu1.data 980792 # number of demand (read+write) MSHR misses
2124system.cpu1.l2cache.demand_mshr_misses::total 1438561 # number of demand (read+write) MSHR misses
2125system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9130 # number of overall MSHR misses
2126system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7601 # number of overall MSHR misses
2127system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 441038 # number of overall MSHR misses
2128system.cpu1.l2cache.overall_mshr_misses::cpu1.data 980792 # number of overall MSHR misses
2129system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of overall MSHR misses
2130system.cpu1.l2cache.overall_mshr_misses::total 1963473 # number of overall MSHR misses
2131system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of ReadReq MSHR miss cycles
2132system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224849501 # number of ReadReq MSHR miss cycles
2133system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10375497328 # number of ReadReq MSHR miss cycles
2134system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 18713747169 # number of ReadReq MSHR miss cycles
2135system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29541935250 # number of ReadReq MSHR miss cycles
2136system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles
2137system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles
2138system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles
2139system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles
2140system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles
2141system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles
2142system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles
2143system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles
2144system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles
2145system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles
2146system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles
2147system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles
2148system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles
2149system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles
2150system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles
2151system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles
2152system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles
2153system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles
2154system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles
2155system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles
2156system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles
2157system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles
2158system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles
2159system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles
2160system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles
2161system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles
2162system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles
2163system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles
2164system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles
2165system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles
2166system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles
2167system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses
2168system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses
2169system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses
2170system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses
2171system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses
2172system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2173system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2174system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses
2175system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses
2176system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses
2177system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses
2178system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses
2179system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses
2180system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2181system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2182system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses
2183system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses
2184system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses
2185system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses
2186system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses
2187system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses
2188system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses
2189system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses
2190system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses
2191system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses
2192system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses
2193system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2194system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
2195system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
2196system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
2197system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
2198system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
2199system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
2200system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
2201system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
2202system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
2203system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
2204system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
2205system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
2206system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
2207system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
2208system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
2209system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
2210system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
2211system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
2212system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
2213system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
2214system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
2215system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
2216system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
2217system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
2218system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
2219system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
2220system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
2221system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
2222system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
2223system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2224system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2225system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2226system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2227system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2228system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2229system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2230system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2231system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2232system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
2233system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
2234system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
2235system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
2236system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
2237system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
2238system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
2239system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
2240system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
2241system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
2242system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
2243system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
2244system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
2245system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
2246system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
2247system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
2248system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
2249system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
2250system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
2251system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
2252system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
2253system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
2254system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
2255system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
2256system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
2257system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
2258system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
2259system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
2260system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
2261system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2262system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2263system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2264system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2265system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
2266system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
2267system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2268system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
2269system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
2270system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
2271system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
2272system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2273system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
2274system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2275system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
2276system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2277system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
2278system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2279system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
2280system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2281system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
2282system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2283system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
2284system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
2285system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
2286system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
2287system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
2288system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
2289system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2290system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2291system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2292system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2293system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2294system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2295system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2296system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2297system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2298system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2299system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2300system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2301system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2302system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2303system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
2304system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
2305system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
2306system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2307system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2308system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
2309system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
2310system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2311system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2312system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2313system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2314system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2315system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2316system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2317system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2318system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2319system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2320system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2321system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2322system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2323system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2324system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes)
2325system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
2326system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
2327system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2328system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2329system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes)
2330system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks)
2331system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2332system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2333system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2334system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2335system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2336system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2337system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2338system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)

--- 11 unchanged lines hidden (view full) ---

2350system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
2351system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2352system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2353system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2354system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2355system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2356system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2357system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2358system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks)
2359system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2360system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2361system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2362system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks)
2363system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2364system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks)
2365system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2366system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
2367system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2368system.iocache.tags.replacements 115606 # number of replacements
2369system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use
2370system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2371system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks.
2372system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2373system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit.
2374system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor
2375system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor
2376system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy
2377system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy
2378system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy
2379system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2380system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2381system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2382system.iocache.tags.tag_accesses 1040802 # Number of tag accesses
2383system.iocache.tags.data_accesses 1040802 # Number of data accesses
2384system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2385system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses
2386system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses
2387system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2388system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2389system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2390system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2391system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2392system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
2393system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
2394system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2395system.iocache.overall_misses::realview.ide 8877 # number of overall misses
2396system.iocache.overall_misses::total 8917 # number of overall misses
2397system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
2398system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles
2399system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles
2400system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2401system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2402system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles
2403system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles
2404system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
2405system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles
2406system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles
2407system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
2408system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles
2409system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles
2410system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2411system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
2412system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
2413system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2414system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2415system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
2416system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
2417system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2418system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
2419system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
2420system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2421system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
2422system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
2423system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2424system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2425system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2426system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2427system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2428system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
2429system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
2430system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2431system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2432system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2433system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2434system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2435system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2436system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
2437system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency
2438system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency
2439system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2440system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2441system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency
2442system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency
2443system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2444system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency
2445system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency
2446system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2447system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency
2448system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency
2449system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked
2450system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2451system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked
2452system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2453system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked
2454system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2455system.iocache.fast_writes 0 # number of fast writes performed
2456system.iocache.cache_copies 0 # number of cache copies performed
2457system.iocache.writebacks::writebacks 106699 # number of writebacks
2458system.iocache.writebacks::total 106699 # number of writebacks
2459system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2460system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses
2461system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses
2462system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2463system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2464system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
2465system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
2466system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2467system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses
2468system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses
2469system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2470system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses
2471system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses
2472system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
2473system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles
2474system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles
2475system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
2476system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
2477system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles
2478system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles
2479system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
2480system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles
2481system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles
2482system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
2483system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles
2484system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles
2485system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2486system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2487system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2488system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2489system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2490system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
2491system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
2492system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2493system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2494system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2495system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2496system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2497system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2498system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
2499system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency
2500system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency
2501system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
2502system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
2503system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency
2504system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency
2505system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2506system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency
2507system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency
2508system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2509system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency
2510system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency
2511system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2512system.l2c.tags.replacements 1063912 # number of replacements
2513system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use
2514system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks.
2515system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks.
2516system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks.
2517system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit.
2518system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor
2519system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor
2520system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor
2521system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor
2522system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor
2523system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor
2524system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor
2525system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor
2526system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor
2527system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor
2528system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor
2529system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy
2530system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy
2531system.l2c.tags.occ_percent::cpu0.itb.walker 0.001634 # Average percentage of cache occupancy
2532system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy
2533system.l2c.tags.occ_percent::cpu0.data 0.115208 # Average percentage of cache occupancy
2534system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy
2535system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy
2536system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy
2537system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy
2538system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy
2539system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy
2540system.l2c.tags.occ_percent::total 0.979281 # Average percentage of cache occupancy
2541system.l2c.tags.occ_task_id_blocks::1022 9644 # Occupied blocks per task id
2542system.l2c.tags.occ_task_id_blocks::1023 191 # Occupied blocks per task id
2543system.l2c.tags.occ_task_id_blocks::1024 49666 # Occupied blocks per task id
2544system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id
2545system.l2c.tags.age_task_id_blocks_1022::3 226 # Occupied blocks per task id
2546system.l2c.tags.age_task_id_blocks_1022::4 9286 # Occupied blocks per task id
2547system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id
2548system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
2549system.l2c.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
2550system.l2c.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id
2551system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id
2552system.l2c.tags.age_task_id_blocks_1024::4 43236 # Occupied blocks per task id
2553system.l2c.tags.occ_task_id_percent::1022 0.147156 # Percentage of cache occupancy per task id
2554system.l2c.tags.occ_task_id_percent::1023 0.002914 # Percentage of cache occupancy per task id
2555system.l2c.tags.occ_task_id_percent::1024 0.757843 # Percentage of cache occupancy per task id
2556system.l2c.tags.tag_accesses 50574940 # Number of tag accesses
2557system.l2c.tags.data_accesses 50574940 # Number of data accesses
2558system.l2c.ReadReq_hits::cpu0.dtb.walker 5180 # number of ReadReq hits
2559system.l2c.ReadReq_hits::cpu0.itb.walker 4259 # number of ReadReq hits
2560system.l2c.ReadReq_hits::cpu0.inst 469863 # number of ReadReq hits
2561system.l2c.ReadReq_hits::cpu0.data 537542 # number of ReadReq hits
2562system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 313027 # number of ReadReq hits
2563system.l2c.ReadReq_hits::cpu1.dtb.walker 4490 # number of ReadReq hits
2564system.l2c.ReadReq_hits::cpu1.itb.walker 3587 # number of ReadReq hits
2565system.l2c.ReadReq_hits::cpu1.inst 401752 # number of ReadReq hits
2566system.l2c.ReadReq_hits::cpu1.data 405704 # number of ReadReq hits
2567system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 231220 # number of ReadReq hits
2568system.l2c.ReadReq_hits::total 2376624 # number of ReadReq hits
2569system.l2c.Writeback_hits::writebacks 2047649 # number of Writeback hits
2570system.l2c.Writeback_hits::total 2047649 # number of Writeback hits
2571system.l2c.WriteInvalidateReq_hits::cpu0.data 135493 # number of WriteInvalidateReq hits
2572system.l2c.WriteInvalidateReq_hits::cpu1.data 115685 # number of WriteInvalidateReq hits
2573system.l2c.WriteInvalidateReq_hits::total 251178 # number of WriteInvalidateReq hits
2574system.l2c.UpgradeReq_hits::cpu0.data 31239 # number of UpgradeReq hits
2575system.l2c.UpgradeReq_hits::cpu1.data 22507 # number of UpgradeReq hits
2576system.l2c.UpgradeReq_hits::total 53746 # number of UpgradeReq hits
2577system.l2c.SCUpgradeReq_hits::cpu0.data 6431 # number of SCUpgradeReq hits
2578system.l2c.SCUpgradeReq_hits::cpu1.data 5062 # number of SCUpgradeReq hits
2579system.l2c.SCUpgradeReq_hits::total 11493 # number of SCUpgradeReq hits
2580system.l2c.ReadExReq_hits::cpu0.data 47681 # number of ReadExReq hits
2581system.l2c.ReadExReq_hits::cpu1.data 46115 # number of ReadExReq hits
2582system.l2c.ReadExReq_hits::total 93796 # number of ReadExReq hits
2583system.l2c.demand_hits::cpu0.dtb.walker 5180 # number of demand (read+write) hits
2584system.l2c.demand_hits::cpu0.itb.walker 4259 # number of demand (read+write) hits
2585system.l2c.demand_hits::cpu0.inst 469863 # number of demand (read+write) hits
2586system.l2c.demand_hits::cpu0.data 585223 # number of demand (read+write) hits
2587system.l2c.demand_hits::cpu0.l2cache.prefetcher 313027 # number of demand (read+write) hits
2588system.l2c.demand_hits::cpu1.dtb.walker 4490 # number of demand (read+write) hits
2589system.l2c.demand_hits::cpu1.itb.walker 3587 # number of demand (read+write) hits
2590system.l2c.demand_hits::cpu1.inst 401752 # number of demand (read+write) hits
2591system.l2c.demand_hits::cpu1.data 451819 # number of demand (read+write) hits
2592system.l2c.demand_hits::cpu1.l2cache.prefetcher 231220 # number of demand (read+write) hits
2593system.l2c.demand_hits::total 2470420 # number of demand (read+write) hits
2594system.l2c.overall_hits::cpu0.dtb.walker 5180 # number of overall hits
2595system.l2c.overall_hits::cpu0.itb.walker 4259 # number of overall hits
2596system.l2c.overall_hits::cpu0.inst 469863 # number of overall hits
2597system.l2c.overall_hits::cpu0.data 585223 # number of overall hits
2598system.l2c.overall_hits::cpu0.l2cache.prefetcher 313027 # number of overall hits
2599system.l2c.overall_hits::cpu1.dtb.walker 4490 # number of overall hits
2600system.l2c.overall_hits::cpu1.itb.walker 3587 # number of overall hits
2601system.l2c.overall_hits::cpu1.inst 401752 # number of overall hits
2602system.l2c.overall_hits::cpu1.data 451819 # number of overall hits
2603system.l2c.overall_hits::cpu1.l2cache.prefetcher 231220 # number of overall hits
2604system.l2c.overall_hits::total 2470420 # number of overall hits
2605system.l2c.ReadReq_misses::cpu0.dtb.walker 577 # number of ReadReq misses
2606system.l2c.ReadReq_misses::cpu0.itb.walker 634 # number of ReadReq misses
2607system.l2c.ReadReq_misses::cpu0.inst 41076 # number of ReadReq misses
2608system.l2c.ReadReq_misses::cpu0.data 94183 # number of ReadReq misses
2609system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 149529 # number of ReadReq misses
2610system.l2c.ReadReq_misses::cpu1.dtb.walker 1129 # number of ReadReq misses
2611system.l2c.ReadReq_misses::cpu1.itb.walker 1344 # number of ReadReq misses
2612system.l2c.ReadReq_misses::cpu1.inst 39286 # number of ReadReq misses
2613system.l2c.ReadReq_misses::cpu1.data 84710 # number of ReadReq misses
2614system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq misses
2615system.l2c.ReadReq_misses::total 531147 # number of ReadReq misses
2616system.l2c.WriteInvalidateReq_misses::cpu0.data 427179 # number of WriteInvalidateReq misses
2617system.l2c.WriteInvalidateReq_misses::cpu1.data 105657 # number of WriteInvalidateReq misses
2618system.l2c.WriteInvalidateReq_misses::total 532836 # number of WriteInvalidateReq misses
2619system.l2c.UpgradeReq_misses::cpu0.data 47914 # number of UpgradeReq misses
2620system.l2c.UpgradeReq_misses::cpu1.data 38699 # number of UpgradeReq misses
2621system.l2c.UpgradeReq_misses::total 86613 # number of UpgradeReq misses
2622system.l2c.SCUpgradeReq_misses::cpu0.data 10572 # number of SCUpgradeReq misses
2623system.l2c.SCUpgradeReq_misses::cpu1.data 7951 # number of SCUpgradeReq misses
2624system.l2c.SCUpgradeReq_misses::total 18523 # number of SCUpgradeReq misses
2625system.l2c.ReadExReq_misses::cpu0.data 64089 # number of ReadExReq misses
2626system.l2c.ReadExReq_misses::cpu1.data 43672 # number of ReadExReq misses
2627system.l2c.ReadExReq_misses::total 107761 # number of ReadExReq misses
2628system.l2c.demand_misses::cpu0.dtb.walker 577 # number of demand (read+write) misses
2629system.l2c.demand_misses::cpu0.itb.walker 634 # number of demand (read+write) misses
2630system.l2c.demand_misses::cpu0.inst 41076 # number of demand (read+write) misses
2631system.l2c.demand_misses::cpu0.data 158272 # number of demand (read+write) misses
2632system.l2c.demand_misses::cpu0.l2cache.prefetcher 149529 # number of demand (read+write) misses
2633system.l2c.demand_misses::cpu1.dtb.walker 1129 # number of demand (read+write) misses
2634system.l2c.demand_misses::cpu1.itb.walker 1344 # number of demand (read+write) misses
2635system.l2c.demand_misses::cpu1.inst 39286 # number of demand (read+write) misses
2636system.l2c.demand_misses::cpu1.data 128382 # number of demand (read+write) misses
2637system.l2c.demand_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) misses
2638system.l2c.demand_misses::total 638908 # number of demand (read+write) misses
2639system.l2c.overall_misses::cpu0.dtb.walker 577 # number of overall misses
2640system.l2c.overall_misses::cpu0.itb.walker 634 # number of overall misses
2641system.l2c.overall_misses::cpu0.inst 41076 # number of overall misses
2642system.l2c.overall_misses::cpu0.data 158272 # number of overall misses
2643system.l2c.overall_misses::cpu0.l2cache.prefetcher 149529 # number of overall misses
2644system.l2c.overall_misses::cpu1.dtb.walker 1129 # number of overall misses
2645system.l2c.overall_misses::cpu1.itb.walker 1344 # number of overall misses
2646system.l2c.overall_misses::cpu1.inst 39286 # number of overall misses
2647system.l2c.overall_misses::cpu1.data 128382 # number of overall misses
2648system.l2c.overall_misses::cpu1.l2cache.prefetcher 118679 # number of overall misses
2649system.l2c.overall_misses::total 638908 # number of overall misses
2650system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 51297750 # number of ReadReq miss cycles
2651system.l2c.ReadReq_miss_latency::cpu0.itb.walker 55466264 # number of ReadReq miss cycles
2652system.l2c.ReadReq_miss_latency::cpu0.inst 3464868273 # number of ReadReq miss cycles
2653system.l2c.ReadReq_miss_latency::cpu0.data 8461586857 # number of ReadReq miss cycles
2654system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of ReadReq miss cycles
2655system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 98269250 # number of ReadReq miss cycles
2656system.l2c.ReadReq_miss_latency::cpu1.itb.walker 120308250 # number of ReadReq miss cycles
2657system.l2c.ReadReq_miss_latency::cpu1.inst 3289147097 # number of ReadReq miss cycles
2658system.l2c.ReadReq_miss_latency::cpu1.data 7432991468 # number of ReadReq miss cycles
2659system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of ReadReq miss cycles
2660system.l2c.ReadReq_miss_latency::total 55049336677 # number of ReadReq miss cycles
2661system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 56781694 # number of WriteInvalidateReq miss cycles
2662system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 44775578 # number of WriteInvalidateReq miss cycles
2663system.l2c.WriteInvalidateReq_miss_latency::total 101557272 # number of WriteInvalidateReq miss cycles
2664system.l2c.UpgradeReq_miss_latency::cpu0.data 267824472 # number of UpgradeReq miss cycles
2665system.l2c.UpgradeReq_miss_latency::cpu1.data 195648800 # number of UpgradeReq miss cycles
2666system.l2c.UpgradeReq_miss_latency::total 463473272 # number of UpgradeReq miss cycles
2667system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46262535 # number of SCUpgradeReq miss cycles
2668system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41400197 # number of SCUpgradeReq miss cycles
2669system.l2c.SCUpgradeReq_miss_latency::total 87662732 # number of SCUpgradeReq miss cycles
2670system.l2c.ReadExReq_miss_latency::cpu0.data 5583608052 # number of ReadExReq miss cycles
2671system.l2c.ReadExReq_miss_latency::cpu1.data 3566659435 # number of ReadExReq miss cycles
2672system.l2c.ReadExReq_miss_latency::total 9150267487 # number of ReadExReq miss cycles
2673system.l2c.demand_miss_latency::cpu0.dtb.walker 51297750 # number of demand (read+write) miss cycles
2674system.l2c.demand_miss_latency::cpu0.itb.walker 55466264 # number of demand (read+write) miss cycles
2675system.l2c.demand_miss_latency::cpu0.inst 3464868273 # number of demand (read+write) miss cycles
2676system.l2c.demand_miss_latency::cpu0.data 14045194909 # number of demand (read+write) miss cycles
2677system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of demand (read+write) miss cycles
2678system.l2c.demand_miss_latency::cpu1.dtb.walker 98269250 # number of demand (read+write) miss cycles
2679system.l2c.demand_miss_latency::cpu1.itb.walker 120308250 # number of demand (read+write) miss cycles
2680system.l2c.demand_miss_latency::cpu1.inst 3289147097 # number of demand (read+write) miss cycles
2681system.l2c.demand_miss_latency::cpu1.data 10999650903 # number of demand (read+write) miss cycles
2682system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of demand (read+write) miss cycles
2683system.l2c.demand_miss_latency::total 64199604164 # number of demand (read+write) miss cycles
2684system.l2c.overall_miss_latency::cpu0.dtb.walker 51297750 # number of overall miss cycles
2685system.l2c.overall_miss_latency::cpu0.itb.walker 55466264 # number of overall miss cycles
2686system.l2c.overall_miss_latency::cpu0.inst 3464868273 # number of overall miss cycles
2687system.l2c.overall_miss_latency::cpu0.data 14045194909 # number of overall miss cycles
2688system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of overall miss cycles
2689system.l2c.overall_miss_latency::cpu1.dtb.walker 98269250 # number of overall miss cycles
2690system.l2c.overall_miss_latency::cpu1.itb.walker 120308250 # number of overall miss cycles
2691system.l2c.overall_miss_latency::cpu1.inst 3289147097 # number of overall miss cycles
2692system.l2c.overall_miss_latency::cpu1.data 10999650903 # number of overall miss cycles
2693system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of overall miss cycles
2694system.l2c.overall_miss_latency::total 64199604164 # number of overall miss cycles
2695system.l2c.ReadReq_accesses::cpu0.dtb.walker 5757 # number of ReadReq accesses(hits+misses)
2696system.l2c.ReadReq_accesses::cpu0.itb.walker 4893 # number of ReadReq accesses(hits+misses)
2697system.l2c.ReadReq_accesses::cpu0.inst 510939 # number of ReadReq accesses(hits+misses)
2698system.l2c.ReadReq_accesses::cpu0.data 631725 # number of ReadReq accesses(hits+misses)
2699system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 462556 # number of ReadReq accesses(hits+misses)
2700system.l2c.ReadReq_accesses::cpu1.dtb.walker 5619 # number of ReadReq accesses(hits+misses)
2701system.l2c.ReadReq_accesses::cpu1.itb.walker 4931 # number of ReadReq accesses(hits+misses)
2702system.l2c.ReadReq_accesses::cpu1.inst 441038 # number of ReadReq accesses(hits+misses)
2703system.l2c.ReadReq_accesses::cpu1.data 490414 # number of ReadReq accesses(hits+misses)
2704system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 349899 # number of ReadReq accesses(hits+misses)
2705system.l2c.ReadReq_accesses::total 2907771 # number of ReadReq accesses(hits+misses)
2706system.l2c.Writeback_accesses::writebacks 2047649 # number of Writeback accesses(hits+misses)
2707system.l2c.Writeback_accesses::total 2047649 # number of Writeback accesses(hits+misses)
2708system.l2c.WriteInvalidateReq_accesses::cpu0.data 562672 # number of WriteInvalidateReq accesses(hits+misses)
2709system.l2c.WriteInvalidateReq_accesses::cpu1.data 221342 # number of WriteInvalidateReq accesses(hits+misses)
2710system.l2c.WriteInvalidateReq_accesses::total 784014 # number of WriteInvalidateReq accesses(hits+misses)
2711system.l2c.UpgradeReq_accesses::cpu0.data 79153 # number of UpgradeReq accesses(hits+misses)
2712system.l2c.UpgradeReq_accesses::cpu1.data 61206 # number of UpgradeReq accesses(hits+misses)
2713system.l2c.UpgradeReq_accesses::total 140359 # number of UpgradeReq accesses(hits+misses)
2714system.l2c.SCUpgradeReq_accesses::cpu0.data 17003 # number of SCUpgradeReq accesses(hits+misses)
2715system.l2c.SCUpgradeReq_accesses::cpu1.data 13013 # number of SCUpgradeReq accesses(hits+misses)
2716system.l2c.SCUpgradeReq_accesses::total 30016 # number of SCUpgradeReq accesses(hits+misses)
2717system.l2c.ReadExReq_accesses::cpu0.data 111770 # number of ReadExReq accesses(hits+misses)
2718system.l2c.ReadExReq_accesses::cpu1.data 89787 # number of ReadExReq accesses(hits+misses)
2719system.l2c.ReadExReq_accesses::total 201557 # number of ReadExReq accesses(hits+misses)
2720system.l2c.demand_accesses::cpu0.dtb.walker 5757 # number of demand (read+write) accesses
2721system.l2c.demand_accesses::cpu0.itb.walker 4893 # number of demand (read+write) accesses
2722system.l2c.demand_accesses::cpu0.inst 510939 # number of demand (read+write) accesses
2723system.l2c.demand_accesses::cpu0.data 743495 # number of demand (read+write) accesses
2724system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462556 # number of demand (read+write) accesses
2725system.l2c.demand_accesses::cpu1.dtb.walker 5619 # number of demand (read+write) accesses
2726system.l2c.demand_accesses::cpu1.itb.walker 4931 # number of demand (read+write) accesses
2727system.l2c.demand_accesses::cpu1.inst 441038 # number of demand (read+write) accesses
2728system.l2c.demand_accesses::cpu1.data 580201 # number of demand (read+write) accesses
2729system.l2c.demand_accesses::cpu1.l2cache.prefetcher 349899 # number of demand (read+write) accesses
2730system.l2c.demand_accesses::total 3109328 # number of demand (read+write) accesses
2731system.l2c.overall_accesses::cpu0.dtb.walker 5757 # number of overall (read+write) accesses
2732system.l2c.overall_accesses::cpu0.itb.walker 4893 # number of overall (read+write) accesses
2733system.l2c.overall_accesses::cpu0.inst 510939 # number of overall (read+write) accesses
2734system.l2c.overall_accesses::cpu0.data 743495 # number of overall (read+write) accesses
2735system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462556 # number of overall (read+write) accesses
2736system.l2c.overall_accesses::cpu1.dtb.walker 5619 # number of overall (read+write) accesses
2737system.l2c.overall_accesses::cpu1.itb.walker 4931 # number of overall (read+write) accesses
2738system.l2c.overall_accesses::cpu1.inst 441038 # number of overall (read+write) accesses
2739system.l2c.overall_accesses::cpu1.data 580201 # number of overall (read+write) accesses
2740system.l2c.overall_accesses::cpu1.l2cache.prefetcher 349899 # number of overall (read+write) accesses
2741system.l2c.overall_accesses::total 3109328 # number of overall (read+write) accesses
2742system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for ReadReq accesses
2743system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129573 # miss rate for ReadReq accesses
2744system.l2c.ReadReq_miss_rate::cpu0.inst 0.080393 # miss rate for ReadReq accesses
2745system.l2c.ReadReq_miss_rate::cpu0.data 0.149089 # miss rate for ReadReq accesses
2746system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for ReadReq accesses
2747system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for ReadReq accesses
2748system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.272561 # miss rate for ReadReq accesses
2749system.l2c.ReadReq_miss_rate::cpu1.inst 0.089076 # miss rate for ReadReq accesses
2750system.l2c.ReadReq_miss_rate::cpu1.data 0.172732 # miss rate for ReadReq accesses
2751system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for ReadReq accesses
2752system.l2c.ReadReq_miss_rate::total 0.182665 # miss rate for ReadReq accesses
2753system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.759197 # miss rate for WriteInvalidateReq accesses
2754system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.477347 # miss rate for WriteInvalidateReq accesses
2755system.l2c.WriteInvalidateReq_miss_rate::total 0.679626 # miss rate for WriteInvalidateReq accesses
2756system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605334 # miss rate for UpgradeReq accesses
2757system.l2c.UpgradeReq_miss_rate::cpu1.data 0.632275 # miss rate for UpgradeReq accesses
2758system.l2c.UpgradeReq_miss_rate::total 0.617082 # miss rate for UpgradeReq accesses
2759system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.621773 # miss rate for SCUpgradeReq accesses
2760system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.611004 # miss rate for SCUpgradeReq accesses
2761system.l2c.SCUpgradeReq_miss_rate::total 0.617104 # miss rate for SCUpgradeReq accesses
2762system.l2c.ReadExReq_miss_rate::cpu0.data 0.573401 # miss rate for ReadExReq accesses
2763system.l2c.ReadExReq_miss_rate::cpu1.data 0.486396 # miss rate for ReadExReq accesses
2764system.l2c.ReadExReq_miss_rate::total 0.534643 # miss rate for ReadExReq accesses
2765system.l2c.demand_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for demand accesses
2766system.l2c.demand_miss_rate::cpu0.itb.walker 0.129573 # miss rate for demand accesses
2767system.l2c.demand_miss_rate::cpu0.inst 0.080393 # miss rate for demand accesses
2768system.l2c.demand_miss_rate::cpu0.data 0.212876 # miss rate for demand accesses
2769system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for demand accesses
2770system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for demand accesses
2771system.l2c.demand_miss_rate::cpu1.itb.walker 0.272561 # miss rate for demand accesses
2772system.l2c.demand_miss_rate::cpu1.inst 0.089076 # miss rate for demand accesses
2773system.l2c.demand_miss_rate::cpu1.data 0.221272 # miss rate for demand accesses
2774system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for demand accesses
2775system.l2c.demand_miss_rate::total 0.205481 # miss rate for demand accesses
2776system.l2c.overall_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for overall accesses
2777system.l2c.overall_miss_rate::cpu0.itb.walker 0.129573 # miss rate for overall accesses
2778system.l2c.overall_miss_rate::cpu0.inst 0.080393 # miss rate for overall accesses
2779system.l2c.overall_miss_rate::cpu0.data 0.212876 # miss rate for overall accesses
2780system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for overall accesses
2781system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for overall accesses
2782system.l2c.overall_miss_rate::cpu1.itb.walker 0.272561 # miss rate for overall accesses
2783system.l2c.overall_miss_rate::cpu1.inst 0.089076 # miss rate for overall accesses
2784system.l2c.overall_miss_rate::cpu1.data 0.221272 # miss rate for overall accesses
2785system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for overall accesses
2786system.l2c.overall_miss_rate::total 0.205481 # miss rate for overall accesses
2787system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average ReadReq miss latency
2788system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87486.220820 # average ReadReq miss latency
2789system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84352.621312 # average ReadReq miss latency
2790system.l2c.ReadReq_avg_miss_latency::cpu0.data 89841.976333 # average ReadReq miss latency
2791system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average ReadReq miss latency
2792system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average ReadReq miss latency
2793system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89515.066964 # average ReadReq miss latency
2794system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83723.135392 # average ReadReq miss latency
2795system.l2c.ReadReq_avg_miss_latency::cpu1.data 87746.328273 # average ReadReq miss latency
2796system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average ReadReq miss latency
2797system.l2c.ReadReq_avg_miss_latency::total 103642.375231 # average ReadReq miss latency
2798system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 132.922484 # average WriteInvalidateReq miss latency
2799system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 423.782409 # average WriteInvalidateReq miss latency
2800system.l2c.WriteInvalidateReq_avg_miss_latency::total 190.597617 # average WriteInvalidateReq miss latency
2801system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5589.691364 # average UpgradeReq miss latency
2802system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5055.655185 # average UpgradeReq miss latency
2803system.l2c.UpgradeReq_avg_miss_latency::total 5351.082078 # average UpgradeReq miss latency
2804system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4375.949205 # average SCUpgradeReq miss latency
2805system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5206.916992 # average SCUpgradeReq miss latency
2806system.l2c.SCUpgradeReq_avg_miss_latency::total 4732.642229 # average SCUpgradeReq miss latency
2807system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87122.720779 # average ReadExReq miss latency
2808system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81669.248832 # average ReadExReq miss latency
2809system.l2c.ReadExReq_avg_miss_latency::total 84912.607409 # average ReadExReq miss latency
2810system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency
2811system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency
2812system.l2c.demand_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency
2813system.l2c.demand_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency
2814system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency
2815system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency
2816system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency
2817system.l2c.demand_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency
2818system.l2c.demand_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency
2819system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency
2820system.l2c.demand_avg_miss_latency::total 100483.331190 # average overall miss latency
2821system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency
2822system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency
2823system.l2c.overall_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency
2824system.l2c.overall_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency
2825system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency
2826system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency
2827system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency
2828system.l2c.overall_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency
2829system.l2c.overall_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency
2830system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency
2831system.l2c.overall_avg_miss_latency::total 100483.331190 # average overall miss latency
2832system.l2c.blocked_cycles::no_mshrs 154 # number of cycles access was blocked
2833system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2834system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked
2835system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2836system.l2c.avg_blocked_cycles::no_mshrs 154 # average number of cycles each access was blocked
2837system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2838system.l2c.fast_writes 0 # number of fast writes performed
2839system.l2c.cache_copies 0 # number of cache copies performed
2840system.l2c.writebacks::writebacks 850996 # number of writebacks
2841system.l2c.writebacks::total 850996 # number of writebacks
2842system.l2c.ReadReq_mshr_hits::cpu0.inst 92 # number of ReadReq MSHR hits
2843system.l2c.ReadReq_mshr_hits::cpu0.data 20 # number of ReadReq MSHR hits
2844system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits
2845system.l2c.ReadReq_mshr_hits::cpu1.inst 88 # number of ReadReq MSHR hits
2846system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits
2847system.l2c.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
2848system.l2c.demand_mshr_hits::cpu0.inst 92 # number of demand (read+write) MSHR hits
2849system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits
2850system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits
2851system.l2c.demand_mshr_hits::cpu1.inst 88 # number of demand (read+write) MSHR hits
2852system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
2853system.l2c.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
2854system.l2c.overall_mshr_hits::cpu0.inst 92 # number of overall MSHR hits
2855system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits
2856system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits
2857system.l2c.overall_mshr_hits::cpu1.inst 88 # number of overall MSHR hits
2858system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
2859system.l2c.overall_mshr_hits::total 223 # number of overall MSHR hits
2860system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 577 # number of ReadReq MSHR misses
2861system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 634 # number of ReadReq MSHR misses
2862system.l2c.ReadReq_mshr_misses::cpu0.inst 40984 # number of ReadReq MSHR misses
2863system.l2c.ReadReq_mshr_misses::cpu0.data 94163 # number of ReadReq MSHR misses
2864system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of ReadReq MSHR misses
2865system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1129 # number of ReadReq MSHR misses
2866system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1344 # number of ReadReq MSHR misses
2867system.l2c.ReadReq_mshr_misses::cpu1.inst 39198 # number of ReadReq MSHR misses
2868system.l2c.ReadReq_mshr_misses::cpu1.data 84689 # number of ReadReq MSHR misses
2869system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq MSHR misses
2870system.l2c.ReadReq_mshr_misses::total 530924 # number of ReadReq MSHR misses
2871system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 427179 # number of WriteInvalidateReq MSHR misses
2872system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 105657 # number of WriteInvalidateReq MSHR misses
2873system.l2c.WriteInvalidateReq_mshr_misses::total 532836 # number of WriteInvalidateReq MSHR misses
2874system.l2c.UpgradeReq_mshr_misses::cpu0.data 47914 # number of UpgradeReq MSHR misses
2875system.l2c.UpgradeReq_mshr_misses::cpu1.data 38699 # number of UpgradeReq MSHR misses
2876system.l2c.UpgradeReq_mshr_misses::total 86613 # number of UpgradeReq MSHR misses
2877system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10572 # number of SCUpgradeReq MSHR misses
2878system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7951 # number of SCUpgradeReq MSHR misses
2879system.l2c.SCUpgradeReq_mshr_misses::total 18523 # number of SCUpgradeReq MSHR misses
2880system.l2c.ReadExReq_mshr_misses::cpu0.data 64089 # number of ReadExReq MSHR misses
2881system.l2c.ReadExReq_mshr_misses::cpu1.data 43672 # number of ReadExReq MSHR misses
2882system.l2c.ReadExReq_mshr_misses::total 107761 # number of ReadExReq MSHR misses
2883system.l2c.demand_mshr_misses::cpu0.dtb.walker 577 # number of demand (read+write) MSHR misses
2884system.l2c.demand_mshr_misses::cpu0.itb.walker 634 # number of demand (read+write) MSHR misses
2885system.l2c.demand_mshr_misses::cpu0.inst 40984 # number of demand (read+write) MSHR misses
2886system.l2c.demand_mshr_misses::cpu0.data 158252 # number of demand (read+write) MSHR misses
2887system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of demand (read+write) MSHR misses
2888system.l2c.demand_mshr_misses::cpu1.dtb.walker 1129 # number of demand (read+write) MSHR misses
2889system.l2c.demand_mshr_misses::cpu1.itb.walker 1344 # number of demand (read+write) MSHR misses
2890system.l2c.demand_mshr_misses::cpu1.inst 39198 # number of demand (read+write) MSHR misses
2891system.l2c.demand_mshr_misses::cpu1.data 128361 # number of demand (read+write) MSHR misses
2892system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) MSHR misses
2893system.l2c.demand_mshr_misses::total 638685 # number of demand (read+write) MSHR misses
2894system.l2c.overall_mshr_misses::cpu0.dtb.walker 577 # number of overall MSHR misses
2895system.l2c.overall_mshr_misses::cpu0.itb.walker 634 # number of overall MSHR misses
2896system.l2c.overall_mshr_misses::cpu0.inst 40984 # number of overall MSHR misses
2897system.l2c.overall_mshr_misses::cpu0.data 158252 # number of overall MSHR misses
2898system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of overall MSHR misses
2899system.l2c.overall_mshr_misses::cpu1.dtb.walker 1129 # number of overall MSHR misses
2900system.l2c.overall_mshr_misses::cpu1.itb.walker 1344 # number of overall MSHR misses
2901system.l2c.overall_mshr_misses::cpu1.inst 39198 # number of overall MSHR misses
2902system.l2c.overall_mshr_misses::cpu1.data 128361 # number of overall MSHR misses
2903system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of overall MSHR misses
2904system.l2c.overall_mshr_misses::total 638685 # number of overall MSHR misses
2905system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of ReadReq MSHR miss cycles
2906system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 47468736 # number of ReadReq MSHR miss cycles
2907system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2944278477 # number of ReadReq MSHR miss cycles
2908system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7281223143 # number of ReadReq MSHR miss cycles
2909system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of ReadReq MSHR miss cycles
2910system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of ReadReq MSHR miss cycles
2911system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 103357750 # number of ReadReq MSHR miss cycles
2912system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2790521653 # number of ReadReq MSHR miss cycles
2913system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6370080782 # number of ReadReq MSHR miss cycles
2914system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of ReadReq MSHR miss cycles
2915system.l2c.ReadReq_mshr_miss_latency::total 48441561155 # number of ReadReq MSHR miss cycles
2916system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13848705306 # number of WriteInvalidateReq MSHR miss cycles
2917system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3323050924 # number of WriteInvalidateReq MSHR miss cycles
2918system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17171756230 # number of WriteInvalidateReq MSHR miss cycles
2919system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 851924300 # number of UpgradeReq MSHR miss cycles
2920system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 688614575 # number of UpgradeReq MSHR miss cycles
2921system.l2c.UpgradeReq_mshr_miss_latency::total 1540538875 # number of UpgradeReq MSHR miss cycles
2922system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 188348548 # number of SCUpgradeReq MSHR miss cycles
2923system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 142101429 # number of SCUpgradeReq MSHR miss cycles
2924system.l2c.SCUpgradeReq_mshr_miss_latency::total 330449977 # number of SCUpgradeReq MSHR miss cycles
2925system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4782492948 # number of ReadExReq MSHR miss cycles
2926system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3019981565 # number of ReadExReq MSHR miss cycles
2927system.l2c.ReadExReq_mshr_miss_latency::total 7802474513 # number of ReadExReq MSHR miss cycles
2928system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of demand (read+write) MSHR miss cycles
2929system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 47468736 # number of demand (read+write) MSHR miss cycles
2930system.l2c.demand_mshr_miss_latency::cpu0.inst 2944278477 # number of demand (read+write) MSHR miss cycles
2931system.l2c.demand_mshr_miss_latency::cpu0.data 12063716091 # number of demand (read+write) MSHR miss cycles
2932system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of demand (read+write) MSHR miss cycles
2933system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of demand (read+write) MSHR miss cycles
2934system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 103357750 # number of demand (read+write) MSHR miss cycles
2935system.l2c.demand_mshr_miss_latency::cpu1.inst 2790521653 # number of demand (read+write) MSHR miss cycles
2936system.l2c.demand_mshr_miss_latency::cpu1.data 9390062347 # number of demand (read+write) MSHR miss cycles
2937system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of demand (read+write) MSHR miss cycles
2938system.l2c.demand_mshr_miss_latency::total 56244035668 # number of demand (read+write) MSHR miss cycles
2939system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of overall MSHR miss cycles
2940system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 47468736 # number of overall MSHR miss cycles
2941system.l2c.overall_mshr_miss_latency::cpu0.inst 2944278477 # number of overall MSHR miss cycles
2942system.l2c.overall_mshr_miss_latency::cpu0.data 12063716091 # number of overall MSHR miss cycles
2943system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of overall MSHR miss cycles
2944system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of overall MSHR miss cycles
2945system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles
2946system.l2c.overall_mshr_miss_latency::cpu1.inst 2790521653 # number of overall MSHR miss cycles
2947system.l2c.overall_mshr_miss_latency::cpu1.data 9390062347 # number of overall MSHR miss cycles
2948system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles
2949system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles
2950system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles
2951system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles
2952system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles
2953system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles
2954system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles
2955system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles
2956system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles
2957system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles
2958system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles
2959system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles
2960system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles
2961system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles
2962system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles
2963system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses
2964system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses
2965system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses
2966system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses
2967system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses
2968system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses
2969system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses
2970system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses
2971system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses
2972system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses
2973system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses
2974system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses
2975system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses
2976system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses
2977system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses
2978system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses
2979system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses
2980system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses
2981system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses
2982system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses
2983system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses
2984system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses
2985system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses
2986system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses
2987system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses
2988system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses
2989system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses
2990system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses
2991system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses
2992system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses
2993system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses
2994system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses
2995system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses
2996system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses
2997system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses
2998system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses
2999system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses
3000system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses
3001system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses
3002system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses
3003system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses
3004system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses
3005system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses
3006system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses
3007system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses
3008system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency
3009system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency
3010system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency
3011system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency
3012system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency
3013system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency
3014system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency
3015system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency
3016system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency
3017system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency
3018system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency
3019system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency
3020system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency
3021system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency
3022system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency
3023system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency
3024system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency
3025system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency
3026system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency
3027system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency
3028system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency
3029system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency
3030system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency
3031system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
3032system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
3033system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
3034system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
3035system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
3036system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
3037system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
3038system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
3039system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
3040system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
3041system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
3042system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
3043system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
3044system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
3045system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
3046system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
3047system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
3048system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
3049system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
3050system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
3051system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
3052system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
3053system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
3054system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
3055system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
3056system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
3057system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
3058system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
3059system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
3060system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
3061system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
3062system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
3063system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
3064system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
3065system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
3066system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3067system.membus.trans_dist::ReadReq 622157 # Transaction distribution
3068system.membus.trans_dist::ReadResp 622157 # Transaction distribution
3069system.membus.trans_dist::WriteReq 38973 # Transaction distribution
3070system.membus.trans_dist::WriteResp 38973 # Transaction distribution
3071system.membus.trans_dist::Writeback 957695 # Transaction distribution
3072system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution
3073system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution
3074system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution
3075system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution
3076system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution
3077system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
3078system.membus.trans_dist::ReadExReq 123220 # Transaction distribution
3079system.membus.trans_dist::ReadExResp 104410 # Transaction distribution
3080system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes)
3081system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3082system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes)
3083system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes)
3084system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes)
3085system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
3086system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
3087system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes)
3088system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes)
3089system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3090system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes)
3091system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes)
3092system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes)
3093system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes)
3094system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes)
3095system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes)
3096system.membus.snoops 581158 # Total snoops (count)
3097system.membus.snoop_fanout::samples 2928688 # Request fanout histogram
3098system.membus.snoop_fanout::mean 1 # Request fanout histogram
3099system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3100system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3101system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3102system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram
3103system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3104system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3105system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3106system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3107system.membus.snoop_fanout::total 2928688 # Request fanout histogram
3108system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks)
3109system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3110system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
3111system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3112system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks)
3113system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3114system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks)
3115system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3116system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks)
3117system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3118system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks)
3119system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3120system.realview.ethernet.txBytes 966 # Bytes Transmitted
3121system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3122system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3123system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3124system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3125system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3126system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3154system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3155system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3156system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3157system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3158system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3159system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3160system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3161system.realview.ethernet.droppedPackets 0 # number of packets dropped
3162system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
3163system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
3164system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
3165system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
3166system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
3167system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
3168system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
3169system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
3170system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
3171system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
3172system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
3173system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
3174system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
3175system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
3176system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
3177system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
3178system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
3179system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
3180system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
3181system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
3182system.toL2Bus.snoops 1518303 # Total snoops (count)
3183system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
3184system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
3185system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
3186system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3187system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3188system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
3189system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
3190system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3191system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3192system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3193system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
3194system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
3195system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3196system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
3197system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3198system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
3199system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3200system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
3201system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3202
3203---------- End Simulation Statistics ----------