1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.579919 # Number of seconds simulated
4sim_ticks 47579919171500 # Number of ticks simulated
5final_tick 47579919171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 994477 # Simulator instruction rate (inst/s)
8host_op_rate 1169790 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 52043300787 # Simulator tick rate (ticks/s)
10host_mem_usage 760992 # Number of bytes of host memory used
11host_seconds 914.24 # Real time elapsed on the host
12sim_insts 909188095 # Number of instructions simulated
13sim_ops 1069465904 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 95808 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 82560 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 3301172 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 14310344 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 18775424 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 218368 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 230464 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3000056 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 12646096 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 13033600 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory
27system.physmem.bytes_read::total 66121412 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 3301172 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3000056 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 6301228 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 84303296 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 84323880 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 1497 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1290 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 91988 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 223612 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 293366 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 3412 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 3601 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 46964 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 197608 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 203650 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1073668 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1317239 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1319813 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2014 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 1735 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 69382 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 300764 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 394608 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 4589 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 4844 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 63053 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 265786 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 273931 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 8985 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1389692 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 69382 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 63053 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 132435 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1771825 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1772258 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1771825 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2014 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 1735 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 69382 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 301197 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 394608 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 4589 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 4844 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 63053 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 265786 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 273931 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 8985 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3161949 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1073668 # Number of read requests accepted
84system.physmem.writeReqs 1319813 # Number of write requests accepted
85system.physmem.readBursts 1073668 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1319813 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 68691008 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 23744 # Total number of bytes read from write queue
89system.physmem.bytesWritten 84321664 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 66121412 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 84323880 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 371 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 64017 # Per bank write bursts
96system.physmem.perBankRdBursts::1 68044 # Per bank write bursts
97system.physmem.perBankRdBursts::2 61517 # Per bank write bursts
98system.physmem.perBankRdBursts::3 65955 # Per bank write bursts
99system.physmem.perBankRdBursts::4 65874 # Per bank write bursts
100system.physmem.perBankRdBursts::5 75726 # Per bank write bursts
101system.physmem.perBankRdBursts::6 64933 # Per bank write bursts
102system.physmem.perBankRdBursts::7 65424 # Per bank write bursts
103system.physmem.perBankRdBursts::8 62003 # Per bank write bursts
104system.physmem.perBankRdBursts::9 113372 # Per bank write bursts
105system.physmem.perBankRdBursts::10 63434 # Per bank write bursts
106system.physmem.perBankRdBursts::11 64718 # Per bank write bursts
107system.physmem.perBankRdBursts::12 56904 # Per bank write bursts
108system.physmem.perBankRdBursts::13 64084 # Per bank write bursts
109system.physmem.perBankRdBursts::14 56898 # Per bank write bursts
110system.physmem.perBankRdBursts::15 60394 # Per bank write bursts
111system.physmem.perBankWrBursts::0 80527 # Per bank write bursts
112system.physmem.perBankWrBursts::1 85904 # Per bank write bursts
113system.physmem.perBankWrBursts::2 80420 # Per bank write bursts
114system.physmem.perBankWrBursts::3 86054 # Per bank write bursts
115system.physmem.perBankWrBursts::4 85401 # Per bank write bursts
116system.physmem.perBankWrBursts::5 88715 # Per bank write bursts
117system.physmem.perBankWrBursts::6 80808 # Per bank write bursts
118system.physmem.perBankWrBursts::7 81222 # Per bank write bursts
119system.physmem.perBankWrBursts::8 80522 # Per bank write bursts
120system.physmem.perBankWrBursts::9 87926 # Per bank write bursts
121system.physmem.perBankWrBursts::10 79616 # Per bank write bursts
122system.physmem.perBankWrBursts::11 81105 # Per bank write bursts
123system.physmem.perBankWrBursts::12 77689 # Per bank write bursts
124system.physmem.perBankWrBursts::13 84231 # Per bank write bursts
125system.physmem.perBankWrBursts::14 77252 # Per bank write bursts
126system.physmem.perBankWrBursts::15 80134 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 116 # Number of times write queue was full causing retry
129system.physmem.totGap 47579915806000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 43195 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1030443 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1317239 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 761963 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 94096 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 44762 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 38689 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 33193 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 29336 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 25572 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 22083 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 17610 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 1054 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 617 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 470 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 330 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 233 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 201 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 153 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 138 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 35874 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 42279 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 54831 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 58608 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 65543 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 69713 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 74423 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 78144 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 80302 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 80268 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 82803 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 85991 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 82780 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 84137 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 91440 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 82956 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 77042 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 74792 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 3448 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 1528 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 878 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 781 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 698 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 574 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 498 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 492 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 412 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 374 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 248 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 154 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 157 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 157 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 302 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1107709 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 138.133954 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 95.206974 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 184.490982 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 762645 68.85% 68.85% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 210995 19.05% 87.90% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 48832 4.41% 92.31% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 22284 2.01% 94.32% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 16979 1.53% 95.85% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 10320 0.93% 96.78% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 6180 0.56% 97.34% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 5743 0.52% 97.86% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 23731 2.14% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1107709 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 70958 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 15.125666 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 121.252784 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-1023 70954 99.99% 99.99% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 70958 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 70958 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 18.567688 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.991036 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 7.306981 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 58539 82.50% 82.50% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 9965 14.04% 96.54% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 642 0.90% 97.45% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 182 0.26% 97.70% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 135 0.19% 97.89% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 121 0.17% 98.06% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 191 0.27% 98.33% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 83 0.12% 98.45% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 286 0.40% 98.85% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 59 0.08% 98.94% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 34 0.05% 98.98% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 42 0.06% 99.04% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 259 0.37% 99.41% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 42 0.06% 99.47% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 31 0.04% 99.51% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 116 0.16% 99.67% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 167 0.24% 99.91% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::124-127 4 0.01% 99.94% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::144-147 8 0.01% 99.98% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::172-175 1 0.00% 99.98% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::176-179 8 0.01% 99.99% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::total 70958 # Writes before turning the bus around for reads
304system.physmem.totQLat 35332291342 # Total ticks spent queuing
305system.physmem.totMemAccLat 55456610092 # Total ticks spent from burst creation until serviced by the DRAM
306system.physmem.totBusLat 5366485000 # Total ticks spent in databus transfers
307system.physmem.avgQLat 32919.40 # Average queueing delay per DRAM burst
308system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
309system.physmem.avgMemAccLat 51669.40 # Average memory access latency per DRAM burst
310system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
311system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s
312system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s
313system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s
314system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
315system.physmem.busUtil 0.03 # Data bus utilization in percentage
316system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
317system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
318system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
319system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing
320system.physmem.readRowHits 793862 # Number of row buffer hits during reads
321system.physmem.writeRowHits 489250 # Number of row buffer hits during writes
322system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads
323system.physmem.writeRowHitRate 37.13 # Row buffer hit rate for writes
324system.physmem.avgGap 19878961.15 # Average gap between requests
325system.physmem.pageHitRate 53.67 # Row buffer hit rate, read and write combined
326system.physmem_0.actEnergy 4296030480 # Energy for activate commands per rank (pJ)
327system.physmem_0.preEnergy 2344064250 # Energy for precharge commands per rank (pJ)
328system.physmem_0.readEnergy 4145606400 # Energy for read commands per rank (pJ)
329system.physmem_0.writeEnergy 4335450480 # Energy for write commands per rank (pJ)
330system.physmem_0.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ)
331system.physmem_0.actBackEnergy 1225363115070 # Energy for active background per rank (pJ)
332system.physmem_0.preBackEnergy 27473067932250 # Energy for precharge background per rank (pJ)
333system.physmem_0.totalEnergy 31821240813090 # Total energy per rank (pJ)
334system.physmem_0.averagePower 668.795690 # Core power per rank (mW)
335system.physmem_0.memoryStateTime::IDLE 45703113685218 # Time in different power states
336system.physmem_0.memoryStateTime::REF 1588797860000 # Time in different power states
337system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
338system.physmem_0.memoryStateTime::ACT 288003145282 # Time in different power states
339system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
340system.physmem_1.actEnergy 4078249560 # Energy for activate commands per rank (pJ)
341system.physmem_1.preEnergy 2225235375 # Energy for precharge commands per rank (pJ)
342system.physmem_1.readEnergy 4226055600 # Energy for read commands per rank (pJ)
343system.physmem_1.writeEnergy 4202118000 # Energy for write commands per rank (pJ)
344system.physmem_1.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ)
345system.physmem_1.actBackEnergy 1219254807825 # Energy for active background per rank (pJ)
346system.physmem_1.preBackEnergy 27478426088250 # Energy for precharge background per rank (pJ)
347system.physmem_1.totalEnergy 31820101168770 # Total energy per rank (pJ)
348system.physmem_1.averagePower 668.771738 # Core power per rank (mW)
349system.physmem_1.memoryStateTime::IDLE 45712034121275 # Time in different power states
350system.physmem_1.memoryStateTime::REF 1588797860000 # Time in different power states
351system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
352system.physmem_1.memoryStateTime::ACT 279086495725 # Time in different power states
353system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
354system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
355system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
359system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
360system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory

--- 14 unchanged lines hidden (view full) ---

375system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
376system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
377system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
378system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
379system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
380system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
381system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
382system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
383system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
384system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
385system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
386system.cpu_clk_domain.clock 500 # Clock period in ticks
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

408system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
409system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
410system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
411system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
412system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
413system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
414system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
415system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
416system.cpu0.dtb.walker.walks 116306 # Table walker walks requested
417system.cpu0.dtb.walker.walksLong 116306 # Table walker walks initiated with long descriptors
418system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10885 # Level at which table walker walks with long descriptors terminate
419system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88573 # Level at which table walker walks with long descriptors terminate
420system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting
421system.cpu0.dtb.walker.walkWaitTime::samples 116284 # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::mean 0.223591 # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::stdev 76.245351 # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::0-2047 116283 100.00% 100.00% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::total 116284 # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkCompletionTime::samples 99480 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731 # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::0-65535 98726 99.24% 99.24% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::65536-131071 154 0.15% 99.40% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::131072-196607 495 0.50% 99.89% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::196608-262143 15 0.02% 99.91% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::262144-327679 37 0.04% 99.95% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::total 99480 # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walksPending::samples 8374009004 # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::mean 0.680543 # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::stdev 0.466266 # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::0 2675132860 31.95% 31.95% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::1 5698876144 68.05% 100.00% # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::total 8374009004 # Table walker pending requests distribution
449system.cpu0.dtb.walker.walkPageSizes::4K 88573 89.06% 89.06% # Table walker page sizes translated
450system.cpu0.dtb.walker.walkPageSizes::2M 10885 10.94% 100.00% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::total 99458 # Table walker page sizes translated
452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116306 # Table walker requests started/completed, data/inst
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116306 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 99458 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 99458 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin::total 215764 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.inst_hits 0 # ITB inst hits
460system.cpu0.dtb.inst_misses 0 # ITB inst misses
461system.cpu0.dtb.read_hits 86290817 # DTB read hits
462system.cpu0.dtb.read_misses 86990 # DTB read misses
463system.cpu0.dtb.write_hits 77965379 # DTB write hits
464system.cpu0.dtb.write_misses 29316 # DTB write misses
465system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
466system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
467system.cpu0.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
468system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
469system.cpu0.dtb.flush_entries 36691 # Number of entries that have been flushed from TLB
470system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
471system.cpu0.dtb.prefetch_faults 4448 # Number of TLB faults due to prefetch
472system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
473system.cpu0.dtb.perms_faults 9789 # Number of TLB faults due to permissions restrictions
474system.cpu0.dtb.read_accesses 86377807 # DTB read accesses
475system.cpu0.dtb.write_accesses 77994695 # DTB write accesses
476system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
477system.cpu0.dtb.hits 164256196 # DTB hits
478system.cpu0.dtb.misses 116306 # DTB misses
479system.cpu0.dtb.accesses 164372502 # DTB accesses
480system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

501system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
502system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
503system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
504system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
505system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
506system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
507system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
508system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
509system.cpu0.itb.walker.walks 53337 # Table walker walks requested
510system.cpu0.itb.walker.walksLong 53337 # Table walker walks initiated with long descriptors
511system.cpu0.itb.walker.walksLongTerminationLevel::Level2 559 # Level at which table walker walks with long descriptors terminate
512system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47077 # Level at which table walker walks with long descriptors terminate
513system.cpu0.itb.walker.walkWaitTime::samples 53337 # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::0 53337 100.00% 100.00% # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkWaitTime::total 53337 # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkCompletionTime::samples 47636 # Table walker service (enqueue to completion) latency
517system.cpu0.itb.walker.walkCompletionTime::mean 25421.330506 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238 # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::0-65535 46963 98.59% 98.59% # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::65536-131071 37 0.08% 98.66% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::131072-196607 536 1.13% 99.79% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::196608-262143 19 0.04% 99.83% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::262144-327679 27 0.06% 99.89% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.05% 99.97% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::total 47636 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution
534system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution
535system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution
536system.cpu0.itb.walker.walkPageSizes::4K 47077 98.83% 98.83% # Table walker page sizes translated
537system.cpu0.itb.walker.walkPageSizes::2M 559 1.17% 100.00% # Table walker page sizes translated
538system.cpu0.itb.walker.walkPageSizes::total 47636 # Table walker page sizes translated
539system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
540system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53337 # Table walker requests started/completed, data/inst
541system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53337 # Table walker requests started/completed, data/inst
542system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
543system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47636 # Table walker requests started/completed, data/inst
544system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47636 # Table walker requests started/completed, data/inst
545system.cpu0.itb.walker.walkRequestOrigin::total 100973 # Table walker requests started/completed, data/inst
546system.cpu0.itb.inst_hits 461259285 # ITB inst hits
547system.cpu0.itb.inst_misses 53337 # ITB inst misses
548system.cpu0.itb.read_hits 0 # DTB read hits
549system.cpu0.itb.read_misses 0 # DTB read misses
550system.cpu0.itb.write_hits 0 # DTB write hits
551system.cpu0.itb.write_misses 0 # DTB write misses
552system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
553system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
554system.cpu0.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
555system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
556system.cpu0.itb.flush_entries 25459 # Number of entries that have been flushed from TLB
557system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
558system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
559system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
560system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
561system.cpu0.itb.read_accesses 0 # DTB read accesses
562system.cpu0.itb.write_accesses 0 # DTB write accesses
563system.cpu0.itb.inst_accesses 461312622 # ITB inst accesses
564system.cpu0.itb.hits 461259285 # DTB hits
565system.cpu0.itb.misses 53337 # DTB misses
566system.cpu0.itb.accesses 461312622 # DTB accesses
567system.cpu0.numCycles 95159838338 # number of cpu cycles simulated
568system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
569system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
570system.cpu0.kern.inst.arm 0 # number of arm instructions executed
571system.cpu0.kern.inst.quiesce 13594 # number of quiesce instructions executed
572system.cpu0.committedInsts 460977499 # Number of instructions committed
573system.cpu0.committedOps 540688150 # Number of ops (including micro ops) committed
574system.cpu0.num_int_alu_accesses 495872658 # Number of integer alu accesses
575system.cpu0.num_fp_alu_accesses 377758 # Number of float alu accesses
576system.cpu0.num_func_calls 27096084 # number of times a function call or return occured
577system.cpu0.num_conditional_control_insts 70442961 # number of instructions that are conditional controls
578system.cpu0.num_int_insts 495872658 # number of integer instructions
579system.cpu0.num_fp_insts 377758 # number of float instructions
580system.cpu0.num_int_register_reads 724744849 # number of times the integer registers were read
581system.cpu0.num_int_register_writes 393986605 # number of times the integer registers were written
582system.cpu0.num_fp_register_reads 623895 # number of times the floating registers were read
583system.cpu0.num_fp_register_writes 289632 # number of times the floating registers were written
584system.cpu0.num_cc_register_reads 122670714 # number of times the CC registers were read
585system.cpu0.num_cc_register_writes 122315787 # number of times the CC registers were written
586system.cpu0.num_mem_refs 164249297 # number of memory refs
587system.cpu0.num_load_insts 86287437 # Number of load instructions
588system.cpu0.num_store_insts 77961860 # Number of store instructions
589system.cpu0.num_idle_cycles 93938070746.252213 # Number of idle cycles
590system.cpu0.num_busy_cycles 1221767591.747779 # Number of busy cycles
591system.cpu0.not_idle_fraction 0.012839 # Percentage of non-idle cycles
592system.cpu0.idle_fraction 0.987161 # Percentage of idle cycles
593system.cpu0.Branches 102925889 # Number of branches fetched
594system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
595system.cpu0.op_class::IntAlu 375485543 69.40% 69.40% # Class of executed instruction
596system.cpu0.op_class::IntMult 1178634 0.22% 69.62% # Class of executed instruction
597system.cpu0.op_class::IntDiv 59866 0.01% 69.63% # Class of executed instruction
598system.cpu0.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction
599system.cpu0.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction
600system.cpu0.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction
601system.cpu0.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction
602system.cpu0.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction
603system.cpu0.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction
604system.cpu0.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction
605system.cpu0.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction
606system.cpu0.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction
607system.cpu0.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction
608system.cpu0.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction
609system.cpu0.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction
610system.cpu0.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction
611system.cpu0.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction
612system.cpu0.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction
613system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction
614system.cpu0.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction
615system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.63% # Class of executed instruction
616system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction
617system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.63% # Class of executed instruction
618system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.63% # Class of executed instruction
619system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction
620system.cpu0.op_class::SimdFloatMisc 39720 0.01% 69.64% # Class of executed instruction
621system.cpu0.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction
622system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction
623system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction
624system.cpu0.op_class::MemRead 86287437 15.95% 85.59% # Class of executed instruction
625system.cpu0.op_class::MemWrite 77961860 14.41% 100.00% # Class of executed instruction
626system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
627system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
628system.cpu0.op_class::total 541013060 # Class of executed instruction
629system.cpu0.dcache.tags.replacements 5729731 # number of replacements
630system.cpu0.dcache.tags.tagsinuse 475.426094 # Cycle average of tags in use
631system.cpu0.dcache.tags.total_refs 158277130 # Total number of references to valid blocks.
632system.cpu0.dcache.tags.sampled_refs 5730241 # Sample count of references to valid blocks.
633system.cpu0.dcache.tags.avg_refs 27.621374 # Average number of references to valid blocks.
634system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit.
635system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.426094 # Average occupied blocks per requestor
636system.cpu0.dcache.tags.occ_percent::cpu0.data 0.928567 # Average percentage of cache occupancy
637system.cpu0.dcache.tags.occ_percent::total 0.928567 # Average percentage of cache occupancy
638system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
639system.cpu0.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
640system.cpu0.dcache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id
641system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id
642system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
643system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
644system.cpu0.dcache.tags.tag_accesses 334208607 # Number of tag accesses
645system.cpu0.dcache.tags.data_accesses 334208607 # Number of data accesses
646system.cpu0.dcache.ReadReq_hits::cpu0.data 80244173 # number of ReadReq hits
647system.cpu0.dcache.ReadReq_hits::total 80244173 # number of ReadReq hits
648system.cpu0.dcache.WriteReq_hits::cpu0.data 73488227 # number of WriteReq hits
649system.cpu0.dcache.WriteReq_hits::total 73488227 # number of WriteReq hits
650system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200421 # number of SoftPFReq hits
651system.cpu0.dcache.SoftPFReq_hits::total 200421 # number of SoftPFReq hits
652system.cpu0.dcache.WriteLineReq_hits::cpu0.data 184838 # number of WriteLineReq hits
653system.cpu0.dcache.WriteLineReq_hits::total 184838 # number of WriteLineReq hits
654system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1883304 # number of LoadLockedReq hits
655system.cpu0.dcache.LoadLockedReq_hits::total 1883304 # number of LoadLockedReq hits
656system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1842196 # number of StoreCondReq hits
657system.cpu0.dcache.StoreCondReq_hits::total 1842196 # number of StoreCondReq hits
658system.cpu0.dcache.demand_hits::cpu0.data 153732400 # number of demand (read+write) hits
659system.cpu0.dcache.demand_hits::total 153732400 # number of demand (read+write) hits
660system.cpu0.dcache.overall_hits::cpu0.data 153932821 # number of overall hits
661system.cpu0.dcache.overall_hits::total 153932821 # number of overall hits
662system.cpu0.dcache.ReadReq_misses::cpu0.data 3080001 # number of ReadReq misses
663system.cpu0.dcache.ReadReq_misses::total 3080001 # number of ReadReq misses
664system.cpu0.dcache.WriteReq_misses::cpu0.data 1447988 # number of WriteReq misses
665system.cpu0.dcache.WriteReq_misses::total 1447988 # number of WriteReq misses
666system.cpu0.dcache.SoftPFReq_misses::cpu0.data 695954 # number of SoftPFReq misses
667system.cpu0.dcache.SoftPFReq_misses::total 695954 # number of SoftPFReq misses
668system.cpu0.dcache.WriteLineReq_misses::cpu0.data 768699 # number of WriteLineReq misses
669system.cpu0.dcache.WriteLineReq_misses::total 768699 # number of WriteLineReq misses
670system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 158470 # number of LoadLockedReq misses
671system.cpu0.dcache.LoadLockedReq_misses::total 158470 # number of LoadLockedReq misses
672system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198134 # number of StoreCondReq misses
673system.cpu0.dcache.StoreCondReq_misses::total 198134 # number of StoreCondReq misses
674system.cpu0.dcache.demand_misses::cpu0.data 4527989 # number of demand (read+write) misses
675system.cpu0.dcache.demand_misses::total 4527989 # number of demand (read+write) misses
676system.cpu0.dcache.overall_misses::cpu0.data 5223943 # number of overall misses
677system.cpu0.dcache.overall_misses::total 5223943 # number of overall misses
678system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52478340000 # number of ReadReq miss cycles
679system.cpu0.dcache.ReadReq_miss_latency::total 52478340000 # number of ReadReq miss cycles
680system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 38322628500 # number of WriteReq miss cycles
681system.cpu0.dcache.WriteReq_miss_latency::total 38322628500 # number of WriteReq miss cycles
682system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 49559521500 # number of WriteLineReq miss cycles
683system.cpu0.dcache.WriteLineReq_miss_latency::total 49559521500 # number of WriteLineReq miss cycles
684system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2516267500 # number of LoadLockedReq miss cycles
685system.cpu0.dcache.LoadLockedReq_miss_latency::total 2516267500 # number of LoadLockedReq miss cycles
686system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5589291500 # number of StoreCondReq miss cycles
687system.cpu0.dcache.StoreCondReq_miss_latency::total 5589291500 # number of StoreCondReq miss cycles
688system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2738500 # number of StoreCondFailReq miss cycles
689system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2738500 # number of StoreCondFailReq miss cycles
690system.cpu0.dcache.demand_miss_latency::cpu0.data 90800968500 # number of demand (read+write) miss cycles
691system.cpu0.dcache.demand_miss_latency::total 90800968500 # number of demand (read+write) miss cycles
692system.cpu0.dcache.overall_miss_latency::cpu0.data 90800968500 # number of overall miss cycles
693system.cpu0.dcache.overall_miss_latency::total 90800968500 # number of overall miss cycles
694system.cpu0.dcache.ReadReq_accesses::cpu0.data 83324174 # number of ReadReq accesses(hits+misses)
695system.cpu0.dcache.ReadReq_accesses::total 83324174 # number of ReadReq accesses(hits+misses)
696system.cpu0.dcache.WriteReq_accesses::cpu0.data 74936215 # number of WriteReq accesses(hits+misses)
697system.cpu0.dcache.WriteReq_accesses::total 74936215 # number of WriteReq accesses(hits+misses)
698system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 896375 # number of SoftPFReq accesses(hits+misses)
699system.cpu0.dcache.SoftPFReq_accesses::total 896375 # number of SoftPFReq accesses(hits+misses)
700system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 953537 # number of WriteLineReq accesses(hits+misses)
701system.cpu0.dcache.WriteLineReq_accesses::total 953537 # number of WriteLineReq accesses(hits+misses)
702system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2041774 # number of LoadLockedReq accesses(hits+misses)
703system.cpu0.dcache.LoadLockedReq_accesses::total 2041774 # number of LoadLockedReq accesses(hits+misses)
704system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2040330 # number of StoreCondReq accesses(hits+misses)
705system.cpu0.dcache.StoreCondReq_accesses::total 2040330 # number of StoreCondReq accesses(hits+misses)
706system.cpu0.dcache.demand_accesses::cpu0.data 158260389 # number of demand (read+write) accesses
707system.cpu0.dcache.demand_accesses::total 158260389 # number of demand (read+write) accesses
708system.cpu0.dcache.overall_accesses::cpu0.data 159156764 # number of overall (read+write) accesses
709system.cpu0.dcache.overall_accesses::total 159156764 # number of overall (read+write) accesses
710system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036964 # miss rate for ReadReq accesses
711system.cpu0.dcache.ReadReq_miss_rate::total 0.036964 # miss rate for ReadReq accesses
712system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019323 # miss rate for WriteReq accesses
713system.cpu0.dcache.WriteReq_miss_rate::total 0.019323 # miss rate for WriteReq accesses
714system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.776409 # miss rate for SoftPFReq accesses
715system.cpu0.dcache.SoftPFReq_miss_rate::total 0.776409 # miss rate for SoftPFReq accesses
716system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.806155 # miss rate for WriteLineReq accesses
717system.cpu0.dcache.WriteLineReq_miss_rate::total 0.806155 # miss rate for WriteLineReq accesses
718system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077614 # miss rate for LoadLockedReq accesses
719system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077614 # miss rate for LoadLockedReq accesses
720system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097109 # miss rate for StoreCondReq accesses
721system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097109 # miss rate for StoreCondReq accesses
722system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028611 # miss rate for demand accesses
723system.cpu0.dcache.demand_miss_rate::total 0.028611 # miss rate for demand accesses
724system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032823 # miss rate for overall accesses
725system.cpu0.dcache.overall_miss_rate::total 0.032823 # miss rate for overall accesses
726system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17038.416546 # average ReadReq miss latency
727system.cpu0.dcache.ReadReq_avg_miss_latency::total 17038.416546 # average ReadReq miss latency
728system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26466.122993 # average WriteReq miss latency
729system.cpu0.dcache.WriteReq_avg_miss_latency::total 26466.122993 # average WriteReq miss latency
730system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 64471.947407 # average WriteLineReq miss latency
731system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 64471.947407 # average WriteLineReq miss latency
732system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15878.510128 # average LoadLockedReq miss latency
733system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15878.510128 # average LoadLockedReq miss latency
734system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28209.653568 # average StoreCondReq miss latency
735system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28209.653568 # average StoreCondReq miss latency
736system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
737system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
738system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20053.266141 # average overall miss latency
739system.cpu0.dcache.demand_avg_miss_latency::total 20053.266141 # average overall miss latency
740system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17381.692048 # average overall miss latency
741system.cpu0.dcache.overall_avg_miss_latency::total 17381.692048 # average overall miss latency
742system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
743system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
744system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
745system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
746system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
747system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
748system.cpu0.dcache.fast_writes 0 # number of fast writes performed
749system.cpu0.dcache.cache_copies 0 # number of cache copies performed
750system.cpu0.dcache.writebacks::writebacks 5729731 # number of writebacks
751system.cpu0.dcache.writebacks::total 5729731 # number of writebacks
752system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28073 # number of ReadReq MSHR hits
753system.cpu0.dcache.ReadReq_mshr_hits::total 28073 # number of ReadReq MSHR hits
754system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21239 # number of WriteReq MSHR hits
755system.cpu0.dcache.WriteReq_mshr_hits::total 21239 # number of WriteReq MSHR hits
756system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41058 # number of LoadLockedReq MSHR hits
757system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41058 # number of LoadLockedReq MSHR hits
758system.cpu0.dcache.demand_mshr_hits::cpu0.data 49312 # number of demand (read+write) MSHR hits
759system.cpu0.dcache.demand_mshr_hits::total 49312 # number of demand (read+write) MSHR hits
760system.cpu0.dcache.overall_mshr_hits::cpu0.data 49312 # number of overall MSHR hits
761system.cpu0.dcache.overall_mshr_hits::total 49312 # number of overall MSHR hits
762system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3051928 # number of ReadReq MSHR misses
763system.cpu0.dcache.ReadReq_mshr_misses::total 3051928 # number of ReadReq MSHR misses
764system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1426749 # number of WriteReq MSHR misses
765system.cpu0.dcache.WriteReq_mshr_misses::total 1426749 # number of WriteReq MSHR misses
766system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694810 # number of SoftPFReq MSHR misses
767system.cpu0.dcache.SoftPFReq_mshr_misses::total 694810 # number of SoftPFReq MSHR misses
768system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 768699 # number of WriteLineReq MSHR misses
769system.cpu0.dcache.WriteLineReq_mshr_misses::total 768699 # number of WriteLineReq MSHR misses
770system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117412 # number of LoadLockedReq MSHR misses
771system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117412 # number of LoadLockedReq MSHR misses
772system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198134 # number of StoreCondReq MSHR misses
773system.cpu0.dcache.StoreCondReq_mshr_misses::total 198134 # number of StoreCondReq MSHR misses
774system.cpu0.dcache.demand_mshr_misses::cpu0.data 4478677 # number of demand (read+write) MSHR misses
775system.cpu0.dcache.demand_mshr_misses::total 4478677 # number of demand (read+write) MSHR misses
776system.cpu0.dcache.overall_mshr_misses::cpu0.data 5173487 # number of overall MSHR misses
777system.cpu0.dcache.overall_mshr_misses::total 5173487 # number of overall MSHR misses
778system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable
779system.cpu0.dcache.ReadReq_mshr_uncacheable::total 28514 # number of ReadReq MSHR uncacheable
780system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable
781system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27871 # number of WriteReq MSHR uncacheable
782system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses
783system.cpu0.dcache.overall_mshr_uncacheable_misses::total 56385 # number of overall MSHR uncacheable misses
784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47315434500 # number of ReadReq MSHR miss cycles
785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47315434500 # number of ReadReq MSHR miss cycles
786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36384996000 # number of WriteReq MSHR miss cycles
787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36384996000 # number of WriteReq MSHR miss cycles
788system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17003029000 # number of SoftPFReq MSHR miss cycles
789system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17003029000 # number of SoftPFReq MSHR miss cycles
790system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 48790822500 # number of WriteLineReq MSHR miss cycles
791system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 48790822500 # number of WriteLineReq MSHR miss cycles
792system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1643233500 # number of LoadLockedReq MSHR miss cycles
793system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1643233500 # number of LoadLockedReq MSHR miss cycles
794system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5391195500 # number of StoreCondReq MSHR miss cycles
795system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5391195500 # number of StoreCondReq MSHR miss cycles
796system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2700500 # number of StoreCondFailReq MSHR miss cycles
797system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2700500 # number of StoreCondFailReq MSHR miss cycles
798system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83700430500 # number of demand (read+write) MSHR miss cycles
799system.cpu0.dcache.demand_mshr_miss_latency::total 83700430500 # number of demand (read+write) MSHR miss cycles
800system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100703459500 # number of overall MSHR miss cycles
801system.cpu0.dcache.overall_mshr_miss_latency::total 100703459500 # number of overall MSHR miss cycles
802system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5280351500 # number of ReadReq MSHR uncacheable cycles
803system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5280351500 # number of ReadReq MSHR uncacheable cycles
804system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086850000 # number of WriteReq MSHR uncacheable cycles
805system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086850000 # number of WriteReq MSHR uncacheable cycles
806system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10367201500 # number of overall MSHR uncacheable cycles
807system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10367201500 # number of overall MSHR uncacheable cycles
808system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036627 # mshr miss rate for ReadReq accesses
809system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036627 # mshr miss rate for ReadReq accesses
810system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019040 # mshr miss rate for WriteReq accesses
811system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019040 # mshr miss rate for WriteReq accesses
812system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775133 # mshr miss rate for SoftPFReq accesses
813system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775133 # mshr miss rate for SoftPFReq accesses
814system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.806155 # mshr miss rate for WriteLineReq accesses
815system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.806155 # mshr miss rate for WriteLineReq accesses
816system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses
817system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses
818system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097109 # mshr miss rate for StoreCondReq accesses
819system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097109 # mshr miss rate for StoreCondReq accesses
820system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028299 # mshr miss rate for demand accesses
821system.cpu0.dcache.demand_mshr_miss_rate::total 0.028299 # mshr miss rate for demand accesses
822system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032506 # mshr miss rate for overall accesses
823system.cpu0.dcache.overall_mshr_miss_rate::total 0.032506 # mshr miss rate for overall accesses
824system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995 # average ReadReq mshr miss latency
825system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995 # average ReadReq mshr miss latency
826system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140 # average WriteReq mshr miss latency
827system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140 # average WriteReq mshr miss latency
828system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973 # average SoftPFReq mshr miss latency
829system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973 # average SoftPFReq mshr miss latency
830system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407 # average WriteLineReq mshr miss latency
831system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407 # average WriteLineReq mshr miss latency
832system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654 # average LoadLockedReq mshr miss latency
833system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654 # average LoadLockedReq mshr miss latency
834system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357 # average StoreCondReq mshr miss latency
835system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357 # average StoreCondReq mshr miss latency
836system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
837system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
838system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18688.650800 # average overall mshr miss latency
839system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800 # average overall mshr miss latency
840system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19465.296714 # average overall mshr miss latency
841system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.296714 # average overall mshr miss latency
842system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392 # average ReadReq mshr uncacheable latency
843system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392 # average ReadReq mshr uncacheable latency
844system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182514.082738 # average WriteReq mshr uncacheable latency
845system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182514.082738 # average WriteReq mshr uncacheable latency
846system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183864.529573 # average overall mshr uncacheable latency
847system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573 # average overall mshr uncacheable latency
848system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
849system.cpu0.icache.tags.replacements 4741257 # number of replacements
850system.cpu0.icache.tags.tagsinuse 511.854043 # Cycle average of tags in use
851system.cpu0.icache.tags.total_refs 456517510 # Total number of references to valid blocks.
852system.cpu0.icache.tags.sampled_refs 4741769 # Sample count of references to valid blocks.
853system.cpu0.icache.tags.avg_refs 96.275780 # Average number of references to valid blocks.
854system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit.
855system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.854043 # Average occupied blocks per requestor
856system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999715 # Average percentage of cache occupancy
857system.cpu0.icache.tags.occ_percent::total 0.999715 # Average percentage of cache occupancy
858system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
859system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
860system.cpu0.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
861system.cpu0.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
862system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
863system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
864system.cpu0.icache.tags.tag_accesses 927260344 # Number of tag accesses
865system.cpu0.icache.tags.data_accesses 927260344 # Number of data accesses
866system.cpu0.icache.ReadReq_hits::cpu0.inst 456517510 # number of ReadReq hits
867system.cpu0.icache.ReadReq_hits::total 456517510 # number of ReadReq hits
868system.cpu0.icache.demand_hits::cpu0.inst 456517510 # number of demand (read+write) hits
869system.cpu0.icache.demand_hits::total 456517510 # number of demand (read+write) hits
870system.cpu0.icache.overall_hits::cpu0.inst 456517510 # number of overall hits
871system.cpu0.icache.overall_hits::total 456517510 # number of overall hits
872system.cpu0.icache.ReadReq_misses::cpu0.inst 4741775 # number of ReadReq misses
873system.cpu0.icache.ReadReq_misses::total 4741775 # number of ReadReq misses
874system.cpu0.icache.demand_misses::cpu0.inst 4741775 # number of demand (read+write) misses
875system.cpu0.icache.demand_misses::total 4741775 # number of demand (read+write) misses
876system.cpu0.icache.overall_misses::cpu0.inst 4741775 # number of overall misses
877system.cpu0.icache.overall_misses::total 4741775 # number of overall misses
878system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53890518500 # number of ReadReq miss cycles
879system.cpu0.icache.ReadReq_miss_latency::total 53890518500 # number of ReadReq miss cycles
880system.cpu0.icache.demand_miss_latency::cpu0.inst 53890518500 # number of demand (read+write) miss cycles
881system.cpu0.icache.demand_miss_latency::total 53890518500 # number of demand (read+write) miss cycles
882system.cpu0.icache.overall_miss_latency::cpu0.inst 53890518500 # number of overall miss cycles
883system.cpu0.icache.overall_miss_latency::total 53890518500 # number of overall miss cycles
884system.cpu0.icache.ReadReq_accesses::cpu0.inst 461259285 # number of ReadReq accesses(hits+misses)
885system.cpu0.icache.ReadReq_accesses::total 461259285 # number of ReadReq accesses(hits+misses)
886system.cpu0.icache.demand_accesses::cpu0.inst 461259285 # number of demand (read+write) accesses
887system.cpu0.icache.demand_accesses::total 461259285 # number of demand (read+write) accesses
888system.cpu0.icache.overall_accesses::cpu0.inst 461259285 # number of overall (read+write) accesses
889system.cpu0.icache.overall_accesses::total 461259285 # number of overall (read+write) accesses
890system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010280 # miss rate for ReadReq accesses
891system.cpu0.icache.ReadReq_miss_rate::total 0.010280 # miss rate for ReadReq accesses
892system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010280 # miss rate for demand accesses
893system.cpu0.icache.demand_miss_rate::total 0.010280 # miss rate for demand accesses
894system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010280 # miss rate for overall accesses
895system.cpu0.icache.overall_miss_rate::total 0.010280 # miss rate for overall accesses
896system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11365.051800 # average ReadReq miss latency
897system.cpu0.icache.ReadReq_avg_miss_latency::total 11365.051800 # average ReadReq miss latency
898system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency
899system.cpu0.icache.demand_avg_miss_latency::total 11365.051800 # average overall miss latency
900system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency
901system.cpu0.icache.overall_avg_miss_latency::total 11365.051800 # average overall miss latency
902system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
903system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
904system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
905system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
906system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
907system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
908system.cpu0.icache.fast_writes 0 # number of fast writes performed
909system.cpu0.icache.cache_copies 0 # number of cache copies performed
910system.cpu0.icache.writebacks::writebacks 4741257 # number of writebacks
911system.cpu0.icache.writebacks::total 4741257 # number of writebacks
912system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4741775 # number of ReadReq MSHR misses
913system.cpu0.icache.ReadReq_mshr_misses::total 4741775 # number of ReadReq MSHR misses
914system.cpu0.icache.demand_mshr_misses::cpu0.inst 4741775 # number of demand (read+write) MSHR misses
915system.cpu0.icache.demand_mshr_misses::total 4741775 # number of demand (read+write) MSHR misses
916system.cpu0.icache.overall_mshr_misses::cpu0.inst 4741775 # number of overall MSHR misses
917system.cpu0.icache.overall_mshr_misses::total 4741775 # number of overall MSHR misses
918system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
919system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
920system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
921system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
922system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51519631500 # number of ReadReq MSHR miss cycles
923system.cpu0.icache.ReadReq_mshr_miss_latency::total 51519631500 # number of ReadReq MSHR miss cycles
924system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51519631500 # number of demand (read+write) MSHR miss cycles
925system.cpu0.icache.demand_mshr_miss_latency::total 51519631500 # number of demand (read+write) MSHR miss cycles
926system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51519631500 # number of overall MSHR miss cycles
927system.cpu0.icache.overall_mshr_miss_latency::total 51519631500 # number of overall MSHR miss cycles
928system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles
929system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles
930system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles
931system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles
932system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for ReadReq accesses
933system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010280 # mshr miss rate for ReadReq accesses
934system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for demand accesses
935system.cpu0.icache.demand_mshr_miss_rate::total 0.010280 # mshr miss rate for demand accesses
936system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for overall accesses
937system.cpu0.icache.overall_mshr_miss_rate::total 0.010280 # mshr miss rate for overall accesses
938system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average ReadReq mshr miss latency
939system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10865.051906 # average ReadReq mshr miss latency
940system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency
941system.cpu0.icache.demand_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency
942system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency
943system.cpu0.icache.overall_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency
944system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency
945system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency
946system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency
947system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency
948system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
949system.cpu0.l2cache.prefetcher.num_hwpf_issued 8039497 # number of hwpf issued
950system.cpu0.l2cache.prefetcher.pfIdentified 8039521 # number of prefetch candidates identified
951system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue
952system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
953system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
954system.cpu0.l2cache.prefetcher.pfSpanPage 1012143 # number of prefetches not generated due to page crossing
955system.cpu0.l2cache.tags.replacements 2514209 # number of replacements
956system.cpu0.l2cache.tags.tagsinuse 16169.325614 # Cycle average of tags in use
957system.cpu0.l2cache.tags.total_refs 14408578 # Total number of references to valid blocks.
958system.cpu0.l2cache.tags.sampled_refs 2529817 # Sample count of references to valid blocks.
959system.cpu0.l2cache.tags.avg_refs 5.695502 # Average number of references to valid blocks.
960system.cpu0.l2cache.tags.warmup_cycle 8106870500 # Cycle when the warmup percentage was hit.
961system.cpu0.l2cache.tags.occ_blocks::writebacks 15164.632353 # Average occupied blocks per requestor
962system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.004325 # Average occupied blocks per requestor
963system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 56.118535 # Average occupied blocks per requestor
964system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 903.570401 # Average occupied blocks per requestor
965system.cpu0.l2cache.tags.occ_percent::writebacks 0.925576 # Average percentage of cache occupancy
966system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002747 # Average percentage of cache occupancy
967system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003425 # Average percentage of cache occupancy
968system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.055150 # Average percentage of cache occupancy
969system.cpu0.l2cache.tags.occ_percent::total 0.986897 # Average percentage of cache occupancy
970system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1599 # Occupied blocks per task id
971system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
972system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13927 # Occupied blocks per task id
973system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id
974system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 682 # Occupied blocks per task id
975system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id
976system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id
977system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id
978system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id
979system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
980system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 76 # Occupied blocks per task id
981system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2528 # Occupied blocks per task id
982system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5951 # Occupied blocks per task id
983system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5308 # Occupied blocks per task id
984system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097595 # Percentage of cache occupancy per task id
985system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
986system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.850037 # Percentage of cache occupancy per task id
987system.cpu0.l2cache.tags.tag_accesses 356318803 # Number of tag accesses
988system.cpu0.l2cache.tags.data_accesses 356318803 # Number of data accesses
989system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 276065 # number of ReadReq hits
990system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 135571 # number of ReadReq hits
991system.cpu0.l2cache.ReadReq_hits::total 411636 # number of ReadReq hits
992system.cpu0.l2cache.WritebackDirty_hits::writebacks 3830429 # number of WritebackDirty hits
993system.cpu0.l2cache.WritebackDirty_hits::total 3830429 # number of WritebackDirty hits
994system.cpu0.l2cache.WritebackClean_hits::writebacks 6639546 # number of WritebackClean hits
995system.cpu0.l2cache.WritebackClean_hits::total 6639546 # number of WritebackClean hits
996system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 500 # number of UpgradeReq hits
997system.cpu0.l2cache.UpgradeReq_hits::total 500 # number of UpgradeReq hits
998system.cpu0.l2cache.ReadExReq_hits::cpu0.data 929961 # number of ReadExReq hits
999system.cpu0.l2cache.ReadExReq_hits::total 929961 # number of ReadExReq hits
1000system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4274266 # number of ReadCleanReq hits
1001system.cpu0.l2cache.ReadCleanReq_hits::total 4274266 # number of ReadCleanReq hits
1002system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2881532 # number of ReadSharedReq hits
1003system.cpu0.l2cache.ReadSharedReq_hits::total 2881532 # number of ReadSharedReq hits
1004system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 169886 # number of InvalidateReq hits
1005system.cpu0.l2cache.InvalidateReq_hits::total 169886 # number of InvalidateReq hits
1006system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 276065 # number of demand (read+write) hits
1007system.cpu0.l2cache.demand_hits::cpu0.itb.walker 135571 # number of demand (read+write) hits
1008system.cpu0.l2cache.demand_hits::cpu0.inst 4274266 # number of demand (read+write) hits
1009system.cpu0.l2cache.demand_hits::cpu0.data 3811493 # number of demand (read+write) hits
1010system.cpu0.l2cache.demand_hits::total 8497395 # number of demand (read+write) hits
1011system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 276065 # number of overall hits
1012system.cpu0.l2cache.overall_hits::cpu0.itb.walker 135571 # number of overall hits
1013system.cpu0.l2cache.overall_hits::cpu0.inst 4274266 # number of overall hits
1014system.cpu0.l2cache.overall_hits::cpu0.data 3811493 # number of overall hits
1015system.cpu0.l2cache.overall_hits::total 8497395 # number of overall hits
1016system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10002 # number of ReadReq misses
1017system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7458 # number of ReadReq misses
1018system.cpu0.l2cache.ReadReq_misses::total 17460 # number of ReadReq misses
1019system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 252814 # number of UpgradeReq misses
1020system.cpu0.l2cache.UpgradeReq_misses::total 252814 # number of UpgradeReq misses
1021system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 198129 # number of SCUpgradeReq misses
1022system.cpu0.l2cache.SCUpgradeReq_misses::total 198129 # number of SCUpgradeReq misses
1023system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
1024system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
1025system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262789 # number of ReadExReq misses
1026system.cpu0.l2cache.ReadExReq_misses::total 262789 # number of ReadExReq misses
1027system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 467509 # number of ReadCleanReq misses
1028system.cpu0.l2cache.ReadCleanReq_misses::total 467509 # number of ReadCleanReq misses
1029system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 982618 # number of ReadSharedReq misses
1030system.cpu0.l2cache.ReadSharedReq_misses::total 982618 # number of ReadSharedReq misses
1031system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 596960 # number of InvalidateReq misses
1032system.cpu0.l2cache.InvalidateReq_misses::total 596960 # number of InvalidateReq misses
1033system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10002 # number of demand (read+write) misses
1034system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7458 # number of demand (read+write) misses
1035system.cpu0.l2cache.demand_misses::cpu0.inst 467509 # number of demand (read+write) misses
1036system.cpu0.l2cache.demand_misses::cpu0.data 1245407 # number of demand (read+write) misses
1037system.cpu0.l2cache.demand_misses::total 1730376 # number of demand (read+write) misses
1038system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10002 # number of overall misses
1039system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7458 # number of overall misses
1040system.cpu0.l2cache.overall_misses::cpu0.inst 467509 # number of overall misses
1041system.cpu0.l2cache.overall_misses::cpu0.data 1245407 # number of overall misses
1042system.cpu0.l2cache.overall_misses::total 1730376 # number of overall misses
1043system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 427118500 # number of ReadReq miss cycles
1044system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 335132000 # number of ReadReq miss cycles
1045system.cpu0.l2cache.ReadReq_miss_latency::total 762250500 # number of ReadReq miss cycles
1046system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3305201500 # number of UpgradeReq miss cycles
1047system.cpu0.l2cache.UpgradeReq_miss_latency::total 3305201500 # number of UpgradeReq miss cycles
1048system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2087626000 # number of SCUpgradeReq miss cycles
1049system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2087626000 # number of SCUpgradeReq miss cycles
1050system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2642498 # number of SCUpgradeFailReq miss cycles
1051system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2642498 # number of SCUpgradeFailReq miss cycles
1052system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18677102500 # number of ReadExReq miss cycles
1053system.cpu0.l2cache.ReadExReq_miss_latency::total 18677102500 # number of ReadExReq miss cycles
1054system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18746620500 # number of ReadCleanReq miss cycles
1055system.cpu0.l2cache.ReadCleanReq_miss_latency::total 18746620500 # number of ReadCleanReq miss cycles
1056system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41394693000 # number of ReadSharedReq miss cycles
1057system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41394693000 # number of ReadSharedReq miss cycles
1058system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 415110500 # number of InvalidateReq miss cycles
1059system.cpu0.l2cache.InvalidateReq_miss_latency::total 415110500 # number of InvalidateReq miss cycles
1060system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 427118500 # number of demand (read+write) miss cycles
1061system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 335132000 # number of demand (read+write) miss cycles
1062system.cpu0.l2cache.demand_miss_latency::cpu0.inst 18746620500 # number of demand (read+write) miss cycles
1063system.cpu0.l2cache.demand_miss_latency::cpu0.data 60071795500 # number of demand (read+write) miss cycles
1064system.cpu0.l2cache.demand_miss_latency::total 79580666500 # number of demand (read+write) miss cycles
1065system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 427118500 # number of overall miss cycles
1066system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 335132000 # number of overall miss cycles
1067system.cpu0.l2cache.overall_miss_latency::cpu0.inst 18746620500 # number of overall miss cycles
1068system.cpu0.l2cache.overall_miss_latency::cpu0.data 60071795500 # number of overall miss cycles
1069system.cpu0.l2cache.overall_miss_latency::total 79580666500 # number of overall miss cycles
1070system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 286067 # number of ReadReq accesses(hits+misses)
1071system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 143029 # number of ReadReq accesses(hits+misses)
1072system.cpu0.l2cache.ReadReq_accesses::total 429096 # number of ReadReq accesses(hits+misses)
1073system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3830429 # number of WritebackDirty accesses(hits+misses)
1074system.cpu0.l2cache.WritebackDirty_accesses::total 3830429 # number of WritebackDirty accesses(hits+misses)
1075system.cpu0.l2cache.WritebackClean_accesses::writebacks 6639546 # number of WritebackClean accesses(hits+misses)
1076system.cpu0.l2cache.WritebackClean_accesses::total 6639546 # number of WritebackClean accesses(hits+misses)
1077system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 253314 # number of UpgradeReq accesses(hits+misses)
1078system.cpu0.l2cache.UpgradeReq_accesses::total 253314 # number of UpgradeReq accesses(hits+misses)
1079system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 198129 # number of SCUpgradeReq accesses(hits+misses)
1080system.cpu0.l2cache.SCUpgradeReq_accesses::total 198129 # number of SCUpgradeReq accesses(hits+misses)
1081system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
1082system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
1083system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1192750 # number of ReadExReq accesses(hits+misses)
1084system.cpu0.l2cache.ReadExReq_accesses::total 1192750 # number of ReadExReq accesses(hits+misses)
1085system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4741775 # number of ReadCleanReq accesses(hits+misses)
1086system.cpu0.l2cache.ReadCleanReq_accesses::total 4741775 # number of ReadCleanReq accesses(hits+misses)
1087system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3864150 # number of ReadSharedReq accesses(hits+misses)
1088system.cpu0.l2cache.ReadSharedReq_accesses::total 3864150 # number of ReadSharedReq accesses(hits+misses)
1089system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 766846 # number of InvalidateReq accesses(hits+misses)
1090system.cpu0.l2cache.InvalidateReq_accesses::total 766846 # number of InvalidateReq accesses(hits+misses)
1091system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 286067 # number of demand (read+write) accesses
1092system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 143029 # number of demand (read+write) accesses
1093system.cpu0.l2cache.demand_accesses::cpu0.inst 4741775 # number of demand (read+write) accesses
1094system.cpu0.l2cache.demand_accesses::cpu0.data 5056900 # number of demand (read+write) accesses
1095system.cpu0.l2cache.demand_accesses::total 10227771 # number of demand (read+write) accesses
1096system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 286067 # number of overall (read+write) accesses
1097system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 143029 # number of overall (read+write) accesses
1098system.cpu0.l2cache.overall_accesses::cpu0.inst 4741775 # number of overall (read+write) accesses
1099system.cpu0.l2cache.overall_accesses::cpu0.data 5056900 # number of overall (read+write) accesses
1100system.cpu0.l2cache.overall_accesses::total 10227771 # number of overall (read+write) accesses
1101system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.034964 # miss rate for ReadReq accesses
1102system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052143 # miss rate for ReadReq accesses
1103system.cpu0.l2cache.ReadReq_miss_rate::total 0.040690 # miss rate for ReadReq accesses
1104system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998026 # miss rate for UpgradeReq accesses
1105system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998026 # miss rate for UpgradeReq accesses
1106system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1107system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1108system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1109system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1110system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.220322 # miss rate for ReadExReq accesses
1111system.cpu0.l2cache.ReadExReq_miss_rate::total 0.220322 # miss rate for ReadExReq accesses
1112system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098594 # miss rate for ReadCleanReq accesses
1113system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098594 # miss rate for ReadCleanReq accesses
1114system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.254291 # miss rate for ReadSharedReq accesses
1115system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.254291 # miss rate for ReadSharedReq accesses
1116system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.778461 # miss rate for InvalidateReq accesses
1117system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.778461 # miss rate for InvalidateReq accesses
1118system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.034964 # miss rate for demand accesses
1119system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052143 # miss rate for demand accesses
1120system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098594 # miss rate for demand accesses
1121system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246279 # miss rate for demand accesses
1122system.cpu0.l2cache.demand_miss_rate::total 0.169184 # miss rate for demand accesses
1123system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.034964 # miss rate for overall accesses
1124system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052143 # miss rate for overall accesses
1125system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098594 # miss rate for overall accesses
1126system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246279 # miss rate for overall accesses
1127system.cpu0.l2cache.overall_miss_rate::total 0.169184 # miss rate for overall accesses
1128system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42703.309338 # average ReadReq miss latency
1129system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44935.907750 # average ReadReq miss latency
1130system.cpu0.l2cache.ReadReq_avg_miss_latency::total 43656.958763 # average ReadReq miss latency
1131system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13073.649007 # average UpgradeReq miss latency
1132system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13073.649007 # average UpgradeReq miss latency
1133system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10536.700836 # average SCUpgradeReq miss latency
1134system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10536.700836 # average SCUpgradeReq miss latency
1135system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528499.600000 # average SCUpgradeFailReq miss latency
1136system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528499.600000 # average SCUpgradeFailReq miss latency
1137system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 71072.619097 # average ReadExReq miss latency
1138system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 71072.619097 # average ReadExReq miss latency
1139system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40098.951036 # average ReadCleanReq miss latency
1140system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40098.951036 # average ReadCleanReq miss latency
1141system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 42126.943532 # average ReadSharedReq miss latency
1142system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 42126.943532 # average ReadSharedReq miss latency
1143system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 695.374062 # average InvalidateReq miss latency
1144system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 695.374062 # average InvalidateReq miss latency
1145system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42703.309338 # average overall miss latency
1146system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44935.907750 # average overall miss latency
1147system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40098.951036 # average overall miss latency
1148system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48234.669871 # average overall miss latency
1149system.cpu0.l2cache.demand_avg_miss_latency::total 45990.389661 # average overall miss latency
1150system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42703.309338 # average overall miss latency
1151system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44935.907750 # average overall miss latency
1152system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40098.951036 # average overall miss latency
1153system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48234.669871 # average overall miss latency
1154system.cpu0.l2cache.overall_avg_miss_latency::total 45990.389661 # average overall miss latency
1155system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1156system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1157system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1158system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1159system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1160system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1161system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1162system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1163system.cpu0.l2cache.writebacks::writebacks 1647047 # number of writebacks
1164system.cpu0.l2cache.writebacks::total 1647047 # number of writebacks
1165system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9683 # number of ReadExReq MSHR hits
1166system.cpu0.l2cache.ReadExReq_mshr_hits::total 9683 # number of ReadExReq MSHR hits
1167system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 697 # number of ReadSharedReq MSHR hits
1168system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 697 # number of ReadSharedReq MSHR hits
1169system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10380 # number of demand (read+write) MSHR hits
1170system.cpu0.l2cache.demand_mshr_hits::total 10380 # number of demand (read+write) MSHR hits
1171system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10380 # number of overall MSHR hits
1172system.cpu0.l2cache.overall_mshr_hits::total 10380 # number of overall MSHR hits
1173system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10002 # number of ReadReq MSHR misses
1174system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7458 # number of ReadReq MSHR misses
1175system.cpu0.l2cache.ReadReq_mshr_misses::total 17460 # number of ReadReq MSHR misses
1176system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 803286 # number of HardPFReq MSHR misses
1177system.cpu0.l2cache.HardPFReq_mshr_misses::total 803286 # number of HardPFReq MSHR misses
1178system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 252814 # number of UpgradeReq MSHR misses
1179system.cpu0.l2cache.UpgradeReq_mshr_misses::total 252814 # number of UpgradeReq MSHR misses
1180system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 198129 # number of SCUpgradeReq MSHR misses
1181system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 198129 # number of SCUpgradeReq MSHR misses
1182system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
1184system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 253106 # number of ReadExReq MSHR misses
1185system.cpu0.l2cache.ReadExReq_mshr_misses::total 253106 # number of ReadExReq MSHR misses
1186system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 467509 # number of ReadCleanReq MSHR misses
1187system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 467509 # number of ReadCleanReq MSHR misses
1188system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 981921 # number of ReadSharedReq MSHR misses
1189system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 981921 # number of ReadSharedReq MSHR misses
1190system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 596960 # number of InvalidateReq MSHR misses
1191system.cpu0.l2cache.InvalidateReq_mshr_misses::total 596960 # number of InvalidateReq MSHR misses
1192system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10002 # number of demand (read+write) MSHR misses
1193system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7458 # number of demand (read+write) MSHR misses
1194system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 467509 # number of demand (read+write) MSHR misses
1195system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1235027 # number of demand (read+write) MSHR misses
1196system.cpu0.l2cache.demand_mshr_misses::total 1719996 # number of demand (read+write) MSHR misses
1197system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10002 # number of overall MSHR misses
1198system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7458 # number of overall MSHR misses
1199system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 467509 # number of overall MSHR misses
1200system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1235027 # number of overall MSHR misses
1201system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 803286 # number of overall MSHR misses
1202system.cpu0.l2cache.overall_mshr_misses::total 2523282 # number of overall MSHR misses
1203system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
1204system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable
1205system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71639 # number of ReadReq MSHR uncacheable
1206system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable
1207system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 27871 # number of WriteReq MSHR uncacheable
1208system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
1209system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses
1210system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 99510 # number of overall MSHR uncacheable misses
1211system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 367106500 # number of ReadReq MSHR miss cycles
1212system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290384000 # number of ReadReq MSHR miss cycles
1213system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 657490500 # number of ReadReq MSHR miss cycles
1214system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 55761183140 # number of HardPFReq MSHR miss cycles
1215system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 55761183140 # number of HardPFReq MSHR miss cycles
1216system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7610950500 # number of UpgradeReq MSHR miss cycles
1217system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7610950500 # number of UpgradeReq MSHR miss cycles
1218system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3903930000 # number of SCUpgradeReq MSHR miss cycles
1219system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3903930000 # number of SCUpgradeReq MSHR miss cycles
1220system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2414498 # number of SCUpgradeFailReq MSHR miss cycles
1221system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2414498 # number of SCUpgradeFailReq MSHR miss cycles
1222system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15925015500 # number of ReadExReq MSHR miss cycles
1223system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15925015500 # number of ReadExReq MSHR miss cycles
1224system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15941566500 # number of ReadCleanReq MSHR miss cycles
1225system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15941566500 # number of ReadCleanReq MSHR miss cycles
1226system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 35435763500 # number of ReadSharedReq MSHR miss cycles
1227system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 35435763500 # number of ReadSharedReq MSHR miss cycles
1228system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 42907731500 # number of InvalidateReq MSHR miss cycles
1229system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 42907731500 # number of InvalidateReq MSHR miss cycles
1230system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 367106500 # number of demand (read+write) MSHR miss cycles
1231system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290384000 # number of demand (read+write) MSHR miss cycles
1232system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15941566500 # number of demand (read+write) MSHR miss cycles
1233system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51360779000 # number of demand (read+write) MSHR miss cycles
1234system.cpu0.l2cache.demand_mshr_miss_latency::total 67959836000 # number of demand (read+write) MSHR miss cycles
1235system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 367106500 # number of overall MSHR miss cycles
1236system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290384000 # number of overall MSHR miss cycles
1237system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15941566500 # number of overall MSHR miss cycles
1238system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51360779000 # number of overall MSHR miss cycles
1239system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 55761183140 # number of overall MSHR miss cycles
1240system.cpu0.l2cache.overall_mshr_miss_latency::total 123721019140 # number of overall MSHR miss cycles
1241system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles
1242system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5051874500 # number of ReadReq MSHR uncacheable cycles
1243system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10682646000 # number of ReadReq MSHR uncacheable cycles
1244system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4877454000 # number of WriteReq MSHR uncacheable cycles
1245system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4877454000 # number of WriteReq MSHR uncacheable cycles
1246system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles
1247system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9929328500 # number of overall MSHR uncacheable cycles
1248system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15560100000 # number of overall MSHR uncacheable cycles
1249system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for ReadReq accesses
1250system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for ReadReq accesses
1251system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040690 # mshr miss rate for ReadReq accesses
1252system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1253system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1254system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998026 # mshr miss rate for UpgradeReq accesses
1255system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998026 # mshr miss rate for UpgradeReq accesses
1256system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1257system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1258system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1259system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1260system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212204 # mshr miss rate for ReadExReq accesses
1261system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212204 # mshr miss rate for ReadExReq accesses
1262system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for ReadCleanReq accesses
1263system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadCleanReq accesses
1264system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254110 # mshr miss rate for ReadSharedReq accesses
1265system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254110 # mshr miss rate for ReadSharedReq accesses
1266system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.778461 # mshr miss rate for InvalidateReq accesses
1267system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.778461 # mshr miss rate for InvalidateReq accesses
1268system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for demand accesses
1269system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for demand accesses
1270system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for demand accesses
1271system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for demand accesses
1272system.cpu0.l2cache.demand_mshr_miss_rate::total 0.168169 # mshr miss rate for demand accesses
1273system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for overall accesses
1274system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for overall accesses
1275system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for overall accesses
1276system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for overall accesses
1277system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1278system.cpu0.l2cache.overall_mshr_miss_rate::total 0.246709 # mshr miss rate for overall accesses
1279system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average ReadReq mshr miss latency
1280system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average ReadReq mshr miss latency
1281system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763 # average ReadReq mshr miss latency
1282system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average HardPFReq mshr miss latency
1283system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262 # average HardPFReq mshr miss latency
1284system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787 # average UpgradeReq mshr miss latency
1285system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787 # average UpgradeReq mshr miss latency
1286system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740 # average SCUpgradeReq mshr miss latency
1287system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740 # average SCUpgradeReq mshr miss latency
1288system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000 # average SCUpgradeFailReq mshr miss latency
1289system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000 # average SCUpgradeFailReq mshr miss latency
1290system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243 # average ReadExReq mshr miss latency
1291system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243 # average ReadExReq mshr miss latency
1292system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average ReadCleanReq mshr miss latency
1293system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036 # average ReadCleanReq mshr miss latency
1294system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106 # average ReadSharedReq mshr miss latency
1295system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106 # average ReadSharedReq mshr miss latency
1296system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952 # average InvalidateReq mshr miss latency
1297system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952 # average InvalidateReq mshr miss latency
1298system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency
1299system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency
1300system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency
1301system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency
1302system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446 # average overall mshr miss latency
1303system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency
1304system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency
1305system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency
1306system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency
1307system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average overall mshr miss latency
1308system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454 # average overall mshr miss latency
1309system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency
1310system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663 # average ReadReq mshr uncacheable latency
1311system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129 # average ReadReq mshr uncacheable latency
1312system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508 # average WriteReq mshr uncacheable latency
1313system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508 # average WriteReq mshr uncacheable latency
1314system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency
1315system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535 # average overall mshr uncacheable latency
1316system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276 # average overall mshr uncacheable latency
1317system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1318system.cpu0.toL2Bus.snoop_filter.tot_requests 21737448 # Total number of requests made to the snoop filter.
1319system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11172038 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1320system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1321system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879362 # Total number of snoops made to the snoop filter.
1322system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879064 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1323system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1324system.cpu0.toL2Bus.trans_dist::ReadReq 568365 # Transaction distribution
1325system.cpu0.toL2Bus.trans_dist::ReadResp 9266330 # Transaction distribution
1326system.cpu0.toL2Bus.trans_dist::WriteReq 27872 # Transaction distribution
1327system.cpu0.toL2Bus.trans_dist::WriteResp 27871 # Transaction distribution
1328system.cpu0.toL2Bus.trans_dist::WritebackDirty 5482404 # Transaction distribution
1329system.cpu0.toL2Bus.trans_dist::WritebackClean 6640558 # Transaction distribution
1330system.cpu0.toL2Bus.trans_dist::CleanEvict 2386717 # Transaction distribution
1331system.cpu0.toL2Bus.trans_dist::HardPFReq 980471 # Transaction distribution
1332system.cpu0.toL2Bus.trans_dist::UpgradeReq 448075 # Transaction distribution
1333system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 360841 # Transaction distribution
1334system.cpu0.toL2Bus.trans_dist::UpgradeResp 517122 # Transaction distribution
1335system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
1336system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
1337system.cpu0.toL2Bus.trans_dist::ReadExReq 1223880 # Transaction distribution
1338system.cpu0.toL2Bus.trans_dist::ReadExResp 1201425 # Transaction distribution
1339system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4741775 # Transaction distribution
1340system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4748017 # Transaction distribution
1341system.cpu0.toL2Bus.trans_dist::InvalidateReq 819035 # Transaction distribution
1342system.cpu0.toL2Bus.trans_dist::InvalidateResp 766846 # Transaction distribution
1343system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14311056 # Packet count per connected master and slave (bytes)
1344system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18559366 # Packet count per connected master and slave (bytes)
1345system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 302345 # Packet count per connected master and slave (bytes)
1346system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 623475 # Packet count per connected master and slave (bytes)
1347system.cpu0.toL2Bus.pkt_count::total 33796242 # Packet count per connected master and slave (bytes)
1348system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607086484 # Cumulative packet size per connected master and slave (bytes)
1349system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696970881 # Cumulative packet size per connected master and slave (bytes)
1350system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1144232 # Cumulative packet size per connected master and slave (bytes)
1351system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2288536 # Cumulative packet size per connected master and slave (bytes)
1352system.cpu0.toL2Bus.pkt_size::total 1307490133 # Cumulative packet size per connected master and slave (bytes)
1353system.cpu0.toL2Bus.snoops 6577979 # Total snoops (count)
1354system.cpu0.toL2Bus.snoop_fanout::samples 17957076 # Request fanout histogram
1355system.cpu0.toL2Bus.snoop_fanout::mean 0.118626 # Request fanout histogram
1356system.cpu0.toL2Bus.snoop_fanout::stdev 0.323399 # Request fanout histogram
1357system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1358system.cpu0.toL2Bus.snoop_fanout::0 15827205 88.14% 88.14% # Request fanout histogram
1359system.cpu0.toL2Bus.snoop_fanout::1 2129573 11.86% 100.00% # Request fanout histogram
1360system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram
1361system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1362system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1363system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1364system.cpu0.toL2Bus.snoop_fanout::total 17957076 # Request fanout histogram
1365system.cpu0.toL2Bus.reqLayer0.occupancy 21527019496 # Layer occupancy (ticks)
1366system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1367system.cpu0.toL2Bus.snoopLayer0.occupancy 184192978 # Layer occupancy (ticks)
1368system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1369system.cpu0.toL2Bus.respLayer0.occupancy 7155786000 # Layer occupancy (ticks)
1370system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1371system.cpu0.toL2Bus.respLayer1.occupancy 8237151691 # Layer occupancy (ticks)
1372system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1373system.cpu0.toL2Bus.respLayer2.occupancy 159316000 # Layer occupancy (ticks)
1374system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1375system.cpu0.toL2Bus.respLayer3.occupancy 337408998 # Layer occupancy (ticks)
1376system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1377system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1378system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1379system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1380system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1381system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1382system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1383system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

1398system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1399system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1400system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1401system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1402system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1403system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1404system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1405system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1406system.cpu1.dtb.walker.walks 108188 # Table walker walks requested
1407system.cpu1.dtb.walker.walksLong 108188 # Table walker walks initiated with long descriptors
1408system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9416 # Level at which table walker walks with long descriptors terminate
1409system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83328 # Level at which table walker walks with long descriptors terminate
1410system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting
1411system.cpu1.dtb.walker.walkWaitTime::samples 108184 # Table walker wait (enqueue to first request) latency
1412system.cpu1.dtb.walker.walkWaitTime::mean 0.073948 # Table walker wait (enqueue to first request) latency
1413system.cpu1.dtb.walker.walkWaitTime::stdev 24.322514 # Table walker wait (enqueue to first request) latency
1414system.cpu1.dtb.walker.walkWaitTime::0-511 108183 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1415system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1416system.cpu1.dtb.walker.walkWaitTime::total 108184 # Table walker wait (enqueue to first request) latency
1417system.cpu1.dtb.walker.walkCompletionTime::samples 92748 # Table walker service (enqueue to completion) latency
1418system.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904 # Table walker service (enqueue to completion) latency
1419system.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311 # Table walker service (enqueue to completion) latency
1420system.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210 # Table walker service (enqueue to completion) latency
1421system.cpu1.dtb.walker.walkCompletionTime::0-65535 90515 97.59% 97.59% # Table walker service (enqueue to completion) latency
1422system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.18% 97.77% # Table walker service (enqueue to completion) latency
1423system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1735 1.87% 99.64% # Table walker service (enqueue to completion) latency
1424system.cpu1.dtb.walker.walkCompletionTime::196608-262143 64 0.07% 99.71% # Table walker service (enqueue to completion) latency
1425system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.12% 99.83% # Table walker service (enqueue to completion) latency
1426system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.05% 99.88% # Table walker service (enqueue to completion) latency
1427system.cpu1.dtb.walker.walkCompletionTime::393216-458751 73 0.08% 99.96% # Table walker service (enqueue to completion) latency
1428system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
1429system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
1430system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
1431system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1432system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1433system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1434system.cpu1.dtb.walker.walkCompletionTime::total 92748 # Table walker service (enqueue to completion) latency
1435system.cpu1.dtb.walker.walksPending::samples -800290088 # Table walker pending requests distribution
1436system.cpu1.dtb.walker.walksPending::mean -1.452962 # Table walker pending requests distribution
1437system.cpu1.dtb.walker.walksPending::0 -1963081332 245.30% 245.30% # Table walker pending requests distribution
1438system.cpu1.dtb.walker.walksPending::1 1162791244 -145.30% 100.00% # Table walker pending requests distribution
1439system.cpu1.dtb.walker.walksPending::total -800290088 # Table walker pending requests distribution
1440system.cpu1.dtb.walker.walkPageSizes::4K 83329 89.85% 89.85% # Table walker page sizes translated
1441system.cpu1.dtb.walker.walkPageSizes::2M 9416 10.15% 100.00% # Table walker page sizes translated
1442system.cpu1.dtb.walker.walkPageSizes::total 92745 # Table walker page sizes translated
1443system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108188 # Table walker requests started/completed, data/inst
1444system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1445system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108188 # Table walker requests started/completed, data/inst
1446system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92745 # Table walker requests started/completed, data/inst
1447system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1448system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92745 # Table walker requests started/completed, data/inst
1449system.cpu1.dtb.walker.walkRequestOrigin::total 200933 # Table walker requests started/completed, data/inst
1450system.cpu1.dtb.inst_hits 0 # ITB inst hits
1451system.cpu1.dtb.inst_misses 0 # ITB inst misses
1452system.cpu1.dtb.read_hits 84911532 # DTB read hits
1453system.cpu1.dtb.read_misses 79075 # DTB read misses
1454system.cpu1.dtb.write_hits 77663318 # DTB write hits
1455system.cpu1.dtb.write_misses 29113 # DTB write misses
1456system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1457system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1458system.cpu1.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
1459system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
1460system.cpu1.dtb.flush_entries 39584 # Number of entries that have been flushed from TLB
1461system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1462system.cpu1.dtb.prefetch_faults 5277 # Number of TLB faults due to prefetch
1463system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1464system.cpu1.dtb.perms_faults 10813 # Number of TLB faults due to permissions restrictions
1465system.cpu1.dtb.read_accesses 84990607 # DTB read accesses
1466system.cpu1.dtb.write_accesses 77692431 # DTB write accesses
1467system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1468system.cpu1.dtb.hits 162574850 # DTB hits
1469system.cpu1.dtb.misses 108188 # DTB misses
1470system.cpu1.dtb.accesses 162683038 # DTB accesses
1471system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1472system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1473system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1474system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1475system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1476system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1477system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1478system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1492system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1493system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1494system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1495system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1496system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1497system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1498system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1499system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1500system.cpu1.itb.walker.walks 63937 # Table walker walks requested
1501system.cpu1.itb.walker.walksLong 63937 # Table walker walks initiated with long descriptors
1502system.cpu1.itb.walker.walksLongTerminationLevel::Level2 631 # Level at which table walker walks with long descriptors terminate
1503system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57861 # Level at which table walker walks with long descriptors terminate
1504system.cpu1.itb.walker.walkWaitTime::samples 63937 # Table walker wait (enqueue to first request) latency
1505system.cpu1.itb.walker.walkWaitTime::0 63937 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1506system.cpu1.itb.walker.walkWaitTime::total 63937 # Table walker wait (enqueue to first request) latency
1507system.cpu1.itb.walker.walkCompletionTime::samples 58492 # Table walker service (enqueue to completion) latency
1508system.cpu1.itb.walker.walkCompletionTime::mean 30403.747521 # Table walker service (enqueue to completion) latency
1509system.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144 # Table walker service (enqueue to completion) latency
1510system.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324 # Table walker service (enqueue to completion) latency
1511system.cpu1.itb.walker.walkCompletionTime::0-65535 55985 95.71% 95.71% # Table walker service (enqueue to completion) latency
1512system.cpu1.itb.walker.walkCompletionTime::65536-131071 47 0.08% 95.79% # Table walker service (enqueue to completion) latency
1513system.cpu1.itb.walker.walkCompletionTime::131072-196607 2099 3.59% 99.38% # Table walker service (enqueue to completion) latency
1514system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.15% 99.53% # Table walker service (enqueue to completion) latency
1515system.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.17% 99.71% # Table walker service (enqueue to completion) latency
1516system.cpu1.itb.walker.walkCompletionTime::327680-393215 51 0.09% 99.79% # Table walker service (enqueue to completion) latency
1517system.cpu1.itb.walker.walkCompletionTime::393216-458751 79 0.14% 99.93% # Table walker service (enqueue to completion) latency
1518system.cpu1.itb.walker.walkCompletionTime::458752-524287 15 0.03% 99.95% # Table walker service (enqueue to completion) latency
1519system.cpu1.itb.walker.walkCompletionTime::524288-589823 17 0.03% 99.98% # Table walker service (enqueue to completion) latency
1520system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
1521system.cpu1.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
1522system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1523system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1524system.cpu1.itb.walker.walkCompletionTime::total 58492 # Table walker service (enqueue to completion) latency
1525system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution
1526system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution
1527system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution
1528system.cpu1.itb.walker.walkPageSizes::4K 57861 98.92% 98.92% # Table walker page sizes translated
1529system.cpu1.itb.walker.walkPageSizes::2M 631 1.08% 100.00% # Table walker page sizes translated
1530system.cpu1.itb.walker.walkPageSizes::total 58492 # Table walker page sizes translated
1531system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1532system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63937 # Table walker requests started/completed, data/inst
1533system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63937 # Table walker requests started/completed, data/inst
1534system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1535system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58492 # Table walker requests started/completed, data/inst
1536system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58492 # Table walker requests started/completed, data/inst
1537system.cpu1.itb.walker.walkRequestOrigin::total 122429 # Table walker requests started/completed, data/inst
1538system.cpu1.itb.inst_hits 448499634 # ITB inst hits
1539system.cpu1.itb.inst_misses 63937 # ITB inst misses
1540system.cpu1.itb.read_hits 0 # DTB read hits
1541system.cpu1.itb.read_misses 0 # DTB read misses
1542system.cpu1.itb.write_hits 0 # DTB write hits
1543system.cpu1.itb.write_misses 0 # DTB write misses
1544system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1545system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1546system.cpu1.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID
1547system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
1548system.cpu1.itb.flush_entries 27923 # Number of entries that have been flushed from TLB
1549system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1550system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1551system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1552system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1553system.cpu1.itb.read_accesses 0 # DTB read accesses
1554system.cpu1.itb.write_accesses 0 # DTB write accesses
1555system.cpu1.itb.inst_accesses 448563571 # ITB inst accesses
1556system.cpu1.itb.hits 448499634 # DTB hits
1557system.cpu1.itb.misses 63937 # DTB misses
1558system.cpu1.itb.accesses 448563571 # DTB accesses
1559system.cpu1.numCycles 95159838343 # number of cpu cycles simulated
1560system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1561system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1562system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1563system.cpu1.kern.inst.quiesce 5923 # number of quiesce instructions executed
1564system.cpu1.committedInsts 448210596 # Number of instructions committed
1565system.cpu1.committedOps 528777754 # Number of ops (including micro ops) committed
1566system.cpu1.num_int_alu_accesses 486415785 # Number of integer alu accesses
1567system.cpu1.num_fp_alu_accesses 519922 # Number of float alu accesses
1568system.cpu1.num_func_calls 27136019 # number of times a function call or return occured
1569system.cpu1.num_conditional_control_insts 67942031 # number of instructions that are conditional controls
1570system.cpu1.num_int_insts 486415785 # number of integer instructions
1571system.cpu1.num_fp_insts 519922 # number of float instructions
1572system.cpu1.num_int_register_reads 706615491 # number of times the integer registers were read
1573system.cpu1.num_int_register_writes 385601488 # number of times the integer registers were written
1574system.cpu1.num_fp_register_reads 832776 # number of times the floating registers were read
1575system.cpu1.num_fp_register_writes 452540 # number of times the floating registers were written
1576system.cpu1.num_cc_register_reads 115428294 # number of times the CC registers were read
1577system.cpu1.num_cc_register_writes 115157338 # number of times the CC registers were written
1578system.cpu1.num_mem_refs 162566757 # number of memory refs
1579system.cpu1.num_load_insts 84909557 # Number of load instructions
1580system.cpu1.num_store_insts 77657200 # Number of store instructions
1581system.cpu1.num_idle_cycles 94045434394.442017 # Number of idle cycles
1582system.cpu1.num_busy_cycles 1114403948.557976 # Number of busy cycles
1583system.cpu1.not_idle_fraction 0.011711 # Percentage of non-idle cycles
1584system.cpu1.idle_fraction 0.988289 # Percentage of idle cycles
1585system.cpu1.Branches 99989008 # Number of branches fetched
1586system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
1587system.cpu1.op_class::IntAlu 365279701 69.04% 69.04% # Class of executed instruction
1588system.cpu1.op_class::IntMult 1087060 0.21% 69.25% # Class of executed instruction
1589system.cpu1.op_class::IntDiv 61840 0.01% 69.26% # Class of executed instruction
1590system.cpu1.op_class::FloatAdd 0 0.00% 69.26% # Class of executed instruction
1591system.cpu1.op_class::FloatCmp 0 0.00% 69.26% # Class of executed instruction
1592system.cpu1.op_class::FloatCvt 0 0.00% 69.26% # Class of executed instruction
1593system.cpu1.op_class::FloatMult 0 0.00% 69.26% # Class of executed instruction
1594system.cpu1.op_class::FloatDiv 0 0.00% 69.26% # Class of executed instruction
1595system.cpu1.op_class::FloatSqrt 0 0.00% 69.26% # Class of executed instruction
1596system.cpu1.op_class::SimdAdd 0 0.00% 69.26% # Class of executed instruction
1597system.cpu1.op_class::SimdAddAcc 0 0.00% 69.26% # Class of executed instruction
1598system.cpu1.op_class::SimdAlu 0 0.00% 69.26% # Class of executed instruction
1599system.cpu1.op_class::SimdCmp 0 0.00% 69.26% # Class of executed instruction
1600system.cpu1.op_class::SimdCvt 0 0.00% 69.26% # Class of executed instruction
1601system.cpu1.op_class::SimdMisc 0 0.00% 69.26% # Class of executed instruction
1602system.cpu1.op_class::SimdMult 0 0.00% 69.26% # Class of executed instruction
1603system.cpu1.op_class::SimdMultAcc 0 0.00% 69.26% # Class of executed instruction
1604system.cpu1.op_class::SimdShift 0 0.00% 69.26% # Class of executed instruction
1605system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.26% # Class of executed instruction
1606system.cpu1.op_class::SimdSqrt 0 0.00% 69.26% # Class of executed instruction
1607system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.26% # Class of executed instruction
1608system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.26% # Class of executed instruction
1609system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.26% # Class of executed instruction
1610system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.26% # Class of executed instruction
1611system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.26% # Class of executed instruction
1612system.cpu1.op_class::SimdFloatMisc 71500 0.01% 69.27% # Class of executed instruction
1613system.cpu1.op_class::SimdFloatMult 0 0.00% 69.27% # Class of executed instruction
1614system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.27% # Class of executed instruction
1615system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.27% # Class of executed instruction
1616system.cpu1.op_class::MemRead 84909557 16.05% 85.32% # Class of executed instruction
1617system.cpu1.op_class::MemWrite 77657200 14.68% 100.00% # Class of executed instruction
1618system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1619system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1620system.cpu1.op_class::total 529066901 # Class of executed instruction
1621system.cpu1.dcache.tags.replacements 5332630 # number of replacements
1622system.cpu1.dcache.tags.tagsinuse 455.913081 # Cycle average of tags in use
1623system.cpu1.dcache.tags.total_refs 157043226 # Total number of references to valid blocks.
1624system.cpu1.dcache.tags.sampled_refs 5333142 # Sample count of references to valid blocks.
1625system.cpu1.dcache.tags.avg_refs 29.446661 # Average number of references to valid blocks.
1626system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit.
1627system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.913081 # Average occupied blocks per requestor
1628system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890455 # Average percentage of cache occupancy
1629system.cpu1.dcache.tags.occ_percent::total 0.890455 # Average percentage of cache occupancy
1630system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1631system.cpu1.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
1632system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
1633system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
1634system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1635system.cpu1.dcache.tags.tag_accesses 330516943 # Number of tag accesses
1636system.cpu1.dcache.tags.data_accesses 330516943 # Number of data accesses
1637system.cpu1.dcache.ReadReq_hits::cpu1.data 79081838 # number of ReadReq hits
1638system.cpu1.dcache.ReadReq_hits::total 79081838 # number of ReadReq hits
1639system.cpu1.dcache.WriteReq_hits::cpu1.data 73714078 # number of WriteReq hits
1640system.cpu1.dcache.WriteReq_hits::total 73714078 # number of WriteReq hits
1641system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184325 # number of SoftPFReq hits
1642system.cpu1.dcache.SoftPFReq_hits::total 184325 # number of SoftPFReq hits
1643system.cpu1.dcache.WriteLineReq_hits::cpu1.data 141992 # number of WriteLineReq hits
1644system.cpu1.dcache.WriteLineReq_hits::total 141992 # number of WriteLineReq hits
1645system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768915 # number of LoadLockedReq hits
1646system.cpu1.dcache.LoadLockedReq_hits::total 1768915 # number of LoadLockedReq hits
1647system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1742986 # number of StoreCondReq hits
1648system.cpu1.dcache.StoreCondReq_hits::total 1742986 # number of StoreCondReq hits
1649system.cpu1.dcache.demand_hits::cpu1.data 152795916 # number of demand (read+write) hits
1650system.cpu1.dcache.demand_hits::total 152795916 # number of demand (read+write) hits
1651system.cpu1.dcache.overall_hits::cpu1.data 152980241 # number of overall hits
1652system.cpu1.dcache.overall_hits::total 152980241 # number of overall hits
1653system.cpu1.dcache.ReadReq_misses::cpu1.data 3051137 # number of ReadReq misses
1654system.cpu1.dcache.ReadReq_misses::total 3051137 # number of ReadReq misses
1655system.cpu1.dcache.WriteReq_misses::cpu1.data 1365469 # number of WriteReq misses
1656system.cpu1.dcache.WriteReq_misses::total 1365469 # number of WriteReq misses
1657system.cpu1.dcache.SoftPFReq_misses::cpu1.data 638330 # number of SoftPFReq misses
1658system.cpu1.dcache.SoftPFReq_misses::total 638330 # number of SoftPFReq misses
1659system.cpu1.dcache.WriteLineReq_misses::cpu1.data 475836 # number of WriteLineReq misses
1660system.cpu1.dcache.WriteLineReq_misses::total 475836 # number of WriteLineReq misses
1661system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 176856 # number of LoadLockedReq misses
1662system.cpu1.dcache.LoadLockedReq_misses::total 176856 # number of LoadLockedReq misses
1663system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201345 # number of StoreCondReq misses
1664system.cpu1.dcache.StoreCondReq_misses::total 201345 # number of StoreCondReq misses
1665system.cpu1.dcache.demand_misses::cpu1.data 4416606 # number of demand (read+write) misses
1666system.cpu1.dcache.demand_misses::total 4416606 # number of demand (read+write) misses
1667system.cpu1.dcache.overall_misses::cpu1.data 5054936 # number of overall misses
1668system.cpu1.dcache.overall_misses::total 5054936 # number of overall misses
1669system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51930161500 # number of ReadReq miss cycles
1670system.cpu1.dcache.ReadReq_miss_latency::total 51930161500 # number of ReadReq miss cycles
1671system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 32223402000 # number of WriteReq miss cycles
1672system.cpu1.dcache.WriteReq_miss_latency::total 32223402000 # number of WriteReq miss cycles
1673system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17094390000 # number of WriteLineReq miss cycles
1674system.cpu1.dcache.WriteLineReq_miss_latency::total 17094390000 # number of WriteLineReq miss cycles
1675system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3024227500 # number of LoadLockedReq miss cycles
1676system.cpu1.dcache.LoadLockedReq_miss_latency::total 3024227500 # number of LoadLockedReq miss cycles
1677system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5760420500 # number of StoreCondReq miss cycles
1678system.cpu1.dcache.StoreCondReq_miss_latency::total 5760420500 # number of StoreCondReq miss cycles
1679system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4429500 # number of StoreCondFailReq miss cycles
1680system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4429500 # number of StoreCondFailReq miss cycles
1681system.cpu1.dcache.demand_miss_latency::cpu1.data 84153563500 # number of demand (read+write) miss cycles
1682system.cpu1.dcache.demand_miss_latency::total 84153563500 # number of demand (read+write) miss cycles
1683system.cpu1.dcache.overall_miss_latency::cpu1.data 84153563500 # number of overall miss cycles
1684system.cpu1.dcache.overall_miss_latency::total 84153563500 # number of overall miss cycles
1685system.cpu1.dcache.ReadReq_accesses::cpu1.data 82132975 # number of ReadReq accesses(hits+misses)
1686system.cpu1.dcache.ReadReq_accesses::total 82132975 # number of ReadReq accesses(hits+misses)
1687system.cpu1.dcache.WriteReq_accesses::cpu1.data 75079547 # number of WriteReq accesses(hits+misses)
1688system.cpu1.dcache.WriteReq_accesses::total 75079547 # number of WriteReq accesses(hits+misses)
1689system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 822655 # number of SoftPFReq accesses(hits+misses)
1690system.cpu1.dcache.SoftPFReq_accesses::total 822655 # number of SoftPFReq accesses(hits+misses)
1691system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 617828 # number of WriteLineReq accesses(hits+misses)
1692system.cpu1.dcache.WriteLineReq_accesses::total 617828 # number of WriteLineReq accesses(hits+misses)
1693system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945771 # number of LoadLockedReq accesses(hits+misses)
1694system.cpu1.dcache.LoadLockedReq_accesses::total 1945771 # number of LoadLockedReq accesses(hits+misses)
1695system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944331 # number of StoreCondReq accesses(hits+misses)
1696system.cpu1.dcache.StoreCondReq_accesses::total 1944331 # number of StoreCondReq accesses(hits+misses)
1697system.cpu1.dcache.demand_accesses::cpu1.data 157212522 # number of demand (read+write) accesses
1698system.cpu1.dcache.demand_accesses::total 157212522 # number of demand (read+write) accesses
1699system.cpu1.dcache.overall_accesses::cpu1.data 158035177 # number of overall (read+write) accesses
1700system.cpu1.dcache.overall_accesses::total 158035177 # number of overall (read+write) accesses
1701system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037149 # miss rate for ReadReq accesses
1702system.cpu1.dcache.ReadReq_miss_rate::total 0.037149 # miss rate for ReadReq accesses
1703system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018187 # miss rate for WriteReq accesses
1704system.cpu1.dcache.WriteReq_miss_rate::total 0.018187 # miss rate for WriteReq accesses
1705system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775939 # miss rate for SoftPFReq accesses
1706system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775939 # miss rate for SoftPFReq accesses
1707system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770176 # miss rate for WriteLineReq accesses
1708system.cpu1.dcache.WriteLineReq_miss_rate::total 0.770176 # miss rate for WriteLineReq accesses
1709system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.090893 # miss rate for LoadLockedReq accesses
1710system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.090893 # miss rate for LoadLockedReq accesses
1711system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103555 # miss rate for StoreCondReq accesses
1712system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103555 # miss rate for StoreCondReq accesses
1713system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028093 # miss rate for demand accesses
1714system.cpu1.dcache.demand_miss_rate::total 0.028093 # miss rate for demand accesses
1715system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031986 # miss rate for overall accesses
1716system.cpu1.dcache.overall_miss_rate::total 0.031986 # miss rate for overall accesses
1717system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649 # average ReadReq miss latency
1718system.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649 # average ReadReq miss latency
1719system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613 # average WriteReq miss latency
1720system.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613 # average WriteReq miss latency
1721system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541 # average WriteLineReq miss latency
1722system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541 # average WriteLineReq miss latency
1723system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891 # average LoadLockedReq miss latency
1724system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891 # average LoadLockedReq miss latency
1725system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252 # average StoreCondReq miss latency
1726system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252 # average StoreCondReq miss latency
1727system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1728system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1729system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19053.898740 # average overall miss latency
1730system.cpu1.dcache.demand_avg_miss_latency::total 19053.898740 # average overall miss latency
1731system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16647.799992 # average overall miss latency
1732system.cpu1.dcache.overall_avg_miss_latency::total 16647.799992 # average overall miss latency
1733system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1734system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1735system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1736system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1737system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1738system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1739system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1740system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1741system.cpu1.dcache.writebacks::writebacks 5332630 # number of writebacks
1742system.cpu1.dcache.writebacks::total 5332630 # number of writebacks
1743system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 22206 # number of ReadReq MSHR hits
1744system.cpu1.dcache.ReadReq_mshr_hits::total 22206 # number of ReadReq MSHR hits
1745system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 454 # number of WriteReq MSHR hits
1746system.cpu1.dcache.WriteReq_mshr_hits::total 454 # number of WriteReq MSHR hits
1747system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46550 # number of LoadLockedReq MSHR hits
1748system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46550 # number of LoadLockedReq MSHR hits
1749system.cpu1.dcache.demand_mshr_hits::cpu1.data 22660 # number of demand (read+write) MSHR hits
1750system.cpu1.dcache.demand_mshr_hits::total 22660 # number of demand (read+write) MSHR hits
1751system.cpu1.dcache.overall_mshr_hits::cpu1.data 22660 # number of overall MSHR hits
1752system.cpu1.dcache.overall_mshr_hits::total 22660 # number of overall MSHR hits
1753system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3028931 # number of ReadReq MSHR misses
1754system.cpu1.dcache.ReadReq_mshr_misses::total 3028931 # number of ReadReq MSHR misses
1755system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1365015 # number of WriteReq MSHR misses
1756system.cpu1.dcache.WriteReq_mshr_misses::total 1365015 # number of WriteReq MSHR misses
1757system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 638330 # number of SoftPFReq MSHR misses
1758system.cpu1.dcache.SoftPFReq_mshr_misses::total 638330 # number of SoftPFReq MSHR misses
1759system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 475836 # number of WriteLineReq MSHR misses
1760system.cpu1.dcache.WriteLineReq_mshr_misses::total 475836 # number of WriteLineReq MSHR misses
1761system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 130306 # number of LoadLockedReq MSHR misses
1762system.cpu1.dcache.LoadLockedReq_mshr_misses::total 130306 # number of LoadLockedReq MSHR misses
1763system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201345 # number of StoreCondReq MSHR misses
1764system.cpu1.dcache.StoreCondReq_mshr_misses::total 201345 # number of StoreCondReq MSHR misses
1765system.cpu1.dcache.demand_mshr_misses::cpu1.data 4393946 # number of demand (read+write) MSHR misses
1766system.cpu1.dcache.demand_mshr_misses::total 4393946 # number of demand (read+write) MSHR misses
1767system.cpu1.dcache.overall_mshr_misses::cpu1.data 5032276 # number of overall MSHR misses
1768system.cpu1.dcache.overall_mshr_misses::total 5032276 # number of overall MSHR misses
1769system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 10149 # number of ReadReq MSHR uncacheable
1770system.cpu1.dcache.ReadReq_mshr_uncacheable::total 10149 # number of ReadReq MSHR uncacheable
1771system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable
1772system.cpu1.dcache.WriteReq_mshr_uncacheable::total 10618 # number of WriteReq MSHR uncacheable
1773system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 20767 # number of overall MSHR uncacheable misses
1774system.cpu1.dcache.overall_mshr_uncacheable_misses::total 20767 # number of overall MSHR uncacheable misses
1775system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46920862500 # number of ReadReq MSHR miss cycles
1776system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46920862500 # number of ReadReq MSHR miss cycles
1777system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30832329000 # number of WriteReq MSHR miss cycles
1778system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30832329000 # number of WriteReq MSHR miss cycles
1779system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15929044000 # number of SoftPFReq MSHR miss cycles
1780system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15929044000 # number of SoftPFReq MSHR miss cycles
1781system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16618554000 # number of WriteLineReq MSHR miss cycles
1782system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16618554000 # number of WriteLineReq MSHR miss cycles
1783system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1916877000 # number of LoadLockedReq MSHR miss cycles
1784system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1916877000 # number of LoadLockedReq MSHR miss cycles
1785system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5559123500 # number of StoreCondReq MSHR miss cycles
1786system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5559123500 # number of StoreCondReq MSHR miss cycles
1787system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4381500 # number of StoreCondFailReq MSHR miss cycles
1788system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4381500 # number of StoreCondFailReq MSHR miss cycles
1789system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77753191500 # number of demand (read+write) MSHR miss cycles
1790system.cpu1.dcache.demand_mshr_miss_latency::total 77753191500 # number of demand (read+write) MSHR miss cycles
1791system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93682235500 # number of overall MSHR miss cycles
1792system.cpu1.dcache.overall_mshr_miss_latency::total 93682235500 # number of overall MSHR miss cycles
1793system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1652437500 # number of ReadReq MSHR uncacheable cycles
1794system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1652437500 # number of ReadReq MSHR uncacheable cycles
1795system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1820826500 # number of WriteReq MSHR uncacheable cycles
1796system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1820826500 # number of WriteReq MSHR uncacheable cycles
1797system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3473264000 # number of overall MSHR uncacheable cycles
1798system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3473264000 # number of overall MSHR uncacheable cycles
1799system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036878 # mshr miss rate for ReadReq accesses
1800system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036878 # mshr miss rate for ReadReq accesses
1801system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018181 # mshr miss rate for WriteReq accesses
1802system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018181 # mshr miss rate for WriteReq accesses
1803system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775939 # mshr miss rate for SoftPFReq accesses
1804system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775939 # mshr miss rate for SoftPFReq accesses
1805system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.770176 # mshr miss rate for WriteLineReq accesses
1806system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.770176 # mshr miss rate for WriteLineReq accesses
1807system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066969 # mshr miss rate for LoadLockedReq accesses
1808system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066969 # mshr miss rate for LoadLockedReq accesses
1809system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103555 # mshr miss rate for StoreCondReq accesses
1810system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103555 # mshr miss rate for StoreCondReq accesses
1811system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027949 # mshr miss rate for demand accesses
1812system.cpu1.dcache.demand_mshr_miss_rate::total 0.027949 # mshr miss rate for demand accesses
1813system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031843 # mshr miss rate for overall accesses
1814system.cpu1.dcache.overall_mshr_miss_rate::total 0.031843 # mshr miss rate for overall accesses
1815system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15490.898439 # average ReadReq mshr miss latency
1816system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15490.898439 # average ReadReq mshr miss latency
1817system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22587.538598 # average WriteReq mshr miss latency
1818system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22587.538598 # average WriteReq mshr miss latency
1819system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24954.246236 # average SoftPFReq mshr miss latency
1820system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24954.246236 # average SoftPFReq mshr miss latency
1821system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 34924.961541 # average WriteLineReq mshr miss latency
1822system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 34924.961541 # average WriteLineReq mshr miss latency
1823system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14710.581247 # average LoadLockedReq mshr miss latency
1824system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14710.581247 # average LoadLockedReq mshr miss latency
1825system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27609.940649 # average StoreCondReq mshr miss latency
1826system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27609.940649 # average StoreCondReq mshr miss latency
1827system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1828system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1829system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17695.527323 # average overall mshr miss latency
1830system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17695.527323 # average overall mshr miss latency
1831system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18616.275320 # average overall mshr miss latency
1832system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18616.275320 # average overall mshr miss latency
1833system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162817.765297 # average ReadReq mshr uncacheable latency
1834system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162817.765297 # average ReadReq mshr uncacheable latency
1835system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171484.884159 # average WriteReq mshr uncacheable latency
1836system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171484.884159 # average WriteReq mshr uncacheable latency
1837system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167249.193432 # average overall mshr uncacheable latency
1838system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167249.193432 # average overall mshr uncacheable latency
1839system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1840system.cpu1.icache.tags.replacements 5368535 # number of replacements
1841system.cpu1.icache.tags.tagsinuse 496.099630 # Cycle average of tags in use
1842system.cpu1.icache.tags.total_refs 443130586 # Total number of references to valid blocks.
1843system.cpu1.icache.tags.sampled_refs 5369047 # Sample count of references to valid blocks.
1844system.cpu1.icache.tags.avg_refs 82.534309 # Average number of references to valid blocks.
1845system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit.
1846system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.099630 # Average occupied blocks per requestor
1847system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968945 # Average percentage of cache occupancy
1848system.cpu1.icache.tags.occ_percent::total 0.968945 # Average percentage of cache occupancy
1849system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1850system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
1851system.cpu1.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
1852system.cpu1.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id
1853system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1854system.cpu1.icache.tags.tag_accesses 902368316 # Number of tag accesses
1855system.cpu1.icache.tags.data_accesses 902368316 # Number of data accesses
1856system.cpu1.icache.ReadReq_hits::cpu1.inst 443130586 # number of ReadReq hits
1857system.cpu1.icache.ReadReq_hits::total 443130586 # number of ReadReq hits
1858system.cpu1.icache.demand_hits::cpu1.inst 443130586 # number of demand (read+write) hits
1859system.cpu1.icache.demand_hits::total 443130586 # number of demand (read+write) hits
1860system.cpu1.icache.overall_hits::cpu1.inst 443130586 # number of overall hits
1861system.cpu1.icache.overall_hits::total 443130586 # number of overall hits
1862system.cpu1.icache.ReadReq_misses::cpu1.inst 5369048 # number of ReadReq misses
1863system.cpu1.icache.ReadReq_misses::total 5369048 # number of ReadReq misses
1864system.cpu1.icache.demand_misses::cpu1.inst 5369048 # number of demand (read+write) misses
1865system.cpu1.icache.demand_misses::total 5369048 # number of demand (read+write) misses
1866system.cpu1.icache.overall_misses::cpu1.inst 5369048 # number of overall misses
1867system.cpu1.icache.overall_misses::total 5369048 # number of overall misses
1868system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 58701560000 # number of ReadReq miss cycles
1869system.cpu1.icache.ReadReq_miss_latency::total 58701560000 # number of ReadReq miss cycles
1870system.cpu1.icache.demand_miss_latency::cpu1.inst 58701560000 # number of demand (read+write) miss cycles
1871system.cpu1.icache.demand_miss_latency::total 58701560000 # number of demand (read+write) miss cycles
1872system.cpu1.icache.overall_miss_latency::cpu1.inst 58701560000 # number of overall miss cycles
1873system.cpu1.icache.overall_miss_latency::total 58701560000 # number of overall miss cycles
1874system.cpu1.icache.ReadReq_accesses::cpu1.inst 448499634 # number of ReadReq accesses(hits+misses)
1875system.cpu1.icache.ReadReq_accesses::total 448499634 # number of ReadReq accesses(hits+misses)
1876system.cpu1.icache.demand_accesses::cpu1.inst 448499634 # number of demand (read+write) accesses
1877system.cpu1.icache.demand_accesses::total 448499634 # number of demand (read+write) accesses
1878system.cpu1.icache.overall_accesses::cpu1.inst 448499634 # number of overall (read+write) accesses
1879system.cpu1.icache.overall_accesses::total 448499634 # number of overall (read+write) accesses
1880system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011971 # miss rate for ReadReq accesses
1881system.cpu1.icache.ReadReq_miss_rate::total 0.011971 # miss rate for ReadReq accesses
1882system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011971 # miss rate for demand accesses
1883system.cpu1.icache.demand_miss_rate::total 0.011971 # miss rate for demand accesses
1884system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011971 # miss rate for overall accesses
1885system.cpu1.icache.overall_miss_rate::total 0.011971 # miss rate for overall accesses
1886system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10933.327473 # average ReadReq miss latency
1887system.cpu1.icache.ReadReq_avg_miss_latency::total 10933.327473 # average ReadReq miss latency
1888system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10933.327473 # average overall miss latency
1889system.cpu1.icache.demand_avg_miss_latency::total 10933.327473 # average overall miss latency
1890system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10933.327473 # average overall miss latency
1891system.cpu1.icache.overall_avg_miss_latency::total 10933.327473 # average overall miss latency
1892system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1893system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1894system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1895system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1896system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1897system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1898system.cpu1.icache.fast_writes 0 # number of fast writes performed
1899system.cpu1.icache.cache_copies 0 # number of cache copies performed
1900system.cpu1.icache.writebacks::writebacks 5368535 # number of writebacks
1901system.cpu1.icache.writebacks::total 5368535 # number of writebacks
1902system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5369048 # number of ReadReq MSHR misses
1903system.cpu1.icache.ReadReq_mshr_misses::total 5369048 # number of ReadReq MSHR misses
1904system.cpu1.icache.demand_mshr_misses::cpu1.inst 5369048 # number of demand (read+write) MSHR misses
1905system.cpu1.icache.demand_mshr_misses::total 5369048 # number of demand (read+write) MSHR misses
1906system.cpu1.icache.overall_mshr_misses::cpu1.inst 5369048 # number of overall MSHR misses
1907system.cpu1.icache.overall_mshr_misses::total 5369048 # number of overall MSHR misses
1908system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
1909system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
1910system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
1911system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
1912system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56017036000 # number of ReadReq MSHR miss cycles
1913system.cpu1.icache.ReadReq_mshr_miss_latency::total 56017036000 # number of ReadReq MSHR miss cycles
1914system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56017036000 # number of demand (read+write) MSHR miss cycles
1915system.cpu1.icache.demand_mshr_miss_latency::total 56017036000 # number of demand (read+write) MSHR miss cycles
1916system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56017036000 # number of overall MSHR miss cycles
1917system.cpu1.icache.overall_mshr_miss_latency::total 56017036000 # number of overall MSHR miss cycles
1918system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14763500 # number of ReadReq MSHR uncacheable cycles
1919system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14763500 # number of ReadReq MSHR uncacheable cycles
1920system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14763500 # number of overall MSHR uncacheable cycles
1921system.cpu1.icache.overall_mshr_uncacheable_latency::total 14763500 # number of overall MSHR uncacheable cycles
1922system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for ReadReq accesses
1923system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011971 # mshr miss rate for ReadReq accesses
1924system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for demand accesses
1925system.cpu1.icache.demand_mshr_miss_rate::total 0.011971 # mshr miss rate for demand accesses
1926system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for overall accesses
1927system.cpu1.icache.overall_mshr_miss_rate::total 0.011971 # mshr miss rate for overall accesses
1928system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average ReadReq mshr miss latency
1929system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10433.327473 # average ReadReq mshr miss latency
1930system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency
1931system.cpu1.icache.demand_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency
1932system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency
1933system.cpu1.icache.overall_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency
1934system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency
1935system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency
1936system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency
1937system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency
1938system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1939system.cpu1.l2cache.prefetcher.num_hwpf_issued 7379094 # number of hwpf issued
1940system.cpu1.l2cache.prefetcher.pfIdentified 7379143 # number of prefetch candidates identified
1941system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue
1942system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1943system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1944system.cpu1.l2cache.prefetcher.pfSpanPage 880313 # number of prefetches not generated due to page crossing
1945system.cpu1.l2cache.tags.replacements 2062305 # number of replacements
1946system.cpu1.l2cache.tags.tagsinuse 13347.402456 # Cycle average of tags in use
1947system.cpu1.l2cache.tags.total_refs 15756881 # Total number of references to valid blocks.
1948system.cpu1.l2cache.tags.sampled_refs 2078287 # Sample count of references to valid blocks.
1949system.cpu1.l2cache.tags.avg_refs 7.581667 # Average number of references to valid blocks.
1950system.cpu1.l2cache.tags.warmup_cycle 10111476094500 # Cycle when the warmup percentage was hit.
1951system.cpu1.l2cache.tags.occ_blocks::writebacks 12484.773775 # Average occupied blocks per requestor
1952system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.991468 # Average occupied blocks per requestor
1953system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.953770 # Average occupied blocks per requestor
1954system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.683443 # Average occupied blocks per requestor
1955system.cpu1.l2cache.tags.occ_percent::writebacks 0.762010 # Average percentage of cache occupancy
1956system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003173 # Average percentage of cache occupancy
1957system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003659 # Average percentage of cache occupancy
1958system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy
1959system.cpu1.l2cache.tags.occ_percent::total 0.814661 # Average percentage of cache occupancy
1960system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1312 # Occupied blocks per task id
1961system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id
1962system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14621 # Occupied blocks per task id
1963system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id
1964system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 231 # Occupied blocks per task id
1965system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 561 # Occupied blocks per task id
1966system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id
1967system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
1968system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id
1969system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id
1970system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
1971system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
1972system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 989 # Occupied blocks per task id
1973system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4575 # Occupied blocks per task id
1974system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5108 # Occupied blocks per task id
1975system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3891 # Occupied blocks per task id
1976system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080078 # Percentage of cache occupancy per task id
1977system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id
1978system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892395 # Percentage of cache occupancy per task id
1979system.cpu1.l2cache.tags.tag_accesses 362674413 # Number of tag accesses
1980system.cpu1.l2cache.tags.data_accesses 362674413 # Number of data accesses
1981system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 250614 # number of ReadReq hits
1982system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 164455 # number of ReadReq hits
1983system.cpu1.l2cache.ReadReq_hits::total 415069 # number of ReadReq hits
1984system.cpu1.l2cache.WritebackDirty_hits::writebacks 3362211 # number of WritebackDirty hits
1985system.cpu1.l2cache.WritebackDirty_hits::total 3362211 # number of WritebackDirty hits
1986system.cpu1.l2cache.WritebackClean_hits::writebacks 7338042 # number of WritebackClean hits
1987system.cpu1.l2cache.WritebackClean_hits::total 7338042 # number of WritebackClean hits
1988system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 793 # number of UpgradeReq hits
1989system.cpu1.l2cache.UpgradeReq_hits::total 793 # number of UpgradeReq hits
1990system.cpu1.l2cache.ReadExReq_hits::cpu1.data 895753 # number of ReadExReq hits
1991system.cpu1.l2cache.ReadExReq_hits::total 895753 # number of ReadExReq hits
1992system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4900610 # number of ReadCleanReq hits
1993system.cpu1.l2cache.ReadCleanReq_hits::total 4900610 # number of ReadCleanReq hits
1994system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2870677 # number of ReadSharedReq hits
1995system.cpu1.l2cache.ReadSharedReq_hits::total 2870677 # number of ReadSharedReq hits
1996system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 215360 # number of InvalidateReq hits
1997system.cpu1.l2cache.InvalidateReq_hits::total 215360 # number of InvalidateReq hits
1998system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 250614 # number of demand (read+write) hits
1999system.cpu1.l2cache.demand_hits::cpu1.itb.walker 164455 # number of demand (read+write) hits
2000system.cpu1.l2cache.demand_hits::cpu1.inst 4900610 # number of demand (read+write) hits
2001system.cpu1.l2cache.demand_hits::cpu1.data 3766430 # number of demand (read+write) hits
2002system.cpu1.l2cache.demand_hits::total 9082109 # number of demand (read+write) hits
2003system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 250614 # number of overall hits
2004system.cpu1.l2cache.overall_hits::cpu1.itb.walker 164455 # number of overall hits
2005system.cpu1.l2cache.overall_hits::cpu1.inst 4900610 # number of overall hits
2006system.cpu1.l2cache.overall_hits::cpu1.data 3766430 # number of overall hits
2007system.cpu1.l2cache.overall_hits::total 9082109 # number of overall hits
2008system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11669 # number of ReadReq misses
2009system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10135 # number of ReadReq misses
2010system.cpu1.l2cache.ReadReq_misses::total 21804 # number of ReadReq misses
2011system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 207192 # number of UpgradeReq misses
2012system.cpu1.l2cache.UpgradeReq_misses::total 207192 # number of UpgradeReq misses
2013system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201338 # number of SCUpgradeReq misses
2014system.cpu1.l2cache.SCUpgradeReq_misses::total 201338 # number of SCUpgradeReq misses
2015system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
2016system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
2017system.cpu1.l2cache.ReadExReq_misses::cpu1.data 263735 # number of ReadExReq misses
2018system.cpu1.l2cache.ReadExReq_misses::total 263735 # number of ReadExReq misses
2019system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 468438 # number of ReadCleanReq misses
2020system.cpu1.l2cache.ReadCleanReq_misses::total 468438 # number of ReadCleanReq misses
2021system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 926890 # number of ReadSharedReq misses
2022system.cpu1.l2cache.ReadSharedReq_misses::total 926890 # number of ReadSharedReq misses
2023system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258258 # number of InvalidateReq misses
2024system.cpu1.l2cache.InvalidateReq_misses::total 258258 # number of InvalidateReq misses
2025system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11669 # number of demand (read+write) misses
2026system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10135 # number of demand (read+write) misses
2027system.cpu1.l2cache.demand_misses::cpu1.inst 468438 # number of demand (read+write) misses
2028system.cpu1.l2cache.demand_misses::cpu1.data 1190625 # number of demand (read+write) misses
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2030system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11669 # number of overall misses
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2032system.cpu1.l2cache.overall_misses::cpu1.inst 468438 # number of overall misses
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2039system.cpu1.l2cache.UpgradeReq_miss_latency::total 3305334500 # number of UpgradeReq miss cycles
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2041system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2142938000 # number of SCUpgradeReq miss cycles
2042system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4308999 # number of SCUpgradeFailReq miss cycles
2043system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4308999 # number of SCUpgradeFailReq miss cycles
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2045system.cpu1.l2cache.ReadExReq_miss_latency::total 15026168500 # number of ReadExReq miss cycles
2046system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18507593500 # number of ReadCleanReq miss cycles
2047system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18507593500 # number of ReadCleanReq miss cycles
2048system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 40367140999 # number of ReadSharedReq miss cycles
2049system.cpu1.l2cache.ReadSharedReq_miss_latency::total 40367140999 # number of ReadSharedReq miss cycles
2050system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 516760500 # number of InvalidateReq miss cycles
2051system.cpu1.l2cache.InvalidateReq_miss_latency::total 516760500 # number of InvalidateReq miss cycles
2052system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 716522000 # number of demand (read+write) miss cycles
2053system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 701084000 # number of demand (read+write) miss cycles
2054system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18507593500 # number of demand (read+write) miss cycles
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2059system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18507593500 # number of overall miss cycles
2060system.cpu1.l2cache.overall_miss_latency::cpu1.data 55393309499 # number of overall miss cycles
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2063system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174590 # number of ReadReq accesses(hits+misses)
2064system.cpu1.l2cache.ReadReq_accesses::total 436873 # number of ReadReq accesses(hits+misses)
2065system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3362211 # number of WritebackDirty accesses(hits+misses)
2066system.cpu1.l2cache.WritebackDirty_accesses::total 3362211 # number of WritebackDirty accesses(hits+misses)
2067system.cpu1.l2cache.WritebackClean_accesses::writebacks 7338042 # number of WritebackClean accesses(hits+misses)
2068system.cpu1.l2cache.WritebackClean_accesses::total 7338042 # number of WritebackClean accesses(hits+misses)
2069system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207985 # number of UpgradeReq accesses(hits+misses)
2070system.cpu1.l2cache.UpgradeReq_accesses::total 207985 # number of UpgradeReq accesses(hits+misses)
2071system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201338 # number of SCUpgradeReq accesses(hits+misses)
2072system.cpu1.l2cache.SCUpgradeReq_accesses::total 201338 # number of SCUpgradeReq accesses(hits+misses)
2073system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
2074system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
2075system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1159488 # number of ReadExReq accesses(hits+misses)
2076system.cpu1.l2cache.ReadExReq_accesses::total 1159488 # number of ReadExReq accesses(hits+misses)
2077system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5369048 # number of ReadCleanReq accesses(hits+misses)
2078system.cpu1.l2cache.ReadCleanReq_accesses::total 5369048 # number of ReadCleanReq accesses(hits+misses)
2079system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3797567 # number of ReadSharedReq accesses(hits+misses)
2080system.cpu1.l2cache.ReadSharedReq_accesses::total 3797567 # number of ReadSharedReq accesses(hits+misses)
2081system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 473618 # number of InvalidateReq accesses(hits+misses)
2082system.cpu1.l2cache.InvalidateReq_accesses::total 473618 # number of InvalidateReq accesses(hits+misses)
2083system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 262283 # number of demand (read+write) accesses
2084system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174590 # number of demand (read+write) accesses
2085system.cpu1.l2cache.demand_accesses::cpu1.inst 5369048 # number of demand (read+write) accesses
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2088system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 262283 # number of overall (read+write) accesses
2089system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174590 # number of overall (read+write) accesses
2090system.cpu1.l2cache.overall_accesses::cpu1.inst 5369048 # number of overall (read+write) accesses
2091system.cpu1.l2cache.overall_accesses::cpu1.data 4957055 # number of overall (read+write) accesses
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2093system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044490 # miss rate for ReadReq accesses
2094system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058050 # miss rate for ReadReq accesses
2095system.cpu1.l2cache.ReadReq_miss_rate::total 0.049909 # miss rate for ReadReq accesses
2096system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996187 # miss rate for UpgradeReq accesses
2097system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996187 # miss rate for UpgradeReq accesses
2098system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2099system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2100system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2101system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2102system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227458 # miss rate for ReadExReq accesses
2103system.cpu1.l2cache.ReadExReq_miss_rate::total 0.227458 # miss rate for ReadExReq accesses
2104system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087248 # miss rate for ReadCleanReq accesses
2105system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087248 # miss rate for ReadCleanReq accesses
2106system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.244075 # miss rate for ReadSharedReq accesses
2107system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.244075 # miss rate for ReadSharedReq accesses
2108system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.545288 # miss rate for InvalidateReq accesses
2109system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.545288 # miss rate for InvalidateReq accesses
2110system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044490 # miss rate for demand accesses
2111system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058050 # miss rate for demand accesses
2112system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087248 # miss rate for demand accesses
2113system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240188 # miss rate for demand accesses
2114system.cpu1.l2cache.demand_miss_rate::total 0.156171 # miss rate for demand accesses
2115system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044490 # miss rate for overall accesses
2116system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058050 # miss rate for overall accesses
2117system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087248 # miss rate for overall accesses
2118system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240188 # miss rate for overall accesses
2119system.cpu1.l2cache.overall_miss_rate::total 0.156171 # miss rate for overall accesses
2120system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 61403.890650 # average ReadReq miss latency
2121system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 69174.543661 # average ReadReq miss latency
2122system.cpu1.l2cache.ReadReq_avg_miss_latency::total 65015.868648 # average ReadReq miss latency
2123system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15953.002529 # average UpgradeReq miss latency
2124system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15953.002529 # average UpgradeReq miss latency
2125system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10643.485085 # average SCUpgradeReq miss latency
2126system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10643.485085 # average SCUpgradeReq miss latency
2127system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 615571.285714 # average SCUpgradeFailReq miss latency
2128system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 615571.285714 # average SCUpgradeFailReq miss latency
2129system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56974.495232 # average ReadExReq miss latency
2130system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56974.495232 # average ReadExReq miss latency
2131system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39509.163433 # average ReadCleanReq miss latency
2132system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39509.163433 # average ReadCleanReq miss latency
2133system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43551.166804 # average ReadSharedReq miss latency
2134system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43551.166804 # average ReadSharedReq miss latency
2135system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 2000.946728 # average InvalidateReq miss latency
2136system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 2000.946728 # average InvalidateReq miss latency
2137system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 61403.890650 # average overall miss latency
2138system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 69174.543661 # average overall miss latency
2139system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39509.163433 # average overall miss latency
2140system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 46524.564409 # average overall miss latency
2141system.cpu1.l2cache.demand_avg_miss_latency::total 44809.321022 # average overall miss latency
2142system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 61403.890650 # average overall miss latency
2143system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 69174.543661 # average overall miss latency
2144system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39509.163433 # average overall miss latency
2145system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 46524.564409 # average overall miss latency
2146system.cpu1.l2cache.overall_avg_miss_latency::total 44809.321022 # average overall miss latency
2147system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2148system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2149system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2150system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2151system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2152system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2153system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2154system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2155system.cpu1.l2cache.writebacks::writebacks 1141854 # number of writebacks
2156system.cpu1.l2cache.writebacks::total 1141854 # number of writebacks
2157system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5992 # number of ReadExReq MSHR hits
2158system.cpu1.l2cache.ReadExReq_mshr_hits::total 5992 # number of ReadExReq MSHR hits
2159system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 581 # number of ReadSharedReq MSHR hits
2160system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 581 # number of ReadSharedReq MSHR hits
2161system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6573 # number of demand (read+write) MSHR hits
2162system.cpu1.l2cache.demand_mshr_hits::total 6573 # number of demand (read+write) MSHR hits
2163system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6573 # number of overall MSHR hits
2164system.cpu1.l2cache.overall_mshr_hits::total 6573 # number of overall MSHR hits
2165system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11669 # number of ReadReq MSHR misses
2166system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10135 # number of ReadReq MSHR misses
2167system.cpu1.l2cache.ReadReq_mshr_misses::total 21804 # number of ReadReq MSHR misses
2168system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 737355 # number of HardPFReq MSHR misses
2169system.cpu1.l2cache.HardPFReq_mshr_misses::total 737355 # number of HardPFReq MSHR misses
2170system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 207192 # number of UpgradeReq MSHR misses
2171system.cpu1.l2cache.UpgradeReq_mshr_misses::total 207192 # number of UpgradeReq MSHR misses
2172system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 201338 # number of SCUpgradeReq MSHR misses
2173system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 201338 # number of SCUpgradeReq MSHR misses
2174system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
2175system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
2176system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257743 # number of ReadExReq MSHR misses
2177system.cpu1.l2cache.ReadExReq_mshr_misses::total 257743 # number of ReadExReq MSHR misses
2178system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 468438 # number of ReadCleanReq MSHR misses
2179system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 468438 # number of ReadCleanReq MSHR misses
2180system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 926309 # number of ReadSharedReq MSHR misses
2181system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 926309 # number of ReadSharedReq MSHR misses
2182system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258258 # number of InvalidateReq MSHR misses
2183system.cpu1.l2cache.InvalidateReq_mshr_misses::total 258258 # number of InvalidateReq MSHR misses
2184system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11669 # number of demand (read+write) MSHR misses
2185system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10135 # number of demand (read+write) MSHR misses
2186system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 468438 # number of demand (read+write) MSHR misses
2187system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1184052 # number of demand (read+write) MSHR misses
2188system.cpu1.l2cache.demand_mshr_misses::total 1674294 # number of demand (read+write) MSHR misses
2189system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11669 # number of overall MSHR misses
2190system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10135 # number of overall MSHR misses
2191system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 468438 # number of overall MSHR misses
2192system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1184052 # number of overall MSHR misses
2193system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 737355 # number of overall MSHR misses
2194system.cpu1.l2cache.overall_mshr_misses::total 2411649 # number of overall MSHR misses
2195system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2196system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 10149 # number of ReadReq MSHR uncacheable
2197system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 10259 # number of ReadReq MSHR uncacheable
2198system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable
2199system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 10618 # number of WriteReq MSHR uncacheable
2200system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2201system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 20767 # number of overall MSHR uncacheable misses
2202system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 20877 # number of overall MSHR uncacheable misses
2203system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 646508000 # number of ReadReq MSHR miss cycles
2204system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 640274000 # number of ReadReq MSHR miss cycles
2205system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1286782000 # number of ReadReq MSHR miss cycles
2206system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39407007921 # number of HardPFReq MSHR miss cycles
2207system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 39407007921 # number of HardPFReq MSHR miss cycles
2208system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6717201500 # number of UpgradeReq MSHR miss cycles
2209system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6717201500 # number of UpgradeReq MSHR miss cycles
2210system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 4047781500 # number of SCUpgradeReq MSHR miss cycles
2211system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 4047781500 # number of SCUpgradeReq MSHR miss cycles
2212system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4020999 # number of SCUpgradeFailReq MSHR miss cycles
2213system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4020999 # number of SCUpgradeFailReq MSHR miss cycles
2214system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12743172000 # number of ReadExReq MSHR miss cycles
2215system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12743172000 # number of ReadExReq MSHR miss cycles
2216system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15696965500 # number of ReadCleanReq MSHR miss cycles
2217system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15696965500 # number of ReadCleanReq MSHR miss cycles
2218system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 34752380999 # number of ReadSharedReq MSHR miss cycles
2219system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 34752380999 # number of ReadSharedReq MSHR miss cycles
2220system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12891073000 # number of InvalidateReq MSHR miss cycles
2221system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12891073000 # number of InvalidateReq MSHR miss cycles
2222system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 646508000 # number of demand (read+write) MSHR miss cycles
2223system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 640274000 # number of demand (read+write) MSHR miss cycles
2224system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15696965500 # number of demand (read+write) MSHR miss cycles
2225system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 47495552999 # number of demand (read+write) MSHR miss cycles
2226system.cpu1.l2cache.demand_mshr_miss_latency::total 64479300499 # number of demand (read+write) MSHR miss cycles
2227system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 646508000 # number of overall MSHR miss cycles
2228system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 640274000 # number of overall MSHR miss cycles
2229system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15696965500 # number of overall MSHR miss cycles
2230system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 47495552999 # number of overall MSHR miss cycles
2231system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39407007921 # number of overall MSHR miss cycles
2232system.cpu1.l2cache.overall_mshr_miss_latency::total 103886308420 # number of overall MSHR miss cycles
2233system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13938500 # number of ReadReq MSHR uncacheable cycles
2234system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1570752500 # number of ReadReq MSHR uncacheable cycles
2235system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1584691000 # number of ReadReq MSHR uncacheable cycles
2236system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1740638000 # number of WriteReq MSHR uncacheable cycles
2237system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1740638000 # number of WriteReq MSHR uncacheable cycles
2238system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13938500 # number of overall MSHR uncacheable cycles
2239system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3311390500 # number of overall MSHR uncacheable cycles
2240system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3325329000 # number of overall MSHR uncacheable cycles
2241system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for ReadReq accesses
2242system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for ReadReq accesses
2243system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.049909 # mshr miss rate for ReadReq accesses
2244system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2245system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2246system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996187 # mshr miss rate for UpgradeReq accesses
2247system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996187 # mshr miss rate for UpgradeReq accesses
2248system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2249system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2250system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2251system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2252system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222290 # mshr miss rate for ReadExReq accesses
2253system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222290 # mshr miss rate for ReadExReq accesses
2254system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses
2255system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses
2256system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.243922 # mshr miss rate for ReadSharedReq accesses
2257system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243922 # mshr miss rate for ReadSharedReq accesses
2258system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.545288 # mshr miss rate for InvalidateReq accesses
2259system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.545288 # mshr miss rate for InvalidateReq accesses
2260system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for demand accesses
2261system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for demand accesses
2262system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses
2263system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for demand accesses
2264system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155561 # mshr miss rate for demand accesses
2265system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for overall accesses
2266system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for overall accesses
2267system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses
2268system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for overall accesses
2269system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2270system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224069 # mshr miss rate for overall accesses
2271system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average ReadReq mshr miss latency
2272system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average ReadReq mshr miss latency
2273system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 59015.868648 # average ReadReq mshr miss latency
2274system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average HardPFReq mshr miss latency
2275system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53443.738662 # average HardPFReq mshr miss latency
2276system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32420.177903 # average UpgradeReq mshr miss latency
2277system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32420.177903 # average UpgradeReq mshr miss latency
2278system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20104.409004 # average SCUpgradeReq mshr miss latency
2279system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20104.409004 # average SCUpgradeReq mshr miss latency
2280system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574428.428571 # average SCUpgradeFailReq mshr miss latency
2281system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574428.428571 # average SCUpgradeFailReq mshr miss latency
2282system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49441.389291 # average ReadExReq mshr miss latency
2283system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49441.389291 # average ReadExReq mshr miss latency
2284system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average ReadCleanReq mshr miss latency
2285system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33509.163433 # average ReadCleanReq mshr miss latency
2286system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37517.049925 # average ReadSharedReq mshr miss latency
2287system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37517.049925 # average ReadSharedReq mshr miss latency
2288system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49915.483741 # average InvalidateReq mshr miss latency
2289system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49915.483741 # average InvalidateReq mshr miss latency
2290system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency
2291system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency
2292system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency
2293system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency
2294system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38511.337017 # average overall mshr miss latency
2295system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency
2296system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency
2297system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency
2298system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency
2299system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average overall mshr miss latency
2300system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43076.877448 # average overall mshr miss latency
2301system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency
2302system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083 # average ReadReq mshr uncacheable latency
2303system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237 # average ReadReq mshr uncacheable latency
2304system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698 # average WriteReq mshr uncacheable latency
2305system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698 # average WriteReq mshr uncacheable latency
2306system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency
2307system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959 # average overall mshr uncacheable latency
2308system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060 # average overall mshr uncacheable latency
2309system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2310system.cpu1.toL2Bus.snoop_filter.tot_requests 22159802 # Total number of requests made to the snoop filter.
2311system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11360195 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2312system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 912 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2313system.cpu1.toL2Bus.snoop_filter.tot_snoops 1833001 # Total number of snoops made to the snoop filter.
2314system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1832814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2315system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2316system.cpu1.toL2Bus.trans_dist::ReadReq 515851 # Transaction distribution
2317system.cpu1.toL2Bus.trans_dist::ReadResp 9779420 # Transaction distribution
2318system.cpu1.toL2Bus.trans_dist::WriteReq 10618 # Transaction distribution
2319system.cpu1.toL2Bus.trans_dist::WriteResp 10618 # Transaction distribution
2320system.cpu1.toL2Bus.trans_dist::WritebackDirty 4509550 # Transaction distribution
2321system.cpu1.toL2Bus.trans_dist::WritebackClean 7338954 # Transaction distribution
2322system.cpu1.toL2Bus.trans_dist::CleanEvict 2389159 # Transaction distribution
2323system.cpu1.toL2Bus.trans_dist::HardPFReq 893791 # Transaction distribution
2324system.cpu1.toL2Bus.trans_dist::UpgradeReq 389403 # Transaction distribution
2325system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363316 # Transaction distribution
2326system.cpu1.toL2Bus.trans_dist::UpgradeResp 479303 # Transaction distribution
2327system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
2328system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
2329system.cpu1.toL2Bus.trans_dist::ReadExReq 1190307 # Transaction distribution
2330system.cpu1.toL2Bus.trans_dist::ReadExResp 1167875 # Transaction distribution
2331system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5369048 # Transaction distribution
2332system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688099 # Transaction distribution
2333system.cpu1.toL2Bus.trans_dist::InvalidateReq 521676 # Transaction distribution
2334system.cpu1.toL2Bus.trans_dist::InvalidateResp 473618 # Transaction distribution
2335system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16106851 # Packet count per connected master and slave (bytes)
2336system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17229570 # Packet count per connected master and slave (bytes)
2337system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365629 # Packet count per connected master and slave (bytes)
2338system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576836 # Packet count per connected master and slave (bytes)
2339system.cpu1.toL2Bus.pkt_count::total 34278886 # Packet count per connected master and slave (bytes)
2340system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 687205752 # Cumulative packet size per connected master and slave (bytes)
2341system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 665341501 # Cumulative packet size per connected master and slave (bytes)
2342system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1396720 # Cumulative packet size per connected master and slave (bytes)
2343system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2098264 # Cumulative packet size per connected master and slave (bytes)
2344system.cpu1.toL2Bus.pkt_size::total 1356042237 # Cumulative packet size per connected master and slave (bytes)
2345system.cpu1.toL2Bus.snoops 5987251 # Total snoops (count)
2346system.cpu1.toL2Bus.snoop_fanout::samples 17478652 # Request fanout histogram
2347system.cpu1.toL2Bus.snoop_fanout::mean 0.119213 # Request fanout histogram
2348system.cpu1.toL2Bus.snoop_fanout::stdev 0.324072 # Request fanout histogram
2349system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2350system.cpu1.toL2Bus.snoop_fanout::0 15395152 88.08% 88.08% # Request fanout histogram
2351system.cpu1.toL2Bus.snoop_fanout::1 2083313 11.92% 100.00% # Request fanout histogram
2352system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram
2353system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2354system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2355system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2356system.cpu1.toL2Bus.snoop_fanout::total 17478652 # Request fanout histogram
2357system.cpu1.toL2Bus.reqLayer0.occupancy 21924818496 # Layer occupancy (ticks)
2358system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2359system.cpu1.toL2Bus.snoopLayer0.occupancy 193282156 # Layer occupancy (ticks)
2360system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2361system.cpu1.toL2Bus.respLayer0.occupancy 8053682000 # Layer occupancy (ticks)
2362system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2363system.cpu1.toL2Bus.respLayer1.occupancy 7892863413 # Layer occupancy (ticks)
2364system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2365system.cpu1.toL2Bus.respLayer2.occupancy 191039000 # Layer occupancy (ticks)
2366system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2367system.cpu1.toL2Bus.respLayer3.occupancy 314553499 # Layer occupancy (ticks)
2368system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2369system.iobus.trans_dist::ReadReq 40370 # Transaction distribution
2370system.iobus.trans_dist::ReadResp 40370 # Transaction distribution
2371system.iobus.trans_dist::WriteReq 136628 # Transaction distribution
2372system.iobus.trans_dist::WriteResp 136628 # Transaction distribution
2373system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
2374system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2375system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2376system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2377system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2378system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2379system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2380system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2381system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2382system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2383system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2384system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2385system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2386system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes)
2387system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231252 # Packet count per connected master and slave (bytes)
2388system.iobus.pkt_count_system.realview.ide.dma::total 231252 # Packet count per connected master and slave (bytes)
2389system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2390system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2391system.iobus.pkt_count::total 353996 # Packet count per connected master and slave (bytes)
2392system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes)
2393system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2394system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2395system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2396system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2397system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2398system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2399system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2400system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2401system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2402system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2403system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2404system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2405system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes)
2406system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339024 # Cumulative packet size per connected master and slave (bytes)
2407system.iobus.pkt_size_system.realview.ide.dma::total 7339024 # Cumulative packet size per connected master and slave (bytes)
2408system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2409system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2410system.iobus.pkt_size::total 7496904 # Cumulative packet size per connected master and slave (bytes)
2411system.iobus.reqLayer0.occupancy 37005501 # Layer occupancy (ticks)
2412system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2413system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
2414system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2415system.iobus.reqLayer2.occupancy 324001 # Layer occupancy (ticks)
2416system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2417system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
2418system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2419system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
2420system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2421system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2422system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2423system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2424system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2425system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2426system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2427system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2428system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2429system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
2430system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2431system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2432system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2433system.iobus.reqLayer23.occupancy 26468500 # Layer occupancy (ticks)
2434system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2435system.iobus.reqLayer24.occupancy 37415000 # Layer occupancy (ticks)
2436system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2437system.iobus.reqLayer25.occupancy 567277400 # Layer occupancy (ticks)
2438system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2439system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks)
2440system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2441system.iobus.respLayer3.occupancy 147948000 # Layer occupancy (ticks)
2442system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2443system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2444system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2445system.iocache.tags.replacements 115622 # number of replacements
2446system.iocache.tags.tagsinuse 11.298154 # Cycle average of tags in use
2447system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2448system.iocache.tags.sampled_refs 115638 # Sample count of references to valid blocks.
2449system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2450system.iocache.tags.warmup_cycle 9192209246000 # Cycle when the warmup percentage was hit.
2451system.iocache.tags.occ_blocks::realview.ethernet 7.385038 # Average occupied blocks per requestor
2452system.iocache.tags.occ_blocks::realview.ide 3.913116 # Average occupied blocks per requestor
2453system.iocache.tags.occ_percent::realview.ethernet 0.461565 # Average percentage of cache occupancy
2454system.iocache.tags.occ_percent::realview.ide 0.244570 # Average percentage of cache occupancy
2455system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy
2456system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2457system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2458system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2459system.iocache.tags.tag_accesses 1040991 # Number of tag accesses
2460system.iocache.tags.data_accesses 1040991 # Number of data accesses
2461system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2462system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses
2463system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses
2464system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2465system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2466system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2467system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2468system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2469system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses
2470system.iocache.demand_misses::total 8938 # number of demand (read+write) misses
2471system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2472system.iocache.overall_misses::realview.ide 8898 # number of overall misses
2473system.iocache.overall_misses::total 8938 # number of overall misses
2474system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles
2475system.iocache.ReadReq_miss_latency::realview.ide 1672896003 # number of ReadReq miss cycles
2476system.iocache.ReadReq_miss_latency::total 1678095503 # number of ReadReq miss cycles
2477system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2478system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2479system.iocache.WriteLineReq_miss_latency::realview.ide 13552714897 # number of WriteLineReq miss cycles
2480system.iocache.WriteLineReq_miss_latency::total 13552714897 # number of WriteLineReq miss cycles
2481system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles
2482system.iocache.demand_miss_latency::realview.ide 1672896003 # number of demand (read+write) miss cycles
2483system.iocache.demand_miss_latency::total 1678464503 # number of demand (read+write) miss cycles
2484system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles
2485system.iocache.overall_miss_latency::realview.ide 1672896003 # number of overall miss cycles
2486system.iocache.overall_miss_latency::total 1678464503 # number of overall miss cycles
2487system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2488system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses)
2489system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses)
2490system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2491system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2492system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2493system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2494system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2495system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses
2496system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses
2497system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2498system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses
2499system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses
2500system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2501system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2502system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2503system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2504system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2505system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2506system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2507system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2508system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2509system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2510system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2511system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2512system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2513system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency
2514system.iocache.ReadReq_avg_miss_latency::realview.ide 188008.092043 # average ReadReq miss latency
2515system.iocache.ReadReq_avg_miss_latency::total 187811.472076 # average ReadReq miss latency
2516system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2517system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2518system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126983.686540 # average WriteLineReq miss latency
2519system.iocache.WriteLineReq_avg_miss_latency::total 126983.686540 # average WriteLineReq miss latency
2520system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
2521system.iocache.demand_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency
2522system.iocache.demand_avg_miss_latency::total 187789.718393 # average overall miss latency
2523system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency
2524system.iocache.overall_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency
2525system.iocache.overall_avg_miss_latency::total 187789.718393 # average overall miss latency
2526system.iocache.blocked_cycles::no_mshrs 33965 # number of cycles access was blocked
2527system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2528system.iocache.blocked::no_mshrs 3500 # number of cycles access was blocked
2529system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2530system.iocache.avg_blocked_cycles::no_mshrs 9.704286 # average number of cycles each access was blocked
2531system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2532system.iocache.fast_writes 0 # number of fast writes performed
2533system.iocache.cache_copies 0 # number of cache copies performed
2534system.iocache.writebacks::writebacks 106694 # number of writebacks
2535system.iocache.writebacks::total 106694 # number of writebacks
2536system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2537system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses
2538system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses
2539system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2540system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2541system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2542system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2543system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2544system.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses
2545system.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses
2546system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2547system.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses
2548system.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses
2549system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles
2550system.iocache.ReadReq_mshr_miss_latency::realview.ide 1227996003 # number of ReadReq MSHR miss cycles
2551system.iocache.ReadReq_mshr_miss_latency::total 1231345503 # number of ReadReq MSHR miss cycles
2552system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2553system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2554system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8209903918 # number of WriteLineReq MSHR miss cycles
2555system.iocache.WriteLineReq_mshr_miss_latency::total 8209903918 # number of WriteLineReq MSHR miss cycles
2556system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles
2557system.iocache.demand_mshr_miss_latency::realview.ide 1227996003 # number of demand (read+write) MSHR miss cycles
2558system.iocache.demand_mshr_miss_latency::total 1231564503 # number of demand (read+write) MSHR miss cycles
2559system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles
2560system.iocache.overall_mshr_miss_latency::realview.ide 1227996003 # number of overall MSHR miss cycles
2561system.iocache.overall_mshr_miss_latency::total 1231564503 # number of overall MSHR miss cycles
2562system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2563system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2564system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2565system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2566system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2567system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2568system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2569system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2570system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2571system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2572system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2573system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2574system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2575system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency
2576system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138008.092043 # average ReadReq mshr miss latency
2577system.iocache.ReadReq_avg_mshr_miss_latency::total 137811.472076 # average ReadReq mshr miss latency
2578system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2579system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2580system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76923.618151 # average WriteLineReq mshr miss latency
2581system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76923.618151 # average WriteLineReq mshr miss latency
2582system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
2583system.iocache.demand_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency
2584system.iocache.demand_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency
2585system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency
2586system.iocache.overall_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency
2587system.iocache.overall_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency
2588system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2589system.l2c.tags.replacements 1521682 # number of replacements
2590system.l2c.tags.tagsinuse 63275.480852 # Cycle average of tags in use
2591system.l2c.tags.total_refs 5639856 # Total number of references to valid blocks.
2592system.l2c.tags.sampled_refs 1580939 # Sample count of references to valid blocks.
2593system.l2c.tags.avg_refs 3.567409 # Average number of references to valid blocks.
2594system.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit.
2595system.l2c.tags.occ_blocks::writebacks 23300.510768 # Average occupied blocks per requestor
2596system.l2c.tags.occ_blocks::cpu0.dtb.walker 120.316787 # Average occupied blocks per requestor
2597system.l2c.tags.occ_blocks::cpu0.itb.walker 198.572474 # Average occupied blocks per requestor
2598system.l2c.tags.occ_blocks::cpu0.inst 3006.389178 # Average occupied blocks per requestor
2599system.l2c.tags.occ_blocks::cpu0.data 5620.523219 # Average occupied blocks per requestor
2600system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9896.072880 # Average occupied blocks per requestor
2601system.l2c.tags.occ_blocks::cpu1.dtb.walker 161.524171 # Average occupied blocks per requestor
2602system.l2c.tags.occ_blocks::cpu1.itb.walker 257.856403 # Average occupied blocks per requestor
2603system.l2c.tags.occ_blocks::cpu1.inst 3567.908148 # Average occupied blocks per requestor
2604system.l2c.tags.occ_blocks::cpu1.data 7366.209685 # Average occupied blocks per requestor
2605system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9779.597138 # Average occupied blocks per requestor
2606system.l2c.tags.occ_percent::writebacks 0.355538 # Average percentage of cache occupancy
2607system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001836 # Average percentage of cache occupancy
2608system.l2c.tags.occ_percent::cpu0.itb.walker 0.003030 # Average percentage of cache occupancy
2609system.l2c.tags.occ_percent::cpu0.inst 0.045874 # Average percentage of cache occupancy
2610system.l2c.tags.occ_percent::cpu0.data 0.085762 # Average percentage of cache occupancy
2611system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.151002 # Average percentage of cache occupancy
2612system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002465 # Average percentage of cache occupancy
2613system.l2c.tags.occ_percent::cpu1.itb.walker 0.003935 # Average percentage of cache occupancy
2614system.l2c.tags.occ_percent::cpu1.inst 0.054442 # Average percentage of cache occupancy
2615system.l2c.tags.occ_percent::cpu1.data 0.112399 # Average percentage of cache occupancy
2616system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.149225 # Average percentage of cache occupancy
2617system.l2c.tags.occ_percent::total 0.965507 # Average percentage of cache occupancy
2618system.l2c.tags.occ_task_id_blocks::1022 10707 # Occupied blocks per task id
2619system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id
2620system.l2c.tags.occ_task_id_blocks::1024 48305 # Occupied blocks per task id
2621system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id
2622system.l2c.tags.age_task_id_blocks_1022::3 740 # Occupied blocks per task id
2623system.l2c.tags.age_task_id_blocks_1022::4 9837 # Occupied blocks per task id
2624system.l2c.tags.age_task_id_blocks_1023::4 245 # Occupied blocks per task id
2625system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
2626system.l2c.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
2627system.l2c.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id
2628system.l2c.tags.age_task_id_blocks_1024::3 5150 # Occupied blocks per task id
2629system.l2c.tags.age_task_id_blocks_1024::4 41466 # Occupied blocks per task id
2630system.l2c.tags.occ_task_id_percent::1022 0.163376 # Percentage of cache occupancy per task id
2631system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id
2632system.l2c.tags.occ_task_id_percent::1024 0.737076 # Percentage of cache occupancy per task id
2633system.l2c.tags.tag_accesses 74056413 # Number of tag accesses
2634system.l2c.tags.data_accesses 74056413 # Number of data accesses
2635system.l2c.WritebackDirty_hits::writebacks 2788899 # number of WritebackDirty hits
2636system.l2c.WritebackDirty_hits::total 2788899 # number of WritebackDirty hits
2637system.l2c.UpgradeReq_hits::cpu0.data 164206 # number of UpgradeReq hits
2638system.l2c.UpgradeReq_hits::cpu1.data 131282 # number of UpgradeReq hits
2639system.l2c.UpgradeReq_hits::total 295488 # number of UpgradeReq hits
2640system.l2c.SCUpgradeReq_hits::cpu0.data 38310 # number of SCUpgradeReq hits
2641system.l2c.SCUpgradeReq_hits::cpu1.data 41053 # number of SCUpgradeReq hits
2642system.l2c.SCUpgradeReq_hits::total 79363 # number of SCUpgradeReq hits
2643system.l2c.ReadExReq_hits::cpu0.data 46553 # number of ReadExReq hits
2644system.l2c.ReadExReq_hits::cpu1.data 57229 # number of ReadExReq hits
2645system.l2c.ReadExReq_hits::total 103782 # number of ReadExReq hits
2646system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5034 # number of ReadSharedReq hits
2647system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3536 # number of ReadSharedReq hits
2648system.l2c.ReadSharedReq_hits::cpu0.inst 418413 # number of ReadSharedReq hits
2649system.l2c.ReadSharedReq_hits::cpu0.data 580330 # number of ReadSharedReq hits
2650system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 274635 # number of ReadSharedReq hits
2651system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits
2652system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4587 # number of ReadSharedReq hits
2653system.l2c.ReadSharedReq_hits::cpu1.inst 421326 # number of ReadSharedReq hits
2654system.l2c.ReadSharedReq_hits::cpu1.data 539744 # number of ReadSharedReq hits
2655system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292866 # number of ReadSharedReq hits
2656system.l2c.ReadSharedReq_hits::total 2546044 # number of ReadSharedReq hits
2657system.l2c.InvalidateReq_hits::cpu0.data 113687 # number of InvalidateReq hits
2658system.l2c.InvalidateReq_hits::cpu1.data 125274 # number of InvalidateReq hits
2659system.l2c.InvalidateReq_hits::total 238961 # number of InvalidateReq hits
2660system.l2c.demand_hits::cpu0.dtb.walker 5034 # number of demand (read+write) hits
2661system.l2c.demand_hits::cpu0.itb.walker 3536 # number of demand (read+write) hits
2662system.l2c.demand_hits::cpu0.inst 418413 # number of demand (read+write) hits
2663system.l2c.demand_hits::cpu0.data 626883 # number of demand (read+write) hits
2664system.l2c.demand_hits::cpu0.l2cache.prefetcher 274635 # number of demand (read+write) hits
2665system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits
2666system.l2c.demand_hits::cpu1.itb.walker 4587 # number of demand (read+write) hits
2667system.l2c.demand_hits::cpu1.inst 421326 # number of demand (read+write) hits
2668system.l2c.demand_hits::cpu1.data 596973 # number of demand (read+write) hits
2669system.l2c.demand_hits::cpu1.l2cache.prefetcher 292866 # number of demand (read+write) hits
2670system.l2c.demand_hits::total 2649826 # number of demand (read+write) hits
2671system.l2c.overall_hits::cpu0.dtb.walker 5034 # number of overall hits
2672system.l2c.overall_hits::cpu0.itb.walker 3536 # number of overall hits
2673system.l2c.overall_hits::cpu0.inst 418413 # number of overall hits
2674system.l2c.overall_hits::cpu0.data 626883 # number of overall hits
2675system.l2c.overall_hits::cpu0.l2cache.prefetcher 274635 # number of overall hits
2676system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits
2677system.l2c.overall_hits::cpu1.itb.walker 4587 # number of overall hits
2678system.l2c.overall_hits::cpu1.inst 421326 # number of overall hits
2679system.l2c.overall_hits::cpu1.data 596973 # number of overall hits
2680system.l2c.overall_hits::cpu1.l2cache.prefetcher 292866 # number of overall hits
2681system.l2c.overall_hits::total 2649826 # number of overall hits
2682system.l2c.UpgradeReq_misses::cpu0.data 62081 # number of UpgradeReq misses
2683system.l2c.UpgradeReq_misses::cpu1.data 62914 # number of UpgradeReq misses
2684system.l2c.UpgradeReq_misses::total 124995 # number of UpgradeReq misses
2685system.l2c.SCUpgradeReq_misses::cpu0.data 13155 # number of SCUpgradeReq misses
2686system.l2c.SCUpgradeReq_misses::cpu1.data 14316 # number of SCUpgradeReq misses
2687system.l2c.SCUpgradeReq_misses::total 27471 # number of SCUpgradeReq misses
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2718system.l2c.overall_misses::cpu0.inst 49096 # number of overall misses
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2721system.l2c.overall_misses::cpu1.dtb.walker 3412 # number of overall misses
2722system.l2c.overall_misses::cpu1.itb.walker 3601 # number of overall misses
2723system.l2c.overall_misses::cpu1.inst 47112 # number of overall misses
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2726system.l2c.overall_misses::total 1029777 # number of overall misses
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2746system.l2c.ReadSharedReq_miss_latency::total 138631838238 # number of ReadSharedReq miss cycles
2747system.l2c.InvalidateReq_miss_latency::cpu0.data 137833000 # number of InvalidateReq miss cycles
2748system.l2c.InvalidateReq_miss_latency::cpu1.data 159862500 # number of InvalidateReq miss cycles
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2760system.l2c.demand_miss_latency::total 158498671237 # number of demand (read+write) miss cycles
2761system.l2c.overall_miss_latency::cpu0.dtb.walker 212874000 # number of overall miss cycles
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2771system.l2c.overall_miss_latency::total 158498671237 # number of overall miss cycles
2772system.l2c.WritebackDirty_accesses::writebacks 2788899 # number of WritebackDirty accesses(hits+misses)
2773system.l2c.WritebackDirty_accesses::total 2788899 # number of WritebackDirty accesses(hits+misses)
2774system.l2c.UpgradeReq_accesses::cpu0.data 226287 # number of UpgradeReq accesses(hits+misses)
2775system.l2c.UpgradeReq_accesses::cpu1.data 194196 # number of UpgradeReq accesses(hits+misses)
2776system.l2c.UpgradeReq_accesses::total 420483 # number of UpgradeReq accesses(hits+misses)
2777system.l2c.SCUpgradeReq_accesses::cpu0.data 51465 # number of SCUpgradeReq accesses(hits+misses)
2778system.l2c.SCUpgradeReq_accesses::cpu1.data 55369 # number of SCUpgradeReq accesses(hits+misses)
2779system.l2c.SCUpgradeReq_accesses::total 106834 # number of SCUpgradeReq accesses(hits+misses)
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2781system.l2c.ReadExReq_accesses::cpu1.data 117730 # number of ReadExReq accesses(hits+misses)
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2788system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8985 # number of ReadSharedReq accesses(hits+misses)
2789system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8188 # number of ReadSharedReq accesses(hits+misses)
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2793system.l2c.ReadSharedReq_accesses::total 3429923 # number of ReadSharedReq accesses(hits+misses)
2794system.l2c.InvalidateReq_accesses::cpu0.data 584862 # number of InvalidateReq accesses(hits+misses)
2795system.l2c.InvalidateReq_accesses::cpu1.data 243078 # number of InvalidateReq accesses(hits+misses)
2796system.l2c.InvalidateReq_accesses::total 827940 # number of InvalidateReq accesses(hits+misses)
2797system.l2c.demand_accesses::cpu0.dtb.walker 6531 # number of demand (read+write) accesses
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2806system.l2c.demand_accesses::cpu1.l2cache.prefetcher 496732 # number of demand (read+write) accesses
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2808system.l2c.overall_accesses::cpu0.dtb.walker 6531 # number of overall (read+write) accesses
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2814system.l2c.overall_accesses::cpu1.itb.walker 8188 # number of overall (read+write) accesses
2815system.l2c.overall_accesses::cpu1.inst 468438 # number of overall (read+write) accesses
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2818system.l2c.overall_accesses::total 3679603 # number of overall (read+write) accesses
2819system.l2c.UpgradeReq_miss_rate::cpu0.data 0.274346 # miss rate for UpgradeReq accesses
2820system.l2c.UpgradeReq_miss_rate::cpu1.data 0.323972 # miss rate for UpgradeReq accesses
2821system.l2c.UpgradeReq_miss_rate::total 0.297265 # miss rate for UpgradeReq accesses
2822system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.255611 # miss rate for SCUpgradeReq accesses
2823system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.258556 # miss rate for SCUpgradeReq accesses
2824system.l2c.SCUpgradeReq_miss_rate::total 0.257137 # miss rate for SCUpgradeReq accesses
2825system.l2c.ReadExReq_miss_rate::cpu0.data 0.647192 # miss rate for ReadExReq accesses
2826system.l2c.ReadExReq_miss_rate::cpu1.data 0.513896 # miss rate for ReadExReq accesses
2827system.l2c.ReadExReq_miss_rate::total 0.584340 # miss rate for ReadExReq accesses
2828system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.229215 # miss rate for ReadSharedReq accesses
2829system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.267302 # miss rate for ReadSharedReq accesses
2830system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.105016 # miss rate for ReadSharedReq accesses
2831system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194782 # miss rate for ReadSharedReq accesses
2832system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.516511 # miss rate for ReadSharedReq accesses
2833system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.379744 # miss rate for ReadSharedReq accesses
2834system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.439790 # miss rate for ReadSharedReq accesses
2835system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.100573 # miss rate for ReadSharedReq accesses
2836system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.206230 # miss rate for ReadSharedReq accesses
2837system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.410414 # miss rate for ReadSharedReq accesses
2838system.l2c.ReadSharedReq_miss_rate::total 0.257696 # miss rate for ReadSharedReq accesses
2839system.l2c.InvalidateReq_miss_rate::cpu0.data 0.805617 # miss rate for InvalidateReq accesses
2840system.l2c.InvalidateReq_miss_rate::cpu1.data 0.484635 # miss rate for InvalidateReq accesses
2841system.l2c.InvalidateReq_miss_rate::total 0.711379 # miss rate for InvalidateReq accesses
2842system.l2c.demand_miss_rate::cpu0.dtb.walker 0.229215 # miss rate for demand accesses
2843system.l2c.demand_miss_rate::cpu0.itb.walker 0.267302 # miss rate for demand accesses
2844system.l2c.demand_miss_rate::cpu0.inst 0.105016 # miss rate for demand accesses
2845system.l2c.demand_miss_rate::cpu0.data 0.264793 # miss rate for demand accesses
2846system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.516511 # miss rate for demand accesses
2847system.l2c.demand_miss_rate::cpu1.dtb.walker 0.379744 # miss rate for demand accesses
2848system.l2c.demand_miss_rate::cpu1.itb.walker 0.439790 # miss rate for demand accesses
2849system.l2c.demand_miss_rate::cpu1.inst 0.100573 # miss rate for demand accesses
2850system.l2c.demand_miss_rate::cpu1.data 0.251637 # miss rate for demand accesses
2851system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.410414 # miss rate for demand accesses
2852system.l2c.demand_miss_rate::total 0.279861 # miss rate for demand accesses
2853system.l2c.overall_miss_rate::cpu0.dtb.walker 0.229215 # miss rate for overall accesses
2854system.l2c.overall_miss_rate::cpu0.itb.walker 0.267302 # miss rate for overall accesses
2855system.l2c.overall_miss_rate::cpu0.inst 0.105016 # miss rate for overall accesses
2856system.l2c.overall_miss_rate::cpu0.data 0.264793 # miss rate for overall accesses
2857system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.516511 # miss rate for overall accesses
2858system.l2c.overall_miss_rate::cpu1.dtb.walker 0.379744 # miss rate for overall accesses
2859system.l2c.overall_miss_rate::cpu1.itb.walker 0.439790 # miss rate for overall accesses
2860system.l2c.overall_miss_rate::cpu1.inst 0.100573 # miss rate for overall accesses
2861system.l2c.overall_miss_rate::cpu1.data 0.251637 # miss rate for overall accesses
2862system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.410414 # miss rate for overall accesses
2863system.l2c.overall_miss_rate::total 0.279861 # miss rate for overall accesses
2864system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15955.388927 # average UpgradeReq miss latency
2865system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16235.305337 # average UpgradeReq miss latency
2866system.l2c.UpgradeReq_avg_miss_latency::total 16096.279851 # average UpgradeReq miss latency
2867system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15253.857849 # average SCUpgradeReq miss latency
2868system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15864.696843 # average SCUpgradeReq miss latency
2869system.l2c.SCUpgradeReq_avg_miss_latency::total 15572.185213 # average SCUpgradeReq miss latency
2870system.l2c.ReadExReq_avg_miss_latency::cpu0.data 137631.960127 # average ReadExReq miss latency
2871system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134104.832978 # average ReadExReq miss latency
2872system.l2c.ReadExReq_avg_miss_latency::total 136169.330621 # average ReadExReq miss latency
2873system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142200.400802 # average ReadSharedReq miss latency
2874system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141885.271318 # average ReadSharedReq miss latency
2875system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 135691.604204 # average ReadSharedReq miss latency
2876system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139482.501318 # average ReadSharedReq miss latency
2877system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860 # average ReadSharedReq miss latency
2878system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140771.981243 # average ReadSharedReq miss latency
2879system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140975.284643 # average ReadSharedReq miss latency
2880system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135624.840805 # average ReadSharedReq miss latency
2881system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141053.846867 # average ReadSharedReq miss latency
2882system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123 # average ReadSharedReq miss latency
2883system.l2c.ReadSharedReq_avg_miss_latency::total 156844.815001 # average ReadSharedReq miss latency
2884system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 292.530376 # average InvalidateReq miss latency
2885system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1357.020984 # average InvalidateReq miss latency
2886system.l2c.InvalidateReq_avg_miss_latency::total 505.443318 # average InvalidateReq miss latency
2887system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142200.400802 # average overall miss latency
2888system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141885.271318 # average overall miss latency
2889system.l2c.demand_avg_miss_latency::cpu0.inst 135691.604204 # average overall miss latency
2890system.l2c.demand_avg_miss_latency::cpu0.data 138782.566133 # average overall miss latency
2891system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860 # average overall miss latency
2892system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140771.981243 # average overall miss latency
2893system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140975.284643 # average overall miss latency
2894system.l2c.demand_avg_miss_latency::cpu1.inst 135624.840805 # average overall miss latency
2895system.l2c.demand_avg_miss_latency::cpu1.data 138959.401092 # average overall miss latency
2896system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123 # average overall miss latency
2897system.l2c.demand_avg_miss_latency::total 153915.528544 # average overall miss latency
2898system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142200.400802 # average overall miss latency
2899system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141885.271318 # average overall miss latency
2900system.l2c.overall_avg_miss_latency::cpu0.inst 135691.604204 # average overall miss latency
2901system.l2c.overall_avg_miss_latency::cpu0.data 138782.566133 # average overall miss latency
2902system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172829.231860 # average overall miss latency
2903system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140771.981243 # average overall miss latency
2904system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140975.284643 # average overall miss latency
2905system.l2c.overall_avg_miss_latency::cpu1.inst 135624.840805 # average overall miss latency
2906system.l2c.overall_avg_miss_latency::cpu1.data 138959.401092 # average overall miss latency
2907system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167408.127123 # average overall miss latency
2908system.l2c.overall_avg_miss_latency::total 153915.528544 # average overall miss latency
2909system.l2c.blocked_cycles::no_mshrs 442 # number of cycles access was blocked
2910system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2911system.l2c.blocked::no_mshrs 7 # number of cycles access was blocked
2912system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2913system.l2c.avg_blocked_cycles::no_mshrs 63.142857 # average number of cycles each access was blocked
2914system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2915system.l2c.fast_writes 0 # number of fast writes performed
2916system.l2c.cache_copies 0 # number of cache copies performed
2917system.l2c.writebacks::writebacks 1210545 # number of writebacks
2918system.l2c.writebacks::total 1210545 # number of writebacks
2919system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 196 # number of ReadSharedReq MSHR hits
2920system.l2c.ReadSharedReq_mshr_hits::cpu0.data 72 # number of ReadSharedReq MSHR hits
2921system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 242 # number of ReadSharedReq MSHR hits
2922system.l2c.ReadSharedReq_mshr_hits::cpu1.data 69 # number of ReadSharedReq MSHR hits
2923system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 10 # number of ReadSharedReq MSHR hits
2924system.l2c.ReadSharedReq_mshr_hits::total 589 # number of ReadSharedReq MSHR hits
2925system.l2c.demand_mshr_hits::cpu0.inst 196 # number of demand (read+write) MSHR hits
2926system.l2c.demand_mshr_hits::cpu0.data 72 # number of demand (read+write) MSHR hits
2927system.l2c.demand_mshr_hits::cpu1.inst 242 # number of demand (read+write) MSHR hits
2928system.l2c.demand_mshr_hits::cpu1.data 69 # number of demand (read+write) MSHR hits
2929system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 10 # number of demand (read+write) MSHR hits
2930system.l2c.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits
2931system.l2c.overall_mshr_hits::cpu0.inst 196 # number of overall MSHR hits
2932system.l2c.overall_mshr_hits::cpu0.data 72 # number of overall MSHR hits
2933system.l2c.overall_mshr_hits::cpu1.inst 242 # number of overall MSHR hits
2934system.l2c.overall_mshr_hits::cpu1.data 69 # number of overall MSHR hits
2935system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 10 # number of overall MSHR hits
2936system.l2c.overall_mshr_hits::total 589 # number of overall MSHR hits
2937system.l2c.CleanEvict_mshr_misses::writebacks 56231 # number of CleanEvict MSHR misses
2938system.l2c.CleanEvict_mshr_misses::total 56231 # number of CleanEvict MSHR misses
2939system.l2c.UpgradeReq_mshr_misses::cpu0.data 62081 # number of UpgradeReq MSHR misses
2940system.l2c.UpgradeReq_mshr_misses::cpu1.data 62914 # number of UpgradeReq MSHR misses
2941system.l2c.UpgradeReq_mshr_misses::total 124995 # number of UpgradeReq MSHR misses
2942system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13155 # number of SCUpgradeReq MSHR misses
2943system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 14316 # number of SCUpgradeReq MSHR misses
2944system.l2c.SCUpgradeReq_mshr_misses::total 27471 # number of SCUpgradeReq MSHR misses
2945system.l2c.ReadExReq_mshr_misses::cpu0.data 85397 # number of ReadExReq MSHR misses
2946system.l2c.ReadExReq_mshr_misses::cpu1.data 60501 # number of ReadExReq MSHR misses
2947system.l2c.ReadExReq_mshr_misses::total 145898 # number of ReadExReq MSHR misses
2948system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1497 # number of ReadSharedReq MSHR misses
2949system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1290 # number of ReadSharedReq MSHR misses
2950system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48900 # number of ReadSharedReq MSHR misses
2951system.l2c.ReadSharedReq_mshr_misses::cpu0.data 140310 # number of ReadSharedReq MSHR misses
2952system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 293392 # number of ReadSharedReq MSHR misses
2953system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3412 # number of ReadSharedReq MSHR misses
2954system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 3601 # number of ReadSharedReq MSHR misses
2955system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46870 # number of ReadSharedReq MSHR misses
2956system.l2c.ReadSharedReq_mshr_misses::cpu1.data 140162 # number of ReadSharedReq MSHR misses
2957system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 203856 # number of ReadSharedReq MSHR misses
2958system.l2c.ReadSharedReq_mshr_misses::total 883290 # number of ReadSharedReq MSHR misses
2959system.l2c.InvalidateReq_mshr_misses::cpu0.data 471175 # number of InvalidateReq MSHR misses
2960system.l2c.InvalidateReq_mshr_misses::cpu1.data 117804 # number of InvalidateReq MSHR misses
2961system.l2c.InvalidateReq_mshr_misses::total 588979 # number of InvalidateReq MSHR misses
2962system.l2c.demand_mshr_misses::cpu0.dtb.walker 1497 # number of demand (read+write) MSHR misses
2963system.l2c.demand_mshr_misses::cpu0.itb.walker 1290 # number of demand (read+write) MSHR misses
2964system.l2c.demand_mshr_misses::cpu0.inst 48900 # number of demand (read+write) MSHR misses
2965system.l2c.demand_mshr_misses::cpu0.data 225707 # number of demand (read+write) MSHR misses
2966system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 293392 # number of demand (read+write) MSHR misses
2967system.l2c.demand_mshr_misses::cpu1.dtb.walker 3412 # number of demand (read+write) MSHR misses
2968system.l2c.demand_mshr_misses::cpu1.itb.walker 3601 # number of demand (read+write) MSHR misses
2969system.l2c.demand_mshr_misses::cpu1.inst 46870 # number of demand (read+write) MSHR misses
2970system.l2c.demand_mshr_misses::cpu1.data 200663 # number of demand (read+write) MSHR misses
2971system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 203856 # number of demand (read+write) MSHR misses
2972system.l2c.demand_mshr_misses::total 1029188 # number of demand (read+write) MSHR misses
2973system.l2c.overall_mshr_misses::cpu0.dtb.walker 1497 # number of overall MSHR misses
2974system.l2c.overall_mshr_misses::cpu0.itb.walker 1290 # number of overall MSHR misses
2975system.l2c.overall_mshr_misses::cpu0.inst 48900 # number of overall MSHR misses
2976system.l2c.overall_mshr_misses::cpu0.data 225707 # number of overall MSHR misses
2977system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 293392 # number of overall MSHR misses
2978system.l2c.overall_mshr_misses::cpu1.dtb.walker 3412 # number of overall MSHR misses
2979system.l2c.overall_mshr_misses::cpu1.itb.walker 3601 # number of overall MSHR misses
2980system.l2c.overall_mshr_misses::cpu1.inst 46870 # number of overall MSHR misses
2981system.l2c.overall_mshr_misses::cpu1.data 200663 # number of overall MSHR misses
2982system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 203856 # number of overall MSHR misses
2983system.l2c.overall_mshr_misses::total 1029188 # number of overall MSHR misses
2984system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
2985system.l2c.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable
2986system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2987system.l2c.ReadReq_mshr_uncacheable::cpu1.data 10147 # number of ReadReq MSHR uncacheable
2988system.l2c.ReadReq_mshr_uncacheable::total 81896 # number of ReadReq MSHR uncacheable
2989system.l2c.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable
2990system.l2c.WriteReq_mshr_uncacheable::cpu1.data 10618 # number of WriteReq MSHR uncacheable
2991system.l2c.WriteReq_mshr_uncacheable::total 38489 # number of WriteReq MSHR uncacheable
2992system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
2993system.l2c.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses
2994system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2995system.l2c.overall_mshr_uncacheable_misses::cpu1.data 20765 # number of overall MSHR uncacheable misses
2996system.l2c.overall_mshr_uncacheable_misses::total 120385 # number of overall MSHR uncacheable misses
2997system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4385750000 # number of UpgradeReq MSHR miss cycles
2998system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4455748500 # number of UpgradeReq MSHR miss cycles
2999system.l2c.UpgradeReq_mshr_miss_latency::total 8841498500 # number of UpgradeReq MSHR miss cycles
3000system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 969977000 # number of SCUpgradeReq MSHR miss cycles
3001system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1055544500 # number of SCUpgradeReq MSHR miss cycles
3002system.l2c.SCUpgradeReq_mshr_miss_latency::total 2025521500 # number of SCUpgradeReq MSHR miss cycles
3003system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10899069105 # number of ReadExReq MSHR miss cycles
3004system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7507982381 # number of ReadExReq MSHR miss cycles
3005system.l2c.ReadExReq_mshr_miss_latency::total 18407051486 # number of ReadExReq MSHR miss cycles
3006system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 197889529 # number of ReadSharedReq MSHR miss cycles
3007system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 170123517 # number of ReadSharedReq MSHR miss cycles
3008system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6149223860 # number of ReadSharedReq MSHR miss cycles
3009system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 18166902374 # number of ReadSharedReq MSHR miss cycles
3010system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47770195366 # number of ReadSharedReq MSHR miss cycles
3011system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 446163561 # number of ReadSharedReq MSHR miss cycles
3012system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 471618547 # number of ReadSharedReq MSHR miss cycles
3013system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5891103441 # number of ReadSharedReq MSHR miss cycles
3014system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 18366630812 # number of ReadSharedReq MSHR miss cycles
3015system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32086715450 # number of ReadSharedReq MSHR miss cycles
3016system.l2c.ReadSharedReq_mshr_miss_latency::total 129716566457 # number of ReadSharedReq MSHR miss cycles
3017system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 32475619499 # number of InvalidateReq MSHR miss cycles
3018system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 8166236998 # number of InvalidateReq MSHR miss cycles
3019system.l2c.InvalidateReq_mshr_miss_latency::total 40641856497 # number of InvalidateReq MSHR miss cycles
3020system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 197889529 # number of demand (read+write) MSHR miss cycles
3021system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 170123517 # number of demand (read+write) MSHR miss cycles
3022system.l2c.demand_mshr_miss_latency::cpu0.inst 6149223860 # number of demand (read+write) MSHR miss cycles
3023system.l2c.demand_mshr_miss_latency::cpu0.data 29065971479 # number of demand (read+write) MSHR miss cycles
3024system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 47770195366 # number of demand (read+write) MSHR miss cycles
3025system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 446163561 # number of demand (read+write) MSHR miss cycles
3026system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 471618547 # number of demand (read+write) MSHR miss cycles
3027system.l2c.demand_mshr_miss_latency::cpu1.inst 5891103441 # number of demand (read+write) MSHR miss cycles
3028system.l2c.demand_mshr_miss_latency::cpu1.data 25874613193 # number of demand (read+write) MSHR miss cycles
3029system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 32086715450 # number of demand (read+write) MSHR miss cycles
3030system.l2c.demand_mshr_miss_latency::total 148123617943 # number of demand (read+write) MSHR miss cycles
3031system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 197889529 # number of overall MSHR miss cycles
3032system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 170123517 # number of overall MSHR miss cycles
3033system.l2c.overall_mshr_miss_latency::cpu0.inst 6149223860 # number of overall MSHR miss cycles
3034system.l2c.overall_mshr_miss_latency::cpu0.data 29065971479 # number of overall MSHR miss cycles
3035system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47770195366 # number of overall MSHR miss cycles
3036system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 446163561 # number of overall MSHR miss cycles
3037system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 471618547 # number of overall MSHR miss cycles
3038system.l2c.overall_mshr_miss_latency::cpu1.inst 5891103441 # number of overall MSHR miss cycles
3039system.l2c.overall_mshr_miss_latency::cpu1.data 25874613193 # number of overall MSHR miss cycles
3040system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32086715450 # number of overall MSHR miss cycles
3041system.l2c.overall_mshr_miss_latency::total 148123617943 # number of overall MSHR miss cycles
3042system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles
3043system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4538545031 # number of ReadReq MSHR uncacheable cycles
3044system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11957000 # number of ReadReq MSHR uncacheable cycles
3045system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1387996535 # number of ReadReq MSHR uncacheable cycles
3046system.l2c.ReadReq_mshr_uncacheable_latency::total 10793019566 # number of ReadReq MSHR uncacheable cycles
3047system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4403248038 # number of WriteReq MSHR uncacheable cycles
3048system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1559838113 # number of WriteReq MSHR uncacheable cycles
3049system.l2c.WriteReq_mshr_uncacheable_latency::total 5963086151 # number of WriteReq MSHR uncacheable cycles
3050system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles
3051system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8941793069 # number of overall MSHR uncacheable cycles
3052system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11957000 # number of overall MSHR uncacheable cycles
3053system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2947834648 # number of overall MSHR uncacheable cycles
3054system.l2c.overall_mshr_uncacheable_latency::total 16756105717 # number of overall MSHR uncacheable cycles
3055system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3056system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3057system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.274346 # mshr miss rate for UpgradeReq accesses
3058system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.323972 # mshr miss rate for UpgradeReq accesses
3059system.l2c.UpgradeReq_mshr_miss_rate::total 0.297265 # mshr miss rate for UpgradeReq accesses
3060system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.255611 # mshr miss rate for SCUpgradeReq accesses
3061system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.258556 # mshr miss rate for SCUpgradeReq accesses
3062system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.257137 # mshr miss rate for SCUpgradeReq accesses
3063system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.647192 # mshr miss rate for ReadExReq accesses
3064system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.513896 # mshr miss rate for ReadExReq accesses
3065system.l2c.ReadExReq_mshr_miss_rate::total 0.584340 # mshr miss rate for ReadExReq accesses
3066system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for ReadSharedReq accesses
3067system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for ReadSharedReq accesses
3068system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for ReadSharedReq accesses
3069system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.194682 # mshr miss rate for ReadSharedReq accesses
3070system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for ReadSharedReq accesses
3071system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for ReadSharedReq accesses
3072system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for ReadSharedReq accesses
3073system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for ReadSharedReq accesses
3074system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.206128 # mshr miss rate for ReadSharedReq accesses
3075system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for ReadSharedReq accesses
3076system.l2c.ReadSharedReq_mshr_miss_rate::total 0.257525 # mshr miss rate for ReadSharedReq accesses
3077system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.805617 # mshr miss rate for InvalidateReq accesses
3078system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.484635 # mshr miss rate for InvalidateReq accesses
3079system.l2c.InvalidateReq_mshr_miss_rate::total 0.711379 # mshr miss rate for InvalidateReq accesses
3080system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for demand accesses
3081system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for demand accesses
3082system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for demand accesses
3083system.l2c.demand_mshr_miss_rate::cpu0.data 0.264709 # mshr miss rate for demand accesses
3084system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for demand accesses
3085system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for demand accesses
3086system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for demand accesses
3087system.l2c.demand_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for demand accesses
3088system.l2c.demand_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for demand accesses
3089system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for demand accesses
3090system.l2c.demand_mshr_miss_rate::total 0.279701 # mshr miss rate for demand accesses
3091system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229215 # mshr miss rate for overall accesses
3092system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.267302 # mshr miss rate for overall accesses
3093system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104597 # mshr miss rate for overall accesses
3094system.l2c.overall_mshr_miss_rate::cpu0.data 0.264709 # mshr miss rate for overall accesses
3095system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.516511 # mshr miss rate for overall accesses
3096system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.379744 # mshr miss rate for overall accesses
3097system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.439790 # mshr miss rate for overall accesses
3098system.l2c.overall_mshr_miss_rate::cpu1.inst 0.100056 # mshr miss rate for overall accesses
3099system.l2c.overall_mshr_miss_rate::cpu1.data 0.251550 # mshr miss rate for overall accesses
3100system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.410394 # mshr miss rate for overall accesses
3101system.l2c.overall_mshr_miss_rate::total 0.279701 # mshr miss rate for overall accesses
3102system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70645.608157 # average UpgradeReq mshr miss latency
3103system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70822.845472 # average UpgradeReq mshr miss latency
3104system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70734.817393 # average UpgradeReq mshr miss latency
3105system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73734.473584 # average SCUpgradeReq mshr miss latency
3106system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73731.803576 # average SCUpgradeReq mshr miss latency
3107system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73733.082159 # average SCUpgradeReq mshr miss latency
3108system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 127628.243439 # average ReadExReq mshr miss latency
3109system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124096.831143 # average ReadExReq mshr miss latency
3110system.l2c.ReadExReq_avg_mshr_miss_latency::total 126163.836968 # average ReadExReq mshr miss latency
3111system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average ReadSharedReq mshr miss latency
3112system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average ReadSharedReq mshr miss latency
3113system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average ReadSharedReq mshr miss latency
3114system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129476.889559 # average ReadSharedReq mshr miss latency
3115system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average ReadSharedReq mshr miss latency
3116system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average ReadSharedReq mshr miss latency
3117system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average ReadSharedReq mshr miss latency
3118system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average ReadSharedReq mshr miss latency
3119system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131038.589718 # average ReadSharedReq mshr miss latency
3120system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average ReadSharedReq mshr miss latency
3121system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146856.147423 # average ReadSharedReq mshr miss latency
3122system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68924.750887 # average InvalidateReq mshr miss latency
3123system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69320.540881 # average InvalidateReq mshr miss latency
3124system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69003.914396 # average InvalidateReq mshr miss latency
3125system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency
3126system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency
3127system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency
3128system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency
3129system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency
3130system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency
3131system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency
3132system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency
3133system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency
3134system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency
3135system.l2c.demand_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency
3136system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132190.734135 # average overall mshr miss latency
3137system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131878.695349 # average overall mshr miss latency
3138system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125750.999182 # average overall mshr miss latency
3139system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128777.448103 # average overall mshr miss latency
3140system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162820.374673 # average overall mshr miss latency
3141system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130763.060082 # average overall mshr miss latency
3142system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130968.771730 # average overall mshr miss latency
3143system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125690.280371 # average overall mshr miss latency
3144system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency
3145system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency
3146system.l2c.overall_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency
3147system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency
3148system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159169.005787 # average ReadReq mshr uncacheable latency
3149system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency
3150system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298 # average ReadReq mshr uncacheable latency
3151system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281 # average ReadReq mshr uncacheable latency
3152system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916 # average WriteReq mshr uncacheable latency
3153system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146905.077510 # average WriteReq mshr uncacheable latency
3154system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177 # average WriteReq mshr uncacheable latency
3155system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency
3156system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158584.607059 # average overall mshr uncacheable latency
3157system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency
3158system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141961.697472 # average overall mshr uncacheable latency
3159system.l2c.overall_avg_mshr_uncacheable_latency::total 139187.653919 # average overall mshr uncacheable latency
3160system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3161system.membus.trans_dist::ReadReq 81896 # Transaction distribution
3162system.membus.trans_dist::ReadResp 974121 # Transaction distribution
3163system.membus.trans_dist::WriteReq 38489 # Transaction distribution
3164system.membus.trans_dist::WriteResp 38489 # Transaction distribution
3165system.membus.trans_dist::WritebackDirty 1317239 # Transaction distribution
3166system.membus.trans_dist::CleanEvict 246913 # Transaction distribution
3167system.membus.trans_dist::UpgradeReq 405326 # Transaction distribution
3168system.membus.trans_dist::SCUpgradeReq 320030 # Transaction distribution
3169system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3170system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
3171system.membus.trans_dist::ReadExReq 159351 # Transaction distribution
3172system.membus.trans_dist::ReadExResp 141190 # Transaction distribution
3173system.membus.trans_dist::ReadSharedReq 892225 # Transaction distribution
3174system.membus.trans_dist::InvalidateReq 691970 # Transaction distribution
3175system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes)
3176system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3177system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26416 # Packet count per connected master and slave (bytes)
3178system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4917130 # Packet count per connected master and slave (bytes)
3179system.membus.pkt_count_system.l2c.mem_side::total 5066302 # Packet count per connected master and slave (bytes)
3180system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes)
3181system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes)
3182system.membus.pkt_count::total 5304270 # Packet count per connected master and slave (bytes)
3183system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes)
3184system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3185system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52832 # Cumulative packet size per connected master and slave (bytes)
3186system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143189356 # Cumulative packet size per connected master and slave (bytes)
3187system.membus.pkt_size_system.l2c.mem_side::total 143398186 # Cumulative packet size per connected master and slave (bytes)
3188system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255936 # Cumulative packet size per connected master and slave (bytes)
3189system.membus.pkt_size_system.iocache.mem_side::total 7255936 # Cumulative packet size per connected master and slave (bytes)
3190system.membus.pkt_size::total 150654122 # Cumulative packet size per connected master and slave (bytes)
3191system.membus.snoops 585601 # Total snoops (count)
3192system.membus.snoop_fanout::samples 4153558 # Request fanout histogram
3193system.membus.snoop_fanout::mean 1 # Request fanout histogram
3194system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3195system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3196system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3197system.membus.snoop_fanout::1 4153558 100.00% 100.00% # Request fanout histogram
3198system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3199system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3200system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3201system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3202system.membus.snoop_fanout::total 4153558 # Request fanout histogram
3203system.membus.reqLayer0.occupancy 101297998 # Layer occupancy (ticks)
3204system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3205system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3206system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3207system.membus.reqLayer2.occupancy 21722999 # Layer occupancy (ticks)
3208system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3209system.membus.reqLayer5.occupancy 9168141817 # Layer occupancy (ticks)
3210system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3211system.membus.respLayer2.occupancy 5620018463 # Layer occupancy (ticks)
3212system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3213system.membus.respLayer3.occupancy 45534588 # Layer occupancy (ticks)
3214system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3215system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3216system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3217system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3218system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3219system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3220system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3221system.realview.ethernet.txBytes 966 # Bytes Transmitted

--- 37 unchanged lines hidden (view full) ---

3259system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3260system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3261system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3262system.realview.ethernet.droppedPackets 0 # number of packets dropped
3263system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3264system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3265system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3266system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3267system.toL2Bus.snoop_filter.tot_requests 11339751 # Total number of requests made to the snoop filter.
3268system.toL2Bus.snoop_filter.hit_single_requests 6165572 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3269system.toL2Bus.snoop_filter.hit_multi_requests 1768705 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3270system.toL2Bus.snoop_filter.tot_snoops 157796 # Total number of snoops made to the snoop filter.
3271system.toL2Bus.snoop_filter.hit_single_snoops 143620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3272system.toL2Bus.snoop_filter.hit_multi_snoops 14176 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3273system.toL2Bus.trans_dist::ReadReq 81898 # Transaction distribution
3274system.toL2Bus.trans_dist::ReadResp 4275837 # Transaction distribution
3275system.toL2Bus.trans_dist::WriteReq 38489 # Transaction distribution
3276system.toL2Bus.trans_dist::WriteResp 38489 # Transaction distribution
3277system.toL2Bus.trans_dist::WritebackDirty 4106250 # Transaction distribution
3278system.toL2Bus.trans_dist::CleanEvict 2453030 # Transaction distribution
3279system.toL2Bus.trans_dist::UpgradeReq 692369 # Transaction distribution
3280system.toL2Bus.trans_dist::SCUpgradeReq 399393 # Transaction distribution
3281system.toL2Bus.trans_dist::UpgradeResp 1091762 # Transaction distribution
3282system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
3283system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
3284system.toL2Bus.trans_dist::ReadExReq 305771 # Transaction distribution
3285system.toL2Bus.trans_dist::ReadExResp 305771 # Transaction distribution
3286system.toL2Bus.trans_dist::ReadSharedReq 4201160 # Transaction distribution
3287system.toL2Bus.trans_dist::InvalidateReq 934668 # Transaction distribution
3288system.toL2Bus.trans_dist::InvalidateResp 827940 # Transaction distribution
3289system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9127029 # Packet count per connected master and slave (bytes)
3290system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7489964 # Packet count per connected master and slave (bytes)
3291system.toL2Bus.pkt_count::total 16616993 # Packet count per connected master and slave (bytes)
3292system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 227401989 # Cumulative packet size per connected master and slave (bytes)
3293system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 187094309 # Cumulative packet size per connected master and slave (bytes)
3294system.toL2Bus.pkt_size::total 414496298 # Cumulative packet size per connected master and slave (bytes)
3295system.toL2Bus.snoops 3137723 # Total snoops (count)
3296system.toL2Bus.snoop_fanout::samples 8291271 # Request fanout histogram
3297system.toL2Bus.snoop_fanout::mean 0.336829 # Request fanout histogram
3298system.toL2Bus.snoop_fanout::stdev 0.476230 # Request fanout histogram
3299system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3300system.toL2Bus.snoop_fanout::0 5512705 66.49% 66.49% # Request fanout histogram
3301system.toL2Bus.snoop_fanout::1 2764390 33.34% 99.83% # Request fanout histogram
3302system.toL2Bus.snoop_fanout::2 14176 0.17% 100.00% # Request fanout histogram
3303system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3304system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3305system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3306system.toL2Bus.snoop_fanout::total 8291271 # Request fanout histogram
3307system.toL2Bus.reqLayer0.occupancy 8991327701 # Layer occupancy (ticks)
3308system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3309system.toL2Bus.snoopLayer0.occupancy 2644911 # Layer occupancy (ticks)
3310system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3311system.toL2Bus.respLayer0.occupancy 4134292430 # Layer occupancy (ticks)
3312system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3313system.toL2Bus.respLayer1.occupancy 3690529810 # Layer occupancy (ticks)
3314system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3315
3316---------- End Simulation Statistics ----------