1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.602418 # Number of seconds simulated
4sim_ticks 47602418253500 # Number of ticks simulated
5final_tick 47602418253500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 704375 # Simulator instruction rate (inst/s)
8host_op_rate 828740 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38464814262 # Simulator tick rate (ticks/s)
10host_mem_usage 746580 # Number of bytes of host memory used
11host_seconds 1237.56 # Real time elapsed on the host
12sim_insts 871704321 # Number of instructions simulated
13sim_ops 1025613965 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 106624 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 114944 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 3306740 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 39207752 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13461760 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 71360 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 71552 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2461816 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 13970768 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 8718016 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 430784 # Number of bytes read from this memory
27system.physmem.bytes_read::total 81922116 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 3306740 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 2461816 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 5768556 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 69209472 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 69230056 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 1666 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1796 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 92075 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 612634 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 210340 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 1115 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1118 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 38554 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 218306 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 136219 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6731 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1320554 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1081398 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1083972 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2240 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 2415 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 69466 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 823650 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 282796 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 1499 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 1503 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 51716 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 293489 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 183142 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9050 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1720965 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 69466 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 51716 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 121182 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1453907 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1454339 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1453907 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2240 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 2415 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 69466 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 824083 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 282796 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 1499 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 1503 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 51716 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 293489 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 183142 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9050 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3175304 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1320554 # Number of read requests accepted
84system.physmem.writeReqs 1083972 # Number of write requests accepted
85system.physmem.readBursts 1320554 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1083972 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 84482048 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 33408 # Total number of bytes read from write queue
89system.physmem.bytesWritten 69229248 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 81922116 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 69230056 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 522 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 79060 # Per bank write bursts
96system.physmem.perBankRdBursts::1 84693 # Per bank write bursts
97system.physmem.perBankRdBursts::2 79264 # Per bank write bursts
98system.physmem.perBankRdBursts::3 82906 # Per bank write bursts
99system.physmem.perBankRdBursts::4 76161 # Per bank write bursts
100system.physmem.perBankRdBursts::5 86285 # Per bank write bursts
101system.physmem.perBankRdBursts::6 80943 # Per bank write bursts
102system.physmem.perBankRdBursts::7 81570 # Per bank write bursts
103system.physmem.perBankRdBursts::8 74520 # Per bank write bursts
104system.physmem.perBankRdBursts::9 121634 # Per bank write bursts
105system.physmem.perBankRdBursts::10 72298 # Per bank write bursts
106system.physmem.perBankRdBursts::11 79752 # Per bank write bursts
107system.physmem.perBankRdBursts::12 77563 # Per bank write bursts
108system.physmem.perBankRdBursts::13 85585 # Per bank write bursts
109system.physmem.perBankRdBursts::14 78768 # Per bank write bursts
110system.physmem.perBankRdBursts::15 79030 # Per bank write bursts
111system.physmem.perBankWrBursts::0 65472 # Per bank write bursts
112system.physmem.perBankWrBursts::1 70626 # Per bank write bursts
113system.physmem.perBankWrBursts::2 66791 # Per bank write bursts
114system.physmem.perBankWrBursts::3 69615 # Per bank write bursts
115system.physmem.perBankWrBursts::4 63756 # Per bank write bursts
116system.physmem.perBankWrBursts::5 71331 # Per bank write bursts
117system.physmem.perBankWrBursts::6 67500 # Per bank write bursts
118system.physmem.perBankWrBursts::7 68943 # Per bank write bursts
119system.physmem.perBankWrBursts::8 63410 # Per bank write bursts
120system.physmem.perBankWrBursts::9 68673 # Per bank write bursts
121system.physmem.perBankWrBursts::10 63007 # Per bank write bursts
122system.physmem.perBankWrBursts::11 67951 # Per bank write bursts
123system.physmem.perBankWrBursts::12 66506 # Per bank write bursts
124system.physmem.perBankWrBursts::13 73077 # Per bank write bursts
125system.physmem.perBankWrBursts::14 66769 # Per bank write bursts
126system.physmem.perBankWrBursts::15 68280 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 42 # Number of times write queue was full causing retry
129system.physmem.totGap 47602414888000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 43195 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1277329 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1081398 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 1104957 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 68933 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 30329 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 25891 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 22057 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 19390 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 16894 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 14853 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 11934 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 867 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 435 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 305 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 221 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 191 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 130 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see
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165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 18639 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 22143 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 48134 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 53739 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 58424 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 60173 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 62461 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 64493 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 65899 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 66079 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 68869 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 71761 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 68201 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 69441 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 73837 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 67956 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 64592 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 63507 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 2802 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 1216 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 964 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 646 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 634 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 560 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 464 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 357 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 329 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 297 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 319 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 247 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 280 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 285 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 172 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 189 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 149 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 850234 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 180.786598 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 111.487051 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 240.213026 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 527654 62.06% 62.06% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 158419 18.63% 80.69% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 52205 6.14% 86.83% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 27644 3.25% 90.08% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 18445 2.17% 92.25% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 11596 1.36% 93.62% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 9081 1.07% 94.68% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 9121 1.07% 95.76% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 36069 4.24% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 850234 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 60429 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 21.843949 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 329.896328 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-4095 60426 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 60429 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 60429 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 17.900462 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.285869 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 7.671229 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 56824 94.03% 94.03% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 1552 2.57% 96.60% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 279 0.46% 97.06% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 180 0.30% 97.36% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 145 0.24% 97.60% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 117 0.19% 97.80% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 182 0.30% 98.10% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 82 0.14% 98.23% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 275 0.46% 98.69% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 67 0.11% 98.80% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 37 0.06% 98.86% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 44 0.07% 98.93% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 253 0.42% 99.35% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 30 0.05% 99.40% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 37 0.06% 99.46% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 152 0.25% 99.89% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::88-91 3 0.00% 99.91% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::140-143 2 0.00% 99.96% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::total 60429 # Writes before turning the bus around for reads
303system.physmem.totQLat 28489428593 # Total ticks spent queuing
304system.physmem.totMemAccLat 53240028593 # Total ticks spent from burst creation until serviced by the DRAM
305system.physmem.totBusLat 6600160000 # Total ticks spent in databus transfers
306system.physmem.avgQLat 21582.38 # Average queueing delay per DRAM burst
307system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
308system.physmem.avgMemAccLat 40332.38 # Average memory access latency per DRAM burst
309system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s
310system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s
311system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s
312system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s
313system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
314system.physmem.busUtil 0.03 # Data bus utilization in percentage
315system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
316system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
317system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
318system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing
319system.physmem.readRowHits 1056858 # Number of row buffer hits during reads
320system.physmem.writeRowHits 494645 # Number of row buffer hits during writes
321system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads
322system.physmem.writeRowHitRate 45.73 # Row buffer hit rate for writes
323system.physmem.avgGap 19797005.68 # Average gap between requests
324system.physmem.pageHitRate 64.60 # Row buffer hit rate, read and write combined
325system.physmem_0.actEnergy 3250149840 # Energy for activate commands per rank (pJ)
326system.physmem_0.preEnergy 1773395250 # Energy for precharge commands per rank (pJ)
327system.physmem_0.readEnergy 5076832800 # Energy for read commands per rank (pJ)
328system.physmem_0.writeEnergy 3525340320 # Energy for write commands per rank (pJ)
329system.physmem_0.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ)
330system.physmem_0.actBackEnergy 1224482966955 # Energy for active background per rank (pJ)
331system.physmem_0.preBackEnergy 27487341349500 # Energy for precharge background per rank (pJ)
332system.physmem_0.totalEnergy 31834608387225 # Total energy per rank (pJ)
333system.physmem_0.averagePower 668.760359 # Core power per rank (mW)
334system.physmem_0.memoryStateTime::IDLE 45727050942416 # Time in different power states
335system.physmem_0.memoryStateTime::REF 1589549260000 # Time in different power states
336system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
337system.physmem_0.memoryStateTime::ACT 285815210084 # Time in different power states
338system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
339system.physmem_1.actEnergy 3177619200 # Energy for activate commands per rank (pJ)
340system.physmem_1.preEnergy 1733820000 # Energy for precharge commands per rank (pJ)
341system.physmem_1.readEnergy 5219370000 # Energy for read commands per rank (pJ)
342system.physmem_1.writeEnergy 3484121040 # Energy for write commands per rank (pJ)
343system.physmem_1.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ)
344system.physmem_1.actBackEnergy 1221031665405 # Energy for active background per rank (pJ)
345system.physmem_1.preBackEnergy 27490368798750 # Energy for precharge background per rank (pJ)
346system.physmem_1.totalEnergy 31834173746955 # Total energy per rank (pJ)
347system.physmem_1.averagePower 668.751229 # Core power per rank (mW)
348system.physmem_1.memoryStateTime::IDLE 45732072121963 # Time in different power states
349system.physmem_1.memoryStateTime::REF 1589549260000 # Time in different power states
350system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
351system.physmem_1.memoryStateTime::ACT 280793976787 # Time in different power states
352system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
353system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
354system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
355system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
358system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
359system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory

--- 14 unchanged lines hidden (view full) ---

374system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
375system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
376system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
377system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
378system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
379system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
380system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
381system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
382system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
383system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
384system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
385system.cpu_clk_domain.clock 500 # Clock period in ticks
386system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

407system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
408system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
409system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
410system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
411system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
412system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
413system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
414system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
415system.cpu0.dtb.walker.walks 112758 # Table walker walks requested
416system.cpu0.dtb.walker.walksLong 112758 # Table walker walks initiated with long descriptors
417system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10038 # Level at which table walker walks with long descriptors terminate
418system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 87373 # Level at which table walker walks with long descriptors terminate
419system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting
420system.cpu0.dtb.walker.walkWaitTime::samples 112734 # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkWaitTime::mean 0.230631 # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::stdev 77.436531 # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::0-2047 112733 100.00% 100.00% # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::total 112734 # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkCompletionTime::samples 97435 # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::mean 23281.346539 # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::gmean 21381.718359 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::stdev 19258.937396 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::0-65535 96246 98.78% 98.78% # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::65536-131071 178 0.18% 98.96% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::131072-196607 868 0.89% 99.85% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.87% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.93% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.95% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::total 97435 # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walksPending::samples 8883013024 # Table walker pending requests distribution
443system.cpu0.dtb.walker.walksPending::mean 0.766632 # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::stdev 0.422974 # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::0 2073007704 23.34% 23.34% # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::1 6810005320 76.66% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::total 8883013024 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walkPageSizes::4K 87373 89.70% 89.70% # Table walker page sizes translated
449system.cpu0.dtb.walker.walkPageSizes::2M 10038 10.30% 100.00% # Table walker page sizes translated
450system.cpu0.dtb.walker.walkPageSizes::total 97411 # Table walker page sizes translated
451system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112758 # Table walker requests started/completed, data/inst
452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112758 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97411 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97411 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin::total 210169 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.inst_hits 0 # ITB inst hits
459system.cpu0.dtb.inst_misses 0 # ITB inst misses
460system.cpu0.dtb.read_hits 88968055 # DTB read hits
461system.cpu0.dtb.read_misses 85634 # DTB read misses
462system.cpu0.dtb.write_hits 80360369 # DTB write hits
463system.cpu0.dtb.write_misses 27124 # DTB write misses
464system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
465system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
466system.cpu0.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
467system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
468system.cpu0.dtb.flush_entries 39097 # Number of entries that have been flushed from TLB
469system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
470system.cpu0.dtb.prefetch_faults 3879 # Number of TLB faults due to prefetch
471system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
472system.cpu0.dtb.perms_faults 10141 # Number of TLB faults due to permissions restrictions
473system.cpu0.dtb.read_accesses 89053689 # DTB read accesses
474system.cpu0.dtb.write_accesses 80387493 # DTB write accesses
475system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
476system.cpu0.dtb.hits 169328424 # DTB hits
477system.cpu0.dtb.misses 112758 # DTB misses
478system.cpu0.dtb.accesses 169441182 # DTB accesses
479system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

500system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
501system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
502system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
503system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
504system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
505system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
506system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
507system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
508system.cpu0.itb.walker.walks 62308 # Table walker walks requested
509system.cpu0.itb.walker.walksLong 62308 # Table walker walks initiated with long descriptors
510system.cpu0.itb.walker.walksLongTerminationLevel::Level2 814 # Level at which table walker walks with long descriptors terminate
511system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55869 # Level at which table walker walks with long descriptors terminate
512system.cpu0.itb.walker.walkWaitTime::samples 62308 # Table walker wait (enqueue to first request) latency
513system.cpu0.itb.walker.walkWaitTime::0 62308 100.00% 100.00% # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::total 62308 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkCompletionTime::samples 56683 # Table walker service (enqueue to completion) latency
516system.cpu0.itb.walker.walkCompletionTime::mean 26679.454157 # Table walker service (enqueue to completion) latency
517system.cpu0.itb.walker.walkCompletionTime::gmean 23625.111342 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::stdev 26536.909948 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::0-65535 55487 97.89% 97.89% # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.07% 97.96% # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::131072-196607 988 1.74% 99.71% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.75% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::262144-327679 65 0.11% 99.87% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.89% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::393216-458751 49 0.09% 99.98% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::total 56683 # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution
531system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution
532system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution
533system.cpu0.itb.walker.walkPageSizes::4K 55869 98.56% 98.56% # Table walker page sizes translated
534system.cpu0.itb.walker.walkPageSizes::2M 814 1.44% 100.00% # Table walker page sizes translated
535system.cpu0.itb.walker.walkPageSizes::total 56683 # Table walker page sizes translated
536system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
537system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62308 # Table walker requests started/completed, data/inst
538system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62308 # Table walker requests started/completed, data/inst
539system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
540system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56683 # Table walker requests started/completed, data/inst
541system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56683 # Table walker requests started/completed, data/inst
542system.cpu0.itb.walker.walkRequestOrigin::total 118991 # Table walker requests started/completed, data/inst
543system.cpu0.itb.inst_hits 472241024 # ITB inst hits
544system.cpu0.itb.inst_misses 62308 # ITB inst misses
545system.cpu0.itb.read_hits 0 # DTB read hits
546system.cpu0.itb.read_misses 0 # DTB read misses
547system.cpu0.itb.write_hits 0 # DTB write hits
548system.cpu0.itb.write_misses 0 # DTB write misses
549system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
550system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
551system.cpu0.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
552system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
553system.cpu0.itb.flush_entries 28001 # Number of entries that have been flushed from TLB
554system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
555system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
556system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
557system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
558system.cpu0.itb.read_accesses 0 # DTB read accesses
559system.cpu0.itb.write_accesses 0 # DTB write accesses
560system.cpu0.itb.inst_accesses 472303332 # ITB inst accesses
561system.cpu0.itb.hits 472241024 # DTB hits
562system.cpu0.itb.misses 62308 # DTB misses
563system.cpu0.itb.accesses 472303332 # DTB accesses
564system.cpu0.numCycles 95204836507 # number of cpu cycles simulated
565system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
566system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
567system.cpu0.kern.inst.arm 0 # number of arm instructions executed
568system.cpu0.kern.inst.quiesce 5131 # number of quiesce instructions executed
569system.cpu0.committedInsts 471986732 # Number of instructions committed
570system.cpu0.committedOps 554132163 # Number of ops (including micro ops) committed
571system.cpu0.num_int_alu_accesses 509304939 # Number of integer alu accesses
572system.cpu0.num_fp_alu_accesses 463756 # Number of float alu accesses
573system.cpu0.num_func_calls 28209702 # number of times a function call or return occured
574system.cpu0.num_conditional_control_insts 71348449 # number of instructions that are conditional controls
575system.cpu0.num_int_insts 509304939 # number of integer instructions
576system.cpu0.num_fp_insts 463756 # number of float instructions
577system.cpu0.num_int_register_reads 736700300 # number of times the integer registers were read
578system.cpu0.num_int_register_writes 403898232 # number of times the integer registers were written
579system.cpu0.num_fp_register_reads 771652 # number of times the floating registers were read
580system.cpu0.num_fp_register_writes 344244 # number of times the floating registers were written
581system.cpu0.num_cc_register_reads 122509563 # number of times the CC registers were read
582system.cpu0.num_cc_register_writes 122079243 # number of times the CC registers were written
583system.cpu0.num_mem_refs 169317654 # number of memory refs
584system.cpu0.num_load_insts 88962856 # Number of load instructions
585system.cpu0.num_store_insts 80354798 # Number of store instructions
586system.cpu0.num_idle_cycles 93934250531.242035 # Number of idle cycles
587system.cpu0.num_busy_cycles 1270585975.757973 # Number of busy cycles
588system.cpu0.not_idle_fraction 0.013346 # Percentage of non-idle cycles
589system.cpu0.idle_fraction 0.986654 # Percentage of idle cycles
590system.cpu0.Branches 105166310 # Number of branches fetched
591system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
592system.cpu0.op_class::IntAlu 383762588 69.22% 69.22% # Class of executed instruction
593system.cpu0.op_class::IntMult 1237276 0.22% 69.44% # Class of executed instruction
594system.cpu0.op_class::IntDiv 66509 0.01% 69.45% # Class of executed instruction
595system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction
596system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction
597system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction
598system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction
599system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction
600system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction
601system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction
602system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction
603system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction
604system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction
605system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction
606system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction
607system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction
608system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction
609system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction
610system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction
611system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction
612system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction
613system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction
614system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction
615system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.45% # Class of executed instruction
616system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction
617system.cpu0.op_class::SimdFloatMisc 45552 0.01% 69.46% # Class of executed instruction
618system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction
619system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction
620system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction
621system.cpu0.op_class::MemRead 88962856 16.05% 85.51% # Class of executed instruction
622system.cpu0.op_class::MemWrite 80354798 14.49% 100.00% # Class of executed instruction
623system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
624system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
625system.cpu0.op_class::total 554429579 # Class of executed instruction
626system.cpu0.dcache.tags.replacements 5824476 # number of replacements
627system.cpu0.dcache.tags.tagsinuse 506.611071 # Cycle average of tags in use
628system.cpu0.dcache.tags.total_refs 163267162 # Total number of references to valid blocks.
629system.cpu0.dcache.tags.sampled_refs 5824987 # Sample count of references to valid blocks.
630system.cpu0.dcache.tags.avg_refs 28.028760 # Average number of references to valid blocks.
631system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit.
632system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.611071 # Average occupied blocks per requestor
633system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989475 # Average percentage of cache occupancy
634system.cpu0.dcache.tags.occ_percent::total 0.989475 # Average percentage of cache occupancy
635system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
636system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
637system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
638system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id
639system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
640system.cpu0.dcache.tags.tag_accesses 344508686 # Number of tag accesses
641system.cpu0.dcache.tags.data_accesses 344508686 # Number of data accesses
642system.cpu0.dcache.ReadReq_hits::cpu0.data 82887500 # number of ReadReq hits
643system.cpu0.dcache.ReadReq_hits::total 82887500 # number of ReadReq hits
644system.cpu0.dcache.WriteReq_hits::cpu0.data 75943802 # number of WriteReq hits
645system.cpu0.dcache.WriteReq_hits::total 75943802 # number of WriteReq hits
646system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196404 # number of SoftPFReq hits
647system.cpu0.dcache.SoftPFReq_hits::total 196404 # number of SoftPFReq hits
648system.cpu0.dcache.WriteLineReq_hits::cpu0.data 140054 # number of WriteLineReq hits
649system.cpu0.dcache.WriteLineReq_hits::total 140054 # number of WriteLineReq hits
650system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847526 # number of LoadLockedReq hits
651system.cpu0.dcache.LoadLockedReq_hits::total 1847526 # number of LoadLockedReq hits
652system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1825483 # number of StoreCondReq hits
653system.cpu0.dcache.StoreCondReq_hits::total 1825483 # number of StoreCondReq hits
654system.cpu0.dcache.demand_hits::cpu0.data 158831302 # number of demand (read+write) hits
655system.cpu0.dcache.demand_hits::total 158831302 # number of demand (read+write) hits
656system.cpu0.dcache.overall_hits::cpu0.data 159027706 # number of overall hits
657system.cpu0.dcache.overall_hits::total 159027706 # number of overall hits
658system.cpu0.dcache.ReadReq_misses::cpu0.data 3189198 # number of ReadReq misses
659system.cpu0.dcache.ReadReq_misses::total 3189198 # number of ReadReq misses
660system.cpu0.dcache.WriteReq_misses::cpu0.data 1439126 # number of WriteReq misses
661system.cpu0.dcache.WriteReq_misses::total 1439126 # number of WriteReq misses
662system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657536 # number of SoftPFReq misses
663system.cpu0.dcache.SoftPFReq_misses::total 657536 # number of SoftPFReq misses
664system.cpu0.dcache.WriteLineReq_misses::cpu0.data 792800 # number of WriteLineReq misses
665system.cpu0.dcache.WriteLineReq_misses::total 792800 # number of WriteLineReq misses
666system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 174919 # number of LoadLockedReq misses
667system.cpu0.dcache.LoadLockedReq_misses::total 174919 # number of LoadLockedReq misses
668system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195568 # number of StoreCondReq misses
669system.cpu0.dcache.StoreCondReq_misses::total 195568 # number of StoreCondReq misses
670system.cpu0.dcache.demand_misses::cpu0.data 4628324 # number of demand (read+write) misses
671system.cpu0.dcache.demand_misses::total 4628324 # number of demand (read+write) misses
672system.cpu0.dcache.overall_misses::cpu0.data 5285860 # number of overall misses
673system.cpu0.dcache.overall_misses::total 5285860 # number of overall misses
674system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52614413500 # number of ReadReq miss cycles
675system.cpu0.dcache.ReadReq_miss_latency::total 52614413500 # number of ReadReq miss cycles
676system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36171191500 # number of WriteReq miss cycles
677system.cpu0.dcache.WriteReq_miss_latency::total 36171191500 # number of WriteReq miss cycles
678system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 66218479500 # number of WriteLineReq miss cycles
679system.cpu0.dcache.WriteLineReq_miss_latency::total 66218479500 # number of WriteLineReq miss cycles
680system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2808474500 # number of LoadLockedReq miss cycles
681system.cpu0.dcache.LoadLockedReq_miss_latency::total 2808474500 # number of LoadLockedReq miss cycles
682system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5670137000 # number of StoreCondReq miss cycles
683system.cpu0.dcache.StoreCondReq_miss_latency::total 5670137000 # number of StoreCondReq miss cycles
684system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6661000 # number of StoreCondFailReq miss cycles
685system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6661000 # number of StoreCondFailReq miss cycles
686system.cpu0.dcache.demand_miss_latency::cpu0.data 88785605000 # number of demand (read+write) miss cycles
687system.cpu0.dcache.demand_miss_latency::total 88785605000 # number of demand (read+write) miss cycles
688system.cpu0.dcache.overall_miss_latency::cpu0.data 88785605000 # number of overall miss cycles
689system.cpu0.dcache.overall_miss_latency::total 88785605000 # number of overall miss cycles
690system.cpu0.dcache.ReadReq_accesses::cpu0.data 86076698 # number of ReadReq accesses(hits+misses)
691system.cpu0.dcache.ReadReq_accesses::total 86076698 # number of ReadReq accesses(hits+misses)
692system.cpu0.dcache.WriteReq_accesses::cpu0.data 77382928 # number of WriteReq accesses(hits+misses)
693system.cpu0.dcache.WriteReq_accesses::total 77382928 # number of WriteReq accesses(hits+misses)
694system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853940 # number of SoftPFReq accesses(hits+misses)
695system.cpu0.dcache.SoftPFReq_accesses::total 853940 # number of SoftPFReq accesses(hits+misses)
696system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 932854 # number of WriteLineReq accesses(hits+misses)
697system.cpu0.dcache.WriteLineReq_accesses::total 932854 # number of WriteLineReq accesses(hits+misses)
698system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2022445 # number of LoadLockedReq accesses(hits+misses)
699system.cpu0.dcache.LoadLockedReq_accesses::total 2022445 # number of LoadLockedReq accesses(hits+misses)
700system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2021051 # number of StoreCondReq accesses(hits+misses)
701system.cpu0.dcache.StoreCondReq_accesses::total 2021051 # number of StoreCondReq accesses(hits+misses)
702system.cpu0.dcache.demand_accesses::cpu0.data 163459626 # number of demand (read+write) accesses
703system.cpu0.dcache.demand_accesses::total 163459626 # number of demand (read+write) accesses
704system.cpu0.dcache.overall_accesses::cpu0.data 164313566 # number of overall (read+write) accesses
705system.cpu0.dcache.overall_accesses::total 164313566 # number of overall (read+write) accesses
706system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037051 # miss rate for ReadReq accesses
707system.cpu0.dcache.ReadReq_miss_rate::total 0.037051 # miss rate for ReadReq accesses
708system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018597 # miss rate for WriteReq accesses
709system.cpu0.dcache.WriteReq_miss_rate::total 0.018597 # miss rate for WriteReq accesses
710system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770003 # miss rate for SoftPFReq accesses
711system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770003 # miss rate for SoftPFReq accesses
712system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.849865 # miss rate for WriteLineReq accesses
713system.cpu0.dcache.WriteLineReq_miss_rate::total 0.849865 # miss rate for WriteLineReq accesses
714system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086489 # miss rate for LoadLockedReq accesses
715system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086489 # miss rate for LoadLockedReq accesses
716system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096765 # miss rate for StoreCondReq accesses
717system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096765 # miss rate for StoreCondReq accesses
718system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028315 # miss rate for demand accesses
719system.cpu0.dcache.demand_miss_rate::total 0.028315 # miss rate for demand accesses
720system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032169 # miss rate for overall accesses
721system.cpu0.dcache.overall_miss_rate::total 0.032169 # miss rate for overall accesses
722system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16497.694248 # average ReadReq miss latency
723system.cpu0.dcache.ReadReq_avg_miss_latency::total 16497.694248 # average ReadReq miss latency
724system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25134.138012 # average WriteReq miss latency
725system.cpu0.dcache.WriteReq_avg_miss_latency::total 25134.138012 # average WriteReq miss latency
726system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83524.822780 # average WriteLineReq miss latency
727system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83524.822780 # average WriteLineReq miss latency
728system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16055.857283 # average LoadLockedReq miss latency
729system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16055.857283 # average LoadLockedReq miss latency
730system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28993.173730 # average StoreCondReq miss latency
731system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28993.173730 # average StoreCondReq miss latency
732system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
733system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
734system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19183.100621 # average overall miss latency
735system.cpu0.dcache.demand_avg_miss_latency::total 19183.100621 # average overall miss latency
736system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16796.813574 # average overall miss latency
737system.cpu0.dcache.overall_avg_miss_latency::total 16796.813574 # average overall miss latency
738system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
739system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
740system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
741system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
742system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
743system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
744system.cpu0.dcache.fast_writes 0 # number of fast writes performed
745system.cpu0.dcache.cache_copies 0 # number of cache copies performed
746system.cpu0.dcache.writebacks::writebacks 5824476 # number of writebacks
747system.cpu0.dcache.writebacks::total 5824476 # number of writebacks
748system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27468 # number of ReadReq MSHR hits
749system.cpu0.dcache.ReadReq_mshr_hits::total 27468 # number of ReadReq MSHR hits
750system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21247 # number of WriteReq MSHR hits
751system.cpu0.dcache.WriteReq_mshr_hits::total 21247 # number of WriteReq MSHR hits
752system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43989 # number of LoadLockedReq MSHR hits
753system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43989 # number of LoadLockedReq MSHR hits
754system.cpu0.dcache.demand_mshr_hits::cpu0.data 48715 # number of demand (read+write) MSHR hits
755system.cpu0.dcache.demand_mshr_hits::total 48715 # number of demand (read+write) MSHR hits
756system.cpu0.dcache.overall_mshr_hits::cpu0.data 48715 # number of overall MSHR hits
757system.cpu0.dcache.overall_mshr_hits::total 48715 # number of overall MSHR hits
758system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3161730 # number of ReadReq MSHR misses
759system.cpu0.dcache.ReadReq_mshr_misses::total 3161730 # number of ReadReq MSHR misses
760system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417879 # number of WriteReq MSHR misses
761system.cpu0.dcache.WriteReq_mshr_misses::total 1417879 # number of WriteReq MSHR misses
762system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656252 # number of SoftPFReq MSHR misses
763system.cpu0.dcache.SoftPFReq_mshr_misses::total 656252 # number of SoftPFReq MSHR misses
764system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792800 # number of WriteLineReq MSHR misses
765system.cpu0.dcache.WriteLineReq_mshr_misses::total 792800 # number of WriteLineReq MSHR misses
766system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 130930 # number of LoadLockedReq MSHR misses
767system.cpu0.dcache.LoadLockedReq_mshr_misses::total 130930 # number of LoadLockedReq MSHR misses
768system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195568 # number of StoreCondReq MSHR misses
769system.cpu0.dcache.StoreCondReq_mshr_misses::total 195568 # number of StoreCondReq MSHR misses
770system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579609 # number of demand (read+write) MSHR misses
771system.cpu0.dcache.demand_mshr_misses::total 4579609 # number of demand (read+write) MSHR misses
772system.cpu0.dcache.overall_mshr_misses::cpu0.data 5235861 # number of overall MSHR misses
773system.cpu0.dcache.overall_mshr_misses::total 5235861 # number of overall MSHR misses
774system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable
775system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14992 # number of ReadReq MSHR uncacheable
776system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable
777system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15725 # number of WriteReq MSHR uncacheable
778system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses
779system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30717 # number of overall MSHR uncacheable misses
780system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47545298500 # number of ReadReq MSHR miss cycles
781system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47545298500 # number of ReadReq MSHR miss cycles
782system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34168378500 # number of WriteReq MSHR miss cycles
783system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34168378500 # number of WriteReq MSHR miss cycles
784system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16138287000 # number of SoftPFReq MSHR miss cycles
785system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16138287000 # number of SoftPFReq MSHR miss cycles
786system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 65425679500 # number of WriteLineReq MSHR miss cycles
787system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65425679500 # number of WriteLineReq MSHR miss cycles
788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1807284000 # number of LoadLockedReq MSHR miss cycles
789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1807284000 # number of LoadLockedReq MSHR miss cycles
790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5474645000 # number of StoreCondReq MSHR miss cycles
791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5474645000 # number of StoreCondReq MSHR miss cycles
792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6585000 # number of StoreCondFailReq MSHR miss cycles
793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6585000 # number of StoreCondFailReq MSHR miss cycles
794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 81713677000 # number of demand (read+write) MSHR miss cycles
795system.cpu0.dcache.demand_mshr_miss_latency::total 81713677000 # number of demand (read+write) MSHR miss cycles
796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97851964000 # number of overall MSHR miss cycles
797system.cpu0.dcache.overall_mshr_miss_latency::total 97851964000 # number of overall MSHR miss cycles
798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2585195500 # number of ReadReq MSHR uncacheable cycles
799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2585195500 # number of ReadReq MSHR uncacheable cycles
800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2654242000 # number of WriteReq MSHR uncacheable cycles
801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654242000 # number of WriteReq MSHR uncacheable cycles
802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5239437500 # number of overall MSHR uncacheable cycles
803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5239437500 # number of overall MSHR uncacheable cycles
804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses
805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036732 # mshr miss rate for ReadReq accesses
806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018323 # mshr miss rate for WriteReq accesses
807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018323 # mshr miss rate for WriteReq accesses
808system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768499 # mshr miss rate for SoftPFReq accesses
809system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768499 # mshr miss rate for SoftPFReq accesses
810system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.849865 # mshr miss rate for WriteLineReq accesses
811system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.849865 # mshr miss rate for WriteLineReq accesses
812system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064738 # mshr miss rate for LoadLockedReq accesses
813system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064738 # mshr miss rate for LoadLockedReq accesses
814system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096765 # mshr miss rate for StoreCondReq accesses
815system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096765 # mshr miss rate for StoreCondReq accesses
816system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028017 # mshr miss rate for demand accesses
817system.cpu0.dcache.demand_mshr_miss_rate::total 0.028017 # mshr miss rate for demand accesses
818system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for overall accesses
819system.cpu0.dcache.overall_mshr_miss_rate::total 0.031865 # mshr miss rate for overall accesses
820system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15037.747847 # average ReadReq mshr miss latency
821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15037.747847 # average ReadReq mshr miss latency
822system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24098.232994 # average WriteReq mshr miss latency
823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24098.232994 # average WriteReq mshr miss latency
824system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24591.600483 # average SoftPFReq mshr miss latency
825system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24591.600483 # average SoftPFReq mshr miss latency
826system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82524.822780 # average WriteLineReq mshr miss latency
827system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82524.822780 # average WriteLineReq mshr miss latency
828system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13803.436951 # average LoadLockedReq mshr miss latency
829system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13803.436951 # average LoadLockedReq mshr miss latency
830system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27993.562341 # average StoreCondReq mshr miss latency
831system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27993.562341 # average StoreCondReq mshr miss latency
832system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
833system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
834system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17842.937465 # average overall mshr miss latency
835system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17842.937465 # average overall mshr miss latency
836system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18688.800944 # average overall mshr miss latency
837system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18688.800944 # average overall mshr miss latency
838system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172438.333778 # average ReadReq mshr uncacheable latency
839system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172438.333778 # average ReadReq mshr uncacheable latency
840system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168791.224165 # average WriteReq mshr uncacheable latency
841system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168791.224165 # average WriteReq mshr uncacheable latency
842system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170571.263470 # average overall mshr uncacheable latency
843system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170571.263470 # average overall mshr uncacheable latency
844system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
845system.cpu0.icache.tags.replacements 5187208 # number of replacements
846system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use
847system.cpu0.icache.tags.total_refs 467053304 # Total number of references to valid blocks.
848system.cpu0.icache.tags.sampled_refs 5187720 # Sample count of references to valid blocks.
849system.cpu0.icache.tags.avg_refs 90.030554 # Average number of references to valid blocks.
850system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit.
851system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor
852system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy
853system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy
854system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
855system.cpu0.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
856system.cpu0.icache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id
857system.cpu0.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id
858system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
859system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
860system.cpu0.icache.tags.tag_accesses 949669768 # Number of tag accesses
861system.cpu0.icache.tags.data_accesses 949669768 # Number of data accesses
862system.cpu0.icache.ReadReq_hits::cpu0.inst 467053304 # number of ReadReq hits
863system.cpu0.icache.ReadReq_hits::total 467053304 # number of ReadReq hits
864system.cpu0.icache.demand_hits::cpu0.inst 467053304 # number of demand (read+write) hits
865system.cpu0.icache.demand_hits::total 467053304 # number of demand (read+write) hits
866system.cpu0.icache.overall_hits::cpu0.inst 467053304 # number of overall hits
867system.cpu0.icache.overall_hits::total 467053304 # number of overall hits
868system.cpu0.icache.ReadReq_misses::cpu0.inst 5187720 # number of ReadReq misses
869system.cpu0.icache.ReadReq_misses::total 5187720 # number of ReadReq misses
870system.cpu0.icache.demand_misses::cpu0.inst 5187720 # number of demand (read+write) misses
871system.cpu0.icache.demand_misses::total 5187720 # number of demand (read+write) misses
872system.cpu0.icache.overall_misses::cpu0.inst 5187720 # number of overall misses
873system.cpu0.icache.overall_misses::total 5187720 # number of overall misses
874system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57877602000 # number of ReadReq miss cycles
875system.cpu0.icache.ReadReq_miss_latency::total 57877602000 # number of ReadReq miss cycles
876system.cpu0.icache.demand_miss_latency::cpu0.inst 57877602000 # number of demand (read+write) miss cycles
877system.cpu0.icache.demand_miss_latency::total 57877602000 # number of demand (read+write) miss cycles
878system.cpu0.icache.overall_miss_latency::cpu0.inst 57877602000 # number of overall miss cycles
879system.cpu0.icache.overall_miss_latency::total 57877602000 # number of overall miss cycles
880system.cpu0.icache.ReadReq_accesses::cpu0.inst 472241024 # number of ReadReq accesses(hits+misses)
881system.cpu0.icache.ReadReq_accesses::total 472241024 # number of ReadReq accesses(hits+misses)
882system.cpu0.icache.demand_accesses::cpu0.inst 472241024 # number of demand (read+write) accesses
883system.cpu0.icache.demand_accesses::total 472241024 # number of demand (read+write) accesses
884system.cpu0.icache.overall_accesses::cpu0.inst 472241024 # number of overall (read+write) accesses
885system.cpu0.icache.overall_accesses::total 472241024 # number of overall (read+write) accesses
886system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010985 # miss rate for ReadReq accesses
887system.cpu0.icache.ReadReq_miss_rate::total 0.010985 # miss rate for ReadReq accesses
888system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010985 # miss rate for demand accesses
889system.cpu0.icache.demand_miss_rate::total 0.010985 # miss rate for demand accesses
890system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010985 # miss rate for overall accesses
891system.cpu0.icache.overall_miss_rate::total 0.010985 # miss rate for overall accesses
892system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11156.654947 # average ReadReq miss latency
893system.cpu0.icache.ReadReq_avg_miss_latency::total 11156.654947 # average ReadReq miss latency
894system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency
895system.cpu0.icache.demand_avg_miss_latency::total 11156.654947 # average overall miss latency
896system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency
897system.cpu0.icache.overall_avg_miss_latency::total 11156.654947 # average overall miss latency
898system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
899system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
900system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
901system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
902system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
903system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
904system.cpu0.icache.fast_writes 0 # number of fast writes performed
905system.cpu0.icache.cache_copies 0 # number of cache copies performed
906system.cpu0.icache.writebacks::writebacks 5187208 # number of writebacks
907system.cpu0.icache.writebacks::total 5187208 # number of writebacks
908system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5187720 # number of ReadReq MSHR misses
909system.cpu0.icache.ReadReq_mshr_misses::total 5187720 # number of ReadReq MSHR misses
910system.cpu0.icache.demand_mshr_misses::cpu0.inst 5187720 # number of demand (read+write) MSHR misses
911system.cpu0.icache.demand_mshr_misses::total 5187720 # number of demand (read+write) MSHR misses
912system.cpu0.icache.overall_mshr_misses::cpu0.inst 5187720 # number of overall MSHR misses
913system.cpu0.icache.overall_mshr_misses::total 5187720 # number of overall MSHR misses
914system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
915system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
916system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
917system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
918system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 55283742000 # number of ReadReq MSHR miss cycles
919system.cpu0.icache.ReadReq_mshr_miss_latency::total 55283742000 # number of ReadReq MSHR miss cycles
920system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 55283742000 # number of demand (read+write) MSHR miss cycles
921system.cpu0.icache.demand_mshr_miss_latency::total 55283742000 # number of demand (read+write) MSHR miss cycles
922system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 55283742000 # number of overall MSHR miss cycles
923system.cpu0.icache.overall_mshr_miss_latency::total 55283742000 # number of overall MSHR miss cycles
924system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles
925system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles
926system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles
927system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles
928system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for ReadReq accesses
929system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010985 # mshr miss rate for ReadReq accesses
930system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for demand accesses
931system.cpu0.icache.demand_mshr_miss_rate::total 0.010985 # mshr miss rate for demand accesses
932system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for overall accesses
933system.cpu0.icache.overall_mshr_miss_rate::total 0.010985 # mshr miss rate for overall accesses
934system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average ReadReq mshr miss latency
935system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10656.654947 # average ReadReq mshr miss latency
936system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency
937system.cpu0.icache.demand_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency
938system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency
939system.cpu0.icache.overall_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency
940system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency
941system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency
942system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency
943system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency
944system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
945system.cpu0.l2cache.prefetcher.num_hwpf_issued 7982984 # number of hwpf issued
946system.cpu0.l2cache.prefetcher.pfIdentified 7983049 # number of prefetch candidates identified
947system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue
948system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
949system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
950system.cpu0.l2cache.prefetcher.pfSpanPage 1030695 # number of prefetches not generated due to page crossing
951system.cpu0.l2cache.tags.replacements 2438237 # number of replacements
952system.cpu0.l2cache.tags.tagsinuse 16163.287998 # Cycle average of tags in use
953system.cpu0.l2cache.tags.total_refs 15536795 # Total number of references to valid blocks.
954system.cpu0.l2cache.tags.sampled_refs 2453930 # Sample count of references to valid blocks.
955system.cpu0.l2cache.tags.avg_refs 6.331393 # Average number of references to valid blocks.
956system.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit.
957system.cpu0.l2cache.tags.occ_blocks::writebacks 15209.476134 # Average occupied blocks per requestor
958system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.686152 # Average occupied blocks per requestor
959system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 84.208097 # Average occupied blocks per requestor
960system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 811.917616 # Average occupied blocks per requestor
961system.cpu0.l2cache.tags.occ_percent::writebacks 0.928313 # Average percentage of cache occupancy
962system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003521 # Average percentage of cache occupancy
963system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005140 # Average percentage of cache occupancy
964system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049556 # Average percentage of cache occupancy
965system.cpu0.l2cache.tags.occ_percent::total 0.986529 # Average percentage of cache occupancy
966system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1345 # Occupied blocks per task id
967system.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id
968system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14277 # Occupied blocks per task id
969system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id
970system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 148 # Occupied blocks per task id
971system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 690 # Occupied blocks per task id
972system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 373 # Occupied blocks per task id
973system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 28 # Occupied blocks per task id
974system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id
975system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
976system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
977system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 836 # Occupied blocks per task id
978system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4477 # Occupied blocks per task id
979system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6612 # Occupied blocks per task id
980system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2188 # Occupied blocks per task id
981system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082092 # Percentage of cache occupancy per task id
982system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
983system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871399 # Percentage of cache occupancy per task id
984system.cpu0.l2cache.tags.tag_accesses 373900742 # Number of tag accesses
985system.cpu0.l2cache.tags.data_accesses 373900742 # Number of data accesses
986system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267168 # number of ReadReq hits
987system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160390 # number of ReadReq hits
988system.cpu0.l2cache.ReadReq_hits::total 427558 # number of ReadReq hits
989system.cpu0.l2cache.WritebackDirty_hits::writebacks 3842470 # number of WritebackDirty hits
990system.cpu0.l2cache.WritebackDirty_hits::total 3842470 # number of WritebackDirty hits
991system.cpu0.l2cache.WritebackClean_hits::writebacks 7168468 # number of WritebackClean hits
992system.cpu0.l2cache.WritebackClean_hits::total 7168468 # number of WritebackClean hits
993system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 471 # number of UpgradeReq hits
994system.cpu0.l2cache.UpgradeReq_hits::total 471 # number of UpgradeReq hits
995system.cpu0.l2cache.ReadExReq_hits::cpu0.data 929656 # number of ReadExReq hits
996system.cpu0.l2cache.ReadExReq_hits::total 929656 # number of ReadExReq hits
997system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695648 # number of ReadCleanReq hits
998system.cpu0.l2cache.ReadCleanReq_hits::total 4695648 # number of ReadCleanReq hits
999system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2994194 # number of ReadSharedReq hits
1000system.cpu0.l2cache.ReadSharedReq_hits::total 2994194 # number of ReadSharedReq hits
1001system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216752 # number of InvalidateReq hits
1002system.cpu0.l2cache.InvalidateReq_hits::total 216752 # number of InvalidateReq hits
1003system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267168 # number of demand (read+write) hits
1004system.cpu0.l2cache.demand_hits::cpu0.itb.walker 160390 # number of demand (read+write) hits
1005system.cpu0.l2cache.demand_hits::cpu0.inst 4695648 # number of demand (read+write) hits
1006system.cpu0.l2cache.demand_hits::cpu0.data 3923850 # number of demand (read+write) hits
1007system.cpu0.l2cache.demand_hits::total 9047056 # number of demand (read+write) hits
1008system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267168 # number of overall hits
1009system.cpu0.l2cache.overall_hits::cpu0.itb.walker 160390 # number of overall hits
1010system.cpu0.l2cache.overall_hits::cpu0.inst 4695648 # number of overall hits
1011system.cpu0.l2cache.overall_hits::cpu0.data 3923850 # number of overall hits
1012system.cpu0.l2cache.overall_hits::total 9047056 # number of overall hits
1013system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10276 # number of ReadReq misses
1014system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8531 # number of ReadReq misses
1015system.cpu0.l2cache.ReadReq_misses::total 18807 # number of ReadReq misses
1016system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 247276 # number of UpgradeReq misses
1017system.cpu0.l2cache.UpgradeReq_misses::total 247276 # number of UpgradeReq misses
1018system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195553 # number of SCUpgradeReq misses
1019system.cpu0.l2cache.SCUpgradeReq_misses::total 195553 # number of SCUpgradeReq misses
1020system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 15 # number of SCUpgradeFailReq misses
1021system.cpu0.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses
1022system.cpu0.l2cache.ReadExReq_misses::cpu0.data 259410 # number of ReadExReq misses
1023system.cpu0.l2cache.ReadExReq_misses::total 259410 # number of ReadExReq misses
1024system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 492072 # number of ReadCleanReq misses
1025system.cpu0.l2cache.ReadCleanReq_misses::total 492072 # number of ReadCleanReq misses
1026system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 954718 # number of ReadSharedReq misses
1027system.cpu0.l2cache.ReadSharedReq_misses::total 954718 # number of ReadSharedReq misses
1028system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 574037 # number of InvalidateReq misses
1029system.cpu0.l2cache.InvalidateReq_misses::total 574037 # number of InvalidateReq misses
1030system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10276 # number of demand (read+write) misses
1031system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8531 # number of demand (read+write) misses
1032system.cpu0.l2cache.demand_misses::cpu0.inst 492072 # number of demand (read+write) misses
1033system.cpu0.l2cache.demand_misses::cpu0.data 1214128 # number of demand (read+write) misses
1034system.cpu0.l2cache.demand_misses::total 1725007 # number of demand (read+write) misses
1035system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10276 # number of overall misses
1036system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8531 # number of overall misses
1037system.cpu0.l2cache.overall_misses::cpu0.inst 492072 # number of overall misses
1038system.cpu0.l2cache.overall_misses::cpu0.data 1214128 # number of overall misses
1039system.cpu0.l2cache.overall_misses::total 1725007 # number of overall misses
1040system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 446033500 # number of ReadReq miss cycles
1041system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 421456000 # number of ReadReq miss cycles
1042system.cpu0.l2cache.ReadReq_miss_latency::total 867489500 # number of ReadReq miss cycles
1043system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3471551500 # number of UpgradeReq miss cycles
1044system.cpu0.l2cache.UpgradeReq_miss_latency::total 3471551500 # number of UpgradeReq miss cycles
1045system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2028869500 # number of SCUpgradeReq miss cycles
1046system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2028869500 # number of SCUpgradeReq miss cycles
1047system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6470500 # number of SCUpgradeFailReq miss cycles
1048system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6470500 # number of SCUpgradeFailReq miss cycles
1049system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16372128999 # number of ReadExReq miss cycles
1050system.cpu0.l2cache.ReadExReq_miss_latency::total 16372128999 # number of ReadExReq miss cycles
1051system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 19305851000 # number of ReadCleanReq miss cycles
1052system.cpu0.l2cache.ReadCleanReq_miss_latency::total 19305851000 # number of ReadCleanReq miss cycles
1053system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40062303500 # number of ReadSharedReq miss cycles
1054system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40062303500 # number of ReadSharedReq miss cycles
1055system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62780545000 # number of InvalidateReq miss cycles
1056system.cpu0.l2cache.InvalidateReq_miss_latency::total 62780545000 # number of InvalidateReq miss cycles
1057system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 446033500 # number of demand (read+write) miss cycles
1058system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 421456000 # number of demand (read+write) miss cycles
1059system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19305851000 # number of demand (read+write) miss cycles
1060system.cpu0.l2cache.demand_miss_latency::cpu0.data 56434432499 # number of demand (read+write) miss cycles
1061system.cpu0.l2cache.demand_miss_latency::total 76607772999 # number of demand (read+write) miss cycles
1062system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 446033500 # number of overall miss cycles
1063system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 421456000 # number of overall miss cycles
1064system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19305851000 # number of overall miss cycles
1065system.cpu0.l2cache.overall_miss_latency::cpu0.data 56434432499 # number of overall miss cycles
1066system.cpu0.l2cache.overall_miss_latency::total 76607772999 # number of overall miss cycles
1067system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277444 # number of ReadReq accesses(hits+misses)
1068system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 168921 # number of ReadReq accesses(hits+misses)
1069system.cpu0.l2cache.ReadReq_accesses::total 446365 # number of ReadReq accesses(hits+misses)
1070system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3842470 # number of WritebackDirty accesses(hits+misses)
1071system.cpu0.l2cache.WritebackDirty_accesses::total 3842470 # number of WritebackDirty accesses(hits+misses)
1072system.cpu0.l2cache.WritebackClean_accesses::writebacks 7168468 # number of WritebackClean accesses(hits+misses)
1073system.cpu0.l2cache.WritebackClean_accesses::total 7168468 # number of WritebackClean accesses(hits+misses)
1074system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 247747 # number of UpgradeReq accesses(hits+misses)
1075system.cpu0.l2cache.UpgradeReq_accesses::total 247747 # number of UpgradeReq accesses(hits+misses)
1076system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195553 # number of SCUpgradeReq accesses(hits+misses)
1077system.cpu0.l2cache.SCUpgradeReq_accesses::total 195553 # number of SCUpgradeReq accesses(hits+misses)
1078system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 15 # number of SCUpgradeFailReq accesses(hits+misses)
1079system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses)
1080system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1189066 # number of ReadExReq accesses(hits+misses)
1081system.cpu0.l2cache.ReadExReq_accesses::total 1189066 # number of ReadExReq accesses(hits+misses)
1082system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5187720 # number of ReadCleanReq accesses(hits+misses)
1083system.cpu0.l2cache.ReadCleanReq_accesses::total 5187720 # number of ReadCleanReq accesses(hits+misses)
1084system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3948912 # number of ReadSharedReq accesses(hits+misses)
1085system.cpu0.l2cache.ReadSharedReq_accesses::total 3948912 # number of ReadSharedReq accesses(hits+misses)
1086system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790789 # number of InvalidateReq accesses(hits+misses)
1087system.cpu0.l2cache.InvalidateReq_accesses::total 790789 # number of InvalidateReq accesses(hits+misses)
1088system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277444 # number of demand (read+write) accesses
1089system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 168921 # number of demand (read+write) accesses
1090system.cpu0.l2cache.demand_accesses::cpu0.inst 5187720 # number of demand (read+write) accesses
1091system.cpu0.l2cache.demand_accesses::cpu0.data 5137978 # number of demand (read+write) accesses
1092system.cpu0.l2cache.demand_accesses::total 10772063 # number of demand (read+write) accesses
1093system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277444 # number of overall (read+write) accesses
1094system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 168921 # number of overall (read+write) accesses
1095system.cpu0.l2cache.overall_accesses::cpu0.inst 5187720 # number of overall (read+write) accesses
1096system.cpu0.l2cache.overall_accesses::cpu0.data 5137978 # number of overall (read+write) accesses
1097system.cpu0.l2cache.overall_accesses::total 10772063 # number of overall (read+write) accesses
1098system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037038 # miss rate for ReadReq accesses
1099system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050503 # miss rate for ReadReq accesses
1100system.cpu0.l2cache.ReadReq_miss_rate::total 0.042134 # miss rate for ReadReq accesses
1101system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998099 # miss rate for UpgradeReq accesses
1102system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998099 # miss rate for UpgradeReq accesses
1103system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1104system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1105system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1106system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1107system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.218163 # miss rate for ReadExReq accesses
1108system.cpu0.l2cache.ReadExReq_miss_rate::total 0.218163 # miss rate for ReadExReq accesses
1109system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.094853 # miss rate for ReadCleanReq accesses
1110system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.094853 # miss rate for ReadCleanReq accesses
1111system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.241767 # miss rate for ReadSharedReq accesses
1112system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.241767 # miss rate for ReadSharedReq accesses
1113system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.725904 # miss rate for InvalidateReq accesses
1114system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.725904 # miss rate for InvalidateReq accesses
1115system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037038 # miss rate for demand accesses
1116system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050503 # miss rate for demand accesses
1117system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.094853 # miss rate for demand accesses
1118system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236305 # miss rate for demand accesses
1119system.cpu0.l2cache.demand_miss_rate::total 0.160137 # miss rate for demand accesses
1120system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037038 # miss rate for overall accesses
1121system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050503 # miss rate for overall accesses
1122system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.094853 # miss rate for overall accesses
1123system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236305 # miss rate for overall accesses
1124system.cpu0.l2cache.overall_miss_rate::total 0.160137 # miss rate for overall accesses
1125system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43405.362009 # average ReadReq miss latency
1126system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 49402.883601 # average ReadReq miss latency
1127system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46125.883979 # average ReadReq miss latency
1128system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14039.176871 # average UpgradeReq miss latency
1129system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14039.176871 # average UpgradeReq miss latency
1130system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10375.036435 # average SCUpgradeReq miss latency
1131system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10375.036435 # average SCUpgradeReq miss latency
1132system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 431366.666667 # average SCUpgradeFailReq miss latency
1133system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 431366.666667 # average SCUpgradeFailReq miss latency
1134system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63112.944755 # average ReadExReq miss latency
1135system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63112.944755 # average ReadExReq miss latency
1136system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39233.793022 # average ReadCleanReq miss latency
1137system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39233.793022 # average ReadCleanReq miss latency
1138system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41962.447026 # average ReadSharedReq miss latency
1139system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41962.447026 # average ReadSharedReq miss latency
1140system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 109366.722006 # average InvalidateReq miss latency
1141system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 109366.722006 # average InvalidateReq miss latency
1142system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43405.362009 # average overall miss latency
1143system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 49402.883601 # average overall miss latency
1144system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39233.793022 # average overall miss latency
1145system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46481.452120 # average overall miss latency
1146system.cpu0.l2cache.demand_avg_miss_latency::total 44410.122973 # average overall miss latency
1147system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43405.362009 # average overall miss latency
1148system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 49402.883601 # average overall miss latency
1149system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39233.793022 # average overall miss latency
1150system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46481.452120 # average overall miss latency
1151system.cpu0.l2cache.overall_avg_miss_latency::total 44410.122973 # average overall miss latency
1152system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1153system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1154system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1155system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1156system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1157system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1158system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1159system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1160system.cpu0.l2cache.writebacks::writebacks 1553882 # number of writebacks
1161system.cpu0.l2cache.writebacks::total 1553882 # number of writebacks
1162system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5243 # number of ReadExReq MSHR hits
1163system.cpu0.l2cache.ReadExReq_mshr_hits::total 5243 # number of ReadExReq MSHR hits
1164system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 604 # number of ReadSharedReq MSHR hits
1165system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 604 # number of ReadSharedReq MSHR hits
1166system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5847 # number of demand (read+write) MSHR hits
1167system.cpu0.l2cache.demand_mshr_hits::total 5847 # number of demand (read+write) MSHR hits
1168system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5847 # number of overall MSHR hits
1169system.cpu0.l2cache.overall_mshr_hits::total 5847 # number of overall MSHR hits
1170system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10276 # number of ReadReq MSHR misses
1171system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8531 # number of ReadReq MSHR misses
1172system.cpu0.l2cache.ReadReq_mshr_misses::total 18807 # number of ReadReq MSHR misses
1173system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 729213 # number of HardPFReq MSHR misses
1174system.cpu0.l2cache.HardPFReq_mshr_misses::total 729213 # number of HardPFReq MSHR misses
1175system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 247276 # number of UpgradeReq MSHR misses
1176system.cpu0.l2cache.UpgradeReq_mshr_misses::total 247276 # number of UpgradeReq MSHR misses
1177system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195553 # number of SCUpgradeReq MSHR misses
1178system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195553 # number of SCUpgradeReq MSHR misses
1179system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 15 # number of SCUpgradeFailReq MSHR misses
1180system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses
1181system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 254167 # number of ReadExReq MSHR misses
1182system.cpu0.l2cache.ReadExReq_mshr_misses::total 254167 # number of ReadExReq MSHR misses
1183system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 492072 # number of ReadCleanReq MSHR misses
1184system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 492072 # number of ReadCleanReq MSHR misses
1185system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 954114 # number of ReadSharedReq MSHR misses
1186system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 954114 # number of ReadSharedReq MSHR misses
1187system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 574037 # number of InvalidateReq MSHR misses
1188system.cpu0.l2cache.InvalidateReq_mshr_misses::total 574037 # number of InvalidateReq MSHR misses
1189system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10276 # number of demand (read+write) MSHR misses
1190system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8531 # number of demand (read+write) MSHR misses
1191system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 492072 # number of demand (read+write) MSHR misses
1192system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1208281 # number of demand (read+write) MSHR misses
1193system.cpu0.l2cache.demand_mshr_misses::total 1719160 # number of demand (read+write) MSHR misses
1194system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10276 # number of overall MSHR misses
1195system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8531 # number of overall MSHR misses
1196system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 492072 # number of overall MSHR misses
1197system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1208281 # number of overall MSHR misses
1198system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 729213 # number of overall MSHR misses
1199system.cpu0.l2cache.overall_mshr_misses::total 2448373 # number of overall MSHR misses
1200system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
1201system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable
1202system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 58117 # number of ReadReq MSHR uncacheable
1203system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable
1204system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15725 # number of WriteReq MSHR uncacheable
1205system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
1206system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses
1207system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 73842 # number of overall MSHR uncacheable misses
1208system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 384377500 # number of ReadReq MSHR miss cycles
1209system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 370270000 # number of ReadReq MSHR miss cycles
1210system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 754647500 # number of ReadReq MSHR miss cycles
1211system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39166505132 # number of HardPFReq MSHR miss cycles
1212system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 39166505132 # number of HardPFReq MSHR miss cycles
1213system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7760971000 # number of UpgradeReq MSHR miss cycles
1214system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7760971000 # number of UpgradeReq MSHR miss cycles
1215system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4006997499 # number of SCUpgradeReq MSHR miss cycles
1216system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4006997499 # number of SCUpgradeReq MSHR miss cycles
1217system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6014500 # number of SCUpgradeFailReq MSHR miss cycles
1218system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6014500 # number of SCUpgradeFailReq MSHR miss cycles
1219system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14251828999 # number of ReadExReq MSHR miss cycles
1220system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14251828999 # number of ReadExReq MSHR miss cycles
1221system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16353419000 # number of ReadCleanReq MSHR miss cycles
1222system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16353419000 # number of ReadCleanReq MSHR miss cycles
1223system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34284773000 # number of ReadSharedReq MSHR miss cycles
1224system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34284773000 # number of ReadSharedReq MSHR miss cycles
1225system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 59336323000 # number of InvalidateReq MSHR miss cycles
1226system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 59336323000 # number of InvalidateReq MSHR miss cycles
1227system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 384377500 # number of demand (read+write) MSHR miss cycles
1228system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 370270000 # number of demand (read+write) MSHR miss cycles
1229system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16353419000 # number of demand (read+write) MSHR miss cycles
1230system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 48536601999 # number of demand (read+write) MSHR miss cycles
1231system.cpu0.l2cache.demand_mshr_miss_latency::total 65644668499 # number of demand (read+write) MSHR miss cycles
1232system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 384377500 # number of overall MSHR miss cycles
1233system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 370270000 # number of overall MSHR miss cycles
1234system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16353419000 # number of overall MSHR miss cycles
1235system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 48536601999 # number of overall MSHR miss cycles
1236system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39166505132 # number of overall MSHR miss cycles
1237system.cpu0.l2cache.overall_mshr_miss_latency::total 104811173631 # number of overall MSHR miss cycles
1238system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles
1239system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2464927000 # number of ReadReq MSHR uncacheable cycles
1240system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8095698500 # number of ReadReq MSHR uncacheable cycles
1241system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2535920000 # number of WriteReq MSHR uncacheable cycles
1242system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2535920000 # number of WriteReq MSHR uncacheable cycles
1243system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles
1244system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5000847000 # number of overall MSHR uncacheable cycles
1245system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10631618500 # number of overall MSHR uncacheable cycles
1246system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037038 # mshr miss rate for ReadReq accesses
1247system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050503 # mshr miss rate for ReadReq accesses
1248system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadReq accesses
1249system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1250system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1251system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998099 # mshr miss rate for UpgradeReq accesses
1252system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998099 # mshr miss rate for UpgradeReq accesses
1253system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1254system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1255system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1256system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1257system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213753 # mshr miss rate for ReadExReq accesses
1258system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213753 # mshr miss rate for ReadExReq accesses
1259system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.094853 # mshr miss rate for ReadCleanReq accesses
1260system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094853 # mshr miss rate for ReadCleanReq accesses
1261system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241614 # mshr miss rate for ReadSharedReq accesses
1262system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241614 # mshr miss rate for ReadSharedReq accesses
1263system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.725904 # mshr miss rate for InvalidateReq accesses
1264system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.725904 # mshr miss rate for InvalidateReq accesses
1265system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037038 # mshr miss rate for demand accesses
1266system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050503 # mshr miss rate for demand accesses
1267system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.094853 # mshr miss rate for demand accesses
1268system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235167 # mshr miss rate for demand accesses
1269system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159594 # mshr miss rate for demand accesses
1270system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037038 # mshr miss rate for overall accesses
1271system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050503 # mshr miss rate for overall accesses
1272system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.094853 # mshr miss rate for overall accesses
1273system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235167 # mshr miss rate for overall accesses
1274system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1275system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227289 # mshr miss rate for overall accesses
1276system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average ReadReq mshr miss latency
1277system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average ReadReq mshr miss latency
1278system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40125.883979 # average ReadReq mshr miss latency
1279system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average HardPFReq mshr miss latency
1280system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53710.651253 # average HardPFReq mshr miss latency
1281system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31385.864378 # average UpgradeReq mshr miss latency
1282system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31385.864378 # average UpgradeReq mshr miss latency
1283system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20490.595895 # average SCUpgradeReq mshr miss latency
1284system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20490.595895 # average SCUpgradeReq mshr miss latency
1285system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400966.666667 # average SCUpgradeFailReq mshr miss latency
1286system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400966.666667 # average SCUpgradeFailReq mshr miss latency
1287system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56072.696294 # average ReadExReq mshr miss latency
1288system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56072.696294 # average ReadExReq mshr miss latency
1289system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average ReadCleanReq mshr miss latency
1290system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33233.793022 # average ReadCleanReq mshr miss latency
1291system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35933.623236 # average ReadSharedReq mshr miss latency
1292system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35933.623236 # average ReadSharedReq mshr miss latency
1293system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 103366.722006 # average InvalidateReq mshr miss latency
1294system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 103366.722006 # average InvalidateReq mshr miss latency
1295system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency
1296system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency
1297system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency
1298system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency
1299system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38184.153016 # average overall mshr miss latency
1300system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency
1301system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency
1302system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency
1303system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency
1304system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average overall mshr miss latency
1305system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42808.499208 # average overall mshr miss latency
1306system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency
1307system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164416.155283 # average ReadReq mshr uncacheable latency
1308system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139300.006883 # average ReadReq mshr uncacheable latency
1309system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161266.772655 # average WriteReq mshr uncacheable latency
1310system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161266.772655 # average WriteReq mshr uncacheable latency
1311system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency
1312system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 162803.887098 # average overall mshr uncacheable latency
1313system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143977.932613 # average overall mshr uncacheable latency
1314system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1315system.cpu0.toL2Bus.snoop_filter.tot_requests 22819923 # Total number of requests made to the snoop filter.
1316system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11703604 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1317system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1318system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879398 # Total number of snoops made to the snoop filter.
1319system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879148 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1320system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 250 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1321system.cpu0.toL2Bus.trans_dist::ReadReq 571604 # Transaction distribution
1322system.cpu0.toL2Bus.trans_dist::ReadResp 9815849 # Transaction distribution
1323system.cpu0.toL2Bus.trans_dist::WriteReq 15726 # Transaction distribution
1324system.cpu0.toL2Bus.trans_dist::WriteResp 15725 # Transaction distribution
1325system.cpu0.toL2Bus.trans_dist::WritebackDirty 5399709 # Transaction distribution
1326system.cpu0.toL2Bus.trans_dist::WritebackClean 7169213 # Transaction distribution
1327system.cpu0.toL2Bus.trans_dist::CleanEvict 2378526 # Transaction distribution
1328system.cpu0.toL2Bus.trans_dist::HardPFReq 893354 # Transaction distribution
1329system.cpu0.toL2Bus.trans_dist::UpgradeReq 436778 # Transaction distribution
1330system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 349583 # Transaction distribution
1331system.cpu0.toL2Bus.trans_dist::UpgradeResp 518285 # Transaction distribution
1332system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution
1333system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution
1334system.cpu0.toL2Bus.trans_dist::ReadExReq 1259427 # Transaction distribution
1335system.cpu0.toL2Bus.trans_dist::ReadExResp 1201684 # Transaction distribution
1336system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5187720 # Transaction distribution
1337system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4806547 # Transaction distribution
1338system.cpu0.toL2Bus.trans_dist::InvalidateReq 796318 # Transaction distribution
1339system.cpu0.toL2Bus.trans_dist::InvalidateResp 790789 # Transaction distribution
1340system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15648898 # Packet count per connected master and slave (bytes)
1341system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18825417 # Packet count per connected master and slave (bytes)
1342system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 354875 # Packet count per connected master and slave (bytes)
1343system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 604975 # Packet count per connected master and slave (bytes)
1344system.cpu0.toL2Bus.pkt_count::total 35434165 # Packet count per connected master and slave (bytes)
1345system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 664167892 # Cumulative packet size per connected master and slave (bytes)
1346system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 709387519 # Cumulative packet size per connected master and slave (bytes)
1347system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1351368 # Cumulative packet size per connected master and slave (bytes)
1348system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2219552 # Cumulative packet size per connected master and slave (bytes)
1349system.cpu0.toL2Bus.pkt_size::total 1377126331 # Cumulative packet size per connected master and slave (bytes)
1350system.cpu0.toL2Bus.snoops 6368237 # Total snoops (count)
1351system.cpu0.toL2Bus.snoop_fanout::samples 18252902 # Request fanout histogram
1352system.cpu0.toL2Bus.snoop_fanout::mean 0.116630 # Request fanout histogram
1353system.cpu0.toL2Bus.snoop_fanout::stdev 0.321021 # Request fanout histogram
1354system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1355system.cpu0.toL2Bus.snoop_fanout::0 16124321 88.34% 88.34% # Request fanout histogram
1356system.cpu0.toL2Bus.snoop_fanout::1 2128331 11.66% 100.00% # Request fanout histogram
1357system.cpu0.toL2Bus.snoop_fanout::2 250 0.00% 100.00% # Request fanout histogram
1358system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1359system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1360system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1361system.cpu0.toL2Bus.snoop_fanout::total 18252902 # Request fanout histogram
1362system.cpu0.toL2Bus.reqLayer0.occupancy 22598952997 # Layer occupancy (ticks)
1363system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1364system.cpu0.toL2Bus.snoopLayer0.occupancy 218107077 # Layer occupancy (ticks)
1365system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1366system.cpu0.toL2Bus.respLayer0.occupancy 7824705000 # Layer occupancy (ticks)
1367system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1368system.cpu0.toL2Bus.respLayer1.occupancy 8347252415 # Layer occupancy (ticks)
1369system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1370system.cpu0.toL2Bus.respLayer2.occupancy 185954998 # Layer occupancy (ticks)
1371system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1372system.cpu0.toL2Bus.respLayer3.occupancy 327531000 # Layer occupancy (ticks)
1373system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1374system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1375system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1376system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1377system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1378system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1379system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1380system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

1395system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1396system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1397system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1398system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1399system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1400system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1401system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1402system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1403system.cpu1.dtb.walker.walks 91986 # Table walker walks requested
1404system.cpu1.dtb.walker.walksLong 91986 # Table walker walks initiated with long descriptors
1405system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7535 # Level at which table walker walks with long descriptors terminate
1406system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69987 # Level at which table walker walks with long descriptors terminate
1407system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
1408system.cpu1.dtb.walker.walkWaitTime::samples 91981 # Table walker wait (enqueue to first request) latency
1409system.cpu1.dtb.walker.walkWaitTime::mean 0.271795 # Table walker wait (enqueue to first request) latency
1410system.cpu1.dtb.walker.walkWaitTime::stdev 82.431072 # Table walker wait (enqueue to first request) latency
1411system.cpu1.dtb.walker.walkWaitTime::0-2047 91980 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1412system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1413system.cpu1.dtb.walker.walkWaitTime::total 91981 # Table walker wait (enqueue to first request) latency
1414system.cpu1.dtb.walker.walkCompletionTime::samples 77527 # Table walker service (enqueue to completion) latency
1415system.cpu1.dtb.walker.walkCompletionTime::mean 23020.089775 # Table walker service (enqueue to completion) latency
1416system.cpu1.dtb.walker.walkCompletionTime::gmean 21173.462910 # Table walker service (enqueue to completion) latency
1417system.cpu1.dtb.walker.walkCompletionTime::stdev 18225.313395 # Table walker service (enqueue to completion) latency
1418system.cpu1.dtb.walker.walkCompletionTime::0-65535 76677 98.90% 98.90% # Table walker service (enqueue to completion) latency
1419system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.21% 99.12% # Table walker service (enqueue to completion) latency
1420system.cpu1.dtb.walker.walkCompletionTime::131072-196607 586 0.76% 99.87% # Table walker service (enqueue to completion) latency
1421system.cpu1.dtb.walker.walkCompletionTime::196608-262143 21 0.03% 99.90% # Table walker service (enqueue to completion) latency
1422system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
1423system.cpu1.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.95% # Table walker service (enqueue to completion) latency
1424system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.03% 99.98% # Table walker service (enqueue to completion) latency
1425system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
1426system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1427system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1428system.cpu1.dtb.walker.walkCompletionTime::total 77527 # Table walker service (enqueue to completion) latency
1429system.cpu1.dtb.walker.walksPending::samples -5562525576 # Table walker pending requests distribution
1430system.cpu1.dtb.walker.walksPending::mean 0.783829 # Table walker pending requests distribution
1431system.cpu1.dtb.walker.walksPending::stdev 0.411632 # Table walker pending requests distribution
1432system.cpu1.dtb.walker.walksPending::0 -1202455220 21.62% 21.62% # Table walker pending requests distribution
1433system.cpu1.dtb.walker.walksPending::1 -4360070356 78.38% 100.00% # Table walker pending requests distribution
1434system.cpu1.dtb.walker.walksPending::total -5562525576 # Table walker pending requests distribution
1435system.cpu1.dtb.walker.walkPageSizes::4K 69988 90.28% 90.28% # Table walker page sizes translated
1436system.cpu1.dtb.walker.walkPageSizes::2M 7535 9.72% 100.00% # Table walker page sizes translated
1437system.cpu1.dtb.walker.walkPageSizes::total 77523 # Table walker page sizes translated
1438system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 91986 # Table walker requests started/completed, data/inst
1439system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1440system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 91986 # Table walker requests started/completed, data/inst
1441system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77523 # Table walker requests started/completed, data/inst
1442system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1443system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77523 # Table walker requests started/completed, data/inst
1444system.cpu1.dtb.walker.walkRequestOrigin::total 169509 # Table walker requests started/completed, data/inst
1445system.cpu1.dtb.inst_hits 0 # ITB inst hits
1446system.cpu1.dtb.inst_misses 0 # ITB inst misses
1447system.cpu1.dtb.read_hits 75524944 # DTB read hits
1448system.cpu1.dtb.read_misses 67300 # DTB read misses
1449system.cpu1.dtb.write_hits 69031204 # DTB write hits
1450system.cpu1.dtb.write_misses 24686 # DTB write misses
1451system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1452system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1453system.cpu1.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
1454system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
1455system.cpu1.dtb.flush_entries 34037 # Number of entries that have been flushed from TLB
1456system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1457system.cpu1.dtb.prefetch_faults 4586 # Number of TLB faults due to prefetch
1458system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1459system.cpu1.dtb.perms_faults 9261 # Number of TLB faults due to permissions restrictions
1460system.cpu1.dtb.read_accesses 75592244 # DTB read accesses
1461system.cpu1.dtb.write_accesses 69055890 # DTB write accesses
1462system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1463system.cpu1.dtb.hits 144556148 # DTB hits
1464system.cpu1.dtb.misses 91986 # DTB misses
1465system.cpu1.dtb.accesses 144648134 # DTB accesses
1466system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1467system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1468system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1469system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1470system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1471system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1472system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1473system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1487system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1488system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1489system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1490system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1491system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1492system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1493system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1494system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1495system.cpu1.itb.walker.walks 54155 # Table walker walks requested
1496system.cpu1.itb.walker.walksLong 54155 # Table walker walks initiated with long descriptors
1497system.cpu1.itb.walker.walksLongTerminationLevel::Level2 390 # Level at which table walker walks with long descriptors terminate
1498system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48650 # Level at which table walker walks with long descriptors terminate
1499system.cpu1.itb.walker.walkWaitTime::samples 54155 # Table walker wait (enqueue to first request) latency
1500system.cpu1.itb.walker.walkWaitTime::0 54155 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1501system.cpu1.itb.walker.walkWaitTime::total 54155 # Table walker wait (enqueue to first request) latency
1502system.cpu1.itb.walker.walkCompletionTime::samples 49040 # Table walker service (enqueue to completion) latency
1503system.cpu1.itb.walker.walkCompletionTime::mean 26306.504894 # Table walker service (enqueue to completion) latency
1504system.cpu1.itb.walker.walkCompletionTime::gmean 23642.829205 # Table walker service (enqueue to completion) latency
1505system.cpu1.itb.walker.walkCompletionTime::stdev 24027.787857 # Table walker service (enqueue to completion) latency
1506system.cpu1.itb.walker.walkCompletionTime::0-65535 48185 98.26% 98.26% # Table walker service (enqueue to completion) latency
1507system.cpu1.itb.walker.walkCompletionTime::65536-131071 51 0.10% 98.36% # Table walker service (enqueue to completion) latency
1508system.cpu1.itb.walker.walkCompletionTime::131072-196607 689 1.40% 99.77% # Table walker service (enqueue to completion) latency
1509system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.04% 99.81% # Table walker service (enqueue to completion) latency
1510system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency
1511system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.92% # Table walker service (enqueue to completion) latency
1512system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency
1513system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
1514system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
1515system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1516system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1517system.cpu1.itb.walker.walkCompletionTime::total 49040 # Table walker service (enqueue to completion) latency
1518system.cpu1.itb.walker.walksPending::samples -2103778220 # Table walker pending requests distribution
1519system.cpu1.itb.walker.walksPending::0 -2103778220 100.00% 100.00% # Table walker pending requests distribution
1520system.cpu1.itb.walker.walksPending::total -2103778220 # Table walker pending requests distribution
1521system.cpu1.itb.walker.walkPageSizes::4K 48650 99.20% 99.20% # Table walker page sizes translated
1522system.cpu1.itb.walker.walkPageSizes::2M 390 0.80% 100.00% # Table walker page sizes translated
1523system.cpu1.itb.walker.walkPageSizes::total 49040 # Table walker page sizes translated
1524system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1525system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54155 # Table walker requests started/completed, data/inst
1526system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54155 # Table walker requests started/completed, data/inst
1527system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1528system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49040 # Table walker requests started/completed, data/inst
1529system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49040 # Table walker requests started/completed, data/inst
1530system.cpu1.itb.walker.walkRequestOrigin::total 103195 # Table walker requests started/completed, data/inst
1531system.cpu1.itb.inst_hits 400011912 # ITB inst hits
1532system.cpu1.itb.inst_misses 54155 # ITB inst misses
1533system.cpu1.itb.read_hits 0 # DTB read hits
1534system.cpu1.itb.read_misses 0 # DTB read misses
1535system.cpu1.itb.write_hits 0 # DTB write hits
1536system.cpu1.itb.write_misses 0 # DTB write misses
1537system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1538system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1539system.cpu1.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID
1540system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
1541system.cpu1.itb.flush_entries 23432 # Number of entries that have been flushed from TLB
1542system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1543system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1544system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1545system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1546system.cpu1.itb.read_accesses 0 # DTB read accesses
1547system.cpu1.itb.write_accesses 0 # DTB write accesses
1548system.cpu1.itb.inst_accesses 400066067 # ITB inst accesses
1549system.cpu1.itb.hits 400011912 # DTB hits
1550system.cpu1.itb.misses 54155 # DTB misses
1551system.cpu1.itb.accesses 400066067 # DTB accesses
1552system.cpu1.numCycles 95204836507 # number of cpu cycles simulated
1553system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1554system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1555system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1556system.cpu1.kern.inst.quiesce 14080 # number of quiesce instructions executed
1557system.cpu1.committedInsts 399717589 # Number of instructions committed
1558system.cpu1.committedOps 471481802 # Number of ops (including micro ops) committed
1559system.cpu1.num_int_alu_accesses 433690793 # Number of integer alu accesses
1560system.cpu1.num_fp_alu_accesses 447669 # Number of float alu accesses
1561system.cpu1.num_func_calls 24290810 # number of times a function call or return occured
1562system.cpu1.num_conditional_control_insts 60559296 # number of instructions that are conditional controls
1563system.cpu1.num_int_insts 433690793 # number of integer instructions
1564system.cpu1.num_fp_insts 447669 # number of float instructions
1565system.cpu1.num_int_register_reads 628918503 # number of times the integer registers were read
1566system.cpu1.num_int_register_writes 343906147 # number of times the integer registers were written
1567system.cpu1.num_fp_register_reads 709471 # number of times the floating registers were read
1568system.cpu1.num_fp_register_writes 405960 # number of times the floating registers were written
1569system.cpu1.num_cc_register_reads 102969972 # number of times the CC registers were read
1570system.cpu1.num_cc_register_writes 102767338 # number of times the CC registers were written
1571system.cpu1.num_mem_refs 144547138 # number of memory refs
1572system.cpu1.num_load_insts 75521772 # Number of load instructions
1573system.cpu1.num_store_insts 69025366 # Number of store instructions
1574system.cpu1.num_idle_cycles 94207572529.552017 # Number of idle cycles
1575system.cpu1.num_busy_cycles 997263977.447979 # Number of busy cycles
1576system.cpu1.not_idle_fraction 0.010475 # Percentage of non-idle cycles
1577system.cpu1.idle_fraction 0.989525 # Percentage of idle cycles
1578system.cpu1.Branches 89155171 # Number of branches fetched
1579system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
1580system.cpu1.op_class::IntAlu 326125112 69.13% 69.13% # Class of executed instruction
1581system.cpu1.op_class::IntMult 978063 0.21% 69.33% # Class of executed instruction
1582system.cpu1.op_class::IntDiv 57214 0.01% 69.35% # Class of executed instruction
1583system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction
1584system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction
1585system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction
1586system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction
1587system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction
1588system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction
1589system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction
1590system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction
1591system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction
1592system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction
1593system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction
1594system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction
1595system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction
1596system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction
1597system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction
1598system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction
1599system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction
1600system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction
1601system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction
1602system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction
1603system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction
1604system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction
1605system.cpu1.op_class::SimdFloatMisc 68664 0.01% 69.36% # Class of executed instruction
1606system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction
1607system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction
1608system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction
1609system.cpu1.op_class::MemRead 75521772 16.01% 85.37% # Class of executed instruction
1610system.cpu1.op_class::MemWrite 69025366 14.63% 100.00% # Class of executed instruction
1611system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1612system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1613system.cpu1.op_class::total 471776234 # Class of executed instruction
1614system.cpu1.dcache.tags.replacements 4623789 # number of replacements
1615system.cpu1.dcache.tags.tagsinuse 430.899907 # Cycle average of tags in use
1616system.cpu1.dcache.tags.total_refs 139725575 # Total number of references to valid blocks.
1617system.cpu1.dcache.tags.sampled_refs 4624300 # Sample count of references to valid blocks.
1618system.cpu1.dcache.tags.avg_refs 30.215508 # Average number of references to valid blocks.
1619system.cpu1.dcache.tags.warmup_cycle 8408408114000 # Cycle when the warmup percentage was hit.
1620system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.899907 # Average occupied blocks per requestor
1621system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841601 # Average percentage of cache occupancy
1622system.cpu1.dcache.tags.occ_percent::total 0.841601 # Average percentage of cache occupancy
1623system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1624system.cpu1.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
1625system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id
1626system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
1627system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1628system.cpu1.dcache.tags.tag_accesses 293714645 # Number of tag accesses
1629system.cpu1.dcache.tags.data_accesses 293714645 # Number of data accesses
1630system.cpu1.dcache.ReadReq_hits::cpu1.data 70428619 # number of ReadReq hits
1631system.cpu1.dcache.ReadReq_hits::total 70428619 # number of ReadReq hits
1632system.cpu1.dcache.WriteReq_hits::cpu1.data 65452147 # number of WriteReq hits
1633system.cpu1.dcache.WriteReq_hits::total 65452147 # number of WriteReq hits
1634system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175356 # number of SoftPFReq hits
1635system.cpu1.dcache.SoftPFReq_hits::total 175356 # number of SoftPFReq hits
1636system.cpu1.dcache.WriteLineReq_hits::cpu1.data 181976 # number of WriteLineReq hits
1637system.cpu1.dcache.WriteLineReq_hits::total 181976 # number of WriteLineReq hits
1638system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1569435 # number of LoadLockedReq hits
1639system.cpu1.dcache.LoadLockedReq_hits::total 1569435 # number of LoadLockedReq hits
1640system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1531483 # number of StoreCondReq hits
1641system.cpu1.dcache.StoreCondReq_hits::total 1531483 # number of StoreCondReq hits
1642system.cpu1.dcache.demand_hits::cpu1.data 135880766 # number of demand (read+write) hits
1643system.cpu1.dcache.demand_hits::total 135880766 # number of demand (read+write) hits
1644system.cpu1.dcache.overall_hits::cpu1.data 136056122 # number of overall hits
1645system.cpu1.dcache.overall_hits::total 136056122 # number of overall hits
1646system.cpu1.dcache.ReadReq_misses::cpu1.data 2625513 # number of ReadReq misses
1647system.cpu1.dcache.ReadReq_misses::total 2625513 # number of ReadReq misses
1648system.cpu1.dcache.WriteReq_misses::cpu1.data 1190956 # number of WriteReq misses
1649system.cpu1.dcache.WriteReq_misses::total 1190956 # number of WriteReq misses
1650system.cpu1.dcache.SoftPFReq_misses::cpu1.data 551150 # number of SoftPFReq misses
1651system.cpu1.dcache.SoftPFReq_misses::total 551150 # number of SoftPFReq misses
1652system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454381 # number of WriteLineReq misses
1653system.cpu1.dcache.WriteLineReq_misses::total 454381 # number of WriteLineReq misses
1654system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150766 # number of LoadLockedReq misses
1655system.cpu1.dcache.LoadLockedReq_misses::total 150766 # number of LoadLockedReq misses
1656system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187526 # number of StoreCondReq misses
1657system.cpu1.dcache.StoreCondReq_misses::total 187526 # number of StoreCondReq misses
1658system.cpu1.dcache.demand_misses::cpu1.data 3816469 # number of demand (read+write) misses
1659system.cpu1.dcache.demand_misses::total 3816469 # number of demand (read+write) misses
1660system.cpu1.dcache.overall_misses::cpu1.data 4367619 # number of overall misses
1661system.cpu1.dcache.overall_misses::total 4367619 # number of overall misses
1662system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39306904500 # number of ReadReq miss cycles
1663system.cpu1.dcache.ReadReq_miss_latency::total 39306904500 # number of ReadReq miss cycles
1664system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28030249500 # number of WriteReq miss cycles
1665system.cpu1.dcache.WriteReq_miss_latency::total 28030249500 # number of WriteReq miss cycles
1666system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20535959500 # number of WriteLineReq miss cycles
1667system.cpu1.dcache.WriteLineReq_miss_latency::total 20535959500 # number of WriteLineReq miss cycles
1668system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2343079000 # number of LoadLockedReq miss cycles
1669system.cpu1.dcache.LoadLockedReq_miss_latency::total 2343079000 # number of LoadLockedReq miss cycles
1670system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5222807000 # number of StoreCondReq miss cycles
1671system.cpu1.dcache.StoreCondReq_miss_latency::total 5222807000 # number of StoreCondReq miss cycles
1672system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5948500 # number of StoreCondFailReq miss cycles
1673system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5948500 # number of StoreCondFailReq miss cycles
1674system.cpu1.dcache.demand_miss_latency::cpu1.data 67337154000 # number of demand (read+write) miss cycles
1675system.cpu1.dcache.demand_miss_latency::total 67337154000 # number of demand (read+write) miss cycles
1676system.cpu1.dcache.overall_miss_latency::cpu1.data 67337154000 # number of overall miss cycles
1677system.cpu1.dcache.overall_miss_latency::total 67337154000 # number of overall miss cycles
1678system.cpu1.dcache.ReadReq_accesses::cpu1.data 73054132 # number of ReadReq accesses(hits+misses)
1679system.cpu1.dcache.ReadReq_accesses::total 73054132 # number of ReadReq accesses(hits+misses)
1680system.cpu1.dcache.WriteReq_accesses::cpu1.data 66643103 # number of WriteReq accesses(hits+misses)
1681system.cpu1.dcache.WriteReq_accesses::total 66643103 # number of WriteReq accesses(hits+misses)
1682system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 726506 # number of SoftPFReq accesses(hits+misses)
1683system.cpu1.dcache.SoftPFReq_accesses::total 726506 # number of SoftPFReq accesses(hits+misses)
1684system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 636357 # number of WriteLineReq accesses(hits+misses)
1685system.cpu1.dcache.WriteLineReq_accesses::total 636357 # number of WriteLineReq accesses(hits+misses)
1686system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1720201 # number of LoadLockedReq accesses(hits+misses)
1687system.cpu1.dcache.LoadLockedReq_accesses::total 1720201 # number of LoadLockedReq accesses(hits+misses)
1688system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1719009 # number of StoreCondReq accesses(hits+misses)
1689system.cpu1.dcache.StoreCondReq_accesses::total 1719009 # number of StoreCondReq accesses(hits+misses)
1690system.cpu1.dcache.demand_accesses::cpu1.data 139697235 # number of demand (read+write) accesses
1691system.cpu1.dcache.demand_accesses::total 139697235 # number of demand (read+write) accesses
1692system.cpu1.dcache.overall_accesses::cpu1.data 140423741 # number of overall (read+write) accesses
1693system.cpu1.dcache.overall_accesses::total 140423741 # number of overall (read+write) accesses
1694system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035939 # miss rate for ReadReq accesses
1695system.cpu1.dcache.ReadReq_miss_rate::total 0.035939 # miss rate for ReadReq accesses
1696system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017871 # miss rate for WriteReq accesses
1697system.cpu1.dcache.WriteReq_miss_rate::total 0.017871 # miss rate for WriteReq accesses
1698system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.758631 # miss rate for SoftPFReq accesses
1699system.cpu1.dcache.SoftPFReq_miss_rate::total 0.758631 # miss rate for SoftPFReq accesses
1700system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.714035 # miss rate for WriteLineReq accesses
1701system.cpu1.dcache.WriteLineReq_miss_rate::total 0.714035 # miss rate for WriteLineReq accesses
1702system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087644 # miss rate for LoadLockedReq accesses
1703system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087644 # miss rate for LoadLockedReq accesses
1704system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109090 # miss rate for StoreCondReq accesses
1705system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109090 # miss rate for StoreCondReq accesses
1706system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027320 # miss rate for demand accesses
1707system.cpu1.dcache.demand_miss_rate::total 0.027320 # miss rate for demand accesses
1708system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031103 # miss rate for overall accesses
1709system.cpu1.dcache.overall_miss_rate::total 0.031103 # miss rate for overall accesses
1710system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.133070 # average ReadReq miss latency
1711system.cpu1.dcache.ReadReq_avg_miss_latency::total 14971.133070 # average ReadReq miss latency
1712system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23535.923661 # average WriteReq miss latency
1713system.cpu1.dcache.WriteReq_avg_miss_latency::total 23535.923661 # average WriteReq miss latency
1714system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45195.462618 # average WriteLineReq miss latency
1715system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45195.462618 # average WriteLineReq miss latency
1716system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15541.163127 # average LoadLockedReq miss latency
1717system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15541.163127 # average LoadLockedReq miss latency
1718system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27851.108646 # average StoreCondReq miss latency
1719system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27851.108646 # average StoreCondReq miss latency
1720system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1721system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1722system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17643.836227 # average overall miss latency
1723system.cpu1.dcache.demand_avg_miss_latency::total 17643.836227 # average overall miss latency
1724system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15417.359893 # average overall miss latency
1725system.cpu1.dcache.overall_avg_miss_latency::total 15417.359893 # average overall miss latency
1726system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1727system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1728system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1729system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1730system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1731system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1732system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1733system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1734system.cpu1.dcache.writebacks::writebacks 4623789 # number of writebacks
1735system.cpu1.dcache.writebacks::total 4623789 # number of writebacks
1736system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13826 # number of ReadReq MSHR hits
1737system.cpu1.dcache.ReadReq_mshr_hits::total 13826 # number of ReadReq MSHR hits
1738system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 458 # number of WriteReq MSHR hits
1739system.cpu1.dcache.WriteReq_mshr_hits::total 458 # number of WriteReq MSHR hits
1740system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43478 # number of LoadLockedReq MSHR hits
1741system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43478 # number of LoadLockedReq MSHR hits
1742system.cpu1.dcache.demand_mshr_hits::cpu1.data 14284 # number of demand (read+write) MSHR hits
1743system.cpu1.dcache.demand_mshr_hits::total 14284 # number of demand (read+write) MSHR hits
1744system.cpu1.dcache.overall_mshr_hits::cpu1.data 14284 # number of overall MSHR hits
1745system.cpu1.dcache.overall_mshr_hits::total 14284 # number of overall MSHR hits
1746system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2611687 # number of ReadReq MSHR misses
1747system.cpu1.dcache.ReadReq_mshr_misses::total 2611687 # number of ReadReq MSHR misses
1748system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1190498 # number of WriteReq MSHR misses
1749system.cpu1.dcache.WriteReq_mshr_misses::total 1190498 # number of WriteReq MSHR misses
1750system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 551150 # number of SoftPFReq MSHR misses
1751system.cpu1.dcache.SoftPFReq_mshr_misses::total 551150 # number of SoftPFReq MSHR misses
1752system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454381 # number of WriteLineReq MSHR misses
1753system.cpu1.dcache.WriteLineReq_mshr_misses::total 454381 # number of WriteLineReq MSHR misses
1754system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 107288 # number of LoadLockedReq MSHR misses
1755system.cpu1.dcache.LoadLockedReq_mshr_misses::total 107288 # number of LoadLockedReq MSHR misses
1756system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187526 # number of StoreCondReq MSHR misses
1757system.cpu1.dcache.StoreCondReq_mshr_misses::total 187526 # number of StoreCondReq MSHR misses
1758system.cpu1.dcache.demand_mshr_misses::cpu1.data 3802185 # number of demand (read+write) MSHR misses
1759system.cpu1.dcache.demand_mshr_misses::total 3802185 # number of demand (read+write) MSHR misses
1760system.cpu1.dcache.overall_mshr_misses::cpu1.data 4353335 # number of overall MSHR misses
1761system.cpu1.dcache.overall_mshr_misses::total 4353335 # number of overall MSHR misses
1762system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 24123 # number of ReadReq MSHR uncacheable
1763system.cpu1.dcache.ReadReq_mshr_uncacheable::total 24123 # number of ReadReq MSHR uncacheable
1764system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 23288 # number of WriteReq MSHR uncacheable
1765system.cpu1.dcache.WriteReq_mshr_uncacheable::total 23288 # number of WriteReq MSHR uncacheable
1766system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 47411 # number of overall MSHR uncacheable misses
1767system.cpu1.dcache.overall_mshr_uncacheable_misses::total 47411 # number of overall MSHR uncacheable misses
1768system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35578565500 # number of ReadReq MSHR miss cycles
1769system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35578565500 # number of ReadReq MSHR miss cycles
1770system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26805763500 # number of WriteReq MSHR miss cycles
1771system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26805763500 # number of WriteReq MSHR miss cycles
1772system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12511151000 # number of SoftPFReq MSHR miss cycles
1773system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12511151000 # number of SoftPFReq MSHR miss cycles
1774system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20081578500 # number of WriteLineReq MSHR miss cycles
1775system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20081578500 # number of WriteLineReq MSHR miss cycles
1776system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1492978000 # number of LoadLockedReq MSHR miss cycles
1777system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1492978000 # number of LoadLockedReq MSHR miss cycles
1778system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035346000 # number of StoreCondReq MSHR miss cycles
1779system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035346000 # number of StoreCondReq MSHR miss cycles
1780system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5883500 # number of StoreCondFailReq MSHR miss cycles
1781system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5883500 # number of StoreCondFailReq MSHR miss cycles
1782system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62384329000 # number of demand (read+write) MSHR miss cycles
1783system.cpu1.dcache.demand_mshr_miss_latency::total 62384329000 # number of demand (read+write) MSHR miss cycles
1784system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74895480000 # number of overall MSHR miss cycles
1785system.cpu1.dcache.overall_mshr_miss_latency::total 74895480000 # number of overall MSHR miss cycles
1786system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4378993500 # number of ReadReq MSHR uncacheable cycles
1787system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4378993500 # number of ReadReq MSHR uncacheable cycles
1788system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4297960500 # number of WriteReq MSHR uncacheable cycles
1789system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4297960500 # number of WriteReq MSHR uncacheable cycles
1790system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8676954000 # number of overall MSHR uncacheable cycles
1791system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8676954000 # number of overall MSHR uncacheable cycles
1792system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035750 # mshr miss rate for ReadReq accesses
1793system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035750 # mshr miss rate for ReadReq accesses
1794system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017864 # mshr miss rate for WriteReq accesses
1795system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017864 # mshr miss rate for WriteReq accesses
1796system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758631 # mshr miss rate for SoftPFReq accesses
1797system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.758631 # mshr miss rate for SoftPFReq accesses
1798system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714035 # mshr miss rate for WriteLineReq accesses
1799system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.714035 # mshr miss rate for WriteLineReq accesses
1800system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062369 # mshr miss rate for LoadLockedReq accesses
1801system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062369 # mshr miss rate for LoadLockedReq accesses
1802system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109090 # mshr miss rate for StoreCondReq accesses
1803system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109090 # mshr miss rate for StoreCondReq accesses
1804system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027217 # mshr miss rate for demand accesses
1805system.cpu1.dcache.demand_mshr_miss_rate::total 0.027217 # mshr miss rate for demand accesses
1806system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031001 # mshr miss rate for overall accesses
1807system.cpu1.dcache.overall_mshr_miss_rate::total 0.031001 # mshr miss rate for overall accesses
1808system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13622.829037 # average ReadReq mshr miss latency
1809system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13622.829037 # average ReadReq mshr miss latency
1810system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22516.428839 # average WriteReq mshr miss latency
1811system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22516.428839 # average WriteReq mshr miss latency
1812system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22700.083462 # average SoftPFReq mshr miss latency
1813system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22700.083462 # average SoftPFReq mshr miss latency
1814system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44195.462618 # average WriteLineReq mshr miss latency
1815system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44195.462618 # average WriteLineReq mshr miss latency
1816system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13915.610320 # average LoadLockedReq mshr miss latency
1817system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13915.610320 # average LoadLockedReq mshr miss latency
1818system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26851.455265 # average StoreCondReq mshr miss latency
1819system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26851.455265 # average StoreCondReq mshr miss latency
1820system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1821system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1822system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16407.494375 # average overall mshr miss latency
1823system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16407.494375 # average overall mshr miss latency
1824system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17204.161867 # average overall mshr miss latency
1825system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17204.161867 # average overall mshr miss latency
1826system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181527.732869 # average ReadReq mshr uncacheable latency
1827system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181527.732869 # average ReadReq mshr uncacheable latency
1828system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 184556.874785 # average WriteReq mshr uncacheable latency
1829system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184556.874785 # average WriteReq mshr uncacheable latency
1830system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 183015.629284 # average overall mshr uncacheable latency
1831system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 183015.629284 # average overall mshr uncacheable latency
1832system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1833system.cpu1.icache.tags.replacements 4822868 # number of replacements
1834system.cpu1.icache.tags.tagsinuse 495.969838 # Cycle average of tags in use
1835system.cpu1.icache.tags.total_refs 395188527 # Total number of references to valid blocks.
1836system.cpu1.icache.tags.sampled_refs 4823380 # Sample count of references to valid blocks.
1837system.cpu1.icache.tags.avg_refs 81.931867 # Average number of references to valid blocks.
1838system.cpu1.icache.tags.warmup_cycle 8408376446000 # Cycle when the warmup percentage was hit.
1839system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.969838 # Average occupied blocks per requestor
1840system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968691 # Average percentage of cache occupancy
1841system.cpu1.icache.tags.occ_percent::total 0.968691 # Average percentage of cache occupancy
1842system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1843system.cpu1.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
1844system.cpu1.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id
1845system.cpu1.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
1846system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1847system.cpu1.icache.tags.tag_accesses 804847209 # Number of tag accesses
1848system.cpu1.icache.tags.data_accesses 804847209 # Number of data accesses
1849system.cpu1.icache.ReadReq_hits::cpu1.inst 395188527 # number of ReadReq hits
1850system.cpu1.icache.ReadReq_hits::total 395188527 # number of ReadReq hits
1851system.cpu1.icache.demand_hits::cpu1.inst 395188527 # number of demand (read+write) hits
1852system.cpu1.icache.demand_hits::total 395188527 # number of demand (read+write) hits
1853system.cpu1.icache.overall_hits::cpu1.inst 395188527 # number of overall hits
1854system.cpu1.icache.overall_hits::total 395188527 # number of overall hits
1855system.cpu1.icache.ReadReq_misses::cpu1.inst 4823385 # number of ReadReq misses
1856system.cpu1.icache.ReadReq_misses::total 4823385 # number of ReadReq misses
1857system.cpu1.icache.demand_misses::cpu1.inst 4823385 # number of demand (read+write) misses
1858system.cpu1.icache.demand_misses::total 4823385 # number of demand (read+write) misses
1859system.cpu1.icache.overall_misses::cpu1.inst 4823385 # number of overall misses
1860system.cpu1.icache.overall_misses::total 4823385 # number of overall misses
1861system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52228876500 # number of ReadReq miss cycles
1862system.cpu1.icache.ReadReq_miss_latency::total 52228876500 # number of ReadReq miss cycles
1863system.cpu1.icache.demand_miss_latency::cpu1.inst 52228876500 # number of demand (read+write) miss cycles
1864system.cpu1.icache.demand_miss_latency::total 52228876500 # number of demand (read+write) miss cycles
1865system.cpu1.icache.overall_miss_latency::cpu1.inst 52228876500 # number of overall miss cycles
1866system.cpu1.icache.overall_miss_latency::total 52228876500 # number of overall miss cycles
1867system.cpu1.icache.ReadReq_accesses::cpu1.inst 400011912 # number of ReadReq accesses(hits+misses)
1868system.cpu1.icache.ReadReq_accesses::total 400011912 # number of ReadReq accesses(hits+misses)
1869system.cpu1.icache.demand_accesses::cpu1.inst 400011912 # number of demand (read+write) accesses
1870system.cpu1.icache.demand_accesses::total 400011912 # number of demand (read+write) accesses
1871system.cpu1.icache.overall_accesses::cpu1.inst 400011912 # number of overall (read+write) accesses
1872system.cpu1.icache.overall_accesses::total 400011912 # number of overall (read+write) accesses
1873system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012058 # miss rate for ReadReq accesses
1874system.cpu1.icache.ReadReq_miss_rate::total 0.012058 # miss rate for ReadReq accesses
1875system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012058 # miss rate for demand accesses
1876system.cpu1.icache.demand_miss_rate::total 0.012058 # miss rate for demand accesses
1877system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012058 # miss rate for overall accesses
1878system.cpu1.icache.overall_miss_rate::total 0.012058 # miss rate for overall accesses
1879system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10828.261999 # average ReadReq miss latency
1880system.cpu1.icache.ReadReq_avg_miss_latency::total 10828.261999 # average ReadReq miss latency
1881system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10828.261999 # average overall miss latency
1882system.cpu1.icache.demand_avg_miss_latency::total 10828.261999 # average overall miss latency
1883system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10828.261999 # average overall miss latency
1884system.cpu1.icache.overall_avg_miss_latency::total 10828.261999 # average overall miss latency
1885system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1886system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1887system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1888system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1889system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1890system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1891system.cpu1.icache.fast_writes 0 # number of fast writes performed
1892system.cpu1.icache.cache_copies 0 # number of cache copies performed
1893system.cpu1.icache.writebacks::writebacks 4822868 # number of writebacks
1894system.cpu1.icache.writebacks::total 4822868 # number of writebacks
1895system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4823385 # number of ReadReq MSHR misses
1896system.cpu1.icache.ReadReq_mshr_misses::total 4823385 # number of ReadReq MSHR misses
1897system.cpu1.icache.demand_mshr_misses::cpu1.inst 4823385 # number of demand (read+write) MSHR misses
1898system.cpu1.icache.demand_mshr_misses::total 4823385 # number of demand (read+write) MSHR misses
1899system.cpu1.icache.overall_mshr_misses::cpu1.inst 4823385 # number of overall MSHR misses
1900system.cpu1.icache.overall_mshr_misses::total 4823385 # number of overall MSHR misses
1901system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
1902system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable
1903system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
1904system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses
1905system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49817184000 # number of ReadReq MSHR miss cycles
1906system.cpu1.icache.ReadReq_mshr_miss_latency::total 49817184000 # number of ReadReq MSHR miss cycles
1907system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49817184000 # number of demand (read+write) MSHR miss cycles
1908system.cpu1.icache.demand_mshr_miss_latency::total 49817184000 # number of demand (read+write) MSHR miss cycles
1909system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49817184000 # number of overall MSHR miss cycles
1910system.cpu1.icache.overall_mshr_miss_latency::total 49817184000 # number of overall MSHR miss cycles
1911system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14655500 # number of ReadReq MSHR uncacheable cycles
1912system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14655500 # number of ReadReq MSHR uncacheable cycles
1913system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14655500 # number of overall MSHR uncacheable cycles
1914system.cpu1.icache.overall_mshr_uncacheable_latency::total 14655500 # number of overall MSHR uncacheable cycles
1915system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012058 # mshr miss rate for ReadReq accesses
1916system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012058 # mshr miss rate for ReadReq accesses
1917system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012058 # mshr miss rate for demand accesses
1918system.cpu1.icache.demand_mshr_miss_rate::total 0.012058 # mshr miss rate for demand accesses
1919system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012058 # mshr miss rate for overall accesses
1920system.cpu1.icache.overall_mshr_miss_rate::total 0.012058 # mshr miss rate for overall accesses
1921system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average ReadReq mshr miss latency
1922system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10328.261999 # average ReadReq mshr miss latency
1923system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average overall mshr miss latency
1924system.cpu1.icache.demand_avg_mshr_miss_latency::total 10328.261999 # average overall mshr miss latency
1925system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10328.261999 # average overall mshr miss latency
1926system.cpu1.icache.overall_avg_mshr_miss_latency::total 10328.261999 # average overall mshr miss latency
1927system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182 # average ReadReq mshr uncacheable latency
1928system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133231.818182 # average ReadReq mshr uncacheable latency
1929system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133231.818182 # average overall mshr uncacheable latency
1930system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133231.818182 # average overall mshr uncacheable latency
1931system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1932system.cpu1.l2cache.prefetcher.num_hwpf_issued 6259356 # number of hwpf issued
1933system.cpu1.l2cache.prefetcher.pfIdentified 6259387 # number of prefetch candidates identified
1934system.cpu1.l2cache.prefetcher.pfBufferHit 27 # number of redundant prefetches already in prefetch queue
1935system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1936system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1937system.cpu1.l2cache.prefetcher.pfSpanPage 793397 # number of prefetches not generated due to page crossing
1938system.cpu1.l2cache.tags.replacements 1777622 # number of replacements
1939system.cpu1.l2cache.tags.tagsinuse 13086.026545 # Cycle average of tags in use
1940system.cpu1.l2cache.tags.total_refs 13889107 # Total number of references to valid blocks.
1941system.cpu1.l2cache.tags.sampled_refs 1793675 # Sample count of references to valid blocks.
1942system.cpu1.l2cache.tags.avg_refs 7.743380 # Average number of references to valid blocks.
1943system.cpu1.l2cache.tags.warmup_cycle 10216605092500 # Cycle when the warmup percentage was hit.
1944system.cpu1.l2cache.tags.occ_blocks::writebacks 11949.147964 # Average occupied blocks per requestor
1945system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 18.692431 # Average occupied blocks per requestor
1946system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.350132 # Average occupied blocks per requestor
1947system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1106.836018 # Average occupied blocks per requestor
1948system.cpu1.l2cache.tags.occ_percent::writebacks 0.729318 # Average percentage of cache occupancy
1949system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001141 # Average percentage of cache occupancy
1950system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000693 # Average percentage of cache occupancy
1951system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.067556 # Average percentage of cache occupancy
1952system.cpu1.l2cache.tags.occ_percent::total 0.798708 # Average percentage of cache occupancy
1953system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1073 # Occupied blocks per task id
1954system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id
1955system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14890 # Occupied blocks per task id
1956system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
1957system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 279 # Occupied blocks per task id
1958system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id
1959system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id
1960system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
1961system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 80 # Occupied blocks per task id
1962system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
1963system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
1964system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 993 # Occupied blocks per task id
1965system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4499 # Occupied blocks per task id
1966system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8129 # Occupied blocks per task id
1967system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id
1968system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.065491 # Percentage of cache occupancy per task id
1969system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id
1970system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908813 # Percentage of cache occupancy per task id
1971system.cpu1.l2cache.tags.tag_accesses 320280578 # Number of tag accesses
1972system.cpu1.l2cache.tags.data_accesses 320280578 # Number of data accesses
1973system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 210783 # number of ReadReq hits
1974system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138334 # number of ReadReq hits
1975system.cpu1.l2cache.ReadReq_hits::total 349117 # number of ReadReq hits
1976system.cpu1.l2cache.WritebackDirty_hits::writebacks 2929003 # number of WritebackDirty hits
1977system.cpu1.l2cache.WritebackDirty_hits::total 2929003 # number of WritebackDirty hits
1978system.cpu1.l2cache.WritebackClean_hits::writebacks 6516555 # number of WritebackClean hits
1979system.cpu1.l2cache.WritebackClean_hits::total 6516555 # number of WritebackClean hits
1980system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 209 # number of UpgradeReq hits
1981system.cpu1.l2cache.UpgradeReq_hits::total 209 # number of UpgradeReq hits
1982system.cpu1.l2cache.ReadExReq_hits::cpu1.data 752189 # number of ReadExReq hits
1983system.cpu1.l2cache.ReadExReq_hits::total 752189 # number of ReadExReq hits
1984system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4404363 # number of ReadCleanReq hits
1985system.cpu1.l2cache.ReadCleanReq_hits::total 4404363 # number of ReadCleanReq hits
1986system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2449744 # number of ReadSharedReq hits
1987system.cpu1.l2cache.ReadSharedReq_hits::total 2449744 # number of ReadSharedReq hits
1988system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191107 # number of InvalidateReq hits
1989system.cpu1.l2cache.InvalidateReq_hits::total 191107 # number of InvalidateReq hits
1990system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 210783 # number of demand (read+write) hits
1991system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138334 # number of demand (read+write) hits
1992system.cpu1.l2cache.demand_hits::cpu1.inst 4404363 # number of demand (read+write) hits
1993system.cpu1.l2cache.demand_hits::cpu1.data 3201933 # number of demand (read+write) hits
1994system.cpu1.l2cache.demand_hits::total 7955413 # number of demand (read+write) hits
1995system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 210783 # number of overall hits
1996system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138334 # number of overall hits
1997system.cpu1.l2cache.overall_hits::cpu1.inst 4404363 # number of overall hits
1998system.cpu1.l2cache.overall_hits::cpu1.data 3201933 # number of overall hits
1999system.cpu1.l2cache.overall_hits::total 7955413 # number of overall hits
2000system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9658 # number of ReadReq misses
2001system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8230 # number of ReadReq misses
2002system.cpu1.l2cache.ReadReq_misses::total 17888 # number of ReadReq misses
2003system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 199042 # number of UpgradeReq misses
2004system.cpu1.l2cache.UpgradeReq_misses::total 199042 # number of UpgradeReq misses
2005system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187508 # number of SCUpgradeReq misses
2006system.cpu1.l2cache.SCUpgradeReq_misses::total 187508 # number of SCUpgradeReq misses
2007system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 18 # number of SCUpgradeFailReq misses
2008system.cpu1.l2cache.SCUpgradeFailReq_misses::total 18 # number of SCUpgradeFailReq misses
2009system.cpu1.l2cache.ReadExReq_misses::cpu1.data 241510 # number of ReadExReq misses
2010system.cpu1.l2cache.ReadExReq_misses::total 241510 # number of ReadExReq misses
2011system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 419022 # number of ReadCleanReq misses
2012system.cpu1.l2cache.ReadCleanReq_misses::total 419022 # number of ReadCleanReq misses
2013system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 820381 # number of ReadSharedReq misses
2014system.cpu1.l2cache.ReadSharedReq_misses::total 820381 # number of ReadSharedReq misses
2015system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261023 # number of InvalidateReq misses
2016system.cpu1.l2cache.InvalidateReq_misses::total 261023 # number of InvalidateReq misses
2017system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9658 # number of demand (read+write) misses
2018system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8230 # number of demand (read+write) misses
2019system.cpu1.l2cache.demand_misses::cpu1.inst 419022 # number of demand (read+write) misses
2020system.cpu1.l2cache.demand_misses::cpu1.data 1061891 # number of demand (read+write) misses
2021system.cpu1.l2cache.demand_misses::total 1498801 # number of demand (read+write) misses
2022system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9658 # number of overall misses
2023system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8230 # number of overall misses
2024system.cpu1.l2cache.overall_misses::cpu1.inst 419022 # number of overall misses
2025system.cpu1.l2cache.overall_misses::cpu1.data 1061891 # number of overall misses
2026system.cpu1.l2cache.overall_misses::total 1498801 # number of overall misses
2027system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 365970000 # number of ReadReq miss cycles
2028system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 332045500 # number of ReadReq miss cycles
2029system.cpu1.l2cache.ReadReq_miss_latency::total 698015500 # number of ReadReq miss cycles
2030system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3049287500 # number of UpgradeReq miss cycles
2031system.cpu1.l2cache.UpgradeReq_miss_latency::total 3049287500 # number of UpgradeReq miss cycles
2032system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1869580500 # number of SCUpgradeReq miss cycles
2033system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1869580500 # number of SCUpgradeReq miss cycles
2034system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5786000 # number of SCUpgradeFailReq miss cycles
2035system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5786000 # number of SCUpgradeFailReq miss cycles
2036system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12702911999 # number of ReadExReq miss cycles
2037system.cpu1.l2cache.ReadExReq_miss_latency::total 12702911999 # number of ReadExReq miss cycles
2038system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16109032000 # number of ReadCleanReq miss cycles
2039system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16109032000 # number of ReadCleanReq miss cycles
2040system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28713782500 # number of ReadSharedReq miss cycles
2041system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28713782500 # number of ReadSharedReq miss cycles
2042system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18098463500 # number of InvalidateReq miss cycles
2043system.cpu1.l2cache.InvalidateReq_miss_latency::total 18098463500 # number of InvalidateReq miss cycles
2044system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 365970000 # number of demand (read+write) miss cycles
2045system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 332045500 # number of demand (read+write) miss cycles
2046system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16109032000 # number of demand (read+write) miss cycles
2047system.cpu1.l2cache.demand_miss_latency::cpu1.data 41416694499 # number of demand (read+write) miss cycles
2048system.cpu1.l2cache.demand_miss_latency::total 58223741999 # number of demand (read+write) miss cycles
2049system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 365970000 # number of overall miss cycles
2050system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 332045500 # number of overall miss cycles
2051system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16109032000 # number of overall miss cycles
2052system.cpu1.l2cache.overall_miss_latency::cpu1.data 41416694499 # number of overall miss cycles
2053system.cpu1.l2cache.overall_miss_latency::total 58223741999 # number of overall miss cycles
2054system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 220441 # number of ReadReq accesses(hits+misses)
2055system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 146564 # number of ReadReq accesses(hits+misses)
2056system.cpu1.l2cache.ReadReq_accesses::total 367005 # number of ReadReq accesses(hits+misses)
2057system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2929003 # number of WritebackDirty accesses(hits+misses)
2058system.cpu1.l2cache.WritebackDirty_accesses::total 2929003 # number of WritebackDirty accesses(hits+misses)
2059system.cpu1.l2cache.WritebackClean_accesses::writebacks 6516555 # number of WritebackClean accesses(hits+misses)
2060system.cpu1.l2cache.WritebackClean_accesses::total 6516555 # number of WritebackClean accesses(hits+misses)
2061system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 199251 # number of UpgradeReq accesses(hits+misses)
2062system.cpu1.l2cache.UpgradeReq_accesses::total 199251 # number of UpgradeReq accesses(hits+misses)
2063system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187508 # number of SCUpgradeReq accesses(hits+misses)
2064system.cpu1.l2cache.SCUpgradeReq_accesses::total 187508 # number of SCUpgradeReq accesses(hits+misses)
2065system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 18 # number of SCUpgradeFailReq accesses(hits+misses)
2066system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 18 # number of SCUpgradeFailReq accesses(hits+misses)
2067system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 993699 # number of ReadExReq accesses(hits+misses)
2068system.cpu1.l2cache.ReadExReq_accesses::total 993699 # number of ReadExReq accesses(hits+misses)
2069system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4823385 # number of ReadCleanReq accesses(hits+misses)
2070system.cpu1.l2cache.ReadCleanReq_accesses::total 4823385 # number of ReadCleanReq accesses(hits+misses)
2071system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3270125 # number of ReadSharedReq accesses(hits+misses)
2072system.cpu1.l2cache.ReadSharedReq_accesses::total 3270125 # number of ReadSharedReq accesses(hits+misses)
2073system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 452130 # number of InvalidateReq accesses(hits+misses)
2074system.cpu1.l2cache.InvalidateReq_accesses::total 452130 # number of InvalidateReq accesses(hits+misses)
2075system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 220441 # number of demand (read+write) accesses
2076system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 146564 # number of demand (read+write) accesses
2077system.cpu1.l2cache.demand_accesses::cpu1.inst 4823385 # number of demand (read+write) accesses
2078system.cpu1.l2cache.demand_accesses::cpu1.data 4263824 # number of demand (read+write) accesses
2079system.cpu1.l2cache.demand_accesses::total 9454214 # number of demand (read+write) accesses
2080system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 220441 # number of overall (read+write) accesses
2081system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 146564 # number of overall (read+write) accesses
2082system.cpu1.l2cache.overall_accesses::cpu1.inst 4823385 # number of overall (read+write) accesses
2083system.cpu1.l2cache.overall_accesses::cpu1.data 4263824 # number of overall (read+write) accesses
2084system.cpu1.l2cache.overall_accesses::total 9454214 # number of overall (read+write) accesses
2085system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.043812 # miss rate for ReadReq accesses
2086system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.056153 # miss rate for ReadReq accesses
2087system.cpu1.l2cache.ReadReq_miss_rate::total 0.048740 # miss rate for ReadReq accesses
2088system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998951 # miss rate for UpgradeReq accesses
2089system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998951 # miss rate for UpgradeReq accesses
2090system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2091system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2092system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2093system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2094system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.243041 # miss rate for ReadExReq accesses
2095system.cpu1.l2cache.ReadExReq_miss_rate::total 0.243041 # miss rate for ReadExReq accesses
2096system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.086873 # miss rate for ReadCleanReq accesses
2097system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.086873 # miss rate for ReadCleanReq accesses
2098system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.250871 # miss rate for ReadSharedReq accesses
2099system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.250871 # miss rate for ReadSharedReq accesses
2100system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.577318 # miss rate for InvalidateReq accesses
2101system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.577318 # miss rate for InvalidateReq accesses
2102system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.043812 # miss rate for demand accesses
2103system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.056153 # miss rate for demand accesses
2104system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086873 # miss rate for demand accesses
2105system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.249047 # miss rate for demand accesses
2106system.cpu1.l2cache.demand_miss_rate::total 0.158533 # miss rate for demand accesses
2107system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.043812 # miss rate for overall accesses
2108system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.056153 # miss rate for overall accesses
2109system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086873 # miss rate for overall accesses
2110system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.249047 # miss rate for overall accesses
2111system.cpu1.l2cache.overall_miss_rate::total 0.158533 # miss rate for overall accesses
2112system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37892.938497 # average ReadReq miss latency
2113system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40345.747266 # average ReadReq miss latency
2114system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39021.438953 # average ReadReq miss latency
2115system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15319.819435 # average UpgradeReq miss latency
2116system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15319.819435 # average UpgradeReq miss latency
2117system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9970.670585 # average SCUpgradeReq miss latency
2118system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9970.670585 # average SCUpgradeReq miss latency
2119system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 321444.444444 # average SCUpgradeFailReq miss latency
2120system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 321444.444444 # average SCUpgradeFailReq miss latency
2121system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52597.871720 # average ReadExReq miss latency
2122system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52597.871720 # average ReadExReq miss latency
2123system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38444.358530 # average ReadCleanReq miss latency
2124system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38444.358530 # average ReadCleanReq miss latency
2125system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.545478 # average ReadSharedReq miss latency
2126system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.545478 # average ReadSharedReq miss latency
2127system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69336.661903 # average InvalidateReq miss latency
2128system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69336.661903 # average InvalidateReq miss latency
2129system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37892.938497 # average overall miss latency
2130system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40345.747266 # average overall miss latency
2131system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38444.358530 # average overall miss latency
2132system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39002.773824 # average overall miss latency
2133system.cpu1.l2cache.demand_avg_miss_latency::total 38846.879605 # average overall miss latency
2134system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37892.938497 # average overall miss latency
2135system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40345.747266 # average overall miss latency
2136system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38444.358530 # average overall miss latency
2137system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39002.773824 # average overall miss latency
2138system.cpu1.l2cache.overall_avg_miss_latency::total 38846.879605 # average overall miss latency
2139system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2140system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2141system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2142system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2143system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2144system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2145system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2146system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2147system.cpu1.l2cache.writebacks::writebacks 999911 # number of writebacks
2148system.cpu1.l2cache.writebacks::total 999911 # number of writebacks
2149system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3856 # number of ReadExReq MSHR hits
2150system.cpu1.l2cache.ReadExReq_mshr_hits::total 3856 # number of ReadExReq MSHR hits
2151system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 484 # number of ReadSharedReq MSHR hits
2152system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 484 # number of ReadSharedReq MSHR hits
2153system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
2154system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
2155system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4340 # number of demand (read+write) MSHR hits
2156system.cpu1.l2cache.demand_mshr_hits::total 4340 # number of demand (read+write) MSHR hits
2157system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4340 # number of overall MSHR hits
2158system.cpu1.l2cache.overall_mshr_hits::total 4340 # number of overall MSHR hits
2159system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9658 # number of ReadReq MSHR misses
2160system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8230 # number of ReadReq MSHR misses
2161system.cpu1.l2cache.ReadReq_mshr_misses::total 17888 # number of ReadReq MSHR misses
2162system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 596510 # number of HardPFReq MSHR misses
2163system.cpu1.l2cache.HardPFReq_mshr_misses::total 596510 # number of HardPFReq MSHR misses
2164system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 199042 # number of UpgradeReq MSHR misses
2165system.cpu1.l2cache.UpgradeReq_mshr_misses::total 199042 # number of UpgradeReq MSHR misses
2166system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 187508 # number of SCUpgradeReq MSHR misses
2167system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 187508 # number of SCUpgradeReq MSHR misses
2168system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 18 # number of SCUpgradeFailReq MSHR misses
2169system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 18 # number of SCUpgradeFailReq MSHR misses
2170system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237654 # number of ReadExReq MSHR misses
2171system.cpu1.l2cache.ReadExReq_mshr_misses::total 237654 # number of ReadExReq MSHR misses
2172system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 419022 # number of ReadCleanReq MSHR misses
2173system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 419022 # number of ReadCleanReq MSHR misses
2174system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 819897 # number of ReadSharedReq MSHR misses
2175system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 819897 # number of ReadSharedReq MSHR misses
2176system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 261021 # number of InvalidateReq MSHR misses
2177system.cpu1.l2cache.InvalidateReq_mshr_misses::total 261021 # number of InvalidateReq MSHR misses
2178system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9658 # number of demand (read+write) MSHR misses
2179system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8230 # number of demand (read+write) MSHR misses
2180system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 419022 # number of demand (read+write) MSHR misses
2181system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1057551 # number of demand (read+write) MSHR misses
2182system.cpu1.l2cache.demand_mshr_misses::total 1494461 # number of demand (read+write) MSHR misses
2183system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9658 # number of overall MSHR misses
2184system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8230 # number of overall MSHR misses
2185system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 419022 # number of overall MSHR misses
2186system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1057551 # number of overall MSHR misses
2187system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 596510 # number of overall MSHR misses
2188system.cpu1.l2cache.overall_mshr_misses::total 2090971 # number of overall MSHR misses
2189system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2190system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 24123 # number of ReadReq MSHR uncacheable
2191system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 24233 # number of ReadReq MSHR uncacheable
2192system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 23288 # number of WriteReq MSHR uncacheable
2193system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 23288 # number of WriteReq MSHR uncacheable
2194system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2195system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 47411 # number of overall MSHR uncacheable misses
2196system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 47521 # number of overall MSHR uncacheable misses
2197system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 308022000 # number of ReadReq MSHR miss cycles
2198system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 282665500 # number of ReadReq MSHR miss cycles
2199system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 590687500 # number of ReadReq MSHR miss cycles
2200system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26979236218 # number of HardPFReq MSHR miss cycles
2201system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26979236218 # number of HardPFReq MSHR miss cycles
2202system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6259584005 # number of UpgradeReq MSHR miss cycles
2203system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6259584005 # number of UpgradeReq MSHR miss cycles
2204system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3627729000 # number of SCUpgradeReq MSHR miss cycles
2205system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3627729000 # number of SCUpgradeReq MSHR miss cycles
2206system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5396000 # number of SCUpgradeFailReq MSHR miss cycles
2207system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5396000 # number of SCUpgradeFailReq MSHR miss cycles
2208system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10808104999 # number of ReadExReq MSHR miss cycles
2209system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10808104999 # number of ReadExReq MSHR miss cycles
2210system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13594900000 # number of ReadCleanReq MSHR miss cycles
2211system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13594900000 # number of ReadCleanReq MSHR miss cycles
2212system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 23755841000 # number of ReadSharedReq MSHR miss cycles
2213system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 23755841000 # number of ReadSharedReq MSHR miss cycles
2214system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16532269500 # number of InvalidateReq MSHR miss cycles
2215system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16532269500 # number of InvalidateReq MSHR miss cycles
2216system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 308022000 # number of demand (read+write) MSHR miss cycles
2217system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 282665500 # number of demand (read+write) MSHR miss cycles
2218system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13594900000 # number of demand (read+write) MSHR miss cycles
2219system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34563945999 # number of demand (read+write) MSHR miss cycles
2220system.cpu1.l2cache.demand_mshr_miss_latency::total 48749533499 # number of demand (read+write) MSHR miss cycles
2221system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 308022000 # number of overall MSHR miss cycles
2222system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 282665500 # number of overall MSHR miss cycles
2223system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13594900000 # number of overall MSHR miss cycles
2224system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34563945999 # number of overall MSHR miss cycles
2225system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26979236218 # number of overall MSHR miss cycles
2226system.cpu1.l2cache.overall_mshr_miss_latency::total 75728769717 # number of overall MSHR miss cycles
2227system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13830500 # number of ReadReq MSHR uncacheable cycles
2228system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4185464000 # number of ReadReq MSHR uncacheable cycles
2229system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4199294500 # number of ReadReq MSHR uncacheable cycles
2230system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 4122722000 # number of WriteReq MSHR uncacheable cycles
2231system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 4122722000 # number of WriteReq MSHR uncacheable cycles
2232system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13830500 # number of overall MSHR uncacheable cycles
2233system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8308186000 # number of overall MSHR uncacheable cycles
2234system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8322016500 # number of overall MSHR uncacheable cycles
2235system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for ReadReq accesses
2236system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for ReadReq accesses
2237system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.048740 # mshr miss rate for ReadReq accesses
2238system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2239system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2240system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998951 # mshr miss rate for UpgradeReq accesses
2241system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998951 # mshr miss rate for UpgradeReq accesses
2242system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2243system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2244system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2245system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2246system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239161 # mshr miss rate for ReadExReq accesses
2247system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239161 # mshr miss rate for ReadExReq accesses
2248system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for ReadCleanReq accesses
2249system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086873 # mshr miss rate for ReadCleanReq accesses
2250system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.250723 # mshr miss rate for ReadSharedReq accesses
2251system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250723 # mshr miss rate for ReadSharedReq accesses
2252system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.577314 # mshr miss rate for InvalidateReq accesses
2253system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.577314 # mshr miss rate for InvalidateReq accesses
2254system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for demand accesses
2255system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for demand accesses
2256system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for demand accesses
2257system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248029 # mshr miss rate for demand accesses
2258system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158074 # mshr miss rate for demand accesses
2259system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.043812 # mshr miss rate for overall accesses
2260system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.056153 # mshr miss rate for overall accesses
2261system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086873 # mshr miss rate for overall accesses
2262system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248029 # mshr miss rate for overall accesses
2263system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2264system.cpu1.l2cache.overall_mshr_miss_rate::total 0.221168 # mshr miss rate for overall accesses
2265system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average ReadReq mshr miss latency
2266system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average ReadReq mshr miss latency
2267system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33021.438953 # average ReadReq mshr miss latency
2268system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average HardPFReq mshr miss latency
2269system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45228.472646 # average HardPFReq mshr miss latency
2270system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31448.558621 # average UpgradeReq mshr miss latency
2271system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31448.558621 # average UpgradeReq mshr miss latency
2272system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19347.062525 # average SCUpgradeReq mshr miss latency
2273system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19347.062525 # average SCUpgradeReq mshr miss latency
2274system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 299777.777778 # average SCUpgradeFailReq mshr miss latency
2275system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 299777.777778 # average SCUpgradeFailReq mshr miss latency
2276system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45478.321421 # average ReadExReq mshr miss latency
2277system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45478.321421 # average ReadExReq mshr miss latency
2278system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average ReadCleanReq mshr miss latency
2279system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32444.358530 # average ReadCleanReq mshr miss latency
2280system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28974.177244 # average ReadSharedReq mshr miss latency
2281system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28974.177244 # average ReadSharedReq mshr miss latency
2282system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63336.932661 # average InvalidateReq mshr miss latency
2283system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63336.932661 # average InvalidateReq mshr miss latency
2284system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency
2285system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency
2286system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency
2287system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency
2288system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32620.144319 # average overall mshr miss latency
2289system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency
2290system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency
2291system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency
2292system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency
2293system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average overall mshr miss latency
2294system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36217.034917 # average overall mshr miss latency
2295system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average ReadReq mshr uncacheable latency
2296system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173505.119595 # average ReadReq mshr uncacheable latency
2297system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173288.263938 # average ReadReq mshr uncacheable latency
2298system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177032.033665 # average WriteReq mshr uncacheable latency
2299system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 177032.033665 # average WriteReq mshr uncacheable latency
2300system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average overall mshr uncacheable latency
2301system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 175237.518719 # average overall mshr uncacheable latency
2302system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 175122.924602 # average overall mshr uncacheable latency
2303system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2304system.cpu1.toL2Bus.snoop_filter.tot_requests 19593534 # Total number of requests made to the snoop filter.
2305system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10054336 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2306system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1096 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2307system.cpu1.toL2Bus.snoop_filter.tot_snoops 1611494 # Total number of snoops made to the snoop filter.
2308system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1611307 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2309system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2310system.cpu1.toL2Bus.trans_dist::ReadReq 454071 # Transaction distribution
2311system.cpu1.toL2Bus.trans_dist::ReadResp 8632529 # Transaction distribution
2312system.cpu1.toL2Bus.trans_dist::WriteReq 23288 # Transaction distribution
2313system.cpu1.toL2Bus.trans_dist::WriteResp 23288 # Transaction distribution
2314system.cpu1.toL2Bus.trans_dist::WritebackDirty 3935373 # Transaction distribution
2315system.cpu1.toL2Bus.trans_dist::WritebackClean 6517651 # Transaction distribution
2316system.cpu1.toL2Bus.trans_dist::CleanEvict 2069350 # Transaction distribution
2317system.cpu1.toL2Bus.trans_dist::HardPFReq 732453 # Transaction distribution
2318system.cpu1.toL2Bus.trans_dist::UpgradeReq 387389 # Transaction distribution
2319system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344195 # Transaction distribution
2320system.cpu1.toL2Bus.trans_dist::UpgradeResp 449127 # Transaction distribution
2321system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
2322system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution
2323system.cpu1.toL2Bus.trans_dist::ReadExReq 1061448 # Transaction distribution
2324system.cpu1.toL2Bus.trans_dist::ReadExResp 1001075 # Transaction distribution
2325system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4823385 # Transaction distribution
2326system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4143057 # Transaction distribution
2327system.cpu1.toL2Bus.trans_dist::InvalidateReq 462376 # Transaction distribution
2328system.cpu1.toL2Bus.trans_dist::InvalidateResp 452130 # Transaction distribution
2329system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14469858 # Packet count per connected master and slave (bytes)
2330system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15078885 # Packet count per connected master and slave (bytes)
2331system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 308515 # Packet count per connected master and slave (bytes)
2332system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 488328 # Packet count per connected master and slave (bytes)
2333system.cpu1.toL2Bus.pkt_count::total 30345586 # Packet count per connected master and slave (bytes)
2334system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617360632 # Cumulative packet size per connected master and slave (bytes)
2335system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 574871104 # Cumulative packet size per connected master and slave (bytes)
2336system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1172512 # Cumulative packet size per connected master and slave (bytes)
2337system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1763528 # Cumulative packet size per connected master and slave (bytes)
2338system.cpu1.toL2Bus.pkt_size::total 1195167776 # Cumulative packet size per connected master and slave (bytes)
2339system.cpu1.toL2Bus.snoops 5321649 # Total snoops (count)
2340system.cpu1.toL2Bus.snoop_fanout::samples 15507476 # Request fanout histogram
2341system.cpu1.toL2Bus.snoop_fanout::mean 0.118236 # Request fanout histogram
2342system.cpu1.toL2Bus.snoop_fanout::stdev 0.322925 # Request fanout histogram
2343system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2344system.cpu1.toL2Bus.snoop_fanout::0 13674115 88.18% 88.18% # Request fanout histogram
2345system.cpu1.toL2Bus.snoop_fanout::1 1833174 11.82% 100.00% # Request fanout histogram
2346system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram
2347system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2348system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2349system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2350system.cpu1.toL2Bus.snoop_fanout::total 15507476 # Request fanout histogram
2351system.cpu1.toL2Bus.reqLayer0.occupancy 19383363503 # Layer occupancy (ticks)
2352system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2353system.cpu1.toL2Bus.snoopLayer0.occupancy 170060906 # Layer occupancy (ticks)
2354system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2355system.cpu1.toL2Bus.respLayer0.occupancy 7235187500 # Layer occupancy (ticks)
2356system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2357system.cpu1.toL2Bus.respLayer1.occupancy 6851260042 # Layer occupancy (ticks)
2358system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2359system.cpu1.toL2Bus.respLayer2.occupancy 161951000 # Layer occupancy (ticks)
2360system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2361system.cpu1.toL2Bus.respLayer3.occupancy 267887000 # Layer occupancy (ticks)
2362system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2363system.iobus.trans_dist::ReadReq 40445 # Transaction distribution
2364system.iobus.trans_dist::ReadResp 40445 # Transaction distribution
2365system.iobus.trans_dist::WriteReq 136989 # Transaction distribution
2366system.iobus.trans_dist::WriteResp 136989 # Transaction distribution
2367system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47854 # Packet count per connected master and slave (bytes)
2368system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2369system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2370system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2371system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2372system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2373system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2374system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2375system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2376system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2377system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2378system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
2379system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2380system.iobus.pkt_count_system.bridge.master::total 122996 # Packet count per connected master and slave (bytes)
2381system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231792 # Packet count per connected master and slave (bytes)
2382system.iobus.pkt_count_system.realview.ide.dma::total 231792 # Packet count per connected master and slave (bytes)
2383system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2384system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2385system.iobus.pkt_count::total 354868 # Packet count per connected master and slave (bytes)
2386system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47874 # Cumulative packet size per connected master and slave (bytes)
2387system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2388system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2389system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2390system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2391system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2392system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2393system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2394system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2395system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2396system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2397system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
2398system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2399system.iobus.pkt_size_system.bridge.master::total 156011 # Cumulative packet size per connected master and slave (bytes)
2400system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355520 # Cumulative packet size per connected master and slave (bytes)
2401system.iobus.pkt_size_system.realview.ide.dma::total 7355520 # Cumulative packet size per connected master and slave (bytes)
2402system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2403system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2404system.iobus.pkt_size::total 7513617 # Cumulative packet size per connected master and slave (bytes)
2405system.iobus.reqLayer0.occupancy 37057000 # Layer occupancy (ticks)
2406system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2407system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks)
2408system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2409system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks)
2410system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2411system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks)
2412system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2413system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
2414system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2415system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2416system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2417system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks)
2418system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2419system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2420system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2421system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2422system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2423system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
2424system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2425system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2426system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2427system.iobus.reqLayer23.occupancy 26714502 # Layer occupancy (ticks)
2428system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2429system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks)
2430system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2431system.iobus.reqLayer25.occupancy 568759261 # Layer occupancy (ticks)
2432system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2433system.iobus.respLayer0.occupancy 92994000 # Layer occupancy (ticks)
2434system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2435system.iobus.respLayer3.occupancy 148232000 # Layer occupancy (ticks)
2436system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2437system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2438system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2439system.iocache.tags.replacements 115885 # number of replacements
2440system.iocache.tags.tagsinuse 11.295009 # Cycle average of tags in use
2441system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2442system.iocache.tags.sampled_refs 115901 # Sample count of references to valid blocks.
2443system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2444system.iocache.tags.warmup_cycle 9206049239000 # Cycle when the warmup percentage was hit.
2445system.iocache.tags.occ_blocks::realview.ethernet 3.821414 # Average occupied blocks per requestor
2446system.iocache.tags.occ_blocks::realview.ide 7.473594 # Average occupied blocks per requestor
2447system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy
2448system.iocache.tags.occ_percent::realview.ide 0.467100 # Average percentage of cache occupancy
2449system.iocache.tags.occ_percent::total 0.705938 # Average percentage of cache occupancy
2450system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2451system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2452system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2453system.iocache.tags.tag_accesses 1043421 # Number of tag accesses
2454system.iocache.tags.data_accesses 1043421 # Number of data accesses
2455system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2456system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses
2457system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses
2458system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2459system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2460system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
2461system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2462system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2463system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses
2464system.iocache.demand_misses::total 8952 # number of demand (read+write) misses
2465system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2466system.iocache.overall_misses::realview.ide 8912 # number of overall misses
2467system.iocache.overall_misses::total 8952 # number of overall misses
2468system.iocache.ReadReq_miss_latency::realview.ethernet 5263500 # number of ReadReq miss cycles
2469system.iocache.ReadReq_miss_latency::realview.ide 1680350485 # number of ReadReq miss cycles
2470system.iocache.ReadReq_miss_latency::total 1685613985 # number of ReadReq miss cycles
2471system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2472system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2473system.iocache.WriteLineReq_miss_latency::realview.ide 13574924276 # number of WriteLineReq miss cycles
2474system.iocache.WriteLineReq_miss_latency::total 13574924276 # number of WriteLineReq miss cycles
2475system.iocache.demand_miss_latency::realview.ethernet 5632500 # number of demand (read+write) miss cycles
2476system.iocache.demand_miss_latency::realview.ide 1680350485 # number of demand (read+write) miss cycles
2477system.iocache.demand_miss_latency::total 1685982985 # number of demand (read+write) miss cycles
2478system.iocache.overall_miss_latency::realview.ethernet 5632500 # number of overall miss cycles
2479system.iocache.overall_miss_latency::realview.ide 1680350485 # number of overall miss cycles
2480system.iocache.overall_miss_latency::total 1685982985 # number of overall miss cycles
2481system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2482system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses)
2483system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses)
2484system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2485system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2486system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
2487system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2488system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2489system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses
2490system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses
2491system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2492system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses
2493system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses
2494system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2495system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2496system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2497system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2498system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2499system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2500system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2501system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2502system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2503system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2504system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2505system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2506system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2507system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142256.756757 # average ReadReq miss latency
2508system.iocache.ReadReq_avg_miss_latency::realview.ide 188549.201638 # average ReadReq miss latency
2509system.iocache.ReadReq_avg_miss_latency::total 188357.803665 # average ReadReq miss latency
2510system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2511system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2512system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126887.424998 # average WriteLineReq miss latency
2513system.iocache.WriteLineReq_avg_miss_latency::total 126887.424998 # average WriteLineReq miss latency
2514system.iocache.demand_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency
2515system.iocache.demand_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency
2516system.iocache.demand_avg_miss_latency::total 188335.900916 # average overall miss latency
2517system.iocache.overall_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency
2518system.iocache.overall_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency
2519system.iocache.overall_avg_miss_latency::total 188335.900916 # average overall miss latency
2520system.iocache.blocked_cycles::no_mshrs 33982 # number of cycles access was blocked
2521system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2522system.iocache.blocked::no_mshrs 3504 # number of cycles access was blocked
2523system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2524system.iocache.avg_blocked_cycles::no_mshrs 9.698059 # average number of cycles each access was blocked
2525system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2526system.iocache.fast_writes 0 # number of fast writes performed
2527system.iocache.cache_copies 0 # number of cache copies performed
2528system.iocache.writebacks::writebacks 106958 # number of writebacks
2529system.iocache.writebacks::total 106958 # number of writebacks
2530system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2531system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses
2532system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses
2533system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2534system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2535system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
2536system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2537system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2538system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses
2539system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses
2540system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2541system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses
2542system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses
2543system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3413500 # number of ReadReq MSHR miss cycles
2544system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234750485 # number of ReadReq MSHR miss cycles
2545system.iocache.ReadReq_mshr_miss_latency::total 1238163985 # number of ReadReq MSHR miss cycles
2546system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2547system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2548system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8219197460 # number of WriteLineReq MSHR miss cycles
2549system.iocache.WriteLineReq_mshr_miss_latency::total 8219197460 # number of WriteLineReq MSHR miss cycles
2550system.iocache.demand_mshr_miss_latency::realview.ethernet 3632500 # number of demand (read+write) MSHR miss cycles
2551system.iocache.demand_mshr_miss_latency::realview.ide 1234750485 # number of demand (read+write) MSHR miss cycles
2552system.iocache.demand_mshr_miss_latency::total 1238382985 # number of demand (read+write) MSHR miss cycles
2553system.iocache.overall_mshr_miss_latency::realview.ethernet 3632500 # number of overall MSHR miss cycles
2554system.iocache.overall_mshr_miss_latency::realview.ide 1234750485 # number of overall MSHR miss cycles
2555system.iocache.overall_mshr_miss_latency::total 1238382985 # number of overall MSHR miss cycles
2556system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2557system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2558system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2559system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2560system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2561system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2562system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2563system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2564system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2565system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2566system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2567system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2568system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2569system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92256.756757 # average ReadReq mshr miss latency
2570system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138549.201638 # average ReadReq mshr miss latency
2571system.iocache.ReadReq_avg_mshr_miss_latency::total 138357.803665 # average ReadReq mshr miss latency
2572system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2573system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2574system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76826.417595 # average WriteLineReq mshr miss latency
2575system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76826.417595 # average WriteLineReq mshr miss latency
2576system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency
2577system.iocache.demand_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency
2578system.iocache.demand_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency
2579system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency
2580system.iocache.overall_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency
2581system.iocache.overall_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency
2582system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2583system.l2c.tags.replacements 1212335 # number of replacements
2584system.l2c.tags.tagsinuse 62688.740428 # Cycle average of tags in use
2585system.l2c.tags.total_refs 5318857 # Total number of references to valid blocks.
2586system.l2c.tags.sampled_refs 1271612 # Sample count of references to valid blocks.
2587system.l2c.tags.avg_refs 4.182767 # Average number of references to valid blocks.
2588system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2589system.l2c.tags.occ_blocks::writebacks 22897.710256 # Average occupied blocks per requestor
2590system.l2c.tags.occ_blocks::cpu0.dtb.walker 262.803618 # Average occupied blocks per requestor
2591system.l2c.tags.occ_blocks::cpu0.itb.walker 467.362186 # Average occupied blocks per requestor
2592system.l2c.tags.occ_blocks::cpu0.inst 4684.066084 # Average occupied blocks per requestor
2593system.l2c.tags.occ_blocks::cpu0.data 11639.690690 # Average occupied blocks per requestor
2594system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16421.765271 # Average occupied blocks per requestor
2595system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.113156 # Average occupied blocks per requestor
2596system.l2c.tags.occ_blocks::cpu1.itb.walker 2.385766 # Average occupied blocks per requestor
2597system.l2c.tags.occ_blocks::cpu1.inst 2988.095077 # Average occupied blocks per requestor
2598system.l2c.tags.occ_blocks::cpu1.data 1979.468778 # Average occupied blocks per requestor
2599system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1337.279546 # Average occupied blocks per requestor
2600system.l2c.tags.occ_percent::writebacks 0.349391 # Average percentage of cache occupancy
2601system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004010 # Average percentage of cache occupancy
2602system.l2c.tags.occ_percent::cpu0.itb.walker 0.007131 # Average percentage of cache occupancy
2603system.l2c.tags.occ_percent::cpu0.inst 0.071473 # Average percentage of cache occupancy
2604system.l2c.tags.occ_percent::cpu0.data 0.177608 # Average percentage of cache occupancy
2605system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.250576 # Average percentage of cache occupancy
2606system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000124 # Average percentage of cache occupancy
2607system.l2c.tags.occ_percent::cpu1.itb.walker 0.000036 # Average percentage of cache occupancy
2608system.l2c.tags.occ_percent::cpu1.inst 0.045595 # Average percentage of cache occupancy
2609system.l2c.tags.occ_percent::cpu1.data 0.030204 # Average percentage of cache occupancy
2610system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.020405 # Average percentage of cache occupancy
2611system.l2c.tags.occ_percent::total 0.956554 # Average percentage of cache occupancy
2612system.l2c.tags.occ_task_id_blocks::1022 10727 # Occupied blocks per task id
2613system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id
2614system.l2c.tags.occ_task_id_blocks::1024 48317 # Occupied blocks per task id
2615system.l2c.tags.age_task_id_blocks_1022::1 79 # Occupied blocks per task id
2616system.l2c.tags.age_task_id_blocks_1022::2 232 # Occupied blocks per task id
2617system.l2c.tags.age_task_id_blocks_1022::3 1534 # Occupied blocks per task id
2618system.l2c.tags.age_task_id_blocks_1022::4 8882 # Occupied blocks per task id
2619system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
2620system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
2621system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id
2622system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
2623system.l2c.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
2624system.l2c.tags.age_task_id_blocks_1024::2 1867 # Occupied blocks per task id
2625system.l2c.tags.age_task_id_blocks_1024::3 10232 # Occupied blocks per task id
2626system.l2c.tags.age_task_id_blocks_1024::4 35894 # Occupied blocks per task id
2627system.l2c.tags.occ_task_id_percent::1022 0.163681 # Percentage of cache occupancy per task id
2628system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id
2629system.l2c.tags.occ_task_id_percent::1024 0.737259 # Percentage of cache occupancy per task id
2630system.l2c.tags.tag_accesses 68046834 # Number of tag accesses
2631system.l2c.tags.data_accesses 68046834 # Number of data accesses
2632system.l2c.WritebackDirty_hits::writebacks 2553793 # number of WritebackDirty hits
2633system.l2c.WritebackDirty_hits::total 2553793 # number of WritebackDirty hits
2634system.l2c.UpgradeReq_hits::cpu0.data 170923 # number of UpgradeReq hits
2635system.l2c.UpgradeReq_hits::cpu1.data 116715 # number of UpgradeReq hits
2636system.l2c.UpgradeReq_hits::total 287638 # number of UpgradeReq hits
2637system.l2c.SCUpgradeReq_hits::cpu0.data 41425 # number of SCUpgradeReq hits
2638system.l2c.SCUpgradeReq_hits::cpu1.data 35212 # number of SCUpgradeReq hits
2639system.l2c.SCUpgradeReq_hits::total 76637 # number of SCUpgradeReq hits
2640system.l2c.ReadExReq_hits::cpu0.data 168896 # number of ReadExReq hits
2641system.l2c.ReadExReq_hits::cpu1.data 169545 # number of ReadExReq hits
2642system.l2c.ReadExReq_hits::total 338441 # number of ReadExReq hits
2643system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5417 # number of ReadSharedReq hits
2644system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4358 # number of ReadSharedReq hits
2645system.l2c.ReadSharedReq_hits::cpu0.inst 442976 # number of ReadSharedReq hits
2646system.l2c.ReadSharedReq_hits::cpu0.data 579881 # number of ReadSharedReq hits
2647system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 303485 # number of ReadSharedReq hits
2648system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5587 # number of ReadSharedReq hits
2649system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4895 # number of ReadSharedReq hits
2650system.l2c.ReadSharedReq_hits::cpu1.inst 380461 # number of ReadSharedReq hits
2651system.l2c.ReadSharedReq_hits::cpu1.data 481285 # number of ReadSharedReq hits
2652system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 259287 # number of ReadSharedReq hits
2653system.l2c.ReadSharedReq_hits::total 2467632 # number of ReadSharedReq hits
2654system.l2c.demand_hits::cpu0.dtb.walker 5417 # number of demand (read+write) hits
2655system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits
2656system.l2c.demand_hits::cpu0.inst 442976 # number of demand (read+write) hits
2657system.l2c.demand_hits::cpu0.data 748777 # number of demand (read+write) hits
2658system.l2c.demand_hits::cpu0.l2cache.prefetcher 303485 # number of demand (read+write) hits
2659system.l2c.demand_hits::cpu1.dtb.walker 5587 # number of demand (read+write) hits
2660system.l2c.demand_hits::cpu1.itb.walker 4895 # number of demand (read+write) hits
2661system.l2c.demand_hits::cpu1.inst 380461 # number of demand (read+write) hits
2662system.l2c.demand_hits::cpu1.data 650830 # number of demand (read+write) hits
2663system.l2c.demand_hits::cpu1.l2cache.prefetcher 259287 # number of demand (read+write) hits
2664system.l2c.demand_hits::total 2806073 # number of demand (read+write) hits
2665system.l2c.overall_hits::cpu0.dtb.walker 5417 # number of overall hits
2666system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits
2667system.l2c.overall_hits::cpu0.inst 442976 # number of overall hits
2668system.l2c.overall_hits::cpu0.data 748777 # number of overall hits
2669system.l2c.overall_hits::cpu0.l2cache.prefetcher 303485 # number of overall hits
2670system.l2c.overall_hits::cpu1.dtb.walker 5587 # number of overall hits
2671system.l2c.overall_hits::cpu1.itb.walker 4895 # number of overall hits
2672system.l2c.overall_hits::cpu1.inst 380461 # number of overall hits
2673system.l2c.overall_hits::cpu1.data 650830 # number of overall hits
2674system.l2c.overall_hits::cpu1.l2cache.prefetcher 259287 # number of overall hits
2675system.l2c.overall_hits::total 2806073 # number of overall hits
2676system.l2c.UpgradeReq_misses::cpu0.data 65926 # number of UpgradeReq misses
2677system.l2c.UpgradeReq_misses::cpu1.data 56137 # number of UpgradeReq misses
2678system.l2c.UpgradeReq_misses::total 122063 # number of UpgradeReq misses
2679system.l2c.SCUpgradeReq_misses::cpu0.data 14762 # number of SCUpgradeReq misses
2680system.l2c.SCUpgradeReq_misses::cpu1.data 11662 # number of SCUpgradeReq misses
2681system.l2c.SCUpgradeReq_misses::total 26424 # number of SCUpgradeReq misses
2682system.l2c.ReadExReq_misses::cpu0.data 479802 # number of ReadExReq misses
2683system.l2c.ReadExReq_misses::cpu1.data 149602 # number of ReadExReq misses
2684system.l2c.ReadExReq_misses::total 629404 # number of ReadExReq misses
2685system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1666 # number of ReadSharedReq misses
2686system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1796 # number of ReadSharedReq misses
2687system.l2c.ReadSharedReq_misses::cpu0.inst 49096 # number of ReadSharedReq misses
2688system.l2c.ReadSharedReq_misses::cpu0.data 137247 # number of ReadSharedReq misses
2689system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 210371 # number of ReadSharedReq misses
2690system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1115 # number of ReadSharedReq misses
2691system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1118 # number of ReadSharedReq misses
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2737system.l2c.ReadSharedReq_miss_latency::total 97567471042 # number of ReadSharedReq miss cycles
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2748system.l2c.demand_miss_latency::total 180536805542 # number of demand (read+write) miss cycles
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2759system.l2c.overall_miss_latency::total 180536805542 # number of overall miss cycles
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2761system.l2c.WritebackDirty_accesses::total 2553793 # number of WritebackDirty accesses(hits+misses)
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2805system.l2c.UpgradeReq_miss_rate::cpu1.data 0.324769 # miss rate for UpgradeReq accesses
2806system.l2c.UpgradeReq_miss_rate::total 0.297932 # miss rate for UpgradeReq accesses
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2808system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.248795 # miss rate for SCUpgradeReq accesses
2809system.l2c.SCUpgradeReq_miss_rate::total 0.256392 # miss rate for SCUpgradeReq accesses
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2815system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.099774 # miss rate for ReadSharedReq accesses
2816system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.191384 # miss rate for ReadSharedReq accesses
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2818system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.166368 # miss rate for ReadSharedReq accesses
2819system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.185930 # miss rate for ReadSharedReq accesses
2820system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.092026 # miss rate for ReadSharedReq accesses
2821system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.131324 # miss rate for ReadSharedReq accesses
2822system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.344750 # miss rate for ReadSharedReq accesses
2823system.l2c.ReadSharedReq_miss_rate::total 0.208529 # miss rate for ReadSharedReq accesses
2824system.l2c.demand_miss_rate::cpu0.dtb.walker 0.235211 # miss rate for demand accesses
2825system.l2c.demand_miss_rate::cpu0.itb.walker 0.291843 # miss rate for demand accesses
2826system.l2c.demand_miss_rate::cpu0.inst 0.099774 # miss rate for demand accesses
2827system.l2c.demand_miss_rate::cpu0.data 0.451777 # miss rate for demand accesses
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2829system.l2c.demand_miss_rate::cpu1.dtb.walker 0.166368 # miss rate for demand accesses
2830system.l2c.demand_miss_rate::cpu1.itb.walker 0.185930 # miss rate for demand accesses
2831system.l2c.demand_miss_rate::cpu1.inst 0.092026 # miss rate for demand accesses
2832system.l2c.demand_miss_rate::cpu1.data 0.254653 # miss rate for demand accesses
2833system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.344750 # miss rate for demand accesses
2834system.l2c.demand_miss_rate::total 0.313184 # miss rate for demand accesses
2835system.l2c.overall_miss_rate::cpu0.dtb.walker 0.235211 # miss rate for overall accesses
2836system.l2c.overall_miss_rate::cpu0.itb.walker 0.291843 # miss rate for overall accesses
2837system.l2c.overall_miss_rate::cpu0.inst 0.099774 # miss rate for overall accesses
2838system.l2c.overall_miss_rate::cpu0.data 0.451777 # miss rate for overall accesses
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2840system.l2c.overall_miss_rate::cpu1.dtb.walker 0.166368 # miss rate for overall accesses
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2842system.l2c.overall_miss_rate::cpu1.inst 0.092026 # miss rate for overall accesses
2843system.l2c.overall_miss_rate::cpu1.data 0.254653 # miss rate for overall accesses
2844system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.344750 # miss rate for overall accesses
2845system.l2c.overall_miss_rate::total 0.313184 # miss rate for overall accesses
2846system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14437.991081 # average UpgradeReq miss latency
2847system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16393.893511 # average UpgradeReq miss latency
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2850system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15069.927971 # average SCUpgradeReq miss latency
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2853system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130849.574204 # average ReadExReq miss latency
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2856system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138408.964365 # average ReadSharedReq miss latency
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2859system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541 # average ReadSharedReq miss latency
2860system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 138894.170404 # average ReadSharedReq miss latency
2861system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141838.998211 # average ReadSharedReq miss latency
2862system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134314.916626 # average ReadSharedReq miss latency
2863system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138707.761239 # average ReadSharedReq miss latency
2864system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441 # average ReadSharedReq miss latency
2865system.l2c.ReadSharedReq_avg_miss_latency::total 150069.401079 # average ReadSharedReq miss latency
2866system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136167.166867 # average overall miss latency
2867system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138408.964365 # average overall miss latency
2868system.l2c.demand_avg_miss_latency::cpu0.inst 134571.044484 # average overall miss latency
2869system.l2c.demand_avg_miss_latency::cpu0.data 133206.535462 # average overall miss latency
2870system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541 # average overall miss latency
2871system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138894.170404 # average overall miss latency
2872system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141838.998211 # average overall miss latency
2873system.l2c.demand_avg_miss_latency::cpu1.inst 134314.916626 # average overall miss latency
2874system.l2c.demand_avg_miss_latency::cpu1.data 133420.860673 # average overall miss latency
2875system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441 # average overall miss latency
2876system.l2c.demand_avg_miss_latency::total 141093.651878 # average overall miss latency
2877system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136167.166867 # average overall miss latency
2878system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138408.964365 # average overall miss latency
2879system.l2c.overall_avg_miss_latency::cpu0.inst 134571.044484 # average overall miss latency
2880system.l2c.overall_avg_miss_latency::cpu0.data 133206.535462 # average overall miss latency
2881system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 160875.941541 # average overall miss latency
2882system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138894.170404 # average overall miss latency
2883system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141838.998211 # average overall miss latency
2884system.l2c.overall_avg_miss_latency::cpu1.inst 134314.916626 # average overall miss latency
2885system.l2c.overall_avg_miss_latency::cpu1.data 133420.860673 # average overall miss latency
2886system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163139.714441 # average overall miss latency
2887system.l2c.overall_avg_miss_latency::total 141093.651878 # average overall miss latency
2888system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2889system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2890system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2891system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2892system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2893system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2894system.l2c.fast_writes 0 # number of fast writes performed
2895system.l2c.cache_copies 0 # number of cache copies performed
2896system.l2c.writebacks::writebacks 974440 # number of writebacks
2897system.l2c.writebacks::total 974440 # number of writebacks
2898system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 109 # number of ReadSharedReq MSHR hits
2899system.l2c.ReadSharedReq_mshr_hits::cpu0.data 16 # number of ReadSharedReq MSHR hits
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2901system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits
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2904system.l2c.demand_mshr_hits::cpu0.data 16 # number of demand (read+write) MSHR hits
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2906system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
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2908system.l2c.overall_mshr_hits::cpu0.inst 109 # number of overall MSHR hits
2909system.l2c.overall_mshr_hits::cpu0.data 16 # number of overall MSHR hits
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2911system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
2912system.l2c.overall_mshr_hits::total 247 # number of overall MSHR hits
2913system.l2c.CleanEvict_mshr_misses::writebacks 38798 # number of CleanEvict MSHR misses
2914system.l2c.CleanEvict_mshr_misses::total 38798 # number of CleanEvict MSHR misses
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2918system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 14762 # number of SCUpgradeReq MSHR misses
2919system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11662 # number of SCUpgradeReq MSHR misses
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2924system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1666 # number of ReadSharedReq MSHR misses
2925system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1796 # number of ReadSharedReq MSHR misses
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2929system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1115 # number of ReadSharedReq MSHR misses
2930system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1118 # number of ReadSharedReq MSHR misses
2931system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 38460 # number of ReadSharedReq MSHR misses
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2934system.l2c.ReadSharedReq_mshr_misses::total 649902 # number of ReadSharedReq MSHR misses
2935system.l2c.demand_mshr_misses::cpu0.dtb.walker 1666 # number of demand (read+write) MSHR misses
2936system.l2c.demand_mshr_misses::cpu0.itb.walker 1796 # number of demand (read+write) MSHR misses
2937system.l2c.demand_mshr_misses::cpu0.inst 48987 # number of demand (read+write) MSHR misses
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2939system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 210371 # number of demand (read+write) MSHR misses
2940system.l2c.demand_mshr_misses::cpu1.dtb.walker 1115 # number of demand (read+write) MSHR misses
2941system.l2c.demand_mshr_misses::cpu1.itb.walker 1118 # number of demand (read+write) MSHR misses
2942system.l2c.demand_mshr_misses::cpu1.inst 38460 # number of demand (read+write) MSHR misses
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2944system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 136420 # number of demand (read+write) MSHR misses
2945system.l2c.demand_mshr_misses::total 1279306 # number of demand (read+write) MSHR misses
2946system.l2c.overall_mshr_misses::cpu0.dtb.walker 1666 # number of overall MSHR misses
2947system.l2c.overall_mshr_misses::cpu0.itb.walker 1796 # number of overall MSHR misses
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2951system.l2c.overall_mshr_misses::cpu1.dtb.walker 1115 # number of overall MSHR misses
2952system.l2c.overall_mshr_misses::cpu1.itb.walker 1118 # number of overall MSHR misses
2953system.l2c.overall_mshr_misses::cpu1.inst 38460 # number of overall MSHR misses
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2955system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 136420 # number of overall MSHR misses
2956system.l2c.overall_mshr_misses::total 1279306 # number of overall MSHR misses
2957system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable
2958system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable
2959system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable
2960system.l2c.ReadReq_mshr_uncacheable::cpu1.data 24121 # number of ReadReq MSHR uncacheable
2961system.l2c.ReadReq_mshr_uncacheable::total 82348 # number of ReadReq MSHR uncacheable
2962system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable
2963system.l2c.WriteReq_mshr_uncacheable::cpu1.data 23288 # number of WriteReq MSHR uncacheable
2964system.l2c.WriteReq_mshr_uncacheable::total 39013 # number of WriteReq MSHR uncacheable
2965system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses
2966system.l2c.overall_mshr_uncacheable_misses::cpu0.data 30717 # number of overall MSHR uncacheable misses
2967system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses
2968system.l2c.overall_mshr_uncacheable_misses::cpu1.data 47409 # number of overall MSHR uncacheable misses
2969system.l2c.overall_mshr_uncacheable_misses::total 121361 # number of overall MSHR uncacheable misses
2970system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4679642000 # number of UpgradeReq MSHR miss cycles
2971system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3966885500 # number of UpgradeReq MSHR miss cycles
2972system.l2c.UpgradeReq_mshr_miss_latency::total 8646527500 # number of UpgradeReq MSHR miss cycles
2973system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1090611500 # number of SCUpgradeReq MSHR miss cycles
2974system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 859764000 # number of SCUpgradeReq MSHR miss cycles
2975system.l2c.SCUpgradeReq_mshr_miss_latency::total 1950375500 # number of SCUpgradeReq MSHR miss cycles
2976system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 58595767959 # number of ReadExReq MSHR miss cycles
2977system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18079108058 # number of ReadExReq MSHR miss cycles
2978system.l2c.ReadExReq_mshr_miss_latency::total 76674876017 # number of ReadExReq MSHR miss cycles
2979system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 210193003 # number of ReadSharedReq MSHR miss cycles
2980system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 230621502 # number of ReadSharedReq MSHR miss cycles
2981system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6104112113 # number of ReadSharedReq MSHR miss cycles
2982system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17426442010 # number of ReadSharedReq MSHR miss cycles
2983system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 31739278014 # number of ReadSharedReq MSHR miss cycles
2984system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 143716501 # number of ReadSharedReq MSHR miss cycles
2985system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 147393505 # number of ReadSharedReq MSHR miss cycles
2986system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4783143154 # number of ReadSharedReq MSHR miss cycles
2987system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9361991430 # number of ReadSharedReq MSHR miss cycles
2988system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20890811537 # number of ReadSharedReq MSHR miss cycles
2989system.l2c.ReadSharedReq_mshr_miss_latency::total 91037702769 # number of ReadSharedReq MSHR miss cycles
2990system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 210193003 # number of demand (read+write) MSHR miss cycles
2991system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 230621502 # number of demand (read+write) MSHR miss cycles
2992system.l2c.demand_mshr_miss_latency::cpu0.inst 6104112113 # number of demand (read+write) MSHR miss cycles
2993system.l2c.demand_mshr_miss_latency::cpu0.data 76022209969 # number of demand (read+write) MSHR miss cycles
2994system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 31739278014 # number of demand (read+write) MSHR miss cycles
2995system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 143716501 # number of demand (read+write) MSHR miss cycles
2996system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 147393505 # number of demand (read+write) MSHR miss cycles
2997system.l2c.demand_mshr_miss_latency::cpu1.inst 4783143154 # number of demand (read+write) MSHR miss cycles
2998system.l2c.demand_mshr_miss_latency::cpu1.data 27441099488 # number of demand (read+write) MSHR miss cycles
2999system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20890811537 # number of demand (read+write) MSHR miss cycles
3000system.l2c.demand_mshr_miss_latency::total 167712578786 # number of demand (read+write) MSHR miss cycles
3001system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 210193003 # number of overall MSHR miss cycles
3002system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 230621502 # number of overall MSHR miss cycles
3003system.l2c.overall_mshr_miss_latency::cpu0.inst 6104112113 # number of overall MSHR miss cycles
3004system.l2c.overall_mshr_miss_latency::cpu0.data 76022209969 # number of overall MSHR miss cycles
3005system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31739278014 # number of overall MSHR miss cycles
3006system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 143716501 # number of overall MSHR miss cycles
3007system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 147393505 # number of overall MSHR miss cycles
3008system.l2c.overall_mshr_miss_latency::cpu1.inst 4783143154 # number of overall MSHR miss cycles
3009system.l2c.overall_mshr_miss_latency::cpu1.data 27441099488 # number of overall MSHR miss cycles
3010system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20890811537 # number of overall MSHR miss cycles
3011system.l2c.overall_mshr_miss_latency::total 167712578786 # number of overall MSHR miss cycles
3012system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles
3013system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2194977011 # number of ReadReq MSHR uncacheable cycles
3014system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11849500 # number of ReadReq MSHR uncacheable cycles
3015system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3751197013 # number of ReadReq MSHR uncacheable cycles
3016system.l2c.ReadReq_mshr_uncacheable_latency::total 10812544524 # number of ReadReq MSHR uncacheable cycles
3017system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2268278521 # number of WriteReq MSHR uncacheable cycles
3018system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3726528606 # number of WriteReq MSHR uncacheable cycles
3019system.l2c.WriteReq_mshr_uncacheable_latency::total 5994807127 # number of WriteReq MSHR uncacheable cycles
3020system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles
3021system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4463255532 # number of overall MSHR uncacheable cycles
3022system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11849500 # number of overall MSHR uncacheable cycles
3023system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7477725619 # number of overall MSHR uncacheable cycles
3024system.l2c.overall_mshr_uncacheable_latency::total 16807351651 # number of overall MSHR uncacheable cycles
3025system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3026system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3027system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.278346 # mshr miss rate for UpgradeReq accesses
3028system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324769 # mshr miss rate for UpgradeReq accesses
3029system.l2c.UpgradeReq_mshr_miss_rate::total 0.297932 # mshr miss rate for UpgradeReq accesses
3030system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.262730 # mshr miss rate for SCUpgradeReq accesses
3031system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.248795 # mshr miss rate for SCUpgradeReq accesses
3032system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.256392 # mshr miss rate for SCUpgradeReq accesses
3033system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739638 # mshr miss rate for ReadExReq accesses
3034system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468756 # mshr miss rate for ReadExReq accesses
3035system.l2c.ReadExReq_mshr_miss_rate::total 0.650315 # mshr miss rate for ReadExReq accesses
3036system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for ReadSharedReq accesses
3037system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for ReadSharedReq accesses
3038system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for ReadSharedReq accesses
3039system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.191362 # mshr miss rate for ReadSharedReq accesses
3040system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for ReadSharedReq accesses
3041system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for ReadSharedReq accesses
3042system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for ReadSharedReq accesses
3043system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for ReadSharedReq accesses
3044system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.131286 # mshr miss rate for ReadSharedReq accesses
3045system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for ReadSharedReq accesses
3046system.l2c.ReadSharedReq_mshr_miss_rate::total 0.208450 # mshr miss rate for ReadSharedReq accesses
3047system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for demand accesses
3048system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for demand accesses
3049system.l2c.demand_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for demand accesses
3050system.l2c.demand_mshr_miss_rate::cpu0.data 0.451765 # mshr miss rate for demand accesses
3051system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for demand accesses
3052system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for demand accesses
3053system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for demand accesses
3054system.l2c.demand_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for demand accesses
3055system.l2c.demand_mshr_miss_rate::cpu1.data 0.254629 # mshr miss rate for demand accesses
3056system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for demand accesses
3057system.l2c.demand_mshr_miss_rate::total 0.313124 # mshr miss rate for demand accesses
3058system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for overall accesses
3059system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for overall accesses
3060system.l2c.overall_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for overall accesses
3061system.l2c.overall_mshr_miss_rate::cpu0.data 0.451765 # mshr miss rate for overall accesses
3062system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for overall accesses
3063system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for overall accesses
3064system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for overall accesses
3065system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for overall accesses
3066system.l2c.overall_mshr_miss_rate::cpu1.data 0.254629 # mshr miss rate for overall accesses
3067system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for overall accesses
3068system.l2c.overall_mshr_miss_rate::total 0.313124 # mshr miss rate for overall accesses
3069system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70983.253951 # average UpgradeReq mshr miss latency
3070system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70664.365748 # average UpgradeReq mshr miss latency
3071system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70836.596675 # average UpgradeReq mshr miss latency
3072system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73879.657228 # average SCUpgradeReq mshr miss latency
3073system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73723.546561 # average SCUpgradeReq mshr miss latency
3074system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73810.759158 # average SCUpgradeReq mshr miss latency
3075system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122124.893100 # average ReadExReq mshr miss latency
3076system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120848.037179 # average ReadExReq mshr miss latency
3077system.l2c.ReadExReq_avg_mshr_miss_latency::total 121821.399319 # average ReadExReq mshr miss latency
3078system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average ReadSharedReq mshr miss latency
3079system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average ReadSharedReq mshr miss latency
3080system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average ReadSharedReq mshr miss latency
3081system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.191240 # average ReadSharedReq mshr miss latency
3082system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average ReadSharedReq mshr miss latency
3083system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average ReadSharedReq mshr miss latency
3084system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average ReadSharedReq mshr miss latency
3085system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average ReadSharedReq mshr miss latency
3086system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128708.397674 # average ReadSharedReq mshr miss latency
3087system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average ReadSharedReq mshr miss latency
3088system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140079.123882 # average ReadSharedReq mshr miss latency
3089system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average overall mshr miss latency
3090system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average overall mshr miss latency
3091system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average overall mshr miss latency
3092system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123206.068345 # average overall mshr miss latency
3093system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average overall mshr miss latency
3094system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average overall mshr miss latency
3095system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average overall mshr miss latency
3096system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average overall mshr miss latency
3097system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123419.535342 # average overall mshr miss latency
3098system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average overall mshr miss latency
3099system.l2c.demand_avg_mshr_miss_latency::total 131096.531077 # average overall mshr miss latency
3100system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average overall mshr miss latency
3101system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average overall mshr miss latency
3102system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average overall mshr miss latency
3103system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123206.068345 # average overall mshr miss latency
3104system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average overall mshr miss latency
3105system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average overall mshr miss latency
3106system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average overall mshr miss latency
3107system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average overall mshr miss latency
3108system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123419.535342 # average overall mshr miss latency
3109system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average overall mshr miss latency
3110system.l2c.overall_avg_mshr_miss_latency::total 131096.531077 # average overall mshr miss latency
3111system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency
3112system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146409.886006 # average ReadReq mshr uncacheable latency
3113system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average ReadReq mshr uncacheable latency
3114system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155515.816633 # average ReadReq mshr uncacheable latency
3115system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131303.061689 # average ReadReq mshr uncacheable latency
3116system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144246.646804 # average WriteReq mshr uncacheable latency
3117system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160019.263397 # average WriteReq mshr uncacheable latency
3118system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153661.782662 # average WriteReq mshr uncacheable latency
3119system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency
3120system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145302.455709 # average overall mshr uncacheable latency
3121system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average overall mshr uncacheable latency
3122system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157727.976102 # average overall mshr uncacheable latency
3123system.l2c.overall_avg_mshr_uncacheable_latency::total 138490.550103 # average overall mshr uncacheable latency
3124system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3125system.membus.trans_dist::ReadReq 82348 # Transaction distribution
3126system.membus.trans_dist::ReadResp 741199 # Transaction distribution
3127system.membus.trans_dist::WriteReq 39013 # Transaction distribution
3128system.membus.trans_dist::WriteResp 39013 # Transaction distribution
3129system.membus.trans_dist::WritebackDirty 1081398 # Transaction distribution
3130system.membus.trans_dist::CleanEvict 196468 # Transaction distribution
3131system.membus.trans_dist::UpgradeReq 401198 # Transaction distribution
3132system.membus.trans_dist::SCUpgradeReq 306316 # Transaction distribution
3133system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
3134system.membus.trans_dist::ReadExReq 643986 # Transaction distribution
3135system.membus.trans_dist::ReadExResp 621414 # Transaction distribution
3136system.membus.trans_dist::ReadSharedReq 658851 # Transaction distribution
3137system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
3138system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122996 # Packet count per connected master and slave (bytes)
3139system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
3140system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28036 # Packet count per connected master and slave (bytes)
3141system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4525576 # Packet count per connected master and slave (bytes)
3142system.membus.pkt_count_system.l2c.mem_side::total 4676700 # Packet count per connected master and slave (bytes)
3143system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238552 # Packet count per connected master and slave (bytes)
3144system.membus.pkt_count_system.iocache.mem_side::total 238552 # Packet count per connected master and slave (bytes)
3145system.membus.pkt_count::total 4915252 # Packet count per connected master and slave (bytes)
3146system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156011 # Cumulative packet size per connected master and slave (bytes)
3147system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
3148system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56072 # Cumulative packet size per connected master and slave (bytes)
3149system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143876076 # Cumulative packet size per connected master and slave (bytes)
3150system.membus.pkt_size_system.l2c.mem_side::total 144088363 # Cumulative packet size per connected master and slave (bytes)
3151system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276096 # Cumulative packet size per connected master and slave (bytes)
3152system.membus.pkt_size_system.iocache.mem_side::total 7276096 # Cumulative packet size per connected master and slave (bytes)
3153system.membus.pkt_size::total 151364459 # Cumulative packet size per connected master and slave (bytes)
3154system.membus.snoops 576558 # Total snoops (count)
3155system.membus.snoop_fanout::samples 3516604 # Request fanout histogram
3156system.membus.snoop_fanout::mean 1 # Request fanout histogram
3157system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3158system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3159system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3160system.membus.snoop_fanout::1 3516604 100.00% 100.00% # Request fanout histogram
3161system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3162system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3163system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3164system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3165system.membus.snoop_fanout::total 3516604 # Request fanout histogram
3166system.membus.reqLayer0.occupancy 101595998 # Layer occupancy (ticks)
3167system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3168system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3169system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3170system.membus.reqLayer2.occupancy 23093498 # Layer occupancy (ticks)
3171system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3172system.membus.reqLayer5.occupancy 7460114319 # Layer occupancy (ticks)
3173system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3174system.membus.respLayer2.occupancy 6921315949 # Layer occupancy (ticks)
3175system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3176system.membus.respLayer3.occupancy 45614101 # Layer occupancy (ticks)
3177system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3178system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3179system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3180system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3181system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3182system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3183system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3184system.realview.ethernet.txBytes 966 # Bytes Transmitted

--- 37 unchanged lines hidden (view full) ---

3222system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3223system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3224system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3225system.realview.ethernet.droppedPackets 0 # number of packets dropped
3226system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3227system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3228system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3229system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3230system.toL2Bus.snoop_filter.tot_requests 10579543 # Total number of requests made to the snoop filter.
3231system.toL2Bus.snoop_filter.hit_single_requests 5766836 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3232system.toL2Bus.snoop_filter.hit_multi_requests 1724769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3233system.toL2Bus.snoop_filter.tot_snoops 116961 # Total number of snoops made to the snoop filter.
3234system.toL2Bus.snoop_filter.hit_single_snoops 105875 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3235system.toL2Bus.snoop_filter.hit_multi_snoops 11086 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3236system.toL2Bus.trans_dist::ReadReq 82350 # Transaction distribution
3237system.toL2Bus.trans_dist::ReadResp 3947474 # Transaction distribution
3238system.toL2Bus.trans_dist::WriteReq 39013 # Transaction distribution
3239system.toL2Bus.trans_dist::WriteResp 39013 # Transaction distribution
3240system.toL2Bus.trans_dist::WritebackDirty 3635231 # Transaction distribution
3241system.toL2Bus.trans_dist::CleanEvict 2252852 # Transaction distribution
3242system.toL2Bus.trans_dist::UpgradeReq 680846 # Transaction distribution
3243system.toL2Bus.trans_dist::SCUpgradeReq 382953 # Transaction distribution
3244system.toL2Bus.trans_dist::UpgradeResp 1063799 # Transaction distribution
3245system.toL2Bus.trans_dist::SCUpgradeFailReq 141 # Transaction distribution
3246system.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution
3247system.toL2Bus.trans_dist::ReadExReq 1092357 # Transaction distribution
3248system.toL2Bus.trans_dist::ReadExResp 1092357 # Transaction distribution
3249system.toL2Bus.trans_dist::ReadSharedReq 3872368 # Transaction distribution
3250system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
3251system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8825237 # Packet count per connected master and slave (bytes)
3252system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6597118 # Packet count per connected master and slave (bytes)
3253system.toL2Bus.pkt_count::total 15422355 # Packet count per connected master and slave (bytes)
3254system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252378371 # Cumulative packet size per connected master and slave (bytes)
3255system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 173059496 # Cumulative packet size per connected master and slave (bytes)
3256system.toL2Bus.pkt_size::total 425437867 # Cumulative packet size per connected master and slave (bytes)
3257system.toL2Bus.snoops 2867232 # Total snoops (count)
3258system.toL2Bus.snoop_fanout::samples 7585274 # Request fanout histogram
3259system.toL2Bus.snoop_fanout::mean 0.353752 # Request fanout histogram
3260system.toL2Bus.snoop_fanout::stdev 0.481180 # Request fanout histogram
3261system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3262system.toL2Bus.snoop_fanout::0 4913057 64.77% 64.77% # Request fanout histogram
3263system.toL2Bus.snoop_fanout::1 2661131 35.08% 99.85% # Request fanout histogram
3264system.toL2Bus.snoop_fanout::2 11086 0.15% 100.00% # Request fanout histogram
3265system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3266system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3267system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3268system.toL2Bus.snoop_fanout::total 7585274 # Request fanout histogram
3269system.toL2Bus.reqLayer0.occupancy 8312830316 # Layer occupancy (ticks)
3270system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3271system.toL2Bus.snoopLayer0.occupancy 2630923 # Layer occupancy (ticks)
3272system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3273system.toL2Bus.respLayer0.occupancy 4557123754 # Layer occupancy (ticks)
3274system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3275system.toL2Bus.respLayer1.occupancy 3526163360 # Layer occupancy (ticks)
3276system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3277
3278---------- End Simulation Statistics ----------