| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing |
| 39mem_ranges=2147483648:2415919103 | 39mem_ranges=2147483648:2415919103:0:0:0:0 |
| 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null | 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null |
| 76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 | 76ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 |
| 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 63 unchanged lines hidden (view full) --- 148tracer=system.cpu0.tracer 149workload= 150dcache_port=system.cpu0.dcache.cpu_side 151icache_port=system.cpu0.icache.cpu_side 152 153[system.cpu0.dcache] 154type=Cache 155children=tags | 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 63 unchanged lines hidden (view full) --- 148tracer=system.cpu0.tracer 149workload= 150dcache_port=system.cpu0.dcache.cpu_side 151icache_port=system.cpu0.icache.cpu_side 152 153[system.cpu0.dcache] 154type=Cache 155children=tags |
| 156addr_ranges=0:18446744073709551615 | 156addr_ranges=0:18446744073709551615:0:0:0:0 |
| 157assoc=2 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160default_p_state=UNDEFINED 161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false --- 80 unchanged lines hidden (view full) --- 245p_state_clk_gate_min=1000 246power_model=Null 247sys=system 248port=system.cpu0.toL2Bus.slave[3] 249 250[system.cpu0.icache] 251type=Cache 252children=tags | 157assoc=2 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl 160default_p_state=UNDEFINED 161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false --- 80 unchanged lines hidden (view full) --- 245p_state_clk_gate_min=1000 246power_model=Null 247sys=system 248port=system.cpu0.toL2Bus.slave[3] 249 250[system.cpu0.icache] 251type=Cache 252children=tags |
| 253addr_ranges=0:18446744073709551615 | 253addr_ranges=0:18446744073709551615:0:0:0:0 |
| 254assoc=2 255clk_domain=system.cpu_clk_domain 256clusivity=mostly_incl 257default_p_state=UNDEFINED 258demand_mshr_reserve=1 259eventq_index=0 260hit_latency=1 261is_read_only=true --- 43 unchanged lines hidden (view full) --- 305id_aa64afr0_el1=0 306id_aa64afr1_el1=0 307id_aa64dfr0_el1=1052678 308id_aa64dfr1_el1=0 309id_aa64isar0_el1=0 310id_aa64isar1_el1=0 311id_aa64mmfr0_el1=15728642 312id_aa64mmfr1_el1=0 | 254assoc=2 255clk_domain=system.cpu_clk_domain 256clusivity=mostly_incl 257default_p_state=UNDEFINED 258demand_mshr_reserve=1 259eventq_index=0 260hit_latency=1 261is_read_only=true --- 43 unchanged lines hidden (view full) --- 305id_aa64afr0_el1=0 306id_aa64afr1_el1=0 307id_aa64dfr0_el1=1052678 308id_aa64dfr1_el1=0 309id_aa64isar0_el1=0 310id_aa64isar1_el1=0 311id_aa64mmfr0_el1=15728642 312id_aa64mmfr1_el1=0 |
| 313id_aa64pfr0_el1=17 | 313id_aa64pfr0_el1=34 |
| 314id_aa64pfr1_el1=0 315id_isar0=34607377 316id_isar1=34677009 317id_isar2=555950401 318id_isar3=17899825 319id_isar4=268501314 320id_isar5=0 321id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 377p_state_clk_gate_min=1000 378power_model=Null 379sys=system 380port=system.cpu0.toL2Bus.slave[2] 381 382[system.cpu0.l2cache] 383type=Cache 384children=prefetcher tags | 314id_aa64pfr1_el1=0 315id_isar0=34607377 316id_isar1=34677009 317id_isar2=555950401 318id_isar3=17899825 319id_isar4=268501314 320id_isar5=0 321id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 377p_state_clk_gate_min=1000 378power_model=Null 379sys=system 380port=system.cpu0.toL2Bus.slave[2] 381 382[system.cpu0.l2cache] 383type=Cache 384children=prefetcher tags |
| 385addr_ranges=0:18446744073709551615 | 385addr_ranges=0:18446744073709551615:0:0:0:0 |
| 386assoc=16 387clk_domain=system.cpu_clk_domain 388clusivity=mostly_excl 389default_p_state=UNDEFINED 390demand_mshr_reserve=1 391eventq_index=0 392hit_latency=12 393is_read_only=false --- 132 unchanged lines hidden (view full) --- 526tracer=system.cpu1.tracer 527workload= 528dcache_port=system.cpu1.dcache.cpu_side 529icache_port=system.cpu1.icache.cpu_side 530 531[system.cpu1.dcache] 532type=Cache 533children=tags | 386assoc=16 387clk_domain=system.cpu_clk_domain 388clusivity=mostly_excl 389default_p_state=UNDEFINED 390demand_mshr_reserve=1 391eventq_index=0 392hit_latency=12 393is_read_only=false --- 132 unchanged lines hidden (view full) --- 526tracer=system.cpu1.tracer 527workload= 528dcache_port=system.cpu1.dcache.cpu_side 529icache_port=system.cpu1.icache.cpu_side 530 531[system.cpu1.dcache] 532type=Cache 533children=tags |
| 534addr_ranges=0:18446744073709551615 | 534addr_ranges=0:18446744073709551615:0:0:0:0 |
| 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=false --- 80 unchanged lines hidden (view full) --- 623p_state_clk_gate_min=1000 624power_model=Null 625sys=system 626port=system.cpu1.toL2Bus.slave[3] 627 628[system.cpu1.icache] 629type=Cache 630children=tags | 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=false --- 80 unchanged lines hidden (view full) --- 623p_state_clk_gate_min=1000 624power_model=Null 625sys=system 626port=system.cpu1.toL2Bus.slave[3] 627 628[system.cpu1.icache] 629type=Cache 630children=tags |
| 631addr_ranges=0:18446744073709551615 | 631addr_ranges=0:18446744073709551615:0:0:0:0 |
| 632assoc=2 633clk_domain=system.cpu_clk_domain 634clusivity=mostly_incl 635default_p_state=UNDEFINED 636demand_mshr_reserve=1 637eventq_index=0 638hit_latency=1 639is_read_only=true --- 43 unchanged lines hidden (view full) --- 683id_aa64afr0_el1=0 684id_aa64afr1_el1=0 685id_aa64dfr0_el1=1052678 686id_aa64dfr1_el1=0 687id_aa64isar0_el1=0 688id_aa64isar1_el1=0 689id_aa64mmfr0_el1=15728642 690id_aa64mmfr1_el1=0 | 632assoc=2 633clk_domain=system.cpu_clk_domain 634clusivity=mostly_incl 635default_p_state=UNDEFINED 636demand_mshr_reserve=1 637eventq_index=0 638hit_latency=1 639is_read_only=true --- 43 unchanged lines hidden (view full) --- 683id_aa64afr0_el1=0 684id_aa64afr1_el1=0 685id_aa64dfr0_el1=1052678 686id_aa64dfr1_el1=0 687id_aa64isar0_el1=0 688id_aa64isar1_el1=0 689id_aa64mmfr0_el1=15728642 690id_aa64mmfr1_el1=0 |
| 691id_aa64pfr0_el1=17 | 691id_aa64pfr0_el1=34 |
| 692id_aa64pfr1_el1=0 693id_isar0=34607377 694id_isar1=34677009 695id_isar2=555950401 696id_isar3=17899825 697id_isar4=268501314 698id_isar5=0 699id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 755p_state_clk_gate_min=1000 756power_model=Null 757sys=system 758port=system.cpu1.toL2Bus.slave[2] 759 760[system.cpu1.l2cache] 761type=Cache 762children=prefetcher tags | 692id_aa64pfr1_el1=0 693id_isar0=34607377 694id_isar1=34677009 695id_isar2=555950401 696id_isar3=17899825 697id_isar4=268501314 698id_isar5=0 699id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 755p_state_clk_gate_min=1000 756power_model=Null 757sys=system 758port=system.cpu1.toL2Bus.slave[2] 759 760[system.cpu1.l2cache] 761type=Cache 762children=prefetcher tags |
| 763addr_ranges=0:18446744073709551615 | 763addr_ranges=0:18446744073709551615:0:0:0:0 |
| 764assoc=16 765clk_domain=system.cpu_clk_domain 766clusivity=mostly_excl 767default_p_state=UNDEFINED 768demand_mshr_reserve=1 769eventq_index=0 770hit_latency=12 771is_read_only=false --- 130 unchanged lines hidden (view full) --- 902use_default_range=false 903width=16 904master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 905slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 906 907[system.iocache] 908type=Cache 909children=tags | 764assoc=16 765clk_domain=system.cpu_clk_domain 766clusivity=mostly_excl 767default_p_state=UNDEFINED 768demand_mshr_reserve=1 769eventq_index=0 770hit_latency=12 771is_read_only=false --- 130 unchanged lines hidden (view full) --- 902use_default_range=false 903width=16 904master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 905slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 906 907[system.iocache] 908type=Cache 909children=tags |
| 910addr_ranges=2147483648:2415919103 | 910addr_ranges=2147483648:2415919103:0:0:0:0 |
| 911assoc=8 912clk_domain=system.clk_domain 913clusivity=mostly_incl 914default_p_state=UNDEFINED 915demand_mshr_reserve=1 916eventq_index=0 917hit_latency=50 918is_read_only=false --- 29 unchanged lines hidden (view full) --- 948p_state_clk_gate_min=1000 949power_model=Null 950sequential_access=false 951size=1024 952 953[system.l2c] 954type=Cache 955children=tags | 911assoc=8 912clk_domain=system.clk_domain 913clusivity=mostly_incl 914default_p_state=UNDEFINED 915demand_mshr_reserve=1 916eventq_index=0 917hit_latency=50 918is_read_only=false --- 29 unchanged lines hidden (view full) --- 948p_state_clk_gate_min=1000 949power_model=Null 950sequential_access=false 951size=1024 952 953[system.l2c] 954type=Cache 955children=tags |
| 956addr_ranges=0:18446744073709551615 | 956addr_ranges=0:18446744073709551615:0:0:0:0 |
| 957assoc=8 958clk_domain=system.cpu_clk_domain 959clusivity=mostly_incl 960default_p_state=UNDEFINED 961demand_mshr_reserve=1 962eventq_index=0 963hit_latency=20 964is_read_only=false --- 81 unchanged lines hidden (view full) --- 1046type=SnoopFilter 1047eventq_index=0 1048lookup_latency=1 1049max_capacity=8388608 1050system=system 1051 1052[system.physmem] 1053type=DRAMCtrl | 957assoc=8 958clk_domain=system.cpu_clk_domain 959clusivity=mostly_incl 960default_p_state=UNDEFINED 961demand_mshr_reserve=1 962eventq_index=0 963hit_latency=20 964is_read_only=false --- 81 unchanged lines hidden (view full) --- 1046type=SnoopFilter 1047eventq_index=0 1048lookup_latency=1 1049max_capacity=8388608 1050system=system 1051 1052[system.physmem] 1053type=DRAMCtrl |
| 1054IDD0=0.075000 | 1054IDD0=0.055000 |
| 1055IDD02=0.000000 | 1055IDD02=0.000000 |
| 1056IDD2N=0.050000 | 1056IDD2N=0.032000 |
| 1057IDD2N2=0.000000 1058IDD2P0=0.000000 1059IDD2P02=0.000000 | 1057IDD2N2=0.000000 1058IDD2P0=0.000000 1059IDD2P02=0.000000 |
| 1060IDD2P1=0.000000 | 1060IDD2P1=0.032000 |
| 1061IDD2P12=0.000000 | 1061IDD2P12=0.000000 |
| 1062IDD3N=0.057000 | 1062IDD3N=0.038000 |
| 1063IDD3N2=0.000000 1064IDD3P0=0.000000 1065IDD3P02=0.000000 | 1063IDD3N2=0.000000 1064IDD3P0=0.000000 1065IDD3P02=0.000000 |
| 1066IDD3P1=0.000000 | 1066IDD3P1=0.038000 |
| 1067IDD3P12=0.000000 | 1067IDD3P12=0.000000 |
| 1068IDD4R=0.187000 | 1068IDD4R=0.157000 |
| 1069IDD4R2=0.000000 | 1069IDD4R2=0.000000 |
| 1070IDD4W=0.165000 | 1070IDD4W=0.125000 |
| 1071IDD4W2=0.000000 | 1071IDD4W2=0.000000 |
| 1072IDD5=0.220000 | 1072IDD5=0.235000 |
| 1073IDD52=0.000000 | 1073IDD52=0.000000 |
| 1074IDD6=0.000000 | 1074IDD6=0.020000 |
| 1075IDD62=0.000000 1076VDD=1.500000 1077VDD2=0.000000 1078activation_limit=4 1079addr_mapping=RoRaBaCoCh 1080bank_groups_per_rank=0 1081banks_per_rank=8 1082burst_length=8 1083channels=1 1084clk_domain=system.clk_domain 1085conf_table_reported=true 1086default_p_state=UNDEFINED 1087device_bus_width=8 1088device_rowbuffer_size=1024 1089device_size=536870912 1090devices_per_rank=8 1091dll=true 1092eventq_index=0 1093in_addr_map=true | 1075IDD62=0.000000 1076VDD=1.500000 1077VDD2=0.000000 1078activation_limit=4 1079addr_mapping=RoRaBaCoCh 1080bank_groups_per_rank=0 1081banks_per_rank=8 1082burst_length=8 1083channels=1 1084clk_domain=system.clk_domain 1085conf_table_reported=true 1086default_p_state=UNDEFINED 1087device_bus_width=8 1088device_rowbuffer_size=1024 1089device_size=536870912 1090devices_per_rank=8 1091dll=true 1092eventq_index=0 1093in_addr_map=true |
| 1094kvm_map=true |
|
| 1094max_accesses_per_row=16 1095mem_sched_policy=frfcfs 1096min_writes_per_switch=16 1097null=false 1098p_state_clk_gate_bins=20 1099p_state_clk_gate_max=1000000000000 1100p_state_clk_gate_min=1000 1101page_policy=open_adaptive 1102power_model=Null | 1095max_accesses_per_row=16 1096mem_sched_policy=frfcfs 1097min_writes_per_switch=16 1098null=false 1099p_state_clk_gate_bins=20 1100p_state_clk_gate_max=1000000000000 1101p_state_clk_gate_min=1000 1102page_policy=open_adaptive 1103power_model=Null |
| 1103range=2147483648:2415919103 | 1104range=2147483648:2415919103:0:0:0:0 |
| 1104ranks_per_channel=2 1105read_buffer_size=32 1106static_backend_latency=10000 1107static_frontend_latency=10000 1108tBURST=5000 1109tCCD_L=0 1110tCK=1250 1111tCL=13750 --- 5 unchanged lines hidden (view full) --- 1117tRP=13750 1118tRRD=6000 1119tRRD_L=0 1120tRTP=7500 1121tRTW=2500 1122tWR=15000 1123tWTR=7500 1124tXAW=30000 | 1105ranks_per_channel=2 1106read_buffer_size=32 1107static_backend_latency=10000 1108static_frontend_latency=10000 1109tBURST=5000 1110tCCD_L=0 1111tCK=1250 1112tCL=13750 --- 5 unchanged lines hidden (view full) --- 1118tRP=13750 1119tRRD=6000 1120tRRD_L=0 1121tRTP=7500 1122tRTW=2500 1123tWR=15000 1124tWTR=7500 1125tXAW=30000 |
| 1125tXP=0 | 1126tXP=6000 |
| 1126tXPDLL=0 | 1127tXPDLL=0 |
| 1127tXS=0 | 1128tXS=270000 |
| 1128tXSDLL=0 1129write_buffer_size=64 1130write_high_thresh_perc=85 1131write_low_thresh_perc=50 1132port=system.membus.master[5] 1133 1134[system.realview] 1135type=RealView --- 336 unchanged lines hidden (view full) --- 1472type=Pl390 1473clk_domain=system.clk_domain 1474cpu_addr=738205696 1475cpu_pio_delay=10000 1476default_p_state=UNDEFINED 1477dist_addr=738201600 1478dist_pio_delay=10000 1479eventq_index=0 | 1129tXSDLL=0 1130write_buffer_size=64 1131write_high_thresh_perc=85 1132write_low_thresh_perc=50 1133port=system.membus.master[5] 1134 1135[system.realview] 1136type=RealView --- 336 unchanged lines hidden (view full) --- 1473type=Pl390 1474clk_domain=system.clk_domain 1475cpu_addr=738205696 1476cpu_pio_delay=10000 1477default_p_state=UNDEFINED 1478dist_addr=738201600 1479dist_pio_delay=10000 1480eventq_index=0 |
| 1480gem5_extensions=true | 1481gem5_extensions=false |
| 1481int_latency=10000 1482it_lines=128 1483p_state_clk_gate_bins=20 1484p_state_clk_gate_max=1000000000000 1485p_state_clk_gate_min=1000 1486platform=system.realview 1487power_model=Null 1488system=system --- 296 unchanged lines hidden (view full) --- 1785power_model=Null 1786system=system 1787pio=system.iobus.master[21] 1788 1789[system.realview.nvmem] 1790type=SimpleMemory 1791bandwidth=73.000000 1792clk_domain=system.clk_domain | 1482int_latency=10000 1483it_lines=128 1484p_state_clk_gate_bins=20 1485p_state_clk_gate_max=1000000000000 1486p_state_clk_gate_min=1000 1487platform=system.realview 1488power_model=Null 1489system=system --- 296 unchanged lines hidden (view full) --- 1786power_model=Null 1787system=system 1788pio=system.iobus.master[21] 1789 1790[system.realview.nvmem] 1791type=SimpleMemory 1792bandwidth=73.000000 1793clk_domain=system.clk_domain |
| 1793conf_table_reported=true | 1794conf_table_reported=false |
| 1794default_p_state=UNDEFINED 1795eventq_index=0 1796in_addr_map=true | 1795default_p_state=UNDEFINED 1796eventq_index=0 1797in_addr_map=true |
| 1798kvm_map=true |
|
| 1797latency=30000 1798latency_var=0 1799null=false 1800p_state_clk_gate_bins=20 1801p_state_clk_gate_max=1000000000000 1802p_state_clk_gate_min=1000 1803power_model=Null | 1799latency=30000 1800latency_var=0 1801null=false 1802p_state_clk_gate_bins=20 1803p_state_clk_gate_max=1000000000000 1804p_state_clk_gate_min=1000 1805power_model=Null |
| 1804range=0:67108863 | 1806range=0:67108863:0:0:0:0 |
| 1805port=system.membus.master[1] 1806 1807[system.realview.pci_host] 1808type=GenericPciHost 1809clk_domain=system.clk_domain 1810conf_base=805306368 1811conf_device_bits=12 1812conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 2027[system.realview.vram] 2028type=SimpleMemory 2029bandwidth=73.000000 2030clk_domain=system.clk_domain 2031conf_table_reported=false 2032default_p_state=UNDEFINED 2033eventq_index=0 2034in_addr_map=true | 1807port=system.membus.master[1] 1808 1809[system.realview.pci_host] 1810type=GenericPciHost 1811clk_domain=system.clk_domain 1812conf_base=805306368 1813conf_device_bits=12 1814conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 2029[system.realview.vram] 2030type=SimpleMemory 2031bandwidth=73.000000 2032clk_domain=system.clk_domain 2033conf_table_reported=false 2034default_p_state=UNDEFINED 2035eventq_index=0 2036in_addr_map=true |
| 2037kvm_map=true |
|
| 2035latency=30000 2036latency_var=0 2037null=false 2038p_state_clk_gate_bins=20 2039p_state_clk_gate_max=1000000000000 2040p_state_clk_gate_min=1000 2041power_model=Null | 2038latency=30000 2039latency_var=0 2040null=false 2041p_state_clk_gate_bins=20 2042p_state_clk_gate_max=1000000000000 2043p_state_clk_gate_min=1000 2044power_model=Null |
| 2042range=402653184:436207615 | 2045range=402653184:436207615:0:0:0:0 |
| 2043port=system.iobus.master[11] 2044 2045[system.realview.watchdog_fake] 2046type=AmbaFake 2047amba_id=0 2048clk_domain=system.clk_domain 2049default_p_state=UNDEFINED 2050eventq_index=0 --- 59 unchanged lines hidden --- | 2046port=system.iobus.master[11] 2047 2048[system.realview.watchdog_fake] 2049type=AmbaFake 2050amba_id=0 2051clk_domain=system.clk_domain 2052default_p_state=UNDEFINED 2053eventq_index=0 --- 59 unchanged lines hidden --- |