1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain 14atags_addr=134217728 |
15boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 |
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 17cache_line_size=64 18clk_domain=system.clk_domain |
19default_p_state=UNDEFINED 20dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb |
21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24exit_on_work_items=false 25flags_addr=469827632 26gic_cpu_addr=738205696 27have_large_asid_64=false |
28have_lpae=true |
29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 |
33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 |
34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 |
45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 |
48panic_on_oops=true 49panic_on_panic=true 50phys_addr_range_64=40 |
51power_model=Null 52readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh |
53reset_addr_64=0 54symbolfile= |
55thermal_components= 56thermal_model=Null |
57work_begin_ckpt_count=0 58work_begin_cpu_id_exit=-1 59work_begin_exit_count=0 60work_cpus_ckpt_count=0 61work_end_ckpt_count=0 62work_end_exit_count=0 63work_item_id=-1 64system_port=system.membus.slave[1] 65 66[system.bridge] 67type=Bridge 68clk_domain=system.clk_domain |
69default_p_state=UNDEFINED |
70delay=50000 71eventq_index=0 |
72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null |
76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk --- 10 unchanged lines hidden (view full) --- 94eventq_index=0 95image_file= 96read_only=false 97table_size=65536 98 99[system.cf0.image.child] 100type=RawDiskImage 101eventq_index=0 |
102image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img |
103read_only=true 104 105[system.clk_domain] 106type=SrcClockDomain 107clock=1000 108domain_id=-1 109eventq_index=0 110init_perf_level=0 111voltage_domain=system.voltage_domain 112 113[system.cpu0] 114type=TimingSimpleCPU 115children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 116branchPred=Null 117checker=Null 118clk_domain=system.cpu_clk_domain 119cpu_id=0 |
120default_p_state=UNDEFINED |
121do_checkpoint_insts=true 122do_quiesce=true 123do_statistics_insts=true 124dstage2_mmu=system.cpu0.dstage2_mmu 125dtb=system.cpu0.dtb 126eventq_index=0 127function_trace=false 128function_trace_start=0 129interrupts=system.cpu0.interrupts 130isa=system.cpu0.isa 131istage2_mmu=system.cpu0.istage2_mmu 132itb=system.cpu0.itb 133max_insts_all_threads=0 134max_insts_any_thread=0 135max_loads_all_threads=0 136max_loads_any_thread=0 137numThreads=1 |
138p_state_clk_gate_bins=20 139p_state_clk_gate_max=1000000000000 140p_state_clk_gate_min=1000 141power_model=Null |
142profile=0 143progress_interval=0 144simpoint_start_insts= 145socket_id=0 146switched_out=false 147system=system 148tracer=system.cpu0.tracer 149workload= 150dcache_port=system.cpu0.dcache.cpu_side 151icache_port=system.cpu0.icache.cpu_side 152 153[system.cpu0.dcache] 154type=Cache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159clusivity=mostly_incl |
160default_p_state=UNDEFINED |
161demand_mshr_reserve=1 162eventq_index=0 163hit_latency=2 164is_read_only=false 165max_miss_count=0 166mshrs=6 |
167p_state_clk_gate_bins=20 168p_state_clk_gate_max=1000000000000 169p_state_clk_gate_min=1000 170power_model=Null |
171prefetch_on_access=false 172prefetcher=Null 173response_latency=2 174sequential_access=false 175size=32768 176system=system 177tags=system.cpu0.dcache.tags 178tgts_per_mshr=8 179write_buffers=16 180writeback_clean=true 181cpu_side=system.cpu0.dcache_port 182mem_side=system.cpu0.toL2Bus.slave[1] 183 184[system.cpu0.dcache.tags] 185type=LRU 186assoc=2 187block_size=64 188clk_domain=system.cpu_clk_domain |
189default_p_state=UNDEFINED |
190eventq_index=0 191hit_latency=2 |
192p_state_clk_gate_bins=20 193p_state_clk_gate_max=1000000000000 194p_state_clk_gate_min=1000 195power_model=Null |
196sequential_access=false 197size=32768 198 199[system.cpu0.dstage2_mmu] 200type=ArmStage2MMU 201children=stage2_tlb 202eventq_index=0 203stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 210eventq_index=0 211is_stage2=true 212size=32 213walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 214 215[system.cpu0.dstage2_mmu.stage2_tlb.walker] 216type=ArmTableWalker 217clk_domain=system.cpu_clk_domain |
218default_p_state=UNDEFINED |
219eventq_index=0 220is_stage2=true 221num_squash_per_cycle=2 |
222p_state_clk_gate_bins=20 223p_state_clk_gate_max=1000000000000 224p_state_clk_gate_min=1000 225power_model=Null |
226sys=system 227 228[system.cpu0.dtb] 229type=ArmTLB 230children=walker 231eventq_index=0 232is_stage2=false 233size=64 234walker=system.cpu0.dtb.walker 235 236[system.cpu0.dtb.walker] 237type=ArmTableWalker 238clk_domain=system.cpu_clk_domain |
239default_p_state=UNDEFINED |
240eventq_index=0 241is_stage2=false 242num_squash_per_cycle=2 |
243p_state_clk_gate_bins=20 244p_state_clk_gate_max=1000000000000 245p_state_clk_gate_min=1000 246power_model=Null |
247sys=system 248port=system.cpu0.toL2Bus.slave[3] 249 250[system.cpu0.icache] 251type=Cache 252children=tags 253addr_ranges=0:18446744073709551615 254assoc=2 255clk_domain=system.cpu_clk_domain 256clusivity=mostly_incl |
257default_p_state=UNDEFINED |
258demand_mshr_reserve=1 259eventq_index=0 260hit_latency=1 261is_read_only=true 262max_miss_count=0 263mshrs=2 |
264p_state_clk_gate_bins=20 265p_state_clk_gate_max=1000000000000 266p_state_clk_gate_min=1000 267power_model=Null |
268prefetch_on_access=false 269prefetcher=Null 270response_latency=1 271sequential_access=false 272size=32768 273system=system 274tags=system.cpu0.icache.tags 275tgts_per_mshr=8 276write_buffers=8 277writeback_clean=true 278cpu_side=system.cpu0.icache_port 279mem_side=system.cpu0.toL2Bus.slave[0] 280 281[system.cpu0.icache.tags] 282type=LRU 283assoc=2 284block_size=64 285clk_domain=system.cpu_clk_domain |
286default_p_state=UNDEFINED |
287eventq_index=0 288hit_latency=1 |
289p_state_clk_gate_bins=20 290p_state_clk_gate_max=1000000000000 291p_state_clk_gate_min=1000 292power_model=Null |
293sequential_access=false 294size=32768 295 296[system.cpu0.interrupts] 297type=ArmInterrupts 298eventq_index=0 299 300[system.cpu0.isa] --- 41 unchanged lines hidden (view full) --- 342eventq_index=0 343is_stage2=true 344size=32 345walker=system.cpu0.istage2_mmu.stage2_tlb.walker 346 347[system.cpu0.istage2_mmu.stage2_tlb.walker] 348type=ArmTableWalker 349clk_domain=system.cpu_clk_domain |
350default_p_state=UNDEFINED |
351eventq_index=0 352is_stage2=true 353num_squash_per_cycle=2 |
354p_state_clk_gate_bins=20 355p_state_clk_gate_max=1000000000000 356p_state_clk_gate_min=1000 357power_model=Null |
358sys=system 359 360[system.cpu0.itb] 361type=ArmTLB 362children=walker 363eventq_index=0 364is_stage2=false 365size=64 366walker=system.cpu0.itb.walker 367 368[system.cpu0.itb.walker] 369type=ArmTableWalker 370clk_domain=system.cpu_clk_domain |
371default_p_state=UNDEFINED |
372eventq_index=0 373is_stage2=false 374num_squash_per_cycle=2 |
375p_state_clk_gate_bins=20 376p_state_clk_gate_max=1000000000000 377p_state_clk_gate_min=1000 378power_model=Null |
379sys=system 380port=system.cpu0.toL2Bus.slave[2] 381 382[system.cpu0.l2cache] 383type=Cache 384children=prefetcher tags 385addr_ranges=0:18446744073709551615 386assoc=16 387clk_domain=system.cpu_clk_domain 388clusivity=mostly_excl |
389default_p_state=UNDEFINED |
390demand_mshr_reserve=1 391eventq_index=0 392hit_latency=12 393is_read_only=false 394max_miss_count=0 395mshrs=16 |
396p_state_clk_gate_bins=20 397p_state_clk_gate_max=1000000000000 398p_state_clk_gate_min=1000 399power_model=Null |
400prefetch_on_access=true 401prefetcher=system.cpu0.l2cache.prefetcher 402response_latency=12 403sequential_access=false 404size=1048576 405system=system 406tags=system.cpu0.l2cache.tags 407tgts_per_mshr=8 408write_buffers=8 409writeback_clean=false 410cpu_side=system.cpu0.toL2Bus.master[0] 411mem_side=system.toL2Bus.slave[0] 412 413[system.cpu0.l2cache.prefetcher] 414type=StridePrefetcher 415cache_snoop=false 416clk_domain=system.cpu_clk_domain |
417default_p_state=UNDEFINED |
418degree=8 419eventq_index=0 420latency=1 421max_conf=7 422min_conf=0 423on_data=true 424on_inst=true 425on_miss=false 426on_read=true 427on_write=true |
428p_state_clk_gate_bins=20 429p_state_clk_gate_max=1000000000000 430p_state_clk_gate_min=1000 431power_model=Null |
432queue_filter=true 433queue_size=32 434queue_squash=true 435start_conf=4 436sys=system 437table_assoc=4 438table_sets=16 439tag_prefetch=true 440thresh_conf=4 441use_master_id=true 442 443[system.cpu0.l2cache.tags] 444type=RandomRepl 445assoc=16 446block_size=64 447clk_domain=system.cpu_clk_domain |
448default_p_state=UNDEFINED |
449eventq_index=0 450hit_latency=12 |
451p_state_clk_gate_bins=20 452p_state_clk_gate_max=1000000000000 453p_state_clk_gate_min=1000 454power_model=Null |
455sequential_access=false 456size=1048576 457 458[system.cpu0.toL2Bus] 459type=CoherentXBar 460children=snoop_filter 461clk_domain=system.cpu_clk_domain |
462default_p_state=UNDEFINED |
463eventq_index=0 464forward_latency=0 465frontend_latency=1 |
466p_state_clk_gate_bins=20 467p_state_clk_gate_max=1000000000000 468p_state_clk_gate_min=1000 |
469point_of_coherency=false |
470power_model=Null |
471response_latency=1 472snoop_filter=system.cpu0.toL2Bus.snoop_filter 473snoop_response_latency=1 474system=system 475use_default_range=false 476width=32 477master=system.cpu0.l2cache.cpu_side 478slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port --- 11 unchanged lines hidden (view full) --- 490 491[system.cpu1] 492type=TimingSimpleCPU 493children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer 494branchPred=Null 495checker=Null 496clk_domain=system.cpu_clk_domain 497cpu_id=1 |
498default_p_state=UNDEFINED |
499do_checkpoint_insts=true 500do_quiesce=true 501do_statistics_insts=true 502dstage2_mmu=system.cpu1.dstage2_mmu 503dtb=system.cpu1.dtb 504eventq_index=0 505function_trace=false 506function_trace_start=0 507interrupts=system.cpu1.interrupts 508isa=system.cpu1.isa 509istage2_mmu=system.cpu1.istage2_mmu 510itb=system.cpu1.itb 511max_insts_all_threads=0 512max_insts_any_thread=0 513max_loads_all_threads=0 514max_loads_any_thread=0 515numThreads=1 |
516p_state_clk_gate_bins=20 517p_state_clk_gate_max=1000000000000 518p_state_clk_gate_min=1000 519power_model=Null |
520profile=0 521progress_interval=0 522simpoint_start_insts= 523socket_id=0 524switched_out=false 525system=system 526tracer=system.cpu1.tracer 527workload= 528dcache_port=system.cpu1.dcache.cpu_side 529icache_port=system.cpu1.icache.cpu_side 530 531[system.cpu1.dcache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl |
538default_p_state=UNDEFINED |
539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=false 543max_miss_count=0 544mshrs=6 |
545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null |
549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=32768 554system=system 555tags=system.cpu1.dcache.tags 556tgts_per_mshr=8 557write_buffers=16 558writeback_clean=true 559cpu_side=system.cpu1.dcache_port 560mem_side=system.cpu1.toL2Bus.slave[1] 561 562[system.cpu1.dcache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain |
567default_p_state=UNDEFINED |
568eventq_index=0 569hit_latency=2 |
570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null |
574sequential_access=false 575size=32768 576 577[system.cpu1.dstage2_mmu] 578type=ArmStage2MMU 579children=stage2_tlb 580eventq_index=0 581stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 588eventq_index=0 589is_stage2=true 590size=32 591walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 592 593[system.cpu1.dstage2_mmu.stage2_tlb.walker] 594type=ArmTableWalker 595clk_domain=system.cpu_clk_domain |
596default_p_state=UNDEFINED |
597eventq_index=0 598is_stage2=true 599num_squash_per_cycle=2 |
600p_state_clk_gate_bins=20 601p_state_clk_gate_max=1000000000000 602p_state_clk_gate_min=1000 603power_model=Null |
604sys=system 605 606[system.cpu1.dtb] 607type=ArmTLB 608children=walker 609eventq_index=0 610is_stage2=false 611size=64 612walker=system.cpu1.dtb.walker 613 614[system.cpu1.dtb.walker] 615type=ArmTableWalker 616clk_domain=system.cpu_clk_domain |
617default_p_state=UNDEFINED |
618eventq_index=0 619is_stage2=false 620num_squash_per_cycle=2 |
621p_state_clk_gate_bins=20 622p_state_clk_gate_max=1000000000000 623p_state_clk_gate_min=1000 624power_model=Null |
625sys=system 626port=system.cpu1.toL2Bus.slave[3] 627 628[system.cpu1.icache] 629type=Cache 630children=tags 631addr_ranges=0:18446744073709551615 632assoc=2 633clk_domain=system.cpu_clk_domain 634clusivity=mostly_incl |
635default_p_state=UNDEFINED |
636demand_mshr_reserve=1 637eventq_index=0 638hit_latency=1 639is_read_only=true 640max_miss_count=0 641mshrs=2 |
642p_state_clk_gate_bins=20 643p_state_clk_gate_max=1000000000000 644p_state_clk_gate_min=1000 645power_model=Null |
646prefetch_on_access=false 647prefetcher=Null 648response_latency=1 649sequential_access=false 650size=32768 651system=system 652tags=system.cpu1.icache.tags 653tgts_per_mshr=8 654write_buffers=8 655writeback_clean=true 656cpu_side=system.cpu1.icache_port 657mem_side=system.cpu1.toL2Bus.slave[0] 658 659[system.cpu1.icache.tags] 660type=LRU 661assoc=2 662block_size=64 663clk_domain=system.cpu_clk_domain |
664default_p_state=UNDEFINED |
665eventq_index=0 666hit_latency=1 |
667p_state_clk_gate_bins=20 668p_state_clk_gate_max=1000000000000 669p_state_clk_gate_min=1000 670power_model=Null |
671sequential_access=false 672size=32768 673 674[system.cpu1.interrupts] 675type=ArmInterrupts 676eventq_index=0 677 678[system.cpu1.isa] --- 41 unchanged lines hidden (view full) --- 720eventq_index=0 721is_stage2=true 722size=32 723walker=system.cpu1.istage2_mmu.stage2_tlb.walker 724 725[system.cpu1.istage2_mmu.stage2_tlb.walker] 726type=ArmTableWalker 727clk_domain=system.cpu_clk_domain |
728default_p_state=UNDEFINED |
729eventq_index=0 730is_stage2=true 731num_squash_per_cycle=2 |
732p_state_clk_gate_bins=20 733p_state_clk_gate_max=1000000000000 734p_state_clk_gate_min=1000 735power_model=Null |
736sys=system 737 738[system.cpu1.itb] 739type=ArmTLB 740children=walker 741eventq_index=0 742is_stage2=false 743size=64 744walker=system.cpu1.itb.walker 745 746[system.cpu1.itb.walker] 747type=ArmTableWalker 748clk_domain=system.cpu_clk_domain |
749default_p_state=UNDEFINED |
750eventq_index=0 751is_stage2=false 752num_squash_per_cycle=2 |
753p_state_clk_gate_bins=20 754p_state_clk_gate_max=1000000000000 755p_state_clk_gate_min=1000 756power_model=Null |
757sys=system 758port=system.cpu1.toL2Bus.slave[2] 759 760[system.cpu1.l2cache] 761type=Cache 762children=prefetcher tags 763addr_ranges=0:18446744073709551615 764assoc=16 765clk_domain=system.cpu_clk_domain 766clusivity=mostly_excl |
767default_p_state=UNDEFINED |
768demand_mshr_reserve=1 769eventq_index=0 770hit_latency=12 771is_read_only=false 772max_miss_count=0 773mshrs=16 |
774p_state_clk_gate_bins=20 775p_state_clk_gate_max=1000000000000 776p_state_clk_gate_min=1000 777power_model=Null |
778prefetch_on_access=true 779prefetcher=system.cpu1.l2cache.prefetcher 780response_latency=12 781sequential_access=false 782size=1048576 783system=system 784tags=system.cpu1.l2cache.tags 785tgts_per_mshr=8 786write_buffers=8 787writeback_clean=false 788cpu_side=system.cpu1.toL2Bus.master[0] 789mem_side=system.toL2Bus.slave[1] 790 791[system.cpu1.l2cache.prefetcher] 792type=StridePrefetcher 793cache_snoop=false 794clk_domain=system.cpu_clk_domain |
795default_p_state=UNDEFINED |
796degree=8 797eventq_index=0 798latency=1 799max_conf=7 800min_conf=0 801on_data=true 802on_inst=true 803on_miss=false 804on_read=true 805on_write=true |
806p_state_clk_gate_bins=20 807p_state_clk_gate_max=1000000000000 808p_state_clk_gate_min=1000 809power_model=Null |
810queue_filter=true 811queue_size=32 812queue_squash=true 813start_conf=4 814sys=system 815table_assoc=4 816table_sets=16 817tag_prefetch=true 818thresh_conf=4 819use_master_id=true 820 821[system.cpu1.l2cache.tags] 822type=RandomRepl 823assoc=16 824block_size=64 825clk_domain=system.cpu_clk_domain |
826default_p_state=UNDEFINED |
827eventq_index=0 828hit_latency=12 |
829p_state_clk_gate_bins=20 830p_state_clk_gate_max=1000000000000 831p_state_clk_gate_min=1000 832power_model=Null |
833sequential_access=false 834size=1048576 835 836[system.cpu1.toL2Bus] 837type=CoherentXBar 838children=snoop_filter 839clk_domain=system.cpu_clk_domain |
840default_p_state=UNDEFINED |
841eventq_index=0 842forward_latency=0 843frontend_latency=1 |
844p_state_clk_gate_bins=20 845p_state_clk_gate_max=1000000000000 846p_state_clk_gate_min=1000 |
847point_of_coherency=false |
848power_model=Null |
849response_latency=1 850snoop_filter=system.cpu1.toL2Bus.snoop_filter 851snoop_response_latency=1 852system=system 853use_default_range=false 854width=32 855master=system.cpu1.l2cache.cpu_side 856slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port --- 28 unchanged lines hidden (view full) --- 885[system.intrctrl] 886type=IntrControl 887eventq_index=0 888sys=system 889 890[system.iobus] 891type=NoncoherentXBar 892clk_domain=system.clk_domain |
893default_p_state=UNDEFINED |
894eventq_index=0 895forward_latency=1 896frontend_latency=2 |
897p_state_clk_gate_bins=20 898p_state_clk_gate_max=1000000000000 899p_state_clk_gate_min=1000 900power_model=Null |
901response_latency=2 902use_default_range=false 903width=16 904master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 905slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 906 907[system.iocache] 908type=Cache 909children=tags 910addr_ranges=2147483648:2415919103 911assoc=8 912clk_domain=system.clk_domain 913clusivity=mostly_incl |
914default_p_state=UNDEFINED |
915demand_mshr_reserve=1 916eventq_index=0 917hit_latency=50 918is_read_only=false 919max_miss_count=0 920mshrs=20 |
921p_state_clk_gate_bins=20 922p_state_clk_gate_max=1000000000000 923p_state_clk_gate_min=1000 924power_model=Null |
925prefetch_on_access=false 926prefetcher=Null 927response_latency=50 928sequential_access=false 929size=1024 930system=system 931tags=system.iocache.tags 932tgts_per_mshr=12 933write_buffers=8 934writeback_clean=false 935cpu_side=system.iobus.master[25] 936mem_side=system.membus.slave[3] 937 938[system.iocache.tags] 939type=LRU 940assoc=8 941block_size=64 942clk_domain=system.clk_domain |
943default_p_state=UNDEFINED |
944eventq_index=0 945hit_latency=50 |
946p_state_clk_gate_bins=20 947p_state_clk_gate_max=1000000000000 948p_state_clk_gate_min=1000 949power_model=Null |
950sequential_access=false 951size=1024 952 953[system.l2c] 954type=Cache 955children=tags 956addr_ranges=0:18446744073709551615 957assoc=8 958clk_domain=system.cpu_clk_domain 959clusivity=mostly_incl |
960default_p_state=UNDEFINED |
961demand_mshr_reserve=1 962eventq_index=0 963hit_latency=20 964is_read_only=false 965max_miss_count=0 966mshrs=20 |
967p_state_clk_gate_bins=20 968p_state_clk_gate_max=1000000000000 969p_state_clk_gate_min=1000 970power_model=Null |
971prefetch_on_access=false 972prefetcher=Null 973response_latency=20 974sequential_access=false 975size=4194304 976system=system 977tags=system.l2c.tags 978tgts_per_mshr=12 979write_buffers=8 980writeback_clean=false 981cpu_side=system.toL2Bus.master[0] 982mem_side=system.membus.slave[2] 983 984[system.l2c.tags] 985type=LRU 986assoc=8 987block_size=64 988clk_domain=system.cpu_clk_domain |
989default_p_state=UNDEFINED |
990eventq_index=0 991hit_latency=20 |
992p_state_clk_gate_bins=20 993p_state_clk_gate_max=1000000000000 994p_state_clk_gate_min=1000 995power_model=Null |
996sequential_access=false 997size=4194304 998 999[system.membus] 1000type=CoherentXBar |
1001children=badaddr_responder snoop_filter |
1002clk_domain=system.clk_domain |
1003default_p_state=UNDEFINED |
1004eventq_index=0 1005forward_latency=4 1006frontend_latency=3 |
1007p_state_clk_gate_bins=20 1008p_state_clk_gate_max=1000000000000 1009p_state_clk_gate_min=1000 |
1010point_of_coherency=true |
1011power_model=Null |
1012response_latency=2 |
1013snoop_filter=system.membus.snoop_filter |
1014snoop_response_latency=4 1015system=system 1016use_default_range=false 1017width=16 1018default=system.membus.badaddr_responder.pio 1019master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port 1020slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side 1021 1022[system.membus.badaddr_responder] 1023type=IsaFake 1024clk_domain=system.clk_domain |
1025default_p_state=UNDEFINED |
1026eventq_index=0 1027fake_mem=false |
1028p_state_clk_gate_bins=20 1029p_state_clk_gate_max=1000000000000 1030p_state_clk_gate_min=1000 |
1031pio_addr=0 1032pio_latency=100000 1033pio_size=8 |
1034power_model=Null |
1035ret_bad_addr=true 1036ret_data16=65535 1037ret_data32=4294967295 1038ret_data64=18446744073709551615 1039ret_data8=255 1040system=system 1041update_data=false 1042warn_access=warn 1043pio=system.membus.default 1044 |
1045[system.membus.snoop_filter] 1046type=SnoopFilter 1047eventq_index=0 1048lookup_latency=1 1049max_capacity=8388608 1050system=system 1051 |
1052[system.physmem] 1053type=DRAMCtrl 1054IDD0=0.075000 1055IDD02=0.000000 1056IDD2N=0.050000 1057IDD2N2=0.000000 1058IDD2P0=0.000000 1059IDD2P02=0.000000 --- 18 unchanged lines hidden (view full) --- 1078activation_limit=4 1079addr_mapping=RoRaBaCoCh 1080bank_groups_per_rank=0 1081banks_per_rank=8 1082burst_length=8 1083channels=1 1084clk_domain=system.clk_domain 1085conf_table_reported=true |
1086default_p_state=UNDEFINED |
1087device_bus_width=8 1088device_rowbuffer_size=1024 1089device_size=536870912 1090devices_per_rank=8 1091dll=true 1092eventq_index=0 1093in_addr_map=true 1094max_accesses_per_row=16 1095mem_sched_policy=frfcfs 1096min_writes_per_switch=16 1097null=false |
1098p_state_clk_gate_bins=20 1099p_state_clk_gate_max=1000000000000 1100p_state_clk_gate_min=1000 |
1101page_policy=open_adaptive |
1102power_model=Null |
1103range=2147483648:2415919103 1104ranks_per_channel=2 1105read_buffer_size=32 1106static_backend_latency=10000 1107static_frontend_latency=10000 1108tBURST=5000 1109tCCD_L=0 1110tCK=1250 --- 26 unchanged lines hidden (view full) --- 1137eventq_index=0 1138intrctrl=system.intrctrl 1139system=system 1140 1141[system.realview.aaci_fake] 1142type=AmbaFake 1143amba_id=0 1144clk_domain=system.clk_domain |
1145default_p_state=UNDEFINED |
1146eventq_index=0 1147ignore_access=false |
1148p_state_clk_gate_bins=20 1149p_state_clk_gate_max=1000000000000 1150p_state_clk_gate_min=1000 |
1151pio_addr=470024192 1152pio_latency=100000 |
1153power_model=Null |
1154system=system 1155pio=system.iobus.master[18] 1156 1157[system.realview.cf_ctrl] 1158type=IdeController 1159BAR0=471465984 1160BAR0LegacyIO=true 1161BAR0Size=256 --- 64 unchanged lines hidden (view full) --- 1226Status=640 1227SubClassCode=1 1228SubsystemID=0 1229SubsystemVendorID=0 1230VendorID=32902 1231clk_domain=system.clk_domain 1232config_latency=20000 1233ctrl_offset=2 |
1234default_p_state=UNDEFINED |
1235disks= 1236eventq_index=0 1237host=system.realview.pci_host 1238io_shift=2 |
1239p_state_clk_gate_bins=20 1240p_state_clk_gate_max=1000000000000 1241p_state_clk_gate_min=1000 |
1242pci_bus=2 1243pci_dev=0 1244pci_func=0 1245pio_latency=30000 |
1246power_model=Null |
1247system=system 1248dma=system.iobus.slave[2] 1249pio=system.iobus.master[9] 1250 1251[system.realview.clcd] 1252type=Pl111 1253amba_id=1315089 1254clk_domain=system.clk_domain |
1255default_p_state=UNDEFINED |
1256enable_capture=true 1257eventq_index=0 1258gic=system.realview.gic 1259int_num=46 |
1260p_state_clk_gate_bins=20 1261p_state_clk_gate_max=1000000000000 1262p_state_clk_gate_min=1000 |
1263pio_addr=471793664 1264pio_latency=10000 1265pixel_clock=41667 |
1266power_model=Null |
1267system=system 1268vnc=system.vncserver 1269dma=system.iobus.slave[1] 1270pio=system.iobus.master[5] 1271 1272[system.realview.dcc] 1273type=SubSystem 1274children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys 1275eventq_index=0 |
1276thermal_domain=Null |
1277 1278[system.realview.dcc.osc_cpu] 1279type=RealViewOsc 1280dcc=0 1281device=0 1282eventq_index=0 1283freq=16667 1284parent=system.realview.realview_io --- 54 unchanged lines hidden (view full) --- 1339parent=system.realview.realview_io 1340position=0 1341site=1 1342voltage_domain=system.voltage_domain 1343 1344[system.realview.energy_ctrl] 1345type=EnergyCtrl 1346clk_domain=system.clk_domain |
1347default_p_state=UNDEFINED |
1348dvfs_handler=system.dvfs_handler 1349eventq_index=0 |
1350p_state_clk_gate_bins=20 1351p_state_clk_gate_max=1000000000000 1352p_state_clk_gate_min=1000 |
1353pio_addr=470286336 1354pio_latency=100000 |
1355power_model=Null |
1356system=system 1357pio=system.iobus.master[22] 1358 1359[system.realview.ethernet] 1360type=IGbE 1361BAR0=0 1362BAR0LegacyIO=false 1363BAR0Size=131072 --- 63 unchanged lines hidden (view full) --- 1427Revision=0 1428Status=0 1429SubClassCode=0 1430SubsystemID=4104 1431SubsystemVendorID=32902 1432VendorID=32902 1433clk_domain=system.clk_domain 1434config_latency=20000 |
1435default_p_state=UNDEFINED |
1436eventq_index=0 1437fetch_comp_delay=10000 1438fetch_delay=10000 1439hardware_address=00:90:00:00:00:01 1440host=system.realview.pci_host |
1441p_state_clk_gate_bins=20 1442p_state_clk_gate_max=1000000000000 1443p_state_clk_gate_min=1000 |
1444pci_bus=0 1445pci_dev=0 1446pci_func=0 1447phy_epid=896 1448phy_pid=680 1449pio_latency=30000 |
1450power_model=Null |
1451rx_desc_cache_size=64 1452rx_fifo_size=393216 1453rx_write_delay=0 1454system=system 1455tx_desc_cache_size=64 1456tx_fifo_size=393216 1457tx_read_delay=0 1458wb_comp_delay=10000 --- 9 unchanged lines hidden (view full) --- 1468int_virt=27 1469system=system 1470 1471[system.realview.gic] 1472type=Pl390 1473clk_domain=system.clk_domain 1474cpu_addr=738205696 1475cpu_pio_delay=10000 |
1476default_p_state=UNDEFINED |
1477dist_addr=738201600 1478dist_pio_delay=10000 1479eventq_index=0 |
1480gem5_extensions=true |
1481int_latency=10000 1482it_lines=128 |
1483p_state_clk_gate_bins=20 1484p_state_clk_gate_max=1000000000000 1485p_state_clk_gate_min=1000 |
1486platform=system.realview |
1487power_model=Null |
1488system=system 1489pio=system.membus.master[2] 1490 1491[system.realview.hdlcd] 1492type=HDLcd 1493amba_id=1314816 1494clk_domain=system.clk_domain |
1495default_p_state=UNDEFINED |
1496enable_capture=true 1497eventq_index=0 1498gic=system.realview.gic 1499int_num=117 |
1500p_state_clk_gate_bins=20 1501p_state_clk_gate_max=1000000000000 1502p_state_clk_gate_min=1000 |
1503pio_addr=721420288 1504pio_latency=10000 1505pixel_buffer_size=2048 1506pixel_chunk=32 |
1507power_model=Null |
1508pxl_clk=system.realview.dcc.osc_pxl 1509system=system 1510vnc=system.vncserver 1511workaround_dma_line_count=true 1512workaround_swap_rb=true 1513dma=system.membus.slave[0] 1514pio=system.iobus.master[6] 1515 --- 69 unchanged lines hidden (view full) --- 1585Status=640 1586SubClassCode=1 1587SubsystemID=0 1588SubsystemVendorID=0 1589VendorID=32902 1590clk_domain=system.clk_domain 1591config_latency=20000 1592ctrl_offset=0 |
1593default_p_state=UNDEFINED |
1594disks=system.cf0 1595eventq_index=0 1596host=system.realview.pci_host 1597io_shift=0 |
1598p_state_clk_gate_bins=20 1599p_state_clk_gate_max=1000000000000 1600p_state_clk_gate_min=1000 |
1601pci_bus=0 1602pci_dev=1 1603pci_func=0 1604pio_latency=30000 |
1605power_model=Null |
1606system=system 1607dma=system.iobus.slave[3] 1608pio=system.iobus.master[23] 1609 1610[system.realview.kmi0] 1611type=Pl050 1612amba_id=1314896 1613clk_domain=system.clk_domain |
1614default_p_state=UNDEFINED |
1615eventq_index=0 1616gic=system.realview.gic 1617int_delay=1000000 1618int_num=44 1619is_mouse=false |
1620p_state_clk_gate_bins=20 1621p_state_clk_gate_max=1000000000000 1622p_state_clk_gate_min=1000 |
1623pio_addr=470155264 1624pio_latency=100000 |
1625power_model=Null |
1626system=system 1627vnc=system.vncserver 1628pio=system.iobus.master[7] 1629 1630[system.realview.kmi1] 1631type=Pl050 1632amba_id=1314896 1633clk_domain=system.clk_domain |
1634default_p_state=UNDEFINED |
1635eventq_index=0 1636gic=system.realview.gic 1637int_delay=1000000 1638int_num=45 1639is_mouse=true |
1640p_state_clk_gate_bins=20 1641p_state_clk_gate_max=1000000000000 1642p_state_clk_gate_min=1000 |
1643pio_addr=470220800 1644pio_latency=100000 |
1645power_model=Null |
1646system=system 1647vnc=system.vncserver 1648pio=system.iobus.master[8] 1649 1650[system.realview.l2x0_fake] 1651type=IsaFake 1652clk_domain=system.clk_domain |
1653default_p_state=UNDEFINED |
1654eventq_index=0 1655fake_mem=false |
1656p_state_clk_gate_bins=20 1657p_state_clk_gate_max=1000000000000 1658p_state_clk_gate_min=1000 |
1659pio_addr=739246080 1660pio_latency=100000 1661pio_size=4095 |
1662power_model=Null |
1663ret_bad_addr=false 1664ret_data16=65535 1665ret_data32=4294967295 1666ret_data64=18446744073709551615 1667ret_data8=255 1668system=system 1669update_data=false 1670warn_access= 1671pio=system.iobus.master[12] 1672 1673[system.realview.lan_fake] 1674type=IsaFake 1675clk_domain=system.clk_domain |
1676default_p_state=UNDEFINED |
1677eventq_index=0 1678fake_mem=false |
1679p_state_clk_gate_bins=20 1680p_state_clk_gate_max=1000000000000 1681p_state_clk_gate_min=1000 |
1682pio_addr=436207616 1683pio_latency=100000 1684pio_size=65535 |
1685power_model=Null |
1686ret_bad_addr=false 1687ret_data16=65535 1688ret_data32=4294967295 1689ret_data64=18446744073709551615 1690ret_data8=255 1691system=system 1692update_data=false 1693warn_access= 1694pio=system.iobus.master[19] 1695 1696[system.realview.local_cpu_timer] 1697type=CpuLocalTimer 1698clk_domain=system.clk_domain |
1699default_p_state=UNDEFINED |
1700eventq_index=0 1701gic=system.realview.gic 1702int_num_timer=29 1703int_num_watchdog=30 |
1704p_state_clk_gate_bins=20 1705p_state_clk_gate_max=1000000000000 1706p_state_clk_gate_min=1000 |
1707pio_addr=738721792 1708pio_latency=100000 |
1709power_model=Null |
1710system=system 1711pio=system.membus.master[4] 1712 1713[system.realview.mcc] 1714type=SubSystem |
1715children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl |
1716eventq_index=0 |
1717thermal_domain=Null |
1718 1719[system.realview.mcc.osc_clcd] 1720type=RealViewOsc 1721dcc=0 1722device=1 1723eventq_index=0 1724freq=42105 1725parent=system.realview.realview_io --- 29 unchanged lines hidden (view full) --- 1755device=4 1756eventq_index=0 1757freq=41667 1758parent=system.realview.realview_io 1759position=0 1760site=0 1761voltage_domain=system.voltage_domain 1762 |
1763[system.realview.mcc.temp_crtl] 1764type=RealViewTemperatureSensor 1765dcc=0 1766device=0 1767eventq_index=0 1768parent=system.realview.realview_io 1769position=0 1770site=0 1771system=system 1772 |
1773[system.realview.mmc_fake] 1774type=AmbaFake 1775amba_id=0 1776clk_domain=system.clk_domain |
1777default_p_state=UNDEFINED |
1778eventq_index=0 1779ignore_access=false |
1780p_state_clk_gate_bins=20 1781p_state_clk_gate_max=1000000000000 1782p_state_clk_gate_min=1000 |
1783pio_addr=470089728 1784pio_latency=100000 |
1785power_model=Null |
1786system=system 1787pio=system.iobus.master[21] 1788 1789[system.realview.nvmem] 1790type=SimpleMemory 1791bandwidth=73.000000 1792clk_domain=system.clk_domain 1793conf_table_reported=true |
1794default_p_state=UNDEFINED |
1795eventq_index=0 1796in_addr_map=true 1797latency=30000 1798latency_var=0 1799null=false |
1800p_state_clk_gate_bins=20 1801p_state_clk_gate_max=1000000000000 1802p_state_clk_gate_min=1000 1803power_model=Null |
1804range=0:67108863 1805port=system.membus.master[1] 1806 1807[system.realview.pci_host] 1808type=GenericPciHost 1809clk_domain=system.clk_domain 1810conf_base=805306368 1811conf_device_bits=12 1812conf_size=268435456 |
1813default_p_state=UNDEFINED |
1814eventq_index=0 |
1815p_state_clk_gate_bins=20 1816p_state_clk_gate_max=1000000000000 1817p_state_clk_gate_min=1000 |
1818pci_dma_base=0 1819pci_mem_base=0 1820pci_pio_base=788529152 1821platform=system.realview |
1822power_model=Null |
1823system=system 1824pio=system.iobus.master[2] 1825 1826[system.realview.realview_io] 1827type=RealViewCtrl 1828clk_domain=system.clk_domain |
1829default_p_state=UNDEFINED |
1830eventq_index=0 1831idreg=35979264 |
1832p_state_clk_gate_bins=20 1833p_state_clk_gate_max=1000000000000 1834p_state_clk_gate_min=1000 |
1835pio_addr=469827584 1836pio_latency=100000 |
1837power_model=Null |
1838proc_id0=335544320 1839proc_id1=335544320 1840system=system 1841pio=system.iobus.master[1] 1842 1843[system.realview.rtc] 1844type=PL031 1845amba_id=3412017 1846clk_domain=system.clk_domain |
1847default_p_state=UNDEFINED |
1848eventq_index=0 1849gic=system.realview.gic 1850int_delay=100000 1851int_num=36 |
1852p_state_clk_gate_bins=20 1853p_state_clk_gate_max=1000000000000 1854p_state_clk_gate_min=1000 |
1855pio_addr=471269376 1856pio_latency=100000 |
1857power_model=Null |
1858system=system 1859time=Thu Jan 1 00:00:00 2009 1860pio=system.iobus.master[10] 1861 1862[system.realview.sp810_fake] 1863type=AmbaFake 1864amba_id=0 1865clk_domain=system.clk_domain |
1866default_p_state=UNDEFINED |
1867eventq_index=0 1868ignore_access=true |
1869p_state_clk_gate_bins=20 1870p_state_clk_gate_max=1000000000000 1871p_state_clk_gate_min=1000 |
1872pio_addr=469893120 1873pio_latency=100000 |
1874power_model=Null |
1875system=system 1876pio=system.iobus.master[16] 1877 1878[system.realview.timer0] 1879type=Sp804 1880amba_id=1316868 1881clk_domain=system.clk_domain 1882clock0=1000000 1883clock1=1000000 |
1884default_p_state=UNDEFINED |
1885eventq_index=0 1886gic=system.realview.gic 1887int_num0=34 1888int_num1=34 |
1889p_state_clk_gate_bins=20 1890p_state_clk_gate_max=1000000000000 1891p_state_clk_gate_min=1000 |
1892pio_addr=470876160 1893pio_latency=100000 |
1894power_model=Null |
1895system=system 1896pio=system.iobus.master[3] 1897 1898[system.realview.timer1] 1899type=Sp804 1900amba_id=1316868 1901clk_domain=system.clk_domain 1902clock0=1000000 1903clock1=1000000 |
1904default_p_state=UNDEFINED |
1905eventq_index=0 1906gic=system.realview.gic 1907int_num0=35 1908int_num1=35 |
1909p_state_clk_gate_bins=20 1910p_state_clk_gate_max=1000000000000 1911p_state_clk_gate_min=1000 |
1912pio_addr=470941696 1913pio_latency=100000 |
1914power_model=Null |
1915system=system 1916pio=system.iobus.master[4] 1917 1918[system.realview.uart] 1919type=Pl011 1920clk_domain=system.clk_domain |
1921default_p_state=UNDEFINED |
1922end_on_eot=false 1923eventq_index=0 1924gic=system.realview.gic 1925int_delay=100000 1926int_num=37 |
1927p_state_clk_gate_bins=20 1928p_state_clk_gate_max=1000000000000 1929p_state_clk_gate_min=1000 |
1930pio_addr=470351872 1931pio_latency=100000 1932platform=system.realview |
1933power_model=Null |
1934system=system 1935terminal=system.terminal 1936pio=system.iobus.master[0] 1937 1938[system.realview.uart1_fake] 1939type=AmbaFake 1940amba_id=0 1941clk_domain=system.clk_domain |
1942default_p_state=UNDEFINED |
1943eventq_index=0 1944ignore_access=false |
1945p_state_clk_gate_bins=20 1946p_state_clk_gate_max=1000000000000 1947p_state_clk_gate_min=1000 |
1948pio_addr=470417408 1949pio_latency=100000 |
1950power_model=Null |
1951system=system 1952pio=system.iobus.master[13] 1953 1954[system.realview.uart2_fake] 1955type=AmbaFake 1956amba_id=0 1957clk_domain=system.clk_domain |
1958default_p_state=UNDEFINED |
1959eventq_index=0 1960ignore_access=false |
1961p_state_clk_gate_bins=20 1962p_state_clk_gate_max=1000000000000 1963p_state_clk_gate_min=1000 |
1964pio_addr=470482944 1965pio_latency=100000 |
1966power_model=Null |
1967system=system 1968pio=system.iobus.master[14] 1969 1970[system.realview.uart3_fake] 1971type=AmbaFake 1972amba_id=0 1973clk_domain=system.clk_domain |
1974default_p_state=UNDEFINED |
1975eventq_index=0 1976ignore_access=false |
1977p_state_clk_gate_bins=20 1978p_state_clk_gate_max=1000000000000 1979p_state_clk_gate_min=1000 |
1980pio_addr=470548480 1981pio_latency=100000 |
1982power_model=Null |
1983system=system 1984pio=system.iobus.master[15] 1985 1986[system.realview.usb_fake] 1987type=IsaFake 1988clk_domain=system.clk_domain |
1989default_p_state=UNDEFINED |
1990eventq_index=0 1991fake_mem=false |
1992p_state_clk_gate_bins=20 1993p_state_clk_gate_max=1000000000000 1994p_state_clk_gate_min=1000 |
1995pio_addr=452984832 1996pio_latency=100000 1997pio_size=131071 |
1998power_model=Null |
1999ret_bad_addr=false 2000ret_data16=65535 2001ret_data32=4294967295 2002ret_data64=18446744073709551615 2003ret_data8=255 2004system=system 2005update_data=false 2006warn_access= 2007pio=system.iobus.master[20] 2008 2009[system.realview.vgic] 2010type=VGic 2011clk_domain=system.clk_domain |
2012default_p_state=UNDEFINED |
2013eventq_index=0 2014gic=system.realview.gic 2015hv_addr=738213888 |
2016p_state_clk_gate_bins=20 2017p_state_clk_gate_max=1000000000000 2018p_state_clk_gate_min=1000 |
2019pio_delay=10000 2020platform=system.realview |
2021power_model=Null |
2022ppint=25 2023system=system 2024vcpu_addr=738222080 2025pio=system.membus.master[3] 2026 2027[system.realview.vram] 2028type=SimpleMemory 2029bandwidth=73.000000 2030clk_domain=system.clk_domain 2031conf_table_reported=false |
2032default_p_state=UNDEFINED |
2033eventq_index=0 2034in_addr_map=true 2035latency=30000 2036latency_var=0 2037null=false |
2038p_state_clk_gate_bins=20 2039p_state_clk_gate_max=1000000000000 2040p_state_clk_gate_min=1000 2041power_model=Null |
2042range=402653184:436207615 2043port=system.iobus.master[11] 2044 2045[system.realview.watchdog_fake] 2046type=AmbaFake 2047amba_id=0 2048clk_domain=system.clk_domain |
2049default_p_state=UNDEFINED |
2050eventq_index=0 2051ignore_access=false |
2052p_state_clk_gate_bins=20 2053p_state_clk_gate_max=1000000000000 2054p_state_clk_gate_min=1000 |
2055pio_addr=470745088 2056pio_latency=100000 |
2057power_model=Null |
2058system=system 2059pio=system.iobus.master[17] 2060 2061[system.terminal] 2062type=Terminal 2063eventq_index=0 2064intr_control=system.intrctrl 2065number=0 2066output=true 2067port=3456 2068 2069[system.toL2Bus] 2070type=CoherentXBar 2071children=snoop_filter 2072clk_domain=system.cpu_clk_domain |
2073default_p_state=UNDEFINED |
2074eventq_index=0 2075forward_latency=0 2076frontend_latency=1 |
2077p_state_clk_gate_bins=20 2078p_state_clk_gate_max=1000000000000 2079p_state_clk_gate_min=1000 |
2080point_of_coherency=false |
2081power_model=Null |
2082response_latency=1 2083snoop_filter=system.toL2Bus.snoop_filter 2084snoop_response_latency=1 2085system=system 2086use_default_range=false 2087width=32 2088master=system.l2c.cpu_side 2089slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side --- 20 unchanged lines hidden --- |