| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated |
| 4sim_ticks 51111167192000 # Number of ticks simulated 5final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 51111167268500 # Number of ticks simulated 5final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 779536 # Simulator instruction rate (inst/s) 8host_op_rate 916124 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40565130498 # Simulator tick rate (ticks/s) 10host_mem_usage 670816 # Number of bytes of host memory used 11host_seconds 1259.98 # Real time elapsed on the host 12sim_insts 982198638 # Number of instructions simulated 13sim_ops 1154296340 # Number of ops (including micro ops) simulated | 7host_inst_rate 937025 # Simulator instruction rate (inst/s) 8host_op_rate 1101207 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48760450215 # Simulator tick rate (ticks/s) 10host_mem_usage 680056 # Number of bytes of host memory used 11host_seconds 1048.21 # Real time elapsed on the host 12sim_insts 982198023 # Number of instructions simulated 13sim_ops 1154295627 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory | 27system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory |
| 28system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory | 36system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory |
| 37system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s) | 42system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) | 46system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) |
| 47system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s) | 51system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) | 53system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) |
| 54system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s) 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 54system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 56system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 63system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 64system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 68system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 69system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 70system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 71system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) | 56system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 63system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 64system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 68system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 69system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 70system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 71system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) |
| 72system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 73system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 74system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 72system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 73system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 74system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 75system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 76system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 77system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 78system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 79system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 80system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 81system.cpu_clk_domain.clock 500 # Clock period in ticks | 75system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 76system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 77system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 78system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 79system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 80system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 81system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 82system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 82system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 83system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 88system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 89system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 90system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 104system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 107system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 108system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 109system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 110system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 111system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 83system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 88system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 89system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 90system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 104system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 107system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 108system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 109system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 110system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 111system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 112system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 113system.cpu.dtb.walker.walks 266586 # Table walker walks requested 114system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors 115system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency 116system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency 117system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency | 112system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 113system.cpu.dtb.walker.walks 266581 # Table walker walks requested 114system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors 115system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency 116system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency 117system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency |
| 118system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 119system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 120system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 121system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated | 118system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 119system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 120system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 121system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated |
| 122system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated 123system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated 124system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst | 122system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated 123system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated 124system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst |
| 125system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 125system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 126system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst 127system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst | 126system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst 127system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst |
| 128system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 128system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 129system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst 130system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst | 129system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst 130system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst |
| 131system.cpu.dtb.inst_hits 0 # ITB inst hits 132system.cpu.dtb.inst_misses 0 # ITB inst misses | 131system.cpu.dtb.inst_hits 0 # ITB inst hits 132system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 133system.cpu.dtb.read_hits 183544097 # DTB read hits 134system.cpu.dtb.read_misses 195348 # DTB read misses 135system.cpu.dtb.write_hits 167774773 # DTB write hits | 133system.cpu.dtb.read_hits 183543984 # DTB read hits 134system.cpu.dtb.read_misses 195343 # DTB read misses 135system.cpu.dtb.write_hits 167774645 # DTB write hits |
| 136system.cpu.dtb.write_misses 71238 # DTB write misses 137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 139system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID 141system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB 142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 136system.cpu.dtb.write_misses 71238 # DTB write misses 137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 139system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID 141system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB 142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 143system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch | 143system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch |
| 144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions | 144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions |
| 146system.cpu.dtb.read_accesses 183739445 # DTB read accesses 147system.cpu.dtb.write_accesses 167846011 # DTB write accesses | 146system.cpu.dtb.read_accesses 183739327 # DTB read accesses 147system.cpu.dtb.write_accesses 167845883 # DTB write accesses |
| 148system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 148system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 149system.cpu.dtb.hits 351318870 # DTB hits 150system.cpu.dtb.misses 266586 # DTB misses 151system.cpu.dtb.accesses 351585456 # DTB accesses 152system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 149system.cpu.dtb.hits 351318629 # DTB hits 150system.cpu.dtb.misses 266581 # DTB misses 151system.cpu.dtb.accesses 351585210 # DTB accesses 152system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 153system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 159system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 160system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 174system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 176system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 177system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 178system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 179system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 180system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 181system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 153system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 159system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 160system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 174system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 176system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 177system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 178system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 179system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 180system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 181system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 182system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 182system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 183system.cpu.itb.walker.walks 126834 # Table walker walks requested 184system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors 185system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency 186system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency 187system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency 188system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 189system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 190system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 191system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated 192system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated 193system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated 194system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 195system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst 196system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst 197system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 198system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst 199system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst 200system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst | 183system.cpu.itb.walker.walks 126834 # Table walker walks requested 184system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors 185system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency 186system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency 187system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency 188system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 189system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 190system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 191system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated 192system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated 193system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated 194system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 195system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst 196system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst 197system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 198system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst 199system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst 200system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst |
| 201system.cpu.itb.inst_hits 982675484 # ITB inst hits | 201system.cpu.itb.inst_hits 982674869 # ITB inst hits |
| 202system.cpu.itb.inst_misses 126834 # ITB inst misses 203system.cpu.itb.read_hits 0 # DTB read hits 204system.cpu.itb.read_misses 0 # DTB read misses 205system.cpu.itb.write_hits 0 # DTB write hits 206system.cpu.itb.write_misses 0 # DTB write misses 207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 209system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID 211system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB 212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses | 202system.cpu.itb.inst_misses 126834 # ITB inst misses 203system.cpu.itb.read_hits 0 # DTB read hits 204system.cpu.itb.read_misses 0 # DTB read misses 205system.cpu.itb.write_hits 0 # DTB write hits 206system.cpu.itb.write_misses 0 # DTB write misses 207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 209system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID 211system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB 212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses |
| 218system.cpu.itb.inst_accesses 982802318 # ITB inst accesses 219system.cpu.itb.hits 982675484 # DTB hits | 218system.cpu.itb.inst_accesses 982801703 # ITB inst accesses 219system.cpu.itb.hits 982674869 # DTB hits |
| 220system.cpu.itb.misses 126834 # DTB misses | 220system.cpu.itb.misses 126834 # DTB misses |
| 221system.cpu.itb.accesses 982802318 # DTB accesses | 221system.cpu.itb.accesses 982801703 # DTB accesses |
| 222system.cpu.numPwrStateTransitions 33550 # Number of power state transitions 223system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state | 222system.cpu.numPwrStateTransitions 33550 # Number of power state transitions 223system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state |
| 224system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state | 224system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state |
| 226system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state 228system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 231system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 232system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state 233system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 234system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 235system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 236system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 237system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 226system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state 228system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 231system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 232system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state 233system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 234system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 235system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 236system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 237system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 238system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state | 238system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state |
| 239system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state | 239system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state |
| 240system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states 241system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states 242system.cpu.numCycles 102222351160 # number of cpu cycles simulated | 240system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states 241system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states 242system.cpu.numCycles 102222351313 # number of cpu cycles simulated |
| 243system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 244system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 245system.cpu.kern.inst.arm 0 # number of arm instructions executed 246system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed | 243system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 244system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 245system.cpu.kern.inst.arm 0 # number of arm instructions executed 246system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed |
| 247system.cpu.committedInsts 982198638 # Number of instructions committed 248system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed 249system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses | 247system.cpu.committedInsts 982198023 # Number of instructions committed 248system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed 249system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses |
| 250system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses | 250system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses |
| 251system.cpu.num_func_calls 56833909 # number of times a function call or return occured 252system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls 253system.cpu.num_int_insts 1057877800 # number of integer instructions | 251system.cpu.num_func_calls 56833843 # number of times a function call or return occured 252system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls 253system.cpu.num_int_insts 1057877135 # number of integer instructions |
| 254system.cpu.num_fp_insts 881349 # number of float instructions | 254system.cpu.num_fp_insts 881349 # number of float instructions |
| 255system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read 256system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written | 255system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read 256system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written |
| 257system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read 258system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written | 257system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read 258system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written |
| 259system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read 260system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written 261system.cpu.num_mem_refs 351538306 # number of memory refs 262system.cpu.num_load_insts 183711405 # Number of load instructions 263system.cpu.num_store_insts 167826901 # Number of store instructions 264system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles 265system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles | 259system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read 260system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written 261system.cpu.num_mem_refs 351538055 # number of memory refs 262system.cpu.num_load_insts 183711282 # Number of load instructions 263system.cpu.num_store_insts 167826773 # Number of store instructions 264system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles 265system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles |
| 266system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles 267system.cpu.idle_fraction 0.988702 # Percentage of idle cycles | 266system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles 267system.cpu.idle_fraction 0.988702 # Percentage of idle cycles |
| 268system.cpu.Branches 219532347 # Number of branches fetched | 268system.cpu.Branches 219532189 # Number of branches fetched |
| 269system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 269system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
| 270system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction 271system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction | 270system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction 271system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction |
| 272system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction 273system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction 274system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction 275system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction 276system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction 277system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction 278system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction 279system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 291system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction 292system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction 293system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction 294system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction 295system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction 296system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction 297system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction 298system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction | 272system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction 273system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction 274system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction 275system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction 276system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction 277system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction 278system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction 279system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 291system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction 292system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction 293system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction 294system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction 295system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction 296system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction 297system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction 298system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction |
| 299system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction 300system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction | 299system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction 300system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction |
| 301system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 302system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 301system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 302system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 303system.cpu.op_class::total 1154931007 # Class of executed instruction 304system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 305system.cpu.dcache.tags.replacements 11605970 # number of replacements | 303system.cpu.op_class::total 1154930294 # Class of executed instruction 304system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 305system.cpu.dcache.tags.replacements 11606056 # number of replacements |
| 306system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use | 306system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use |
| 307system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks. 308system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks. 309system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks. | 307system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. 308system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. 309system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks. |
| 310system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 311system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 312system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 313system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 314system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 315system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 316system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 317system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 318system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 310system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 311system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 312system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 313system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 314system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 315system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 316system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 317system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 318system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 319system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses 320system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses 321system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 322system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits 323system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits 324system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits 325system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits 326system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits 327system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits | 319system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses 320system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses 321system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 322system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits 323system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits 324system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits 325system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits 326system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits 327system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits |
| 328system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits 329system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits | 328system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits 329system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits |
| 330system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits 331system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits 332system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits 333system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits 334system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits 335system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits 336system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits 337system.cpu.dcache.overall_hits::total 330944693 # number of overall hits 338system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses 339system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses 340system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses 341system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses 342system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses 343system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses | 330system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits 331system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits 332system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits 333system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits 334system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits 335system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits 336system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits 337system.cpu.dcache.overall_hits::total 330960928 # number of overall hits 338system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses 339system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses 340system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses 341system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses 342system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses 343system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses |
| 344system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses 345system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses | 344system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses 345system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses |
| 346system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses 347system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses | 346system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses 347system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses |
| 348system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 349system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses | 348system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 349system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses |
| 350system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses 351system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses 352system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses 353system.cpu.dcache.overall_misses::total 11403820 # number of overall misses 354system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses) 355system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses) 356system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses) 357system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses) 358system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses) 359system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses) | 350system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses 351system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses 352system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses 353system.cpu.dcache.overall_misses::total 11387343 # number of overall misses 354system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) 355system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) 356system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) 357system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) 358system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) 359system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) |
| 360system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) 361system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) | 360system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) 361system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) |
| 362system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses) 363system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses) 364system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) 365system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) 366system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses 367system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses 368system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses 369system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses 370system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses 371system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses 372system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses 373system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses 374system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses 375system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses | 362system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) 363system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) 364system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) 365system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) 366system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses 367system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses 368system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses 369system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses 370system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses 371system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses 372system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses 373system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses 374system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses 375system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses |
| 376system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses 377system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses | 376system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses 377system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses |
| 378system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses 379system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses | 378system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses 379system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses |
| 380system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 381system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses | 380system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 381system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses |
| 382system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses 383system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses 384system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses 385system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses | 382system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses 383system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses 384system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses 385system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses |
| 386system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 386system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 392system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks 393system.cpu.dcache.writebacks::total 8916642 # number of writebacks 394system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 395system.cpu.icache.tags.replacements 14265273 # number of replacements | 392system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks 393system.cpu.dcache.writebacks::total 8918956 # number of writebacks 394system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 395system.cpu.icache.tags.replacements 14265255 # number of replacements |
| 396system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use | 396system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use |
| 397system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks. 398system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks. 399system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks. | 397system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. 398system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. 399system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. |
| 400system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. 401system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 402system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 403system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 404system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 405system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 406system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 407system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 408system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 400system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. 401system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 402system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 403system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 404system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 405system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 406system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 407system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 408system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 409system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses 410system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses 411system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 412system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits 413system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits 414system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits 415system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits 416system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits 417system.cpu.icache.overall_hits::total 968524390 # number of overall hits 418system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses 419system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses 420system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses 421system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses 422system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses 423system.cpu.icache.overall_misses::total 14265790 # number of overall misses 424system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses) 425system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses) 426system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses 427system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses 428system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses 429system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses | 409system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses 410system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses 411system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 412system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits 413system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits 414system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits 415system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits 416system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits 417system.cpu.icache.overall_hits::total 968523793 # number of overall hits 418system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses 419system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses 420system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses 421system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses 422system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses 423system.cpu.icache.overall_misses::total 14265772 # number of overall misses 424system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) 425system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) 426system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses 427system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses 428system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses 429system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses |
| 430system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses 431system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses 432system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses 433system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses 434system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses 435system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses 436system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 437system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 438system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 439system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 440system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 441system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 430system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses 431system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses 432system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses 433system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses 434system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses 435system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses 436system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 437system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 438system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 439system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 440system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 441system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 442system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks 443system.cpu.icache.writebacks::total 14265273 # number of writebacks 444system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 442system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks 443system.cpu.icache.writebacks::total 14265255 # number of writebacks 444system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 445system.cpu.l2cache.tags.replacements 1725823 # number of replacements | 445system.cpu.l2cache.tags.replacements 1725823 # number of replacements |
| 446system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use 447system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks. 448system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks. 449system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks. 450system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. 451system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor 452system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor 453system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor 454system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor 455system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor 456system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy 457system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy 458system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy 459system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy 460system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy 461system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id 463system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id 464system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id 465system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id 470system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits 478system.cpu.l2cache.WritebackDirty_hits::writebacks 8916642 # number of WritebackDirty hits 479system.cpu.l2cache.WritebackDirty_hits::total 8916642 # number of WritebackDirty hits 480system.cpu.l2cache.WritebackClean_hits::writebacks 14263696 # number of WritebackClean hits 481system.cpu.l2cache.WritebackClean_hits::total 14263696 # number of WritebackClean hits 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 11204 # number of UpgradeReq hits 483system.cpu.l2cache.UpgradeReq_hits::total 11204 # number of UpgradeReq hits 484system.cpu.l2cache.ReadExReq_hits::cpu.data 1689386 # number of ReadExReq hits 485system.cpu.l2cache.ReadExReq_hits::total 1689386 # number of ReadExReq hits 486system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182781 # number of ReadCleanReq hits 487system.cpu.l2cache.ReadCleanReq_hits::total 14182781 # number of ReadCleanReq hits 488system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498617 # number of ReadSharedReq hits 489system.cpu.l2cache.ReadSharedReq_hits::total 7498617 # number of ReadSharedReq hits 490system.cpu.l2cache.InvalidateReq_hits::cpu.data 694560 # number of InvalidateReq hits 491system.cpu.l2cache.InvalidateReq_hits::total 694560 # number of InvalidateReq hits 492system.cpu.l2cache.demand_hits::cpu.dtb.walker 509088 # number of demand (read+write) hits 493system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits 494system.cpu.l2cache.demand_hits::cpu.inst 14182781 # number of demand (read+write) hits 495system.cpu.l2cache.demand_hits::cpu.data 9188003 # number of demand (read+write) hits 496system.cpu.l2cache.demand_hits::total 24135825 # number of demand (read+write) hits 497system.cpu.l2cache.overall_hits::cpu.dtb.walker 509088 # number of overall hits 498system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits 499system.cpu.l2cache.overall_hits::cpu.inst 14182781 # number of overall hits 500system.cpu.l2cache.overall_hits::cpu.data 9188003 # number of overall hits 501system.cpu.l2cache.overall_hits::total 24135825 # number of overall hits | 446system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use 447system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks. 448system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks. 449system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks. 450system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. 451system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor 452system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor 453system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor 454system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor 455system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor 456system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy 457system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy 458system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy 459system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy 460system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy 461system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id 463system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id 464system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id 465system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 466system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id 470system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits 478system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits 479system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits 480system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits 481system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits 483system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits 484system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits 485system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits 486system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits 487system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits 488system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits 489system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits 490system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits 491system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits 492system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits 493system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits 494system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits 495system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits 496system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits 497system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits 498system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits 499system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits 500system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits 501system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits |
| 502system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses 503system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses 504system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses | 502system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses 503system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses 504system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses |
| 505system.cpu.l2cache.UpgradeReq_misses::cpu.data 39927 # number of UpgradeReq misses 506system.cpu.l2cache.UpgradeReq_misses::total 39927 # number of UpgradeReq misses | 505system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses 506system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses |
| 507system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 508system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses | 507system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 508system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses |
| 509system.cpu.l2cache.ReadExReq_misses::cpu.data 827609 # number of ReadExReq misses 510system.cpu.l2cache.ReadExReq_misses::total 827609 # number of ReadExReq misses 511system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83009 # number of ReadCleanReq misses 512system.cpu.l2cache.ReadCleanReq_misses::total 83009 # number of ReadCleanReq misses 513system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344111 # number of ReadSharedReq misses 514system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses 515system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses 516system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses | 509system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses 510system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses 511system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses 512system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses 513system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses 514system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses 515system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses 516system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses |
| 517system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses 518system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses | 517system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses 518system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses |
| 519system.cpu.l2cache.demand_misses::cpu.inst 83009 # number of demand (read+write) misses 520system.cpu.l2cache.demand_misses::cpu.data 1171720 # number of demand (read+write) misses 521system.cpu.l2cache.demand_misses::total 1267042 # number of demand (read+write) misses | 519system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses 520system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses 521system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses |
| 522system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses 523system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses | 522system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses 523system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses |
| 524system.cpu.l2cache.overall_misses::cpu.inst 83009 # number of overall misses 525system.cpu.l2cache.overall_misses::cpu.data 1171720 # number of overall misses 526system.cpu.l2cache.overall_misses::total 1267042 # number of overall misses 527system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses) 528system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses) 529system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses) 530system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses) 531system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses) 532system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses) 533system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses) 534system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses) 535system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses) | 524system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses 525system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses 526system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses 527system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) 528system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) 529system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) 530system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) 531system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) 532system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) 533system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) 534system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) 535system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses) |
| 536system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 537system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) | 536system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 537system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) |
| 538system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses) 539system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses) 540system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses) 541system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses) 542system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses) 543system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses) | 538system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) 539system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) 540system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) 541system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) 542system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) 543system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) |
| 544system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) 545system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) | 544system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) 545system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) |
| 546system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses 547system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses 548system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses 549system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses 550system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses 551system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses 552system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses 555system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses 558system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses 559system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses 560system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses | 546system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses 547system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses 548system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses 549system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses 550system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses 551system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses 552system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses 555system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses 558system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses 559system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses 560system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses |
| 561system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 562system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 561system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 562system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 563system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses 564system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses 565system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses 566system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses 567system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses 568system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses 569system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses 570system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses 571system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses 572system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses 573system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses | 563system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses 564system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses 565system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses 566system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses 567system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses 568system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses 569system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses 570system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses 571system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses 572system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses 573system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses |
| 574system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses | 574system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses |
| 575system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses 576system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses 577system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses 578system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses | 575system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses 576system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses 577system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses 578system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses |
| 579system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses | 579system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses |
| 580system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses | 580system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses |
| 581system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 581system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 587system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks 588system.cpu.l2cache.writebacks::total 1507088 # number of writebacks 589system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter. 590system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 587system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks 588system.cpu.l2cache.writebacks::total 1507096 # number of writebacks 589system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. 590system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 591system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 591system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 592system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. 593system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 592system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. 593system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 594system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 594system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 595system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 596system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution | 595system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 596system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution |
| 598system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution | 598system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution |
| 600system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution | 600system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution |
| 604system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution | 604system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution |
| 605system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution | 605system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution |
| 610system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution | 610system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution |
| 612system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes) | 612system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) |
| 614system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) | 614system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) |
| 615system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes) | 615system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) |
| 619system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) | 619system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) |
| 620system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes) 622system.cpu.toL2Bus.snoops 1957594 # Total snoops (count) 623system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes) 624system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram | 620system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) 622system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) 623system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) 624system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram |
| 627system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 627system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 628system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram | 628system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram |
| 630system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 630system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 634system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram 635system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 634system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram 635system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 636system.iobus.trans_dist::ReadReq 40242 # Transaction distribution 637system.iobus.trans_dist::ReadResp 40242 # Transaction distribution 638system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 639system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 640system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 642system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 643system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 670system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 676system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 677system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) | 636system.iobus.trans_dist::ReadReq 40242 # Transaction distribution 637system.iobus.trans_dist::ReadResp 40242 # Transaction distribution 638system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 639system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 640system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 642system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 643system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 670system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 676system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 677system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) |
| 678system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 678system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 679system.iocache.tags.replacements 115459 # number of replacements 680system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use 681system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 682system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. 683system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 679system.iocache.tags.replacements 115459 # number of replacements 680system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use 681system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 682system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. 683system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 684system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit. | 684system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. |
| 685system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor 686system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor 687system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 688system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 689system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 690system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 691system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 692system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 693system.iocache.tags.tag_accesses 1039650 # Number of tag accesses 694system.iocache.tags.data_accesses 1039650 # Number of data accesses | 685system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor 686system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor 687system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 688system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 689system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 690system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 691system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 692system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 693system.iocache.tags.tag_accesses 1039650 # Number of tag accesses 694system.iocache.tags.data_accesses 1039650 # Number of data accesses |
| 695system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 695system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 696system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 697system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 698system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 699system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 700system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 701system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 702system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 703system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 31 unchanged lines hidden (view full) --- 735system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.iocache.blocked::no_targets 0 # number of cycles access was blocked 739system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.iocache.writebacks::writebacks 106631 # number of writebacks 742system.iocache.writebacks::total 106631 # number of writebacks | 696system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 697system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 698system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 699system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 700system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 701system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 702system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 703system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 31 unchanged lines hidden (view full) --- 735system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.iocache.blocked::no_targets 0 # number of cycles access was blocked 739system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.iocache.writebacks::writebacks 106631 # number of writebacks 742system.iocache.writebacks::total 106631 # number of writebacks |
| 743system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 743system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. 744system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. 745system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 746system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 747system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 748system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 749system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 744system.membus.trans_dist::ReadReq 76679 # Transaction distribution | 750system.membus.trans_dist::ReadReq 76679 # Transaction distribution |
| 745system.membus.trans_dist::ReadResp 524962 # Transaction distribution | 751system.membus.trans_dist::ReadResp 524960 # Transaction distribution |
| 746system.membus.trans_dist::WriteReq 33606 # Transaction distribution 747system.membus.trans_dist::WriteResp 33606 # Transaction distribution | 752system.membus.trans_dist::WriteReq 33606 # Transaction distribution 753system.membus.trans_dist::WriteResp 33606 # Transaction distribution |
| 748system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution 749system.membus.trans_dist::CleanEvict 226329 # Transaction distribution 750system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution | 754system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution 755system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 756system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution |
| 751system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution | 757system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution |
| 752system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution 753system.membus.trans_dist::ReadExReq 827052 # Transaction distribution 754system.membus.trans_dist::ReadExResp 827052 # Transaction distribution 755system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution 756system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution 757system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution | 758system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution 759system.membus.trans_dist::ReadExReq 827049 # Transaction distribution 760system.membus.trans_dist::ReadExResp 827049 # Transaction distribution 761system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution 762system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution 763system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution |
| 758system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 759system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 760system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) | 764system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 765system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 766system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) |
| 761system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes) 762system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes) | 767system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) 768system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) |
| 763system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) 764system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) | 769system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) 770system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) |
| 765system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes) | 771system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes) |
| 766system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 767system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 768system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) | 772system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 773system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 774system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) |
| 769system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes) 770system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes) | 775system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) 776system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) |
| 771system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) 772system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) | 777system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) 778system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) |
| 773system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes) | 779system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes) |
| 774system.membus.snoops 0 # Total snoops (count) 775system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 780system.membus.snoops 0 # Total snoops (count) 781system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 776system.membus.snoop_fanout::samples 3925032 # Request fanout histogram 777system.membus.snoop_fanout::mean 1 # Request fanout histogram 778system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 782system.membus.snoop_fanout::samples 3888979 # Request fanout histogram 783system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram 784system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram |
| 779system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 785system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 780system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 781system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram | 786system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram 787system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram |
| 782system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 783system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 788system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 789system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 784system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 790system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 785system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 791system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 786system.membus.snoop_fanout::total 3925032 # Request fanout histogram 787system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 788system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 789system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 790system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 791system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 792system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 793system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 792system.membus.snoop_fanout::total 3888979 # Request fanout histogram 793system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 794system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 795system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 796system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 797system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 798system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 799system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 794system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 795system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 796system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 797system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 798system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 799system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 800system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 801system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 802system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 803system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 804system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 805system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 800system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 801system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 806system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 807system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 802system.realview.ethernet.txBytes 966 # Bytes Transmitted 803system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 804system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 805system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 806system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 807system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 808system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 809system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 836system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 837system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 838system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 839system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 840system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 841system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 842system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 843system.realview.ethernet.droppedPackets 0 # number of packets dropped | 808system.realview.ethernet.txBytes 966 # Bytes Transmitted 809system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 810system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 811system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 812system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 813system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 814system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 815system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 842system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 843system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 844system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 845system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 846system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 847system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 848system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 849system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 844system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 845system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 846system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 847system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 848system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 849system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 850system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 850system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 851system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 852system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 853system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 854system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 855system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 856system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 851system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 852system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 853system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 854system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 857system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 858system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 859system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 860system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 855system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 856system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 857system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 858system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 859system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 860system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 861system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 862system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 863system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 864system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 865system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states 866system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states | 861system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 862system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 863system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 864system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 865system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 866system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 867system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 868system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 869system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 870system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 871system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 872system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states |
| 867 868---------- End Simulation Statistics ---------- | 873 874---------- End Simulation Statistics ---------- |