Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt

Deleted Added

sdiff udiff text old ( 11530:6e143fd2cabf ) new ( 11547:dd6dfd38b6c2 )

full compact

stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1675396 # Simulator instruction rate (inst/s) 8host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 87182982694 # Simulator tick rate (ticks/s) 10host_mem_usage 718784 # Number of bytes of host memory used 11host_seconds 586.25 # Real time elapsed on the host	7host_inst_rate 967952 # Simulator instruction rate (inst/s) 8host_op_rate 1137552 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50369548013 # Simulator tick rate (ticks/s) 10host_mem_usage 676592 # Number of bytes of host memory used 11host_seconds 1014.72 # Real time elapsed on the host
12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory --- 113 unchanged lines hidden (view full) --- 133system.cpu.dtb.read_hits 183545125 # DTB read hits 134system.cpu.dtb.read_misses 195347 # DTB read misses 135system.cpu.dtb.write_hits 167774776 # DTB write hits 136system.cpu.dtb.write_misses 71239 # DTB write misses 137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 139system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID	12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory --- 113 unchanged lines hidden (view full) --- 133system.cpu.dtb.read_hits 183545125 # DTB read hits 134system.cpu.dtb.read_misses 195347 # DTB read misses 135system.cpu.dtb.write_hits 167774776 # DTB write hits 136system.cpu.dtb.write_misses 71239 # DTB write misses 137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 139system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
141system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB	141system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB
142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 143system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch 144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions 146system.cpu.dtb.read_accesses 183740472 # DTB read accesses 147system.cpu.dtb.write_accesses 167846015 # DTB write accesses 148system.cpu.dtb.inst_accesses 0 # ITB inst accesses 149system.cpu.dtb.hits 351319901 # DTB hits --- 53 unchanged lines hidden (view full) --- 203system.cpu.itb.read_hits 0 # DTB read hits 204system.cpu.itb.read_misses 0 # DTB read misses 205system.cpu.itb.write_hits 0 # DTB write hits 206system.cpu.itb.write_misses 0 # DTB write misses 207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 209system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID	142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 143system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch 144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions 146system.cpu.dtb.read_accesses 183740472 # DTB read accesses 147system.cpu.dtb.write_accesses 167846015 # DTB write accesses 148system.cpu.dtb.inst_accesses 0 # ITB inst accesses 149system.cpu.dtb.hits 351319901 # DTB hits --- 53 unchanged lines hidden (view full) --- 203system.cpu.itb.read_hits 0 # DTB read hits 204system.cpu.itb.read_misses 0 # DTB read misses 205system.cpu.itb.write_hits 0 # DTB write hits 206system.cpu.itb.write_misses 0 # DTB write misses 207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 209system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
211system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB	211system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB
212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses 218system.cpu.itb.inst_accesses 982807118 # ITB inst accesses 219system.cpu.itb.hits 982680284 # DTB hits --- 647 unchanged lines hidden ---	212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses 218system.cpu.itb.inst_accesses 982807118 # ITB inst accesses 219system.cpu.itb.hits 982680284 # DTB hits --- 647 unchanged lines hidden ---