| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1142928 # Simulator instruction rate (inst/s) 8host_op_rate 1343188 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59474849541 # Simulator tick rate (ticks/s) 10host_mem_usage 670860 # Number of bytes of host memory used 11host_seconds 859.37 # Real time elapsed on the host | 7host_inst_rate 1675396 # Simulator instruction rate (inst/s) 8host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 87182982694 # Simulator tick rate (ticks/s) 10host_mem_usage 718784 # Number of bytes of host memory used 11host_seconds 586.25 # Real time elapsed on the host |
| 12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory 21system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory --- 22 unchanged lines hidden (view full) --- 46system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory 22system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory --- 22 unchanged lines hidden (view full) --- 47system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) |
| 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 54system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 56system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 57system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 58system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 59system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 60system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 62system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) | 56system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 63system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 64system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 68system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 69system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 70system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 71system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) |
| 72system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 73system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 74system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 70system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 71system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 72system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 73system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 74system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 75system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 76system.cpu_clk_domain.clock 500 # Clock period in ticks | 75system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 76system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 77system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 78system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 79system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 80system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 81system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 82system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 77system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 78system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 79system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 98system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 101system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 102system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 103system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 104system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 105system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 83system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 88system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 89system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 90system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 104system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 107system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 108system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 109system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 110system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 111system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 112system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 106system.cpu.dtb.walker.walks 266586 # Table walker walks requested 107system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors 108system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency 109system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency 110system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency 111system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 112system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 113system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 137system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 138system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions 139system.cpu.dtb.read_accesses 183740472 # DTB read accesses 140system.cpu.dtb.write_accesses 167846015 # DTB write accesses 141system.cpu.dtb.inst_accesses 0 # ITB inst accesses 142system.cpu.dtb.hits 351319901 # DTB hits 143system.cpu.dtb.misses 266586 # DTB misses 144system.cpu.dtb.accesses 351586487 # DTB accesses | 113system.cpu.dtb.walker.walks 266586 # Table walker walks requested 114system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors 115system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency 116system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency 117system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency 118system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 119system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 120system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions 146system.cpu.dtb.read_accesses 183740472 # DTB read accesses 147system.cpu.dtb.write_accesses 167846015 # DTB write accesses 148system.cpu.dtb.inst_accesses 0 # ITB inst accesses 149system.cpu.dtb.hits 351319901 # DTB hits 150system.cpu.dtb.misses 266586 # DTB misses 151system.cpu.dtb.accesses 351586487 # DTB accesses |
| 152system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 145system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 149system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 166system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 167system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 168system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 169system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 170system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 171system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 172system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 173system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 153system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 159system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 160system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 174system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 176system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 177system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 178system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 179system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 180system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 181system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 182system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 174system.cpu.itb.walker.walks 126834 # Table walker walks requested 175system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors 176system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency 177system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency 178system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency 179system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 180system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 181system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 205system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu.itb.read_accesses 0 # DTB read accesses 208system.cpu.itb.write_accesses 0 # DTB write accesses 209system.cpu.itb.inst_accesses 982807118 # ITB inst accesses 210system.cpu.itb.hits 982680284 # DTB hits 211system.cpu.itb.misses 126834 # DTB misses 212system.cpu.itb.accesses 982807118 # DTB accesses | 183system.cpu.itb.walker.walks 126834 # Table walker walks requested 184system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors 185system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency 186system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency 187system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency 188system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 189system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 190system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses 218system.cpu.itb.inst_accesses 982807118 # ITB inst accesses 219system.cpu.itb.hits 982680284 # DTB hits 220system.cpu.itb.misses 126834 # DTB misses 221system.cpu.itb.accesses 982807118 # DTB accesses |
| 222system.cpu.numPwrStateTransitions 33550 # Number of power state transitions 223system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state 224system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state 226system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state 228system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 231system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 232system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state 233system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 234system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 235system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 236system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 237system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 238system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state 239system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state 240system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states 241system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states |
|
| 213system.cpu.numCycles 102222351209 # number of cpu cycles simulated 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 216system.cpu.kern.inst.arm 0 # number of arm instructions executed 217system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed 218system.cpu.committedInsts 982203438 # Number of instructions committed 219system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed 220system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 267system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction 268system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction 269system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction 270system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction 271system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction 272system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 273system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 274system.cpu.op_class::total 1154935820 # Class of executed instruction | 242system.cpu.numCycles 102222351209 # number of cpu cycles simulated 243system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 244system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 245system.cpu.kern.inst.arm 0 # number of arm instructions executed 246system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed 247system.cpu.committedInsts 982203438 # Number of instructions committed 248system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed 249system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 296system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction 297system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction 298system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction 299system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction 300system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction 301system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 302system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 303system.cpu.op_class::total 1154935820 # Class of executed instruction |
| 304system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 275system.cpu.dcache.tags.replacements 11606642 # number of replacements 276system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use 277system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. 278system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. 279system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. 280system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 281system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 282system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 283system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 284system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 285system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 286system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 287system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 288system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 289system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses 290system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses | 305system.cpu.dcache.tags.replacements 11606642 # number of replacements 306system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use 307system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. 308system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. 309system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. 310system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 311system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 312system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 313system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 314system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 315system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 316system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 317system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id 318system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 319system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses 320system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses |
| 321system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 291system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits 292system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits 293system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits 294system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits 295system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits 296system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits 297system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits 298system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits --- 56 unchanged lines hidden (view full) --- 355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 361system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks 362system.cpu.dcache.writebacks::total 8917390 # number of writebacks | 322system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits 323system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits 324system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits 325system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits 326system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits 327system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits 328system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits 329system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits --- 56 unchanged lines hidden (view full) --- 386system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks 393system.cpu.dcache.writebacks::total 8917390 # number of writebacks |
| 394system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 363system.cpu.icache.tags.replacements 14265253 # number of replacements 364system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use 365system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. 366system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. 367system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. 368system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 369system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 370system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 371system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 372system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 373system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 374system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 375system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 376system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 377system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses 378system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses | 395system.cpu.icache.tags.replacements 14265253 # number of replacements 396system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use 397system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. 398system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. 399system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. 400system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 401system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 402system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 403system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 404system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 405system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 406system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 407system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 408system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 409system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses 410system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses |
| 411system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 379system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits 380system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits 381system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits 382system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits 383system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits 384system.cpu.icache.overall_hits::total 968529210 # number of overall hits 385system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses 386system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 409system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks 410system.cpu.icache.writebacks::total 14265253 # number of writebacks | 412system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits 413system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits 414system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits 415system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits 416system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits 417system.cpu.icache.overall_hits::total 968529210 # number of overall hits 418system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses 419system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 436system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 437system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 438system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 439system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 440system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 441system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 442system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks 443system.cpu.icache.writebacks::total 14265253 # number of writebacks |
| 444system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 411system.cpu.l2cache.tags.replacements 1725806 # number of replacements 412system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use 413system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. 414system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. 415system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. 416system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. 417system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor 418system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 432system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id 433system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id 434system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id 435system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id 436system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id 437system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id 438system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses 439system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses | 445system.cpu.l2cache.tags.replacements 1725806 # number of replacements 446system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use 447system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. 448system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. 449system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. 450system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. 451system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor 452system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 466system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id 467system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id 470system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id 471system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id 472system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses 473system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses |
| 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 440system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits 441system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits 442system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits 443system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits 444system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits 445system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits 446system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits 447system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits --- 104 unchanged lines hidden (view full) --- 552system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks 553system.cpu.l2cache.writebacks::total 1507080 # number of writebacks 554system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. 555system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. 556system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 557system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. 558system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 559system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits 478system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits 479system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits 480system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits 481system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits --- 104 unchanged lines hidden (view full) --- 587system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks 588system.cpu.l2cache.writebacks::total 1507080 # number of writebacks 589system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. 590system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. 591system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 592system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. 593system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 594system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 595system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 560system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution 562system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 563system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 590system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram | 596system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution 600system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 626system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram 628system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram |
| 634system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 598system.iobus.trans_dist::ReadReq 40242 # Transaction distribution 599system.iobus.trans_dist::ReadResp 40242 # Transaction distribution 600system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 601system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 602system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 604system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 605system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 632system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) | 635system.iobus.trans_dist::ReadReq 40242 # Transaction distribution 636system.iobus.trans_dist::ReadResp 40242 # Transaction distribution 637system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 638system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 639system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 640system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 642system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 669system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 670system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 676system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) |
| 677system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 640system.iocache.tags.replacements 115459 # number of replacements 641system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use 642system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 643system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. 644system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 645system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. 646system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor 647system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor 648system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 649system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 650system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 651system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 652system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 653system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 654system.iocache.tags.tag_accesses 1039650 # Number of tag accesses 655system.iocache.tags.data_accesses 1039650 # Number of data accesses | 678system.iocache.tags.replacements 115459 # number of replacements 679system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use 680system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 681system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. 682system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 683system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. 684system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor 685system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor 686system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 687system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 688system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 689system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 690system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 691system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 692system.iocache.tags.tag_accesses 1039650 # Number of tag accesses 693system.iocache.tags.data_accesses 1039650 # Number of data accesses |
| 694system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 656system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 657system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 658system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 659system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 660system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 661system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 662system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 663system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 31 unchanged lines hidden (view full) --- 695system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 696system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 697system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 698system.iocache.blocked::no_targets 0 # number of cycles access was blocked 699system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 700system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 701system.iocache.writebacks::writebacks 106631 # number of writebacks 702system.iocache.writebacks::total 106631 # number of writebacks | 695system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 696system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 697system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 698system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 699system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 700system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 701system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 702system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 31 unchanged lines hidden (view full) --- 734system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.iocache.blocked::no_targets 0 # number of cycles access was blocked 738system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.iocache.writebacks::writebacks 106631 # number of writebacks 741system.iocache.writebacks::total 106631 # number of writebacks |
| 742system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 703system.membus.trans_dist::ReadReq 76679 # Transaction distribution 704system.membus.trans_dist::ReadResp 524946 # Transaction distribution 705system.membus.trans_dist::WriteReq 33606 # Transaction distribution 706system.membus.trans_dist::WriteResp 33606 # Transaction distribution 707system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution 708system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 709system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution 710system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 737system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 738system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 739system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram 740system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 741system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 742system.membus.snoop_fanout::min_value 1 # Request fanout histogram 743system.membus.snoop_fanout::max_value 1 # Request fanout histogram 744system.membus.snoop_fanout::total 3924997 # Request fanout histogram | 743system.membus.trans_dist::ReadReq 76679 # Transaction distribution 744system.membus.trans_dist::ReadResp 524946 # Transaction distribution 745system.membus.trans_dist::WriteReq 33606 # Transaction distribution 746system.membus.trans_dist::WriteResp 33606 # Transaction distribution 747system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution 748system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 749system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution 750system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 777system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 778system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 779system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram 780system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 781system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 782system.membus.snoop_fanout::min_value 1 # Request fanout histogram 783system.membus.snoop_fanout::max_value 1 # Request fanout histogram 784system.membus.snoop_fanout::total 3924997 # Request fanout histogram |
| 785system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 786system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 787system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 788system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 789system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 790system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 791system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 745system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 746system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 747system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 748system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 749system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 750system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 792system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 793system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 794system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 795system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 796system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 797system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 798system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 799system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 751system.realview.ethernet.txBytes 966 # Bytes Transmitted 752system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 753system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 754system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 755system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 756system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 757system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 758system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 785system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 786system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 787system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 788system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 789system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 790system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 791system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 792system.realview.ethernet.droppedPackets 0 # number of packets dropped | 800system.realview.ethernet.txBytes 966 # Bytes Transmitted 801system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 802system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 803system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 804system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 805system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 806system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 807system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 834system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 835system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 836system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 837system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 838system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 839system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 840system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 841system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 842system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 843system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 844system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 845system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 846system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 847system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 848system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 793system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 794system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 795system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 796system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 849system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 850system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 851system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 852system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 853system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 854system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 855system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 856system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 857system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 858system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 859system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 860system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 861system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 862system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 863system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states 864system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states |
|
| 797 798---------- End Simulation Statistics ---------- | 865 866---------- End Simulation Statistics ---------- |