| stats.txt (11353:31c5786945b4) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1770185 # Simulator instruction rate (inst/s) 8host_op_rate 2080350 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 92115569363 # Simulator tick rate (ticks/s) 10host_mem_usage 676500 # Number of bytes of host memory used 11host_seconds 554.86 # Real time elapsed on the host | 7host_inst_rate 1114977 # Simulator instruction rate (inst/s) 8host_op_rate 1310339 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58020354238 # Simulator tick rate (ticks/s) 10host_mem_usage 675736 # Number of bytes of host memory used 11host_seconds 880.92 # Real time elapsed on the host |
| 12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory --- 275 unchanged lines hidden (view full) --- 295system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits 296system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits 297system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits 298system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits 299system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits 300system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits 301system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits 302system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits | 12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory --- 275 unchanged lines hidden (view full) --- 295system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits 296system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits 297system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits 298system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits 299system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits 300system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits 301system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits 302system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits |
| 303system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits 304system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits 305system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits 306system.cpu.dcache.overall_hits::total 330608768 # number of overall hits | 303system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits 304system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits 305system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits 306system.cpu.dcache.overall_hits::total 330945053 # number of overall hits |
| 307system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses 308system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses 309system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses 310system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses 311system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses 312system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses 313system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses 314system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses 315system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses 316system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses 317system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 318system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses | 307system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses 308system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses 309system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses 310system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses 311system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses 312system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses 313system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses 314system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses 315system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses 316system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses 317system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 318system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses |
| 319system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses 320system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses 321system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses 322system.cpu.dcache.overall_misses::total 10157717 # number of overall misses | 319system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses 320system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses 321system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses 322system.cpu.dcache.overall_misses::total 11404487 # number of overall misses |
| 323system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) 324system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) 325system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) 326system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) 327system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) 328system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) 329system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) 330system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) 331system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) 332system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) 333system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) 334system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) | 323system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) 324system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) 325system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) 326system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) 327system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) 328system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) 329system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) 330system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) 331system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) 332system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) 333system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) 334system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) |
| 335system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses 336system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses 337system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses 338system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses | 335system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses 336system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses 337system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses 338system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses |
| 339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses 340system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses 341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses 342system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses 343system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses 344system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses 345system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses 346system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses 347system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses 348system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses 349system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 350system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses | 339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses 340system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses 341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses 342system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses 343system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses 344system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses 345system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses 346system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses 347system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses 348system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses 349system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 350system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses |
| 351system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses 352system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses 353system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses 354system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses | 351system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses 352system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses 353system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses 354system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses |
| 355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 361system.cpu.dcache.fast_writes 0 # number of fast writes performed 362system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 363system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks 364system.cpu.dcache.writebacks::total 8917390 # number of writebacks | 361system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks 362system.cpu.dcache.writebacks::total 8917390 # number of writebacks |
| 365system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 366system.cpu.icache.tags.replacements 14265253 # number of replacements 367system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use 368system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. 369system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. 370system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. 371system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 372system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 373system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 404system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses 405system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses 406system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 363system.cpu.icache.tags.replacements 14265253 # number of replacements 364system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use 365system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. 366system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. 367system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. 368system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 369system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 370system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 401system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses 402system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses 403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 412system.cpu.icache.fast_writes 0 # number of fast writes performed 413system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 414system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks 415system.cpu.icache.writebacks::total 14265253 # number of writebacks | 409system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks 410system.cpu.icache.writebacks::total 14265253 # number of writebacks |
| 416system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 417system.cpu.l2cache.tags.replacements 1725806 # number of replacements 418system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use 419system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. 420system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. 421system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. 422system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. 423system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor 424system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor --- 125 unchanged lines hidden (view full) --- 550system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses 552system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 411system.cpu.l2cache.tags.replacements 1725806 # number of replacements 412system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use 413system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. 414system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. 415system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. 416system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. 417system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor 418system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor --- 125 unchanged lines hidden (view full) --- 544system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses 545system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses 546system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 547system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 558system.cpu.l2cache.fast_writes 0 # number of fast writes performed 559system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 560system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks 561system.cpu.l2cache.writebacks::total 1507080 # number of writebacks | 552system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks 553system.cpu.l2cache.writebacks::total 1507080 # number of writebacks |
| 562system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 563system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. 564system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. 565system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 566system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. 567system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 568system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 569system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution --- 94 unchanged lines hidden (view full) --- 665system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 666system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 667system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 668system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 669system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 670system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 671system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 672system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 554system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. 555system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. 556system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 557system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. 558system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 559system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 560system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution 561system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution --- 94 unchanged lines hidden (view full) --- 656system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 657system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 658system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses 659system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 660system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 661system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 662system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 663system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 673system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses 674system.iocache.demand_misses::total 8853 # number of demand (read+write) misses | 664system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses 665system.iocache.demand_misses::total 115517 # number of demand (read+write) misses |
| 675system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 666system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 676system.iocache.overall_misses::realview.ide 8813 # number of overall misses 677system.iocache.overall_misses::total 8853 # number of overall misses | 667system.iocache.overall_misses::realview.ide 115477 # number of overall misses 668system.iocache.overall_misses::total 115517 # number of overall misses |
| 678system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 679system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) 680system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) 681system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 682system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 683system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 684system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 685system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 669system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 670system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) 671system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) 672system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 673system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 674system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 675system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 676system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 686system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses 687system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses | 677system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses 678system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses |
| 688system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 679system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 689system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses 690system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses | 680system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses 681system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses |
| 691system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 692system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 693system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 694system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 695system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 696system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 697system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 698system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 699system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 700system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 701system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 702system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 703system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 704system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 705system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 706system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 707system.iocache.blocked::no_targets 0 # number of cycles access was blocked 708system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 709system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 682system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 683system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 684system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 685system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 686system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 687system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 688system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 689system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 690system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 691system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 692system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 693system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 694system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 695system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 696system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 697system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 698system.iocache.blocked::no_targets 0 # number of cycles access was blocked 699system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 700system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 710system.iocache.fast_writes 0 # number of fast writes performed 711system.iocache.cache_copies 0 # number of cache copies performed | |
| 712system.iocache.writebacks::writebacks 106631 # number of writebacks 713system.iocache.writebacks::total 106631 # number of writebacks | 701system.iocache.writebacks::writebacks 106631 # number of writebacks 702system.iocache.writebacks::total 106631 # number of writebacks |
| 714system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 715system.membus.trans_dist::ReadReq 76679 # Transaction distribution 716system.membus.trans_dist::ReadResp 524946 # Transaction distribution 717system.membus.trans_dist::WriteReq 33606 # Transaction distribution 718system.membus.trans_dist::WriteResp 33606 # Transaction distribution 719system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution 720system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 721system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution 722system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution --- 88 unchanged lines hidden --- | 703system.membus.trans_dist::ReadReq 76679 # Transaction distribution 704system.membus.trans_dist::ReadResp 524946 # Transaction distribution 705system.membus.trans_dist::WriteReq 33606 # Transaction distribution 706system.membus.trans_dist::WriteResp 33606 # Transaction distribution 707system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution 708system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 709system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution 710system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution --- 88 unchanged lines hidden --- |