| stats.txt (11245:1c5102c0a7a9) | stats.txt (11336:b318499f676c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 51.111153 # Number of seconds simulated 4sim_ticks 51111152682000 # Number of ticks simulated 5final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167216500 # Number of ticks simulated 5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 958498 # Simulator instruction rate (inst/s) 8host_op_rate 1126393 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49757685011 # Simulator tick rate (ticks/s) 10host_mem_usage 676912 # Number of bytes of host memory used 11host_seconds 1027.20 # Real time elapsed on the host 12sim_insts 984570519 # Number of instructions simulated 13sim_ops 1157031967 # Number of ops (including micro ops) simulated | 7host_inst_rate 1152055 # Simulator instruction rate (inst/s) 8host_op_rate 1353914 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59949794817 # Simulator tick rate (ticks/s) 10host_mem_usage 676672 # Number of bytes of host memory used 11host_seconds 852.57 # Real time elapsed on the host 12sim_insts 982203438 # Number of instructions simulated 13sim_ops 1154301153 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory 21system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 110253960 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory 21system.physmem.bytes_read::total 116962748 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory | 26system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1722731 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1867963 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s) | 35system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 2157140 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2288399 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) |
| 45system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) | 45system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 2157543 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4309446 # Total bandwidth to/from this memory (bytes/s) |
| 54system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 56system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 57system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 58system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 59system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 60system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory --- 36 unchanged lines hidden (view full) --- 98system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 101system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 102system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 103system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 104system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 105system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 54system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 56system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 57system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 58system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 59system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 60system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory --- 36 unchanged lines hidden (view full) --- 98system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 101system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 102system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 103system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 104system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 105system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 106system.cpu.dtb.walker.walks 265715 # Table walker walks requested 107system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors 108system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency 109system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency 110system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency | 106system.cpu.dtb.walker.walks 266586 # Table walker walks requested 107system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors 108system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency 109system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency 110system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency |
| 111system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 112system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 113system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution | 111system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 112system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 113system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution |
| 114system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated 115system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated 116system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated 117system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst | 114system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated 115system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated 116system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated 117system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst |
| 118system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 118system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 119system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst 120system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst | 119system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst 120system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst |
| 121system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 121system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 122system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst 123system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst | 122system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst 123system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst |
| 124system.cpu.dtb.inst_hits 0 # ITB inst hits 125system.cpu.dtb.inst_misses 0 # ITB inst misses | 124system.cpu.dtb.inst_hits 0 # ITB inst hits 125system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 126system.cpu.dtb.read_hits 184014035 # DTB read hits 127system.cpu.dtb.read_misses 194198 # DTB read misses 128system.cpu.dtb.write_hits 168232768 # DTB write hits 129system.cpu.dtb.write_misses 71517 # DTB write misses | 126system.cpu.dtb.read_hits 183545125 # DTB read hits 127system.cpu.dtb.read_misses 195347 # DTB read misses 128system.cpu.dtb.write_hits 167774776 # DTB write hits 129system.cpu.dtb.write_misses 71239 # DTB write misses |
| 130system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 131system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 133system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID | 130system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 131system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 133system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID |
| 134system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB | 134system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB |
| 135system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 135system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 136system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch | 136system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch |
| 137system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 138system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions | 137system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 138system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions |
| 139system.cpu.dtb.read_accesses 184208233 # DTB read accesses 140system.cpu.dtb.write_accesses 168304285 # DTB write accesses | 139system.cpu.dtb.read_accesses 183740472 # DTB read accesses 140system.cpu.dtb.write_accesses 167846015 # DTB write accesses |
| 141system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 141system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 142system.cpu.dtb.hits 352246803 # DTB hits 143system.cpu.dtb.misses 265715 # DTB misses 144system.cpu.dtb.accesses 352512518 # DTB accesses | 142system.cpu.dtb.hits 351319901 # DTB hits 143system.cpu.dtb.misses 266586 # DTB misses 144system.cpu.dtb.accesses 351586487 # DTB accesses |
| 145system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 149system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 166system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 167system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 168system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 169system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 170system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 171system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 172system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 173system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 145system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 149system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 166system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 167system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 168system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 169system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 170system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 171system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 172system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 173system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 174system.cpu.itb.walker.walks 126837 # Table walker walks requested 175system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors 176system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency 177system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency 178system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency | 174system.cpu.itb.walker.walks 126834 # Table walker walks requested 175system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors 176system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency 177system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency 178system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency |
| 179system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 180system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 181system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution | 179system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 180system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 181system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution |
| 182system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated 183system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated 184system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated | 182system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated 183system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated 184system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated |
| 185system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 185system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 186system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst 187system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst | 186system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst 187system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst |
| 188system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 188system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 189system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst 190system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst 191system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst 192system.cpu.itb.inst_hits 985047321 # ITB inst hits 193system.cpu.itb.inst_misses 126837 # ITB inst misses | 189system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst 190system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst 191system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst 192system.cpu.itb.inst_hits 982680284 # ITB inst hits 193system.cpu.itb.inst_misses 126834 # ITB inst misses |
| 194system.cpu.itb.read_hits 0 # DTB read hits 195system.cpu.itb.read_misses 0 # DTB read misses 196system.cpu.itb.write_hits 0 # DTB write hits 197system.cpu.itb.write_misses 0 # DTB write misses 198system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 199system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 200system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 201system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID | 194system.cpu.itb.read_hits 0 # DTB read hits 195system.cpu.itb.read_misses 0 # DTB read misses 196system.cpu.itb.write_hits 0 # DTB write hits 197system.cpu.itb.write_misses 0 # DTB write misses 198system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 199system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 200system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID 201system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID |
| 202system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB | 202system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB |
| 203system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 204system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 205system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu.itb.read_accesses 0 # DTB read accesses 208system.cpu.itb.write_accesses 0 # DTB write accesses | 203system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 204system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 205system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu.itb.read_accesses 0 # DTB read accesses 208system.cpu.itb.write_accesses 0 # DTB write accesses |
| 209system.cpu.itb.inst_accesses 985174158 # ITB inst accesses 210system.cpu.itb.hits 985047321 # DTB hits 211system.cpu.itb.misses 126837 # DTB misses 212system.cpu.itb.accesses 985174158 # DTB accesses 213system.cpu.numCycles 102222322140 # number of cpu cycles simulated | 209system.cpu.itb.inst_accesses 982807118 # ITB inst accesses 210system.cpu.itb.hits 982680284 # DTB hits 211system.cpu.itb.misses 126834 # DTB misses 212system.cpu.itb.accesses 982807118 # DTB accesses 213system.cpu.numCycles 102222351209 # number of cpu cycles simulated |
| 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 216system.cpu.kern.inst.arm 0 # number of arm instructions executed 217system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed | 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 216system.cpu.kern.inst.arm 0 # number of arm instructions executed 217system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed |
| 218system.cpu.committedInsts 984570519 # Number of instructions committed 219system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed 220system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses 221system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses 222system.cpu.num_func_calls 57056367 # number of times a function call or return occured 223system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls 224system.cpu.num_int_insts 1060455466 # number of integer instructions 225system.cpu.num_fp_insts 880805 # number of float instructions 226system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read 227system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written 228system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read 229system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written 230system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read 231system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written 232system.cpu.num_mem_refs 352465606 # number of memory refs 233system.cpu.num_load_insts 184180431 # Number of load instructions 234system.cpu.num_store_insts 168285175 # Number of store instructions 235system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles 236system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles 237system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles 238system.cpu.idle_fraction 0.988675 # Percentage of idle cycles 239system.cpu.Branches 220088562 # Number of branches fetched | 218system.cpu.committedInsts 982203438 # Number of instructions committed 219system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed 220system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses 221system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses 222system.cpu.num_func_calls 56834581 # number of times a function call or return occured 223system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls 224system.cpu.num_int_insts 1057882257 # number of integer instructions 225system.cpu.num_fp_insts 881349 # number of float instructions 226system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read 227system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written 228system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read 229system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written 230system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read 231system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written 232system.cpu.num_mem_refs 351539335 # number of memory refs 233system.cpu.num_load_insts 183712430 # Number of load instructions 234system.cpu.num_store_insts 167826905 # Number of store instructions 235system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles 236system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles 237system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles 238system.cpu.idle_fraction 0.988702 # Percentage of idle cycles 239system.cpu.Branches 219534054 # Number of branches fetched |
| 240system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 240system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
| 241system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction 242system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction 243system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction 244system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 245system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 246system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 247system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 248system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 249system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 250system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 251system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 252system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 253system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 254system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 255system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 256system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 257system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 258system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 259system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 260system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 261system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction 262system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 263system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction 264system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction 265system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 266system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction 267system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 268system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 269system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 270system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction 271system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction | 241system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction 242system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction 243system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction 244system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction 245system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction 246system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction 247system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction 248system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction 249system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction 250system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction 251system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction 252system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction 253system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction 254system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction 255system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction 256system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction 257system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction 258system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction 259system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction 260system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction 261system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction 262system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction 263system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction 264system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction 265system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction 266system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction 267system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction 268system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction 269system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction 270system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction 271system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction |
| 272system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 273system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 272system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 273system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 274system.cpu.op_class::total 1157666593 # Class of executed instruction 275system.cpu.dcache.tags.replacements 11612141 # number of replacements | 274system.cpu.op_class::total 1154935820 # Class of executed instruction 275system.cpu.dcache.tags.replacements 11606642 # number of replacements |
| 276system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use | 276system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use |
| 277system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. 278system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. 279system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. | 277system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. 278system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. 279system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. |
| 280system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 281system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 282system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 283system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 284system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 280system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 281system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor 282system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 283system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 284system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 285system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 286system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 287system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id | 285system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 286system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 287system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id |
| 288system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 288system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 289system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses 290system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses 291system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits 292system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits 293system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits 294system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits 295system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits 296system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits 297system.cpu.dcache.WriteLineReq_hits::cpu.data 337709 # number of WriteLineReq hits 298system.cpu.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits 299system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits 300system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits 301system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits 302system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits 303system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits 304system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits 305system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits 306system.cpu.dcache.overall_hits::total 331514149 # number of overall hits 307system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses 308system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses 309system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses 310system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses 311system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses 312system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses 313system.cpu.dcache.WriteLineReq_misses::cpu.data 1245349 # number of WriteLineReq misses 314system.cpu.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses 315system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses 316system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses | 289system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses 290system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses 291system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits 292system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits 293system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits 294system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits 295system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits 296system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits 297system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits 298system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits 299system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits 300system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits 301system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits 302system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits 303system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits 304system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits 305system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits 306system.cpu.dcache.overall_hits::total 330608768 # number of overall hits 307system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses 308system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses 309system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses 310system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses 311system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses 312system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses 313system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses 314system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses 315system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses 316system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses |
| 317system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 318system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses | 317system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 318system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses |
| 319system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses 320system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses 321system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses 322system.cpu.dcache.overall_misses::total 10164734 # number of overall misses 323system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) 324system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) 325system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) 326system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) 327system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) 328system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) 329system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583058 # number of WriteLineReq accesses(hits+misses) 330system.cpu.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses) 331system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) 332system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) 333system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) 334system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) 335system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses 336system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses 337system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses 338system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses 339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses 340system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses 341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses 342system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses 343system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses 344system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses 345system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786673 # miss rate for WriteLineReq accesses 346system.cpu.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses 347system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses 348system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses | 319system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses 320system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses 321system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses 322system.cpu.dcache.overall_misses::total 10157717 # number of overall misses 323system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) 324system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) 325system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) 326system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) 327system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) 328system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) 329system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) 330system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) 331system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) 332system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) 333system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) 334system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) 335system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses 336system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses 337system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses 338system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses 339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses 340system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses 341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses 342system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses 343system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses 344system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses 345system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses 346system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses 347system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses 348system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses |
| 349system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 350system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses | 349system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 350system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses |
| 351system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses 352system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses 353system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses 354system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses | 351system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses 352system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses 353system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses 354system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses |
| 355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 361system.cpu.dcache.fast_writes 0 # number of fast writes performed 362system.cpu.dcache.cache_copies 0 # number of cache copies performed | 355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 361system.cpu.dcache.fast_writes 0 # number of fast writes performed 362system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 363system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks 364system.cpu.dcache.writebacks::total 8921277 # number of writebacks | 363system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks 364system.cpu.dcache.writebacks::total 8917390 # number of writebacks |
| 365system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 365system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 366system.cpu.icache.tags.replacements 14295641 # number of replacements | 366system.cpu.icache.tags.replacements 14265253 # number of replacements |
| 367system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use | 367system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use |
| 368system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. 369system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. 370system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. | 368system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. 369system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. 370system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. |
| 371system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 372system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 373system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 374system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 375system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 371system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. 372system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor 373system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 374system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 375system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 376system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id | 376system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 377system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 378system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id |
| 379system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 379system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 380system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses 382system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits 383system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits 384system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits 385system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits 386system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits 387system.cpu.icache.overall_hits::total 970865862 # number of overall hits 388system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses 389system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses 390system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses 391system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses 392system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses 393system.cpu.icache.overall_misses::total 14296158 # number of overall misses 394system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses) 395system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) 396system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses 397system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses 398system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses 399system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses 400system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses 401system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses 402system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses 403system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses 404system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses 405system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses | 380system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses 381system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses 382system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits 383system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits 384system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits 385system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits 386system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits 387system.cpu.icache.overall_hits::total 968529210 # number of overall hits 388system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses 389system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses 390system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses 391system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses 392system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses 393system.cpu.icache.overall_misses::total 14265770 # number of overall misses 394system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses) 395system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses) 396system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses 397system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses 398system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses 399system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses 400system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses 401system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses 402system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses 403system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses 404system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses 405system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses |
| 406system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 412system.cpu.icache.fast_writes 0 # number of fast writes performed 413system.cpu.icache.cache_copies 0 # number of cache copies performed | 406system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 412system.cpu.icache.fast_writes 0 # number of fast writes performed 413system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 414system.cpu.icache.writebacks::writebacks 14295641 # number of writebacks 415system.cpu.icache.writebacks::total 14295641 # number of writebacks | 414system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks 415system.cpu.icache.writebacks::total 14265253 # number of writebacks |
| 416system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 416system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 417system.cpu.l2cache.tags.replacements 1723188 # number of replacements 418system.cpu.l2cache.tags.tagsinuse 65341.862570 # Cycle average of tags in use 419system.cpu.l2cache.tags.total_refs 46967342 # Total number of references to valid blocks. 420system.cpu.l2cache.tags.sampled_refs 1786484 # Sample count of references to valid blocks. 421system.cpu.l2cache.tags.avg_refs 26.290379 # Average number of references to valid blocks. | 417system.cpu.l2cache.tags.replacements 1725806 # number of replacements 418system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use 419system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. 420system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. 421system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. |
| 422system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. | 422system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. |
| 423system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155 # Average occupied blocks per requestor 424system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.194068 # Average occupied blocks per requestor 425system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.716842 # Average occupied blocks per requestor 426system.cpu.l2cache.tags.occ_blocks::cpu.inst 6119.396908 # Average occupied blocks per requestor 427system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596 # Average occupied blocks per requestor 428system.cpu.l2cache.tags.occ_percent::writebacks 0.568229 # Average percentage of cache occupancy 429system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy 430system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy 431system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093375 # Average percentage of cache occupancy 432system.cpu.l2cache.tags.occ_percent::cpu.data 0.323930 # Average percentage of cache occupancy 433system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy 434system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id 435system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id 436system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id | 423system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor 424system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor 425system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor 426system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor 427system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor 428system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy 429system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy 430system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy 431system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy 432system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy 433system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy 434system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id 435system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id 436system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id |
| 437system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id | 437system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id |
| 438system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id 439system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id 440system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id 441system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id 442system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id 443system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id 444system.cpu.l2cache.tags.tag_accesses 426185861 # Number of tag accesses 445system.cpu.l2cache.tags.data_accesses 426185861 # Number of data accesses 446system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits 447system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits 448system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits 449system.cpu.l2cache.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits 450system.cpu.l2cache.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits 451system.cpu.l2cache.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits 452system.cpu.l2cache.WritebackClean_hits::total 14294063 # number of WritebackClean hits 453system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits 454system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits 455system.cpu.l2cache.ReadExReq_hits::cpu.data 1692549 # number of ReadExReq hits 456system.cpu.l2cache.ReadExReq_hits::total 1692549 # number of ReadExReq hits 457system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14213121 # number of ReadCleanReq hits 458system.cpu.l2cache.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits 459system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7503843 # number of ReadSharedReq hits 460system.cpu.l2cache.ReadSharedReq_hits::total 7503843 # number of ReadSharedReq hits 461system.cpu.l2cache.InvalidateReq_hits::cpu.data 694318 # number of InvalidateReq hits 462system.cpu.l2cache.InvalidateReq_hits::total 694318 # number of InvalidateReq hits 463system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits 464system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits 465system.cpu.l2cache.demand_hits::cpu.inst 14213121 # number of demand (read+write) hits 466system.cpu.l2cache.demand_hits::cpu.data 9196392 # number of demand (read+write) hits 467system.cpu.l2cache.demand_hits::total 24171745 # number of demand (read+write) hits 468system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits 469system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits 470system.cpu.l2cache.overall_hits::cpu.inst 14213121 # number of overall hits 471system.cpu.l2cache.overall_hits::cpu.data 9196392 # number of overall hits 472system.cpu.l2cache.overall_hits::total 24171745 # number of overall hits 473system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses 474system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses 475system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses 476system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses 477system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses | 438system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id 439system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id 440system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id 441system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id 442system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id 443system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id 444system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses 445system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses 446system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits 447system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits 448system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits 449system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits 450system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits 451system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits 452system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits 453system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits 454system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits 455system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits 456system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits 457system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits 458system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits 459system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits 460system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits 461system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits 462system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits 463system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits 464system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits 465system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits 466system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits 467system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits 468system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits 469system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits 470system.cpu.l2cache.overall_hits::cpu.inst 14182764 # number of overall hits 471system.cpu.l2cache.overall_hits::cpu.data 9188700 # number of overall hits 472system.cpu.l2cache.overall_hits::total 24136508 # number of overall hits 473system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses 474system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses 475system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses 476system.cpu.l2cache.UpgradeReq_misses::cpu.data 39924 # number of UpgradeReq misses 477system.cpu.l2cache.UpgradeReq_misses::total 39924 # number of UpgradeReq misses |
| 478system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 479system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses | 478system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 479system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses |
| 480system.cpu.l2cache.ReadExReq_misses::cpu.data 826568 # number of ReadExReq misses 481system.cpu.l2cache.ReadExReq_misses::total 826568 # number of ReadExReq misses 482system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83037 # number of ReadCleanReq misses 483system.cpu.l2cache.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses 484system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344355 # number of ReadSharedReq misses 485system.cpu.l2cache.ReadSharedReq_misses::total 344355 # number of ReadSharedReq misses 486system.cpu.l2cache.InvalidateReq_misses::cpu.data 551031 # number of InvalidateReq misses 487system.cpu.l2cache.InvalidateReq_misses::total 551031 # number of InvalidateReq misses 488system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses 489system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses 490system.cpu.l2cache.demand_misses::cpu.inst 83037 # number of demand (read+write) misses 491system.cpu.l2cache.demand_misses::cpu.data 1170923 # number of demand (read+write) misses 492system.cpu.l2cache.demand_misses::total 1266289 # number of demand (read+write) misses 493system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses 494system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses 495system.cpu.l2cache.overall_misses::cpu.inst 83037 # number of overall misses 496system.cpu.l2cache.overall_misses::cpu.data 1170923 # number of overall misses 497system.cpu.l2cache.overall_misses::total 1266289 # number of overall misses 498system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) 499system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) 500system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses) 502system.cpu.l2cache.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses) 503system.cpu.l2cache.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses) 504system.cpu.l2cache.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses) 505system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) 506system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) | 480system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses 481system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses 482system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses 483system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses 484system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses 485system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses 486system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses 487system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses 488system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses 489system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses 490system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses 491system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses 492system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses 493system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses 494system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses 495system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses 496system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses 497system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses 498system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses) 499system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses) 500system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses) 501system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses) 502system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses) 503system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses) 504system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses) 505system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses) 506system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses) |
| 507system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 508system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) | 507system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 508system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) |
| 509system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) 510system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) 511system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14296158 # number of ReadCleanReq accesses(hits+misses) 512system.cpu.l2cache.ReadCleanReq_accesses::total 14296158 # number of ReadCleanReq accesses(hits+misses) 513system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7848198 # number of ReadSharedReq accesses(hits+misses) 514system.cpu.l2cache.ReadSharedReq_accesses::total 7848198 # number of ReadSharedReq accesses(hits+misses) 515system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245349 # number of InvalidateReq accesses(hits+misses) 516system.cpu.l2cache.InvalidateReq_accesses::total 1245349 # number of InvalidateReq accesses(hits+misses) 517system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses 518system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses 519system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses 520system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses 521system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses 522system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses 523system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses 524system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses 525system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses 526system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses 527system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses 528system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022508 # miss rate for ReadReq accesses 529system.cpu.l2cache.ReadReq_miss_rate::total 0.015917 # miss rate for ReadReq accesses 530system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses 531system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses | 509system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses) 510system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses) 511system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses) 512system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses) 513system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses) 514system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses) 515system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses) 516system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses) 517system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses 518system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses 519system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses 520system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses 521system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses 522system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses 523system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses 524system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses 525system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses 526system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses 527system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses 528system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses 529system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses 530system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses 531system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses |
| 532system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 533system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 532system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 533system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 534system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses 535system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses 536system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses 537system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses 538system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses 539system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses 540system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses 541system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses 542system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses 543system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses 544system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses 545system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses 546system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses 547system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses 548system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses 549system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses 550system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses | 534system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses 535system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses 536system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses 537system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses 538system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses 539system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses 540system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses 541system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses 542system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses 543system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses 544system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses 545system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses 546system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses 547system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses 548system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses 549system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses 550system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses |
| 552system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.l2cache.fast_writes 0 # number of fast writes performed 559system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 552system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.l2cache.fast_writes 0 # number of fast writes performed 559system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 560system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks 561system.cpu.l2cache.writebacks::total 1503967 # number of writebacks | 560system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks 561system.cpu.l2cache.writebacks::total 1507080 # number of writebacks |
| 562system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 562system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 563system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. 564system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. 565system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 566system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. 567system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 563system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. 564system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. 565system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 566system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. 567system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 568system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 568system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 569system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution | 569system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution |
| 571system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution | 571system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution |
| 573system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution | 573system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution |
| 577system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution | 577system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution |
| 578system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution 580system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution 585system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes) 586system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) 588system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes) 595system.cpu.toL2Bus.snoops 1954989 # Total snoops (count) 596system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram | 578system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution 580system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution 585system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes) 586system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) 588system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) 591system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) 593system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes) 595system.cpu.toL2Bus.snoops 1957577 # Total snoops (count) 596system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram |
| 599system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 599system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 600system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram | 600system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram |
| 602system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 602system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 606system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram 607system.iobus.trans_dist::ReadReq 40246 # Transaction distribution 608system.iobus.trans_dist::ReadResp 40246 # Transaction distribution | 606system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram 607system.iobus.trans_dist::ReadReq 40242 # Transaction distribution 608system.iobus.trans_dist::ReadResp 40242 # Transaction distribution |
| 609system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 610system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 611system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 612system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 622system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 623system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 624system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) | 609system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 610system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 611system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 612system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 622system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 623system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 624system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) |
| 625system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) 626system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) | 625system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) 626system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) |
| 627system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 628system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 627system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 628system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 629system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) | 629system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) |
| 630system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) | 630system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) |
| 644system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) 645system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) | 644system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 645system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) |
| 646system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 647system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 646system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 647system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 648system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) 649system.iocache.tags.replacements 115463 # number of replacements 650system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use | 648system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) 649system.iocache.tags.replacements 115459 # number of replacements 650system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use |
| 651system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 651system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 652system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. | 652system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. |
| 653system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 654system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. | 653system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 654system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. |
| 655system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor 656system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor | 655system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor 656system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor |
| 657system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 658system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 659system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 660system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 661system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 662system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 657system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 658system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 659system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy 660system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 661system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 662system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 663system.iocache.tags.tag_accesses 1039686 # Number of tag accesses 664system.iocache.tags.data_accesses 1039686 # Number of data accesses | 663system.iocache.tags.tag_accesses 1039650 # Number of tag accesses 664system.iocache.tags.data_accesses 1039650 # Number of data accesses |
| 665system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 665system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 666system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses 667system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses | 666system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 667system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses |
| 668system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 669system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 670system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 671system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 672system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 668system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 669system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 670system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 671system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 672system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 673system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses 674system.iocache.demand_misses::total 8857 # number of demand (read+write) misses | 673system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses 674system.iocache.demand_misses::total 8853 # number of demand (read+write) misses |
| 675system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 675system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 676system.iocache.overall_misses::realview.ide 8817 # number of overall misses 677system.iocache.overall_misses::total 8857 # number of overall misses | 676system.iocache.overall_misses::realview.ide 8813 # number of overall misses 677system.iocache.overall_misses::total 8853 # number of overall misses |
| 678system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 678system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 679system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) 680system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) | 679system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) 680system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) |
| 681system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 682system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 683system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 684system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 685system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 681system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 682system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 683system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 684system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 685system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 686system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses 687system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses | 686system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses 687system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses |
| 688system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 688system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 689system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses 690system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses | 689system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses 690system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses |
| 691system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 692system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 693system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 694system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 695system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 696system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 697system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 698system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 9 unchanged lines hidden (view full) --- 708system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 709system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.iocache.fast_writes 0 # number of fast writes performed 711system.iocache.cache_copies 0 # number of cache copies performed 712system.iocache.writebacks::writebacks 106631 # number of writebacks 713system.iocache.writebacks::total 106631 # number of writebacks 714system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 715system.membus.trans_dist::ReadReq 76679 # Transaction distribution | 691system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 692system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 693system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 694system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 695system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 696system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 697system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 698system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 9 unchanged lines hidden (view full) --- 708system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 709system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.iocache.fast_writes 0 # number of fast writes performed 711system.iocache.cache_copies 0 # number of cache copies performed 712system.iocache.writebacks::writebacks 106631 # number of writebacks 713system.iocache.writebacks::total 106631 # number of writebacks 714system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 715system.membus.trans_dist::ReadReq 76679 # Transaction distribution |
| 716system.membus.trans_dist::ReadResp 525254 # Transaction distribution | 716system.membus.trans_dist::ReadResp 524946 # Transaction distribution |
| 717system.membus.trans_dist::WriteReq 33606 # Transaction distribution 718system.membus.trans_dist::WriteResp 33606 # Transaction distribution | 717system.membus.trans_dist::WriteReq 33606 # Transaction distribution 718system.membus.trans_dist::WriteResp 33606 # Transaction distribution |
| 719system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution 720system.membus.trans_dist::CleanEvict 224691 # Transaction distribution 721system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution | 719system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution 720system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 721system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution |
| 722system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution | 722system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution |
| 723system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution 724system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution 725system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution 726system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution | 723system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution 724system.membus.trans_dist::ReadExReq 1379258 # Transaction distribution 725system.membus.trans_dist::ReadExResp 1379258 # Transaction distribution 726system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution |
| 727system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 728system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 729system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 730system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 731system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) | 727system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 728system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 729system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 730system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 731system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) |
| 732system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes) 733system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes) 734system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) 735system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) 736system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes) | 732system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes) 733system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes) 734system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) 735system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) 736system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes) |
| 737system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 738system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 739system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) | 737system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 738system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 739system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) |
| 740system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes) 741system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes) 742system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) 743system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) 744system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes) | 740system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213041440 # Cumulative packet size per connected master and slave (bytes) 741system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213210490 # Cumulative packet size per connected master and slave (bytes) 742system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) 743system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) 744system.membus.pkt_size::total 220601274 # Cumulative packet size per connected master and slave (bytes) |
| 745system.membus.snoops 0 # Total snoops (count) | 745system.membus.snoops 0 # Total snoops (count) |
| 746system.membus.snoop_fanout::samples 3920464 # Request fanout histogram | 746system.membus.snoop_fanout::samples 3924997 # Request fanout histogram |
| 747system.membus.snoop_fanout::mean 1 # Request fanout histogram 748system.membus.snoop_fanout::stdev 0 # Request fanout histogram 749system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 750system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 747system.membus.snoop_fanout::mean 1 # Request fanout histogram 748system.membus.snoop_fanout::stdev 0 # Request fanout histogram 749system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 750system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 751system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram | 751system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram |
| 752system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 754system.membus.snoop_fanout::min_value 1 # Request fanout histogram 755system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 752system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 754system.membus.snoop_fanout::min_value 1 # Request fanout histogram 755system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 756system.membus.snoop_fanout::total 3920464 # Request fanout histogram | 756system.membus.snoop_fanout::total 3924997 # Request fanout histogram |
| 757system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 758system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 759system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 760system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 761system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 762system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 763system.realview.ethernet.txBytes 966 # Bytes Transmitted 764system.realview.ethernet.txPackets 3 # Number of Packets Transmitted --- 46 unchanged lines hidden --- | 757system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 758system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 759system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 760system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 761system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 762system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 763system.realview.ethernet.txBytes 966 # Bytes Transmitted 764system.realview.ethernet.txPackets 3 # Number of Packets Transmitted --- 46 unchanged lines hidden --- |