Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt

Deleted Added

sdiff udiff text old ( 11570:4aac82f10951 ) new ( 11606:6b749761c398 )

full compact

4,5c4,5
< sim_ticks 51111167192000 # Number of ticks simulated
< final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 51111167268500 # Number of ticks simulated
> final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 779536 # Simulator instruction rate (inst/s)
< host_op_rate 916124 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 40565130498 # Simulator tick rate (ticks/s)
< host_mem_usage 670816 # Number of bytes of host memory used
< host_seconds 1259.98 # Real time elapsed on the host
< sim_insts 982198638 # Number of instructions simulated
< sim_ops 1154296340 # Number of ops (including micro ops) simulated
---
> host_inst_rate 937025 # Simulator instruction rate (inst/s)
> host_op_rate 1101207 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48760450215 # Simulator tick rate (ticks/s)
> host_mem_usage 680056 # Number of bytes of host memory used
> host_seconds 1048.21 # Real time elapsed on the host
> sim_insts 982198023 # Number of instructions simulated
> sim_ops 1154295627 # Number of ops (including micro ops) simulated
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
19,20c19,20
< system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory
22,25c22,25
< system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory
30,31c30,31
< system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory
36c36
< system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory
39,40c39,40
< system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s)
42,45c42,45
< system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s)
51,52c51,52
< system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s)
54,55c54,55
< system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
72,74c72,74
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
82c82
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
112,117c112,117
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 266586 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 266581 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency
122,124c122,124
< system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst
126,127c126,127
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst
129,130c129,130
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst
133,135c133,135
< system.cpu.dtb.read_hits 183544097 # DTB read hits
< system.cpu.dtb.read_misses 195348 # DTB read misses
< system.cpu.dtb.write_hits 167774773 # DTB write hits
---
> system.cpu.dtb.read_hits 183543984 # DTB read hits
> system.cpu.dtb.read_misses 195343 # DTB read misses
> system.cpu.dtb.write_hits 167774645 # DTB write hits
143c143
< system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch
146,147c146,147
< system.cpu.dtb.read_accesses 183739445 # DTB read accesses
< system.cpu.dtb.write_accesses 167846011 # DTB write accesses
---
> system.cpu.dtb.read_accesses 183739327 # DTB read accesses
> system.cpu.dtb.write_accesses 167845883 # DTB write accesses
149,152c149,152
< system.cpu.dtb.hits 351318870 # DTB hits
< system.cpu.dtb.misses 266586 # DTB misses
< system.cpu.dtb.accesses 351585456 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 351318629 # DTB hits
> system.cpu.dtb.misses 266581 # DTB misses
> system.cpu.dtb.accesses 351585210 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
182c182
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
201c201
< system.cpu.itb.inst_hits 982675484 # ITB inst hits
---
> system.cpu.itb.inst_hits 982674869 # ITB inst hits
218,219c218,219
< system.cpu.itb.inst_accesses 982802318 # ITB inst accesses
< system.cpu.itb.hits 982675484 # DTB hits
---
> system.cpu.itb.inst_accesses 982801703 # ITB inst accesses
> system.cpu.itb.hits 982674869 # DTB hits
221c221
< system.cpu.itb.accesses 982802318 # DTB accesses
---
> system.cpu.itb.accesses 982801703 # DTB accesses
224,225c224,225
< system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state
238c238
< system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state
240,242c240,242
< system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 102222351160 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 102222351313 # number of cpu cycles simulated
247,249c247,249
< system.cpu.committedInsts 982198638 # Number of instructions committed
< system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses
---
> system.cpu.committedInsts 982198023 # Number of instructions committed
> system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses
251,253c251,253
< system.cpu.num_func_calls 56833909 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls
< system.cpu.num_int_insts 1057877800 # number of integer instructions
---
> system.cpu.num_func_calls 56833843 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls
> system.cpu.num_int_insts 1057877135 # number of integer instructions
255,256c255,256
< system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read
< system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read
> system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written
259,265c259,265
< system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written
< system.cpu.num_mem_refs 351538306 # number of memory refs
< system.cpu.num_load_insts 183711405 # Number of load instructions
< system.cpu.num_store_insts 167826901 # Number of store instructions
< system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles
< system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written
> system.cpu.num_mem_refs 351538055 # number of memory refs
> system.cpu.num_load_insts 183711282 # Number of load instructions
> system.cpu.num_store_insts 167826773 # Number of store instructions
> system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles
> system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles
268c268
< system.cpu.Branches 219532347 # Number of branches fetched
---
> system.cpu.Branches 219532189 # Number of branches fetched
270,271c270,271
< system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction
< system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction
> system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction
299,300c299,300
< system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction
< system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction
> system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction
303,305c303,305
< system.cpu.op_class::total 1154931007 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 11605970 # number of replacements
---
> system.cpu.op_class::total 1154930294 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 11606056 # number of replacements
307,309c307,309
< system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks.
319,327c319,327
< system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits
330,343c330,343
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits
< system.cpu.dcache.overall_hits::total 330944693 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses
---
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits
> system.cpu.dcache.overall_hits::total 330960928 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses
346,347c346,347
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses
---
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses
350,359c350,359
< system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses
< system.cpu.dcache.overall_misses::total 11403820 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses
> system.cpu.dcache.overall_misses::total 11387343 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses)
362,375c362,375
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses
378,379c378,379
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
382,385c382,385
< system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses
392,395c392,395
< system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks
< system.cpu.dcache.writebacks::total 8916642 # number of writebacks
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 14265273 # number of replacements
---
> system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks
> system.cpu.dcache.writebacks::total 8918956 # number of writebacks
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 14265255 # number of replacements
397,399c397,399
< system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks.
409,429c409,429
< system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits
< system.cpu.icache.overall_hits::total 968524390 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses
< system.cpu.icache.overall_misses::total 14265790 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits
> system.cpu.icache.overall_hits::total 968523793 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses
> system.cpu.icache.overall_misses::total 14265772 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses
442,444c442,444
< system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks
< system.cpu.icache.writebacks::total 14265273 # number of writebacks
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks
> system.cpu.icache.writebacks::total 14265255 # number of writebacks
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
446,501c446,501
< system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 8916642 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 8916642 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 14263696 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 14263696 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 11204 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 11204 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1689386 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1689386 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182781 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 14182781 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498617 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 7498617 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 694560 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 694560 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 509088 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 14182781 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 9188003 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 24135825 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 509088 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 14182781 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 9188003 # number of overall hits
< system.cpu.l2cache.overall_hits::total 24135825 # number of overall hits
---
> system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits
> system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits
505,506c505,506
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 39927 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 39927 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses
509,516c509,516
< system.cpu.l2cache.ReadExReq_misses::cpu.data 827609 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 827609 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83009 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 83009 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344111 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses
519,521c519,521
< system.cpu.l2cache.demand_misses::cpu.inst 83009 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1171720 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1267042 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses
524,535c524,535
< system.cpu.l2cache.overall_misses::cpu.inst 83009 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1171720 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1267042 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses)
538,543c538,543
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses)
546,560c546,560
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses
563,573c563,573
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses
575,578c575,578
< system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses
580c580
< system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses
587,590c587,590
< system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks
< system.cpu.l2cache.writebacks::total 1507088 # number of writebacks
< system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks
> system.cpu.l2cache.writebacks::total 1507096 # number of writebacks
> system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data.
592,593c592,593
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
595,597c595,597
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution
600,603c600,603
< system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution
605,609c605,609
< system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution
612,613c612,613
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes)
615,618c615,618
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes)
620,626c620,626
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1957594 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1762518 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram
628,629c628,629
< system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram
634,635c634,635
< system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram
< system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram
> system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
678c678
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
684c684
< system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit.
---
> system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit.
695c695
< system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
743c743,749
< system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
745c751
< system.membus.trans_dist::ReadResp 524962 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 524960 # Transaction distribution
748,750c754,756
< system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution
< system.membus.trans_dist::CleanEvict 226329 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution
> system.membus.trans_dist::CleanEvict 226320 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution
752,757c758,763
< system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution
< system.membus.trans_dist::ReadExReq 827052 # Transaction distribution
< system.membus.trans_dist::ReadExResp 827052 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution
> system.membus.trans_dist::ReadExReq 827049 # Transaction distribution
> system.membus.trans_dist::ReadExResp 827049 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution
761,762c767,768
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes)
765c771
< system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes)
769,770c775,776
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes)
773c779
< system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes)
776,778c782,784
< system.membus.snoop_fanout::samples 3925032 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 3888979 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram
780,781c786,787
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram
> system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram
784c790
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
786,793c792,799
< system.membus.snoop_fanout::total 3925032 # Request fanout histogram
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_fanout::total 3888979 # Request fanout histogram
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
800,801c806,807
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
844,850c850,856
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
855,866c861,872
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states