1 2---------- Begin Simulation Statistics ----------
| 1 2---------- Begin Simulation Statistics ----------
|
3sim_seconds 51.111167 # Number of seconds simulated 4sim_ticks 51111167268500 # Number of ticks simulated 5final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 51.548252 # Number of seconds simulated 4sim_ticks 51548252400500 # Number of ticks simulated 5final_tick 51548252400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1788186 # Simulator instruction rate (inst/s) 8host_op_rate 2101506 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93052770956 # Simulator tick rate (ticks/s) 10host_mem_usage 679348 # Number of bytes of host memory used 11host_seconds 549.27 # Real time elapsed on the host 12sim_insts 982198023 # Number of instructions simulated 13sim_ops 1154295627 # Number of ops (including micro ops) simulated
| 7host_inst_rate 1717705 # Simulator instruction rate (inst/s) 8host_op_rate 1880520 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48787200192 # Simulator tick rate (ticks/s) 10host_mem_usage 679528 # Number of bytes of host memory used 11host_seconds 1056.59 # Real time elapsed on the host 12sim_insts 1814916572 # Number of instructions simulated 13sim_ops 1986945286 # Number of ops (including micro ops) simulated
|
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
|
16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory 22system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 388608 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 367808 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5292340 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 73326152 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 442368 # Number of bytes read from this memory 22system.physmem.bytes_read::total 79817276 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5292340 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5292340 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 101858624 # Number of bytes written to this memory
|
26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
| 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
|
27system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory
| 27system.physmem.bytes_written::total 101879204 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 6072 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5747 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 123100 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1145734 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6912 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1287565 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1591541 # Number of write requests responded to by this memory
|
35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
| 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
|
36system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 36system.physmem.num_writes::total 1594114 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 7539 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 7135 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 102668 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1422476 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 8582 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1548399 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 102668 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 102668 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1975986 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1976385 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1975986 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 7539 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 7135 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 102668 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1422875 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 8582 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3524784 # Total bandwidth to/from this memory (bytes/s) 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
56system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 63system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 64system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 68system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 69system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 70system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 71system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
| 56system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 63system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 64system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 68system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 69system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 70system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 71system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
72system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 73system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 74system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 72system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 73system.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 74system.bridge.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
75system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 76system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 77system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 78system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 79system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 80system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 81system.cpu_clk_domain.clock 500 # Clock period in ticks
| 75system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 76system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 77system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 78system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 79system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 80system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 81system.cpu_clk_domain.clock 500 # Clock period in ticks
|
82system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 82system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
83system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 88system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 89system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 90system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 91system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 92system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 93system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 94system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 95system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 96system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 97system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 98system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 100system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 101system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 102system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 107system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 108system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 109system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 110system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 111system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 83system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 88system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 89system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 90system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 91system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 92system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 93system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 94system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 95system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 96system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 97system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 98system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 100system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 101system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 102system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 107system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 108system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 109system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 110system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 111system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
112system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 113system.cpu.dtb.walker.walks 266581 # Table walker walks requested 114system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors 115system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency 116system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency 117system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency
| 112system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 113system.cpu.dtb.walker.walks 267664 # Table walker walks requested 114system.cpu.dtb.walker.walksLong 267664 # Table walker walks initiated with long descriptors 115system.cpu.dtb.walker.walkWaitTime::samples 267664 # Table walker wait (enqueue to first request) latency 116system.cpu.dtb.walker.walkWaitTime::0 267664 100.00% 100.00% # Table walker wait (enqueue to first request) latency 117system.cpu.dtb.walker.walkWaitTime::total 267664 # Table walker wait (enqueue to first request) latency
|
118system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 119system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 120system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
| 118system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 119system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 120system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
|
121system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated 122system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated 123system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated 124system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst
| 121system.cpu.dtb.walker.walkPageSizes::4K 206672 89.75% 89.75% # Table walker page sizes translated 122system.cpu.dtb.walker.walkPageSizes::2M 23595 10.25% 100.00% # Table walker page sizes translated 123system.cpu.dtb.walker.walkPageSizes::total 230267 # Table walker page sizes translated 124system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 267664 # Table walker requests started/completed, data/inst
|
125system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
| 125system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
126system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst 127system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst
| 126system.cpu.dtb.walker.walkRequestOrigin_Requested::total 267664 # Table walker requests started/completed, data/inst 127system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 230267 # Table walker requests started/completed, data/inst
|
128system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
| 128system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
129system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst 130system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst
| 129system.cpu.dtb.walker.walkRequestOrigin_Completed::total 230267 # Table walker requests started/completed, data/inst 130system.cpu.dtb.walker.walkRequestOrigin::total 497931 # Table walker requests started/completed, data/inst
|
131system.cpu.dtb.inst_hits 0 # ITB inst hits 132system.cpu.dtb.inst_misses 0 # ITB inst misses
| 131system.cpu.dtb.inst_hits 0 # ITB inst hits 132system.cpu.dtb.inst_misses 0 # ITB inst misses
|
133system.cpu.dtb.read_hits 183543984 # DTB read hits 134system.cpu.dtb.read_misses 195343 # DTB read misses 135system.cpu.dtb.write_hits 167774645 # DTB write hits 136system.cpu.dtb.write_misses 71238 # DTB write misses
| 133system.cpu.dtb.read_hits 421603994 # DTB read hits 134system.cpu.dtb.read_misses 196270 # DTB read misses 135system.cpu.dtb.write_hits 167651282 # DTB write hits 136system.cpu.dtb.write_misses 71394 # DTB write misses
|
137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
| 137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
139system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
| 139system.cpu.dtb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID
|
140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
| 140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
|
141system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB
| 141system.cpu.dtb.flush_entries 81418 # Number of entries that have been flushed from TLB
|
142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
| 142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
143system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch
| 143system.cpu.dtb.prefetch_faults 9097 # Number of TLB faults due to prefetch
|
144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
| 144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions 146system.cpu.dtb.read_accesses 183739327 # DTB read accesses 147system.cpu.dtb.write_accesses 167845883 # DTB write accesses
| 145system.cpu.dtb.perms_faults 21656 # Number of TLB faults due to permissions restrictions 146system.cpu.dtb.read_accesses 421800264 # DTB read accesses 147system.cpu.dtb.write_accesses 167722676 # DTB write accesses
|
148system.cpu.dtb.inst_accesses 0 # ITB inst accesses
| 148system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
149system.cpu.dtb.hits 351318629 # DTB hits 150system.cpu.dtb.misses 266581 # DTB misses 151system.cpu.dtb.accesses 351585210 # DTB accesses 152system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 149system.cpu.dtb.hits 589255276 # DTB hits 150system.cpu.dtb.misses 267664 # DTB misses 151system.cpu.dtb.accesses 589522940 # DTB accesses 152system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
153system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 159system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 160system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 161system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 162system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 163system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 164system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 165system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 166system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 167system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 168system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 169system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 170system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 171system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 172system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 173system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 174system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 176system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 177system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 178system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 179system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 180system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 181system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 153system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 159system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 160system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 161system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 162system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 163system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 164system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 165system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 166system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 167system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 168system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 169system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 170system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 171system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 172system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 173system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 174system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 176system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 177system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 178system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 179system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 180system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 181system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
182system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 183system.cpu.itb.walker.walks 126834 # Table walker walks requested 184system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors 185system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency 186system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency 187system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency
| 182system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 183system.cpu.itb.walker.walks 126885 # Table walker walks requested 184system.cpu.itb.walker.walksLong 126885 # Table walker walks initiated with long descriptors 185system.cpu.itb.walker.walkWaitTime::samples 126885 # Table walker wait (enqueue to first request) latency 186system.cpu.itb.walker.walkWaitTime::0 126885 100.00% 100.00% # Table walker wait (enqueue to first request) latency 187system.cpu.itb.walker.walkWaitTime::total 126885 # Table walker wait (enqueue to first request) latency
|
188system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 189system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 190system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
| 188system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 189system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 190system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
|
191system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated
| 191system.cpu.itb.walker.walkPageSizes::4K 113624 99.02% 99.02% # Table walker page sizes translated
|
192system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated
| 192system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated
|
193system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated
| 193system.cpu.itb.walker.walkPageSizes::total 114746 # Table walker page sizes translated
|
194system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
| 194system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
195system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst 196system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst
| 195system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126885 # Table walker requests started/completed, data/inst 196system.cpu.itb.walker.walkRequestOrigin_Requested::total 126885 # Table walker requests started/completed, data/inst
|
197system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
| 197system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
198system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst 199system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst 200system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst 201system.cpu.itb.inst_hits 982674869 # ITB inst hits 202system.cpu.itb.inst_misses 126834 # ITB inst misses
| 198system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114746 # Table walker requests started/completed, data/inst 199system.cpu.itb.walker.walkRequestOrigin_Completed::total 114746 # Table walker requests started/completed, data/inst 200system.cpu.itb.walker.walkRequestOrigin::total 241631 # Table walker requests started/completed, data/inst 201system.cpu.itb.inst_hits 1815394284 # ITB inst hits 202system.cpu.itb.inst_misses 126885 # ITB inst misses
|
203system.cpu.itb.read_hits 0 # DTB read hits 204system.cpu.itb.read_misses 0 # DTB read misses 205system.cpu.itb.write_hits 0 # DTB write hits 206system.cpu.itb.write_misses 0 # DTB write misses 207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
| 203system.cpu.itb.read_hits 0 # DTB read hits 204system.cpu.itb.read_misses 0 # DTB read misses 205system.cpu.itb.write_hits 0 # DTB write hits 206system.cpu.itb.write_misses 0 # DTB write misses 207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
209system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
| 209system.cpu.itb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID
|
210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
| 210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
|
211system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB
| 211system.cpu.itb.flush_entries 57333 # Number of entries that have been flushed from TLB
|
212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses
| 212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 216system.cpu.itb.read_accesses 0 # DTB read accesses 217system.cpu.itb.write_accesses 0 # DTB write accesses
|
218system.cpu.itb.inst_accesses 982801703 # ITB inst accesses 219system.cpu.itb.hits 982674869 # DTB hits 220system.cpu.itb.misses 126834 # DTB misses 221system.cpu.itb.accesses 982801703 # DTB accesses 222system.cpu.numPwrStateTransitions 33550 # Number of power state transitions 223system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state 224system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state 226system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state
| 218system.cpu.itb.inst_accesses 1815521169 # ITB inst accesses 219system.cpu.itb.hits 1815394284 # DTB hits 220system.cpu.itb.misses 126885 # DTB misses 221system.cpu.itb.accesses 1815521169 # DTB accesses 222system.cpu.numPwrStateTransitions 33574 # Number of power state transitions 223system.cpu.pwrStateClkGateDist::samples 16787 # Distribution of time spent in the clock gated state 224system.cpu.pwrStateClkGateDist::mean 3011524161.053136 # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::stdev 59680214632.955681 # Distribution of time spent in the clock gated state 226system.cpu.pwrStateClkGateDist::underflows 7463 44.46% 44.46% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::1000-5e+10 9289 55.33% 99.79% # Distribution of time spent in the clock gated state
|
228system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 231system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 232system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state 233system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 234system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
| 228system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 231system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 232system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state 233system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 234system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
235system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
| 235system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
236system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 237system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
| 236system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 237system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
238system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state 239system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state 240system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states 241system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states 242system.cpu.numCycles 102222351313 # number of cpu cycles simulated
| 238system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state 239system.cpu.pwrStateClkGateDist::total 16787 # Distribution of time spent in the clock gated state 240system.cpu.pwrStateResidencyTicks::ON 993796308901 # Cumulative time (in ticks) in various power states 241system.cpu.pwrStateResidencyTicks::CLK_GATED 50554456091599 # Cumulative time (in ticks) in various power states 242system.cpu.numCycles 103096521589 # number of cpu cycles simulated
|
243system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 244system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 245system.cpu.kern.inst.arm 0 # number of arm instructions executed
| 243system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 244system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 245system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
246system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed 247system.cpu.committedInsts 982198023 # Number of instructions committed 248system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed 249system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses 250system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses 251system.cpu.num_func_calls 56833843 # number of times a function call or return occured 252system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls 253system.cpu.num_int_insts 1057877135 # number of integer instructions 254system.cpu.num_fp_insts 881349 # number of float instructions 255system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read 256system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written 257system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read 258system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written 259system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read 260system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written 261system.cpu.num_mem_refs 351538055 # number of memory refs 262system.cpu.num_load_insts 183711282 # Number of load instructions 263system.cpu.num_store_insts 167826773 # Number of store instructions 264system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles 265system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles 266system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles 267system.cpu.idle_fraction 0.988702 # Percentage of idle cycles 268system.cpu.Branches 219532189 # Number of branches fetched
| 246system.cpu.kern.inst.quiesce 16787 # number of quiesce instructions executed 247system.cpu.committedInsts 1814916572 # Number of instructions committed 248system.cpu.committedOps 1986945286 # Number of ops (including micro ops) committed 249system.cpu.num_int_alu_accesses 1711962456 # Number of integer alu accesses 250system.cpu.num_fp_alu_accesses 884728 # Number of float alu accesses 251system.cpu.num_func_calls 56754008 # number of times a function call or return occured 252system.cpu.num_conditional_control_insts 449117161 # number of instructions that are conditional controls 253system.cpu.num_int_insts 1711962456 # number of integer instructions 254system.cpu.num_fp_insts 884728 # number of float instructions 255system.cpu.num_int_register_reads 2333816547 # number of times the integer registers were read 256system.cpu.num_int_register_writes 1316284167 # number of times the integer registers were written 257system.cpu.num_fp_register_reads 1424283 # number of times the floating registers were read 258system.cpu.num_fp_register_writes 753044 # number of times the floating registers were written 259system.cpu.num_cc_register_reads 621173289 # number of times the CC registers were read 260system.cpu.num_cc_register_writes 620585461 # number of times the CC registers were written 261system.cpu.num_mem_refs 589476099 # number of memory refs 262system.cpu.num_load_insts 421772480 # Number of load instructions 263system.cpu.num_store_insts 167703619 # Number of store instructions 264system.cpu.num_idle_cycles 101108928647.540985 # Number of idle cycles 265system.cpu.num_busy_cycles 1987592941.459016 # Number of busy cycles 266system.cpu.not_idle_fraction 0.019279 # Percentage of non-idle cycles 267system.cpu.idle_fraction 0.980721 # Percentage of idle cycles 268system.cpu.Branches 576475057 # Number of branches fetched
|
269system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
| 269system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
270system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction 271system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction 272system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction 273system.cpu.op_class::FloatAdd 8 0.00% 69.55% # Class of executed instruction 274system.cpu.op_class::FloatCmp 13 0.00% 69.55% # Class of executed instruction 275system.cpu.op_class::FloatCvt 21 0.00% 69.55% # Class of executed instruction 276system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction 277system.cpu.op_class::FloatMultAcc 0 0.00% 69.55% # Class of executed instruction 278system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction 279system.cpu.op_class::FloatMisc 107822 0.01% 69.56% # Class of executed instruction 280system.cpu.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction 281system.cpu.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction 282system.cpu.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction 283system.cpu.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction 284system.cpu.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction 285system.cpu.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction 286system.cpu.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction 287system.cpu.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction 288system.cpu.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction 289system.cpu.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction 290system.cpu.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction 291system.cpu.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction 292system.cpu.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction 293system.cpu.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction 294system.cpu.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction 295system.cpu.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction 296system.cpu.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction 297system.cpu.op_class::SimdFloatMisc 0 0.00% 69.56% # Class of executed instruction 298system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction 299system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction 300system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction 301system.cpu.op_class::MemRead 183598958 15.90% 85.46% # Class of executed instruction 302system.cpu.op_class::MemWrite 167165612 14.47% 99.93% # Class of executed instruction 303system.cpu.op_class::FloatMemRead 112324 0.01% 99.94% # Class of executed instruction 304system.cpu.op_class::FloatMemWrite 661161 0.06% 100.00% # Class of executed instruction
| 270system.cpu.op_class::IntAlu 1395540402 70.21% 70.21% # Class of executed instruction 271system.cpu.op_class::IntMult 2356131 0.12% 70.33% # Class of executed instruction 272system.cpu.op_class::IntDiv 100370 0.01% 70.34% # Class of executed instruction 273system.cpu.op_class::FloatAdd 8 0.00% 70.34% # Class of executed instruction 274system.cpu.op_class::FloatCmp 13 0.00% 70.34% # Class of executed instruction 275system.cpu.op_class::FloatCvt 21 0.00% 70.34% # Class of executed instruction 276system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction 277system.cpu.op_class::FloatMultAcc 0 0.00% 70.34% # Class of executed instruction 278system.cpu.op_class::FloatDiv 0 0.00% 70.34% # Class of executed instruction 279system.cpu.op_class::FloatMisc 107824 0.01% 70.34% # Class of executed instruction 280system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction 281system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction 282system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction 283system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction 284system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction 285system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction 286system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction 287system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction 288system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction 289system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction 290system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction 291system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction 292system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction 293system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction 294system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction 295system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction 296system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction 297system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction 298system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction 299system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction 300system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction 301system.cpu.op_class::MemRead 421659035 21.21% 91.56% # Class of executed instruction 302system.cpu.op_class::MemWrite 167040202 8.40% 99.96% # Class of executed instruction 303system.cpu.op_class::FloatMemRead 113445 0.01% 99.97% # Class of executed instruction 304system.cpu.op_class::FloatMemWrite 663417 0.03% 100.00% # Class of executed instruction
|
305system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 306system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
| 305system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 306system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
307system.cpu.op_class::total 1154930294 # Class of executed instruction 308system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 309system.cpu.dcache.tags.replacements 11606056 # number of replacements 310system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use 311system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. 312system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. 313system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks.
| 307system.cpu.op_class::total 1987580869 # Class of executed instruction 308system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 309system.cpu.dcache.tags.replacements 11603445 # number of replacements 310system.cpu.dcache.tags.tagsinuse 511.999721 # Cycle average of tags in use 311system.cpu.dcache.tags.total_refs 577795083 # Total number of references to valid blocks. 312system.cpu.dcache.tags.sampled_refs 11603957 # Sample count of references to valid blocks. 313system.cpu.dcache.tags.avg_refs 49.792936 # Average number of references to valid blocks.
|
314system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
| 314system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
|
315system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
| 315system.cpu.dcache.tags.occ_blocks::cpu.data 511.999721 # Average occupied blocks per requestor
|
316system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 317system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 318system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
| 316system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 317system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 318system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
319system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 320system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 321system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
| 319system.cpu.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 320system.cpu.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id 321system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
322system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
| 322system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
323system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses 324system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses 325system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 326system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits 327system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits 328system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits 329system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits 330system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits 331system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits 332system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits 333system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits 334system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits 335system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits 336system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits 337system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits 338system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits 339system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits 340system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits 341system.cpu.dcache.overall_hits::total 330960928 # number of overall hits 342system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses 343system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses 344system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses 345system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses 346system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses 347system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses 348system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses 349system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses 350system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses 351system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses
| 323system.cpu.dcache.tags.tag_accesses 2369200172 # Number of tag accesses 324system.cpu.dcache.tags.data_accesses 2369200172 # Number of data accesses 325system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 326system.cpu.dcache.ReadReq_hits::cpu.data 409181313 # number of ReadReq hits 327system.cpu.dcache.ReadReq_hits::total 409181313 # number of ReadReq hits 328system.cpu.dcache.WriteReq_hits::cpu.data 158964390 # number of WriteReq hits 329system.cpu.dcache.WriteReq_hits::total 158964390 # number of WriteReq hits 330system.cpu.dcache.SoftPFReq_hits::cpu.data 425694 # number of SoftPFReq hits 331system.cpu.dcache.SoftPFReq_hits::total 425694 # number of SoftPFReq hits 332system.cpu.dcache.WriteLineReq_hits::cpu.data 336647 # number of WriteLineReq hits 333system.cpu.dcache.WriteLineReq_hits::total 336647 # number of WriteLineReq hits 334system.cpu.dcache.LoadLockedReq_hits::cpu.data 4299455 # number of LoadLockedReq hits 335system.cpu.dcache.LoadLockedReq_hits::total 4299455 # number of LoadLockedReq hits 336system.cpu.dcache.StoreCondReq_hits::cpu.data 4553147 # number of StoreCondReq hits 337system.cpu.dcache.StoreCondReq_hits::total 4553147 # number of StoreCondReq hits 338system.cpu.dcache.demand_hits::cpu.data 568482350 # number of demand (read+write) hits 339system.cpu.dcache.demand_hits::total 568482350 # number of demand (read+write) hits 340system.cpu.dcache.overall_hits::cpu.data 568908044 # number of overall hits 341system.cpu.dcache.overall_hits::total 568908044 # number of overall hits 342system.cpu.dcache.ReadReq_misses::cpu.data 5993326 # number of ReadReq misses 343system.cpu.dcache.ReadReq_misses::total 5993326 # number of ReadReq misses 344system.cpu.dcache.WriteReq_misses::cpu.data 2556217 # number of WriteReq misses 345system.cpu.dcache.WriteReq_misses::total 2556217 # number of WriteReq misses 346system.cpu.dcache.SoftPFReq_misses::cpu.data 1586747 # number of SoftPFReq misses 347system.cpu.dcache.SoftPFReq_misses::total 1586747 # number of SoftPFReq misses 348system.cpu.dcache.WriteLineReq_misses::cpu.data 1246619 # number of WriteLineReq misses 349system.cpu.dcache.WriteLineReq_misses::total 1246619 # number of WriteLineReq misses 350system.cpu.dcache.LoadLockedReq_misses::cpu.data 255495 # number of LoadLockedReq misses 351system.cpu.dcache.LoadLockedReq_misses::total 255495 # number of LoadLockedReq misses
|
352system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 353system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
| 352system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 353system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
354system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses 355system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses 356system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses 357system.cpu.dcache.overall_misses::total 11387343 # number of overall misses 358system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) 359system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) 360system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) 361system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) 362system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) 363system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) 364system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) 365system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) 366system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) 367system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) 368system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) 369system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) 370system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses 371system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses 372system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses 373system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses 374system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses 375system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses 376system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses 377system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses 378system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses 379system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses 380system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses 381system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses 382system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses 383system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
| 354system.cpu.dcache.demand_misses::cpu.data 9796162 # number of demand (read+write) misses 355system.cpu.dcache.demand_misses::total 9796162 # number of demand (read+write) misses 356system.cpu.dcache.overall_misses::cpu.data 11382909 # number of overall misses 357system.cpu.dcache.overall_misses::total 11382909 # number of overall misses 358system.cpu.dcache.ReadReq_accesses::cpu.data 415174639 # number of ReadReq accesses(hits+misses) 359system.cpu.dcache.ReadReq_accesses::total 415174639 # number of ReadReq accesses(hits+misses) 360system.cpu.dcache.WriteReq_accesses::cpu.data 161520607 # number of WriteReq accesses(hits+misses) 361system.cpu.dcache.WriteReq_accesses::total 161520607 # number of WriteReq accesses(hits+misses) 362system.cpu.dcache.SoftPFReq_accesses::cpu.data 2012441 # number of SoftPFReq accesses(hits+misses) 363system.cpu.dcache.SoftPFReq_accesses::total 2012441 # number of SoftPFReq accesses(hits+misses) 364system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583266 # number of WriteLineReq accesses(hits+misses) 365system.cpu.dcache.WriteLineReq_accesses::total 1583266 # number of WriteLineReq accesses(hits+misses) 366system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4554950 # number of LoadLockedReq accesses(hits+misses) 367system.cpu.dcache.LoadLockedReq_accesses::total 4554950 # number of LoadLockedReq accesses(hits+misses) 368system.cpu.dcache.StoreCondReq_accesses::cpu.data 4553148 # number of StoreCondReq accesses(hits+misses) 369system.cpu.dcache.StoreCondReq_accesses::total 4553148 # number of StoreCondReq accesses(hits+misses) 370system.cpu.dcache.demand_accesses::cpu.data 578278512 # number of demand (read+write) accesses 371system.cpu.dcache.demand_accesses::total 578278512 # number of demand (read+write) accesses 372system.cpu.dcache.overall_accesses::cpu.data 580290953 # number of overall (read+write) accesses 373system.cpu.dcache.overall_accesses::total 580290953 # number of overall (read+write) accesses 374system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014436 # miss rate for ReadReq accesses 375system.cpu.dcache.ReadReq_miss_rate::total 0.014436 # miss rate for ReadReq accesses 376system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015826 # miss rate for WriteReq accesses 377system.cpu.dcache.WriteReq_miss_rate::total 0.015826 # miss rate for WriteReq accesses 378system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788469 # miss rate for SoftPFReq accesses 379system.cpu.dcache.SoftPFReq_miss_rate::total 0.788469 # miss rate for SoftPFReq accesses 380system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787372 # miss rate for WriteLineReq accesses 381system.cpu.dcache.WriteLineReq_miss_rate::total 0.787372 # miss rate for WriteLineReq accesses 382system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056092 # miss rate for LoadLockedReq accesses 383system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056092 # miss rate for LoadLockedReq accesses
|
384system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 385system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
| 384system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 385system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
386system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses 387system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses 388system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses 389system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses
| 386system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses 387system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses 388system.cpu.dcache.overall_miss_rate::cpu.data 0.019616 # miss rate for overall accesses 389system.cpu.dcache.overall_miss_rate::total 0.019616 # miss rate for overall accesses
|
390system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 391system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 392system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 393system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 394system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 395system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 390system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 391system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 392system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 393system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 394system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 395system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
396system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks 397system.cpu.dcache.writebacks::total 8918956 # number of writebacks 398system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 399system.cpu.icache.tags.replacements 14265255 # number of replacements 400system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use 401system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. 402system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. 403system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks.
| 396system.cpu.dcache.writebacks::writebacks 8939334 # number of writebacks 397system.cpu.dcache.writebacks::total 8939334 # number of writebacks 398system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 399system.cpu.icache.tags.replacements 14289332 # number of replacements 400system.cpu.icache.tags.tagsinuse 511.984730 # Cycle average of tags in use 401system.cpu.icache.tags.total_refs 1801219181 # Total number of references to valid blocks. 402system.cpu.icache.tags.sampled_refs 14289844 # Sample count of references to valid blocks. 403system.cpu.icache.tags.avg_refs 126.048904 # Average number of references to valid blocks.
|
404system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit.
| 404system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit.
|
405system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
| 405system.cpu.icache.tags.occ_blocks::cpu.inst 511.984730 # Average occupied blocks per requestor
|
406system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 407system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 408system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
| 406system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy 407system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy 408system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
409system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 410system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 411system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
| 409system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 410system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 411system.cpu.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
|
412system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
| 412system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
413system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses 414system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses 415system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 416system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits 417system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits 418system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits 419system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits 420system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits 421system.cpu.icache.overall_hits::total 968523793 # number of overall hits 422system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses 423system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses 424system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses 425system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses 426system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses 427system.cpu.icache.overall_misses::total 14265772 # number of overall misses 428system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) 429system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) 430system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses 431system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses 432system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses 433system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses 434system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses 435system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses 436system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses 437system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses 438system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses 439system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses
| 413system.cpu.icache.tags.tag_accesses 1829798879 # Number of tag accesses 414system.cpu.icache.tags.data_accesses 1829798879 # Number of data accesses 415system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 416system.cpu.icache.ReadReq_hits::cpu.inst 1801219181 # number of ReadReq hits 417system.cpu.icache.ReadReq_hits::total 1801219181 # number of ReadReq hits 418system.cpu.icache.demand_hits::cpu.inst 1801219181 # number of demand (read+write) hits 419system.cpu.icache.demand_hits::total 1801219181 # number of demand (read+write) hits 420system.cpu.icache.overall_hits::cpu.inst 1801219181 # number of overall hits 421system.cpu.icache.overall_hits::total 1801219181 # number of overall hits 422system.cpu.icache.ReadReq_misses::cpu.inst 14289849 # number of ReadReq misses 423system.cpu.icache.ReadReq_misses::total 14289849 # number of ReadReq misses 424system.cpu.icache.demand_misses::cpu.inst 14289849 # number of demand (read+write) misses 425system.cpu.icache.demand_misses::total 14289849 # number of demand (read+write) misses 426system.cpu.icache.overall_misses::cpu.inst 14289849 # number of overall misses 427system.cpu.icache.overall_misses::total 14289849 # number of overall misses 428system.cpu.icache.ReadReq_accesses::cpu.inst 1815509030 # number of ReadReq accesses(hits+misses) 429system.cpu.icache.ReadReq_accesses::total 1815509030 # number of ReadReq accesses(hits+misses) 430system.cpu.icache.demand_accesses::cpu.inst 1815509030 # number of demand (read+write) accesses 431system.cpu.icache.demand_accesses::total 1815509030 # number of demand (read+write) accesses 432system.cpu.icache.overall_accesses::cpu.inst 1815509030 # number of overall (read+write) accesses 433system.cpu.icache.overall_accesses::total 1815509030 # number of overall (read+write) accesses 434system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007871 # miss rate for ReadReq accesses 435system.cpu.icache.ReadReq_miss_rate::total 0.007871 # miss rate for ReadReq accesses 436system.cpu.icache.demand_miss_rate::cpu.inst 0.007871 # miss rate for demand accesses 437system.cpu.icache.demand_miss_rate::total 0.007871 # miss rate for demand accesses 438system.cpu.icache.overall_miss_rate::cpu.inst 0.007871 # miss rate for overall accesses 439system.cpu.icache.overall_miss_rate::total 0.007871 # miss rate for overall accesses
|
440system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 441system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 442system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 443system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 444system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 445system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 440system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 441system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 442system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 443system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 444system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 445system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
446system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks 447system.cpu.icache.writebacks::total 14265255 # number of writebacks 448system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 449system.cpu.l2cache.tags.replacements 1725823 # number of replacements 450system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use 451system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks. 452system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks. 453system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks.
| 446system.cpu.icache.writebacks::writebacks 14289332 # number of writebacks 447system.cpu.icache.writebacks::total 14289332 # number of writebacks 448system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 449system.cpu.l2cache.tags.replacements 1684196 # number of replacements 450system.cpu.l2cache.tags.tagsinuse 65394.978455 # Cycle average of tags in use 451system.cpu.l2cache.tags.total_refs 49472483 # Total number of references to valid blocks. 452system.cpu.l2cache.tags.sampled_refs 1746767 # Sample count of references to valid blocks. 453system.cpu.l2cache.tags.avg_refs 28.322314 # Average number of references to valid blocks.
|
454system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit.
| 454system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit.
|
455system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor 456system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor 457system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor 458system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor 459system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy 461system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy 466system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id 467system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 471system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id 472system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id 473system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id 474system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id 475system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id 476system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses 477system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses 478system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 479system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits 480system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits 481system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits 482system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits 483system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits 484system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits 485system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits 486system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits 487system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits 488system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits 489system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits 490system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits 491system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits 492system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits 493system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits 494system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits 495system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits 496system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits 497system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits 498system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits 499system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits 500system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits 501system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits 502system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits 503system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits 504system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits 505system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits 506system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses 507system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses 508system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses 509system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses 510system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses
| 455system.cpu.l2cache.tags.occ_blocks::writebacks 9677.706964 # Average occupied blocks per requestor 456system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 426.448625 # Average occupied blocks per requestor 457system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 480.005287 # Average occupied blocks per requestor 458system.cpu.l2cache.tags.occ_blocks::cpu.inst 6101.422178 # Average occupied blocks per requestor 459system.cpu.l2cache.tags.occ_blocks::cpu.data 48709.395401 # Average occupied blocks per requestor 460system.cpu.l2cache.tags.occ_percent::writebacks 0.147670 # Average percentage of cache occupancy 461system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006507 # Average percentage of cache occupancy 462system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007324 # Average percentage of cache occupancy 463system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093100 # Average percentage of cache occupancy 464system.cpu.l2cache.tags.occ_percent::cpu.data 0.743246 # Average percentage of cache occupancy 465system.cpu.l2cache.tags.occ_percent::total 0.997848 # Average percentage of cache occupancy 466system.cpu.l2cache.tags.occ_task_id_blocks::1023 329 # Occupied blocks per task id 467system.cpu.l2cache.tags.occ_task_id_blocks::1024 62242 # Occupied blocks per task id 468system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 469system.cpu.l2cache.tags.age_task_id_blocks_1023::4 328 # Occupied blocks per task id 470system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 471system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 472system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1404 # Occupied blocks per task id 473system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5082 # Occupied blocks per task id 474system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55348 # Occupied blocks per task id 475system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005020 # Percentage of cache occupancy per task id 476system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id 477system.cpu.l2cache.tags.tag_accesses 422888423 # Number of tag accesses 478system.cpu.l2cache.tags.data_accesses 422888423 # Number of data accesses 479system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 480system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 482010 # number of ReadReq hits 481system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237204 # number of ReadReq hits 482system.cpu.l2cache.ReadReq_hits::total 719214 # number of ReadReq hits 483system.cpu.l2cache.WritebackDirty_hits::writebacks 8939334 # number of WritebackDirty hits 484system.cpu.l2cache.WritebackDirty_hits::total 8939334 # number of WritebackDirty hits 485system.cpu.l2cache.WritebackClean_hits::writebacks 14287756 # number of WritebackClean hits 486system.cpu.l2cache.WritebackClean_hits::total 14287756 # number of WritebackClean hits 487system.cpu.l2cache.UpgradeReq_hits::cpu.data 30651 # number of UpgradeReq hits 488system.cpu.l2cache.UpgradeReq_hits::total 30651 # number of UpgradeReq hits 489system.cpu.l2cache.ReadExReq_hits::cpu.data 1695121 # number of ReadExReq hits 490system.cpu.l2cache.ReadExReq_hits::total 1695121 # number of ReadExReq hits 491system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14209837 # number of ReadCleanReq hits 492system.cpu.l2cache.ReadCleanReq_hits::total 14209837 # number of ReadCleanReq hits 493system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7515311 # number of ReadSharedReq hits 494system.cpu.l2cache.ReadSharedReq_hits::total 7515311 # number of ReadSharedReq hits 495system.cpu.l2cache.InvalidateReq_hits::cpu.data 704740 # number of InvalidateReq hits 496system.cpu.l2cache.InvalidateReq_hits::total 704740 # number of InvalidateReq hits 497system.cpu.l2cache.demand_hits::cpu.dtb.walker 482010 # number of demand (read+write) hits 498system.cpu.l2cache.demand_hits::cpu.itb.walker 237204 # number of demand (read+write) hits 499system.cpu.l2cache.demand_hits::cpu.inst 14209837 # number of demand (read+write) hits 500system.cpu.l2cache.demand_hits::cpu.data 9210432 # number of demand (read+write) hits 501system.cpu.l2cache.demand_hits::total 24139483 # number of demand (read+write) hits 502system.cpu.l2cache.overall_hits::cpu.dtb.walker 482010 # number of overall hits 503system.cpu.l2cache.overall_hits::cpu.itb.walker 237204 # number of overall hits 504system.cpu.l2cache.overall_hits::cpu.inst 14209837 # number of overall hits 505system.cpu.l2cache.overall_hits::cpu.data 9210432 # number of overall hits 506system.cpu.l2cache.overall_hits::total 24139483 # number of overall hits 507system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6072 # number of ReadReq misses 508system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5747 # number of ReadReq misses 509system.cpu.l2cache.ReadReq_misses::total 11819 # number of ReadReq misses 510system.cpu.l2cache.UpgradeReq_misses::cpu.data 3785 # number of UpgradeReq misses 511system.cpu.l2cache.UpgradeReq_misses::total 3785 # number of UpgradeReq misses
|
511system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 512system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
| 512system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 513system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
513system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses 514system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses 515system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses 516system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses 517system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses 518system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses 519system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses 520system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses 521system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses 522system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses 523system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses 524system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses 525system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses 526system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses 527system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses 528system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses 529system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses 530system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses 531system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) 532system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) 533system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) 534system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) 535system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) 536system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) 537system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) 538system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) 539system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses)
| 514system.cpu.l2cache.ReadExReq_misses::cpu.data 826660 # number of ReadExReq misses 515system.cpu.l2cache.ReadExReq_misses::total 826660 # number of ReadExReq misses 516system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 80012 # number of ReadCleanReq misses 517system.cpu.l2cache.ReadCleanReq_misses::total 80012 # number of ReadCleanReq misses 518system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320257 # number of ReadSharedReq misses 519system.cpu.l2cache.ReadSharedReq_misses::total 320257 # number of ReadSharedReq misses 520system.cpu.l2cache.InvalidateReq_misses::cpu.data 541879 # number of InvalidateReq misses 521system.cpu.l2cache.InvalidateReq_misses::total 541879 # number of InvalidateReq misses 522system.cpu.l2cache.demand_misses::cpu.dtb.walker 6072 # number of demand (read+write) misses 523system.cpu.l2cache.demand_misses::cpu.itb.walker 5747 # number of demand (read+write) misses 524system.cpu.l2cache.demand_misses::cpu.inst 80012 # number of demand (read+write) misses 525system.cpu.l2cache.demand_misses::cpu.data 1146917 # number of demand (read+write) misses 526system.cpu.l2cache.demand_misses::total 1238748 # number of demand (read+write) misses 527system.cpu.l2cache.overall_misses::cpu.dtb.walker 6072 # number of overall misses 528system.cpu.l2cache.overall_misses::cpu.itb.walker 5747 # number of overall misses 529system.cpu.l2cache.overall_misses::cpu.inst 80012 # number of overall misses 530system.cpu.l2cache.overall_misses::cpu.data 1146917 # number of overall misses 531system.cpu.l2cache.overall_misses::total 1238748 # number of overall misses 532system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 488082 # number of ReadReq accesses(hits+misses) 533system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 242951 # number of ReadReq accesses(hits+misses) 534system.cpu.l2cache.ReadReq_accesses::total 731033 # number of ReadReq accesses(hits+misses) 535system.cpu.l2cache.WritebackDirty_accesses::writebacks 8939334 # number of WritebackDirty accesses(hits+misses) 536system.cpu.l2cache.WritebackDirty_accesses::total 8939334 # number of WritebackDirty accesses(hits+misses) 537system.cpu.l2cache.WritebackClean_accesses::writebacks 14287756 # number of WritebackClean accesses(hits+misses) 538system.cpu.l2cache.WritebackClean_accesses::total 14287756 # number of WritebackClean accesses(hits+misses) 539system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34436 # number of UpgradeReq accesses(hits+misses) 540system.cpu.l2cache.UpgradeReq_accesses::total 34436 # number of UpgradeReq accesses(hits+misses)
|
540system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 541system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
| 541system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 542system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
542system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) 543system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) 544system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) 545system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) 546system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) 547system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) 548system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) 549system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) 550system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses 552system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses 553system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses 554system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses 555system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses 556system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses 557system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses 558system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses 559system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses 560system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses 561system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses 563system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses 564system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses
| 543system.cpu.l2cache.ReadExReq_accesses::cpu.data 2521781 # number of ReadExReq accesses(hits+misses) 544system.cpu.l2cache.ReadExReq_accesses::total 2521781 # number of ReadExReq accesses(hits+misses) 545system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14289849 # number of ReadCleanReq accesses(hits+misses) 546system.cpu.l2cache.ReadCleanReq_accesses::total 14289849 # number of ReadCleanReq accesses(hits+misses) 547system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7835568 # number of ReadSharedReq accesses(hits+misses) 548system.cpu.l2cache.ReadSharedReq_accesses::total 7835568 # number of ReadSharedReq accesses(hits+misses) 549system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246619 # number of InvalidateReq accesses(hits+misses) 550system.cpu.l2cache.InvalidateReq_accesses::total 1246619 # number of InvalidateReq accesses(hits+misses) 551system.cpu.l2cache.demand_accesses::cpu.dtb.walker 488082 # number of demand (read+write) accesses 552system.cpu.l2cache.demand_accesses::cpu.itb.walker 242951 # number of demand (read+write) accesses 553system.cpu.l2cache.demand_accesses::cpu.inst 14289849 # number of demand (read+write) accesses 554system.cpu.l2cache.demand_accesses::cpu.data 10357349 # number of demand (read+write) accesses 555system.cpu.l2cache.demand_accesses::total 25378231 # number of demand (read+write) accesses 556system.cpu.l2cache.overall_accesses::cpu.dtb.walker 488082 # number of overall (read+write) accesses 557system.cpu.l2cache.overall_accesses::cpu.itb.walker 242951 # number of overall (read+write) accesses 558system.cpu.l2cache.overall_accesses::cpu.inst 14289849 # number of overall (read+write) accesses 559system.cpu.l2cache.overall_accesses::cpu.data 10357349 # number of overall (read+write) accesses 560system.cpu.l2cache.overall_accesses::total 25378231 # number of overall (read+write) accesses 561system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012441 # miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.023655 # miss rate for ReadReq accesses 563system.cpu.l2cache.ReadReq_miss_rate::total 0.016168 # miss rate for ReadReq accesses 564system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109914 # miss rate for UpgradeReq accesses 565system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109914 # miss rate for UpgradeReq accesses
|
565system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 566system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
| 566system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 567system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
567system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses 568system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses 569system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses 570system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses 571system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses 572system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses 573system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses 574system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses 575system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses 576system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses 577system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses 578system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses 579system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses 580system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses 581system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses 582system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses 583system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses 584system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses
| 568system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327808 # miss rate for ReadExReq accesses 569system.cpu.l2cache.ReadExReq_miss_rate::total 0.327808 # miss rate for ReadExReq accesses 570system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005599 # miss rate for ReadCleanReq accesses 571system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005599 # miss rate for ReadCleanReq accesses 572system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040872 # miss rate for ReadSharedReq accesses 573system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040872 # miss rate for ReadSharedReq accesses 574system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.434679 # miss rate for InvalidateReq accesses 575system.cpu.l2cache.InvalidateReq_miss_rate::total 0.434679 # miss rate for InvalidateReq accesses 576system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012441 # miss rate for demand accesses 577system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.023655 # miss rate for demand accesses 578system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005599 # miss rate for demand accesses 579system.cpu.l2cache.demand_miss_rate::cpu.data 0.110735 # miss rate for demand accesses 580system.cpu.l2cache.demand_miss_rate::total 0.048811 # miss rate for demand accesses 581system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012441 # miss rate for overall accesses 582system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.023655 # miss rate for overall accesses 583system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005599 # miss rate for overall accesses 584system.cpu.l2cache.overall_miss_rate::cpu.data 0.110735 # miss rate for overall accesses 585system.cpu.l2cache.overall_miss_rate::total 0.048811 # miss rate for overall accesses
|
585system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 586system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 588system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 589system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 590system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
| 586system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 587system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 588system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 589system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 590system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 591system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
591system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks 592system.cpu.l2cache.writebacks::total 1507096 # number of writebacks 593system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. 594system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. 595system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 596system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. 597system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
| 592system.cpu.l2cache.writebacks::writebacks 1484910 # number of writebacks 593system.cpu.l2cache.writebacks::total 1484910 # number of writebacks 594system.cpu.toL2Bus.snoop_filter.tot_requests 52410934 # Total number of requests made to the snoop filter. 595system.cpu.toL2Bus.snoop_filter.hit_single_requests 26517119 # Number of requests hitting in the snoop filter with a single holder of the requested data. 596system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 597system.cpu.toL2Bus.snoop_filter.tot_snoops 2740 # Total number of snoops made to the snoop filter. 598system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2740 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
598system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
| 599system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
599system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 600system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution 601system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution
| 600system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 601system.cpu.toL2Bus.trans_dist::ReadReq 1234221 # Transaction distribution 602system.cpu.toL2Bus.trans_dist::ReadResp 23359638 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::WriteReq 33618 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::WriteResp 33618 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::WritebackDirty 8939334 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::WritebackClean 14289332 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::CleanEvict 2664111 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::UpgradeReq 34436 # Transaction distribution
|
608system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
| 609system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
609system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution 616system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) 619system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) 620system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) 622system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) 623system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) 624system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) 625system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) 626system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) 627system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) 628system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram
| 610system.cpu.toL2Bus.trans_dist::UpgradeResp 34437 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExReq 2521781 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExResp 2521781 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::ReadCleanReq 14289849 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::ReadSharedReq 7835568 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::InvalidateReq 1246619 # Transaction distribution 616system.cpu.toL2Bus.trans_dist::InvalidateResp 1246619 # Transaction distribution 617system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42955280 # Packet count per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35014647 # Packet count per connected master and slave (bytes) 619system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758514 # Packet count per connected master and slave (bytes) 620system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1556522 # Packet count per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_count::total 80284963 # Packet count per connected master and slave (bytes) 622system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829240084 # Cumulative packet size per connected master and slave (bytes) 623system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235177526 # Cumulative packet size per connected master and slave (bytes) 624system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3034056 # Cumulative packet size per connected master and slave (bytes) 625system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6226088 # Cumulative packet size per connected master and slave (bytes) 626system.cpu.toL2Bus.pkt_size::total 3073677754 # Cumulative packet size per connected master and slave (bytes) 627system.cpu.toL2Bus.snoops 1724598 # Total snoops (count) 628system.cpu.toL2Bus.snoopTraffic 95094976 # Total snoop traffic (bytes) 629system.cpu.toL2Bus.snoop_fanout::samples 54812635 # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::mean 0.010876 # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::stdev 0.103719 # Request fanout histogram
|
631system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
| 632system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
632system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram
| 633system.cpu.toL2Bus.snoop_fanout::0 54216500 98.91% 98.91% # Request fanout histogram 634system.cpu.toL2Bus.snoop_fanout::1 596135 1.09% 100.00% # Request fanout histogram
|
634system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 635system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 637system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
| 635system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 637system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 638system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
638system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram 639system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 640system.iobus.trans_dist::ReadReq 40242 # Transaction distribution 641system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
| 639system.cpu.toL2Bus.snoop_fanout::total 54812635 # Request fanout histogram 640system.iobus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 641system.iobus.trans_dist::ReadReq 40253 # Transaction distribution 642system.iobus.trans_dist::ReadResp 40253 # Transaction distribution
|
642system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 643system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 644system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 645system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 646system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 647system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 648system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 649system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 650system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 651system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 652system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 653system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 654system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 655system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 656system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 657system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
| 643system.iobus.trans_dist::WriteReq 136515 # Transaction distribution 644system.iobus.trans_dist::WriteResp 136515 # Transaction distribution 645system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) 646system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 647system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 648system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 649system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 650system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 651system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 652system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 653system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 654system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 655system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 656system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 657system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 658system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
|
658system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) 659system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
| 659system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) 660system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes)
|
660system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 661system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
| 661system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 662system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
662system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes)
| 663system.iobus.pkt_count::total 353536 # Packet count per connected master and slave (bytes)
|
663system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) 664system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 665system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 666system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 667system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 668system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 669system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 670system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 676system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
| 664system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) 665system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 666system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 667system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 668system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 669system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 670system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 676system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 677system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
|
677system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) 678system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
| 678system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) 679system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes)
|
679system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 680system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
| 680system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 681system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
681system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) 682system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 683system.iocache.tags.replacements 115459 # number of replacements 684system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
| 682system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) 683system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 684system.iocache.tags.replacements 115470 # number of replacements 685system.iocache.tags.tagsinuse 10.454534 # Cycle average of tags in use
|
685system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
| 686system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
686system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
| 687system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks.
|
687system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 688system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit.
| 688system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 689system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit.
|
689system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor 690system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor 691system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy 692system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy 693system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
| 690system.iocache.tags.occ_blocks::realview.ethernet 3.524459 # Average occupied blocks per requestor 691system.iocache.tags.occ_blocks::realview.ide 6.930076 # Average occupied blocks per requestor 692system.iocache.tags.occ_percent::realview.ethernet 0.220279 # Average percentage of cache occupancy 693system.iocache.tags.occ_percent::realview.ide 0.433130 # Average percentage of cache occupancy 694system.iocache.tags.occ_percent::total 0.653408 # Average percentage of cache occupancy
|
694system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 695system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 696system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
| 695system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 696system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 697system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
697system.iocache.tags.tag_accesses 1039650 # Number of tag accesses 698system.iocache.tags.data_accesses 1039650 # Number of data accesses 699system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 698system.iocache.tags.tag_accesses 1039749 # Number of tag accesses 699system.iocache.tags.data_accesses 1039749 # Number of data accesses 700system.iocache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
700system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
| 701system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
701system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses 702system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
| 702system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses 703system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses
|
703system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 704system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 705system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 706system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 707system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
| 704system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 705system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 706system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 707system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 708system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
708system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses 709system.iocache.demand_misses::total 115517 # number of demand (read+write) misses
| 709system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses 710system.iocache.demand_misses::total 115528 # number of demand (read+write) misses
|
710system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
| 711system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
711system.iocache.overall_misses::realview.ide 115477 # number of overall misses 712system.iocache.overall_misses::total 115517 # number of overall misses
| 712system.iocache.overall_misses::realview.ide 115488 # number of overall misses 713system.iocache.overall_misses::total 115528 # number of overall misses
|
713system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
| 714system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
714system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) 715system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
| 715system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) 716system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses)
|
716system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 717system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 718system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 719system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 720system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
| 717system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 718system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 719system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 720system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 721system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
721system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses 722system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses
| 722system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses 723system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses
|
723system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
| 724system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
724system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses 725system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses
| 725system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses 726system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses
|
726system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 727system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 728system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 729system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 730system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 731system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 732system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 733system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 734system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 735system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 736system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 737system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 738system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 739system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 740system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 741system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 742system.iocache.blocked::no_targets 0 # number of cycles access was blocked 743system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 744system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 745system.iocache.writebacks::writebacks 106631 # number of writebacks 746system.iocache.writebacks::total 106631 # number of writebacks
| 727system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 728system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 729system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 730system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 731system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 732system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 733system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 734system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 735system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 736system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 737system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 738system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 739system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 740system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 741system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 742system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 743system.iocache.blocked::no_targets 0 # number of cycles access was blocked 744system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 745system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.iocache.writebacks::writebacks 106631 # number of writebacks 747system.iocache.writebacks::total 106631 # number of writebacks
|
747system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. 748system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. 749system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
| 748system.membus.snoop_filter.tot_requests 3698370 # Total number of requests made to the snoop filter. 749system.membus.snoop_filter.hit_single_requests 1836830 # Number of requests hitting in the snoop filter with a single holder of the requested data. 750system.membus.snoop_filter.hit_multi_requests 3132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
750system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 751system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 752system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
| 751system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 752system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 753system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
753system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 754system.membus.trans_dist::ReadReq 76679 # Transaction distribution 755system.membus.trans_dist::ReadResp 524960 # Transaction distribution 756system.membus.trans_dist::WriteReq 33606 # Transaction distribution 757system.membus.trans_dist::WriteResp 33606 # Transaction distribution 758system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution 759system.membus.trans_dist::CleanEvict 226320 # Transaction distribution 760system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution
| 754system.membus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 755system.membus.trans_dist::ReadReq 76703 # Transaction distribution 756system.membus.trans_dist::ReadResp 497652 # Transaction distribution 757system.membus.trans_dist::WriteReq 33618 # Transaction distribution 758system.membus.trans_dist::WriteResp 33618 # Transaction distribution 759system.membus.trans_dist::WritebackDirty 1591541 # Transaction distribution 760system.membus.trans_dist::CleanEvict 206888 # Transaction distribution 761system.membus.trans_dist::UpgradeReq 4346 # Transaction distribution
|
761system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
| 762system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
762system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution 763system.membus.trans_dist::ReadExReq 827049 # Transaction distribution 764system.membus.trans_dist::ReadExResp 827049 # Transaction distribution 765system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution 766system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution 767system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution
| 763system.membus.trans_dist::UpgradeResp 4347 # Transaction distribution 764system.membus.trans_dist::ReadExReq 826102 # Transaction distribution 765system.membus.trans_dist::ReadExResp 826102 # Transaction distribution 766system.membus.trans_dist::ReadSharedReq 420949 # Transaction distribution 767system.membus.trans_dist::InvalidateReq 648543 # Transaction distribution 768system.membus.trans_dist::InvalidateResp 648543 # Transaction distribution
|
768system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 769system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
| 769system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) 770system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
770system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) 771system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) 772system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) 773system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) 774system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) 775system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes)
| 771system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6726 # Packet count per connected master and slave (bytes) 772system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5343163 # Packet count per connected master and slave (bytes) 773system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5472427 # Packet count per connected master and slave (bytes) 774system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346526 # Packet count per connected master and slave (bytes) 775system.membus.pkt_count_system.iocache.mem_side::total 346526 # Packet count per connected master and slave (bytes) 776system.membus.pkt_count::total 5818953 # Packet count per connected master and slave (bytes)
|
776system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 777system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
| 777system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) 778system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
778system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) 779system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) 780system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) 781system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) 782system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) 783system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes)
| 779system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13452 # Cumulative packet size per connected master and slave (bytes) 780system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 174471520 # Cumulative packet size per connected master and slave (bytes) 781system.membus.pkt_size_system.cpu.l2cache.mem_side::total 174640714 # Cumulative packet size per connected master and slave (bytes) 782system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391488 # Cumulative packet size per connected master and slave (bytes) 783system.membus.pkt_size_system.iocache.mem_side::total 7391488 # Cumulative packet size per connected master and slave (bytes) 784system.membus.pkt_size::total 182032202 # Cumulative packet size per connected master and slave (bytes)
|
784system.membus.snoops 0 # Total snoops (count) 785system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
| 785system.membus.snoops 0 # Total snoops (count) 786system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
786system.membus.snoop_fanout::samples 3888979 # Request fanout histogram 787system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram 788system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram
| 787system.membus.snoop_fanout::samples 3808691 # Request fanout histogram 788system.membus.snoop_fanout::mean 0.010569 # Request fanout histogram 789system.membus.snoop_fanout::stdev 0.102262 # Request fanout histogram
|
789system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
| 790system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
790system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram 791system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram
| 791system.membus.snoop_fanout::0 3768436 98.94% 98.94% # Request fanout histogram 792system.membus.snoop_fanout::1 40255 1.06% 100.00% # Request fanout histogram
|
792system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 793system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 794system.membus.snoop_fanout::min_value 0 # Request fanout histogram 795system.membus.snoop_fanout::max_value 1 # Request fanout histogram
| 793system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 794system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 795system.membus.snoop_fanout::min_value 0 # Request fanout histogram 796system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
796system.membus.snoop_fanout::total 3888979 # Request fanout histogram 797system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 798system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 799system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 800system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 801system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 802system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 803system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 797system.membus.snoop_fanout::total 3808691 # Request fanout histogram 798system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 799system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 800system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 801system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 802system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 803system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 804system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
804system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 805system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 806system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 807system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 808system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 809system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
| 805system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 806system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 807system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 808system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 809system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 810system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
810system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 811system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 811system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 812system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
812system.realview.ethernet.txBytes 966 # Bytes Transmitted 813system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 814system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 815system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 816system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 817system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 818system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 819system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 820system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
| 813system.realview.ethernet.txBytes 966 # Bytes Transmitted 814system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 815system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 816system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 817system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 818system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 819system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 820system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 821system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
821system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
| 822system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
|
822system.realview.ethernet.totPackets 3 # Total Packets 823system.realview.ethernet.totBytes 966 # Total Bytes 824system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
| 823system.realview.ethernet.totPackets 3 # Total Packets 824system.realview.ethernet.totBytes 966 # Total Bytes 825system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
825system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
| 826system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
|
826system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 827system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 828system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 829system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 830system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 831system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 832system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 833system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 834system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 835system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 836system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 837system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 838system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 839system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 840system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 841system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 842system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 843system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 844system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 845system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 846system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 847system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 848system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 849system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 850system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 851system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 852system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 853system.realview.ethernet.droppedPackets 0 # number of packets dropped
| 827system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 828system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 829system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 830system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 831system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 832system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 833system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 834system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 835system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 836system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 837system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 838system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 839system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 840system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 841system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 842system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 843system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 844system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 845system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 846system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 847system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 848system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 849system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 850system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 851system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 852system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 853system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 854system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
854system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 855system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 856system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 857system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 858system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 859system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 860system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 855system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 856system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 857system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 858system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 859system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 860system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 861system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
861system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 862system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 863system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 864system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
| 862system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 863system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 864system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 865system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
865system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 866system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 867system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 868system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 869system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 870system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 871system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 872system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 873system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 874system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 875system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states 876system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
| 866system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 867system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 868system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 869system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 870system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 871system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 872system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 873system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 874system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 875system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 876system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states 877system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states
|
877 878---------- End Simulation Statistics ----------
| 878 879---------- End Simulation Statistics ----------
|