1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.111167 # Number of seconds simulated
4sim_ticks 51111167216500 # Number of ticks simulated
5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.111167 # Number of seconds simulated
4sim_ticks 51111167216500 # Number of ticks simulated
5final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1142928 # Simulator instruction rate (inst/s)
8host_op_rate 1343188 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59474849541 # Simulator tick rate (ticks/s)
10host_mem_usage 670860 # Number of bytes of host memory used
11host_seconds 859.37 # Real time elapsed on the host
| 7host_inst_rate 1675396 # Simulator instruction rate (inst/s)
8host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 87182982694 # Simulator tick rate (ticks/s)
10host_mem_usage 718784 # Number of bytes of host memory used
11host_seconds 586.25 # Real time elapsed on the host
|
12sim_insts 982203438 # Number of instructions simulated
13sim_ops 1154301153 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
| 12sim_insts 982203438 # Number of instructions simulated
13sim_ops 1154301153 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
|
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
16system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory
21system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
26system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s)
| 17system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory
21system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory
22system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory
26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
27system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory
28system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory
32system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory
35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s)
|
| 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
54system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
55system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
56system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
57system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
58system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
59system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
60system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
61system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
62system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
63system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
64system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
65system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
66system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
67system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
68system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
69system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
| 56system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
57system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
58system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
59system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
60system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
61system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
62system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
63system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
64system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
65system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
66system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
67system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
68system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
69system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
70system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
71system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
| 72system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
73system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
74system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
70system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
71system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
72system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
73system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
74system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
75system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
76system.cpu_clk_domain.clock 500 # Clock period in ticks
| 75system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
76system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
77system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
78system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
79system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
80system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
81system.cpu_clk_domain.clock 500 # Clock period in ticks
|
| 82system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
77system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
78system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
79system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
85system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
86system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
87system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
88system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
89system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
90system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
91system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
92system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
93system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
94system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
95system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
96system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
97system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
98system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
99system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
100system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
101system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
102system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
103system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
104system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
105system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 83system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
87system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
88system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
89system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
90system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
91system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
92system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
93system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
94system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
95system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
96system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
97system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
98system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
99system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
100system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
101system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
102system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
103system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
104system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
105system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
106system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
107system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
108system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
109system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
110system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
111system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
| 112system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
106system.cpu.dtb.walker.walks 266586 # Table walker walks requested
107system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
108system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
109system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency
110system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency
111system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
112system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
113system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
114system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated
115system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated
116system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated
117system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst
118system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
119system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst
120system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst
121system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
122system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst
123system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst
124system.cpu.dtb.inst_hits 0 # ITB inst hits
125system.cpu.dtb.inst_misses 0 # ITB inst misses
126system.cpu.dtb.read_hits 183545125 # DTB read hits
127system.cpu.dtb.read_misses 195347 # DTB read misses
128system.cpu.dtb.write_hits 167774776 # DTB write hits
129system.cpu.dtb.write_misses 71239 # DTB write misses
130system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
131system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
132system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
133system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
134system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB
135system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
136system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
137system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
138system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
139system.cpu.dtb.read_accesses 183740472 # DTB read accesses
140system.cpu.dtb.write_accesses 167846015 # DTB write accesses
141system.cpu.dtb.inst_accesses 0 # ITB inst accesses
142system.cpu.dtb.hits 351319901 # DTB hits
143system.cpu.dtb.misses 266586 # DTB misses
144system.cpu.dtb.accesses 351586487 # DTB accesses
| 113system.cpu.dtb.walker.walks 266586 # Table walker walks requested
114system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
115system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
116system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency
117system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency
118system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
119system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
120system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
121system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated
122system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated
123system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated
124system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst
125system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst
127system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst
128system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst
130system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst
131system.cpu.dtb.inst_hits 0 # ITB inst hits
132system.cpu.dtb.inst_misses 0 # ITB inst misses
133system.cpu.dtb.read_hits 183545125 # DTB read hits
134system.cpu.dtb.read_misses 195347 # DTB read misses
135system.cpu.dtb.write_hits 167774776 # DTB write hits
136system.cpu.dtb.write_misses 71239 # DTB write misses
137system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
138system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
139system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
140system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
141system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB
142system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
143system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
144system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
145system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
146system.cpu.dtb.read_accesses 183740472 # DTB read accesses
147system.cpu.dtb.write_accesses 167846015 # DTB write accesses
148system.cpu.dtb.inst_accesses 0 # ITB inst accesses
149system.cpu.dtb.hits 351319901 # DTB hits
150system.cpu.dtb.misses 266586 # DTB misses
151system.cpu.dtb.accesses 351586487 # DTB accesses
|
| 152system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
145system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
149system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
153system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
154system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
155system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
156system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
157system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
158system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
159system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
160system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
161system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
162system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
163system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
164system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
165system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
166system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
167system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
168system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
169system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
170system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
171system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
172system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
173system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 153system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
157system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
158system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
159system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
160system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
161system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
162system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
163system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
164system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
165system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
166system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
167system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
168system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
169system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
170system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
171system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
172system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
173system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
174system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
175system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
176system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
177system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
178system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
179system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
180system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
181system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
| 182system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
174system.cpu.itb.walker.walks 126834 # Table walker walks requested
175system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors
176system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency
177system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency
178system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency
179system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
180system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
181system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
182system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated
183system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated
184system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated
185system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
186system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst
187system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst
188system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
189system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst
190system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst
191system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst
192system.cpu.itb.inst_hits 982680284 # ITB inst hits
193system.cpu.itb.inst_misses 126834 # ITB inst misses
194system.cpu.itb.read_hits 0 # DTB read hits
195system.cpu.itb.read_misses 0 # DTB read misses
196system.cpu.itb.write_hits 0 # DTB write hits
197system.cpu.itb.write_misses 0 # DTB write misses
198system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
199system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
200system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
201system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
202system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB
203system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
204system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
205system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
206system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
207system.cpu.itb.read_accesses 0 # DTB read accesses
208system.cpu.itb.write_accesses 0 # DTB write accesses
209system.cpu.itb.inst_accesses 982807118 # ITB inst accesses
210system.cpu.itb.hits 982680284 # DTB hits
211system.cpu.itb.misses 126834 # DTB misses
212system.cpu.itb.accesses 982807118 # DTB accesses
| 183system.cpu.itb.walker.walks 126834 # Table walker walks requested
184system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors
185system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency
186system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency
187system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency
188system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
189system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
190system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
191system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated
192system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated
193system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated
194system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
195system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst
196system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst
197system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
198system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst
199system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst
200system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst
201system.cpu.itb.inst_hits 982680284 # ITB inst hits
202system.cpu.itb.inst_misses 126834 # ITB inst misses
203system.cpu.itb.read_hits 0 # DTB read hits
204system.cpu.itb.read_misses 0 # DTB read misses
205system.cpu.itb.write_hits 0 # DTB write hits
206system.cpu.itb.write_misses 0 # DTB write misses
207system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
208system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
209system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
210system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
211system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB
212system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
213system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
214system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
215system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
216system.cpu.itb.read_accesses 0 # DTB read accesses
217system.cpu.itb.write_accesses 0 # DTB write accesses
218system.cpu.itb.inst_accesses 982807118 # ITB inst accesses
219system.cpu.itb.hits 982680284 # DTB hits
220system.cpu.itb.misses 126834 # DTB misses
221system.cpu.itb.accesses 982807118 # DTB accesses
|
| 222system.cpu.numPwrStateTransitions 33550 # Number of power state transitions
223system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state
224system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state
225system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state
226system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state
227system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state
228system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
229system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
230system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
231system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
232system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state
233system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
234system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
235system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
236system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
237system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
238system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state
239system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state
240system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states
241system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states
|
213system.cpu.numCycles 102222351209 # number of cpu cycles simulated
214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
216system.cpu.kern.inst.arm 0 # number of arm instructions executed
217system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
218system.cpu.committedInsts 982203438 # Number of instructions committed
219system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed
220system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses
221system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses
222system.cpu.num_func_calls 56834581 # number of times a function call or return occured
223system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls
224system.cpu.num_int_insts 1057882257 # number of integer instructions
225system.cpu.num_fp_insts 881349 # number of float instructions
226system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read
227system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written
228system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read
229system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written
230system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read
231system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written
232system.cpu.num_mem_refs 351539335 # number of memory refs
233system.cpu.num_load_insts 183712430 # Number of load instructions
234system.cpu.num_store_insts 167826905 # Number of store instructions
235system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles
236system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles
237system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles
238system.cpu.idle_fraction 0.988702 # Percentage of idle cycles
239system.cpu.Branches 219534054 # Number of branches fetched
240system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
241system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction
242system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction
243system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction
244system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
245system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
246system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction
247system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction
248system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction
249system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction
250system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction
251system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction
252system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction
253system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction
254system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction
255system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction
256system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction
257system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction
258system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction
259system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction
260system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction
261system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction
262system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction
263system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction
264system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction
265system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction
266system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction
267system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction
268system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction
269system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction
270system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction
271system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction
272system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
273system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
274system.cpu.op_class::total 1154935820 # Class of executed instruction
| 242system.cpu.numCycles 102222351209 # number of cpu cycles simulated
243system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
244system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
245system.cpu.kern.inst.arm 0 # number of arm instructions executed
246system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
247system.cpu.committedInsts 982203438 # Number of instructions committed
248system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed
249system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses
250system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses
251system.cpu.num_func_calls 56834581 # number of times a function call or return occured
252system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls
253system.cpu.num_int_insts 1057882257 # number of integer instructions
254system.cpu.num_fp_insts 881349 # number of float instructions
255system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read
256system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written
257system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read
258system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written
259system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read
260system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written
261system.cpu.num_mem_refs 351539335 # number of memory refs
262system.cpu.num_load_insts 183712430 # Number of load instructions
263system.cpu.num_store_insts 167826905 # Number of store instructions
264system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles
265system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles
266system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles
267system.cpu.idle_fraction 0.988702 # Percentage of idle cycles
268system.cpu.Branches 219534054 # Number of branches fetched
269system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
270system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction
271system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction
272system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction
273system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
274system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
275system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction
276system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction
277system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction
278system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction
279system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction
280system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction
281system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction
282system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction
283system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction
284system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction
285system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction
286system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction
287system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction
288system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction
289system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction
290system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction
291system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction
292system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction
293system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction
294system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction
295system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction
296system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction
297system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction
298system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction
299system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction
300system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction
301system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
302system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
303system.cpu.op_class::total 1154935820 # Class of executed instruction
|
| 304system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
275system.cpu.dcache.tags.replacements 11606642 # number of replacements
276system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
277system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks.
278system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks.
279system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks.
280system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
281system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
282system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
283system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
284system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
285system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
286system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
287system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
288system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
289system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses
290system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses
| 305system.cpu.dcache.tags.replacements 11606642 # number of replacements
306system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
307system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks.
308system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks.
309system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks.
310system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
311system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
312system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
313system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
314system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
315system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
316system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
317system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
318system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
319system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses
320system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses
|
| 321system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
291system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits
292system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits
293system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits
294system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits
295system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits
296system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits
297system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits
298system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits
299system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits
300system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits
301system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
302system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
303system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits
304system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits
305system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits
306system.cpu.dcache.overall_hits::total 330945053 # number of overall hits
307system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses
308system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses
309system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses
310system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses
311system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses
312system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses
313system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses
314system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses
315system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses
316system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses
317system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
318system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
319system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses
320system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses
321system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses
322system.cpu.dcache.overall_misses::total 11404487 # number of overall misses
323system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses)
324system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
325system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses)
326system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses)
327system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses)
328system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses)
329system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses)
330system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses)
331system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses)
332system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses)
333system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
334system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
335system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses
336system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
337system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses
338system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses
339system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses
340system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses
341system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
342system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
343system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses
344system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses
345system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses
346system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses
347system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses
348system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
349system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
350system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
351system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses
352system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
353system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses
354system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
355system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
356system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
357system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
358system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
359system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
360system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
361system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
362system.cpu.dcache.writebacks::total 8917390 # number of writebacks
| 322system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits
323system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits
324system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits
325system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits
326system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits
327system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits
328system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits
329system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits
330system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits
331system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits
332system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
333system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
334system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits
335system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits
336system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits
337system.cpu.dcache.overall_hits::total 330945053 # number of overall hits
338system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses
339system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses
340system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses
341system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses
342system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses
343system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses
344system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses
345system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses
346system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses
347system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses
348system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
349system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
350system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses
351system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses
352system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses
353system.cpu.dcache.overall_misses::total 11404487 # number of overall misses
354system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses)
355system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
356system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses)
357system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses)
358system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses)
359system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses)
360system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses)
361system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses)
362system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses)
363system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses)
364system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
365system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
366system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses
367system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
368system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses
369system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses
370system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses
371system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses
372system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
373system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
374system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses
375system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses
376system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses
377system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses
378system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses
379system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
380system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
381system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
382system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses
383system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
384system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses
385system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
386system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
387system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
388system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
389system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
390system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
391system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
392system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
393system.cpu.dcache.writebacks::total 8917390 # number of writebacks
|
| 394system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
363system.cpu.icache.tags.replacements 14265253 # number of replacements
364system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
365system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
366system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks.
367system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks.
368system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
369system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
370system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
371system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
372system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
373system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
374system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
375system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
376system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
377system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses
378system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses
| 395system.cpu.icache.tags.replacements 14265253 # number of replacements
396system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
397system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
398system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks.
399system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks.
400system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
401system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
402system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
403system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
404system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
405system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
406system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
407system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
408system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
409system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses
410system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses
|
| 411system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
379system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits
380system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits
381system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits
382system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits
383system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits
384system.cpu.icache.overall_hits::total 968529210 # number of overall hits
385system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses
386system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses
387system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses
388system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses
389system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses
390system.cpu.icache.overall_misses::total 14265770 # number of overall misses
391system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses)
392system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses)
393system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses
394system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses
395system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses
396system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses
397system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses
398system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses
399system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses
400system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses
401system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses
402system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses
403system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
404system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
405system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
406system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
407system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
408system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
409system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
410system.cpu.icache.writebacks::total 14265253 # number of writebacks
| 412system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits
413system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits
414system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits
415system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits
416system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits
417system.cpu.icache.overall_hits::total 968529210 # number of overall hits
418system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses
419system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses
420system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses
421system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses
422system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses
423system.cpu.icache.overall_misses::total 14265770 # number of overall misses
424system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses)
425system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses)
426system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses
427system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses
428system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses
429system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses
430system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses
431system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses
432system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses
433system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses
434system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses
435system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses
436system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
437system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
438system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
439system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
440system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
441system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
442system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
443system.cpu.icache.writebacks::total 14265253 # number of writebacks
|
| 444system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
411system.cpu.l2cache.tags.replacements 1725806 # number of replacements
412system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
413system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
414system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks.
415system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks.
416system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
417system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor
418system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor
419system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor
420system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor
421system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor
422system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy
423system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy
424system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy
425system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy
426system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy
427system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
428system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id
429system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id
430system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id
431system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
432system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id
433system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id
434system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id
435system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id
436system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id
437system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
438system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses
439system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses
| 445system.cpu.l2cache.tags.replacements 1725806 # number of replacements
446system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
447system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
448system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks.
449system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks.
450system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
451system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor
452system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor
453system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor
454system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor
455system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor
456system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy
457system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy
458system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy
459system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy
460system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy
461system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
462system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id
463system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id
464system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id
465system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
466system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id
467system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id
468system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id
469system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id
470system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id
471system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
472system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses
473system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses
|
| 474system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
440system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits
441system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
442system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits
443system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits
444system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits
445system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits
446system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits
447system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits
448system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits
449system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits
450system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits
451system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits
452system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits
453system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits
454system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits
455system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits
456system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits
457system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits
458system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits
459system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits
460system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits
461system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits
462system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits
463system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits
464system.cpu.l2cache.overall_hits::cpu.inst 14182764 # number of overall hits
465system.cpu.l2cache.overall_hits::cpu.data 9188700 # number of overall hits
466system.cpu.l2cache.overall_hits::total 24136508 # number of overall hits
467system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses
468system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses
469system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses
470system.cpu.l2cache.UpgradeReq_misses::cpu.data 39924 # number of UpgradeReq misses
471system.cpu.l2cache.UpgradeReq_misses::total 39924 # number of UpgradeReq misses
472system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
473system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
474system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses
475system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses
476system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses
477system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses
478system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses
479system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses
480system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses
481system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses
482system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses
483system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses
484system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses
485system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses
486system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses
487system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses
488system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses
489system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses
490system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses
491system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses
492system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses)
493system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses)
494system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses)
495system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses)
496system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses)
497system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses)
498system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses)
499system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses)
500system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses)
501system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
502system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
503system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses)
504system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses)
506system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses)
507system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses)
508system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses)
509system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses)
510system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses)
511system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses
512system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses
513system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses
514system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses
516system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses
520system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses
522system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses
523system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
524system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses
525system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses
526system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
527system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
528system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses
529system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses
530system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses
531system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses
532system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses
533system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses
534system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses
535system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses
536system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses
537system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses
538system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses
539system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses
540system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses
541system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses
542system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses
543system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses
544system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses
545system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses
546system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
547system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
548system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
549system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
550system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
551system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
552system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks
553system.cpu.l2cache.writebacks::total 1507080 # number of writebacks
554system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter.
555system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data.
556system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
557system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
558system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
559system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
| 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits
476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
477system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits
478system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits
479system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits
480system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits
481system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits
482system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits
483system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits
484system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits
485system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits
486system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits
487system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits
488system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits
489system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits
490system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits
491system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits
492system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits
493system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits
494system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits
495system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits
496system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits
497system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits
498system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits
499system.cpu.l2cache.overall_hits::cpu.inst 14182764 # number of overall hits
500system.cpu.l2cache.overall_hits::cpu.data 9188700 # number of overall hits
501system.cpu.l2cache.overall_hits::total 24136508 # number of overall hits
502system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses
503system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses
504system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses
505system.cpu.l2cache.UpgradeReq_misses::cpu.data 39924 # number of UpgradeReq misses
506system.cpu.l2cache.UpgradeReq_misses::total 39924 # number of UpgradeReq misses
507system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
508system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
509system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses
510system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses
511system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses
512system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses
513system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses
514system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses
515system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses
516system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses
517system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses
518system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses
519system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses
520system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses
521system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses
522system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses
523system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses
524system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses
525system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses
526system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses
527system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses)
528system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses)
529system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses)
530system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses)
531system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses)
532system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses)
533system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses)
534system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses)
535system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses)
536system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
537system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
538system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses)
539system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses)
540system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses)
541system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses)
542system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses)
543system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses)
544system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses)
545system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses)
546system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses
547system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses
548system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses
549system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses
550system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses
551system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses
552system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses
553system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses
554system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses
555system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses
556system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses
557system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses
558system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
559system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses
560system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses
561system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
562system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
563system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses
564system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses
565system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses
566system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses
567system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses
568system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses
569system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses
570system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses
571system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses
572system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses
573system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses
574system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses
575system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses
576system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses
577system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses
578system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses
579system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses
580system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses
581system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
582system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
583system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
584system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
585system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
586system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
587system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks
588system.cpu.l2cache.writebacks::total 1507080 # number of writebacks
589system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter.
590system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data.
591system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
592system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
593system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
594system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
| 595system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
560system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution
561system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution
562system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
563system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
564system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution
565system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
569system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution
570system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution
571system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution
572system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution
573system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution
574system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution
576system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes)
577system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes)
578system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes)
579system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes)
580system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes)
582system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes)
583system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes)
584system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes)
585system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes)
586system.cpu.toL2Bus.snoops 1957577 # Total snoops (count)
587system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram
588system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram
589system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram
590system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
591system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram
592system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram
593system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
594system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
595system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
596system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
597system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram
| 596system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution
598system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
599system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
600system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution
610system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution
611system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution
612system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes)
613system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes)
614system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes)
615system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes)
616system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes)
617system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes)
618system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes)
619system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes)
620system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes)
621system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes)
622system.cpu.toL2Bus.snoops 1957577 # Total snoops (count)
623system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram
624system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram
625system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram
626system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
627system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram
628system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram
629system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
630system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
631system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
632system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
633system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram
|
| 634system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
598system.iobus.trans_dist::ReadReq 40242 # Transaction distribution
599system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
600system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
601system.iobus.trans_dist::WriteResp 136515 # Transaction distribution
602system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
603system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
604system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
605system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
606system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
607system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
608system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
609system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
610system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
611system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
612system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
613system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
614system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
615system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
616system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
617system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
618system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
619system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
620system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes)
621system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
622system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
623system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
624system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
625system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
626system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
627system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
628system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
629system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
630system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
631system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
632system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
633system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
634system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
635system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
636system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
637system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
638system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
639system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes)
| 635system.iobus.trans_dist::ReadReq 40242 # Transaction distribution
636system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
637system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
638system.iobus.trans_dist::WriteResp 136515 # Transaction distribution
639system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
640system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
641system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
642system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
643system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
644system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
645system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
646system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
647system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
648system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
649system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
650system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
651system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
652system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
653system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
654system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
655system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
656system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
657system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes)
658system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
659system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
660system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
661system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
662system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
663system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
664system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
665system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
666system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
667system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
668system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
669system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
670system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
671system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
672system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
673system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
674system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
675system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
676system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes)
|
| 677system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
640system.iocache.tags.replacements 115459 # number of replacements
641system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
642system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
643system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
644system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
645system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
646system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
647system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
648system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
649system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
650system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
651system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
652system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
653system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
654system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
655system.iocache.tags.data_accesses 1039650 # Number of data accesses
| 678system.iocache.tags.replacements 115459 # number of replacements
679system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
680system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
681system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
682system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
683system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
684system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
685system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
686system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
687system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
688system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
689system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
690system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
691system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
692system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
693system.iocache.tags.data_accesses 1039650 # Number of data accesses
|
| 694system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
656system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
657system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
658system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
659system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
660system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
661system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
662system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
663system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
664system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses
665system.iocache.demand_misses::total 115517 # number of demand (read+write) misses
666system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
667system.iocache.overall_misses::realview.ide 115477 # number of overall misses
668system.iocache.overall_misses::total 115517 # number of overall misses
669system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
670system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
671system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
672system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
673system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
674system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
675system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
676system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
677system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses
678system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses
679system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
680system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses
681system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses
682system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
683system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
684system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
685system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
686system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
687system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
688system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
689system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
690system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
691system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
692system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
693system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
694system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
695system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
696system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
697system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
698system.iocache.blocked::no_targets 0 # number of cycles access was blocked
699system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
700system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
701system.iocache.writebacks::writebacks 106631 # number of writebacks
702system.iocache.writebacks::total 106631 # number of writebacks
| 695system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
696system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
697system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
698system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
699system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
700system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
701system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
702system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
703system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses
704system.iocache.demand_misses::total 115517 # number of demand (read+write) misses
705system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
706system.iocache.overall_misses::realview.ide 115477 # number of overall misses
707system.iocache.overall_misses::total 115517 # number of overall misses
708system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
709system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
710system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
711system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
712system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
713system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
714system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
715system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
716system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses
717system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses
718system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
719system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses
720system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses
721system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
722system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
723system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
724system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
725system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
726system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
727system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
728system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
729system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
730system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
731system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
732system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
733system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
734system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
735system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
736system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
737system.iocache.blocked::no_targets 0 # number of cycles access was blocked
738system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
739system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
740system.iocache.writebacks::writebacks 106631 # number of writebacks
741system.iocache.writebacks::total 106631 # number of writebacks
|
| 742system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
703system.membus.trans_dist::ReadReq 76679 # Transaction distribution
704system.membus.trans_dist::ReadResp 524946 # Transaction distribution
705system.membus.trans_dist::WriteReq 33606 # Transaction distribution
706system.membus.trans_dist::WriteResp 33606 # Transaction distribution
707system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution
708system.membus.trans_dist::CleanEvict 226320 # Transaction distribution
709system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution
710system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
711system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution
712system.membus.trans_dist::ReadExReq 827042 # Transaction distribution
713system.membus.trans_dist::ReadExResp 827042 # Transaction distribution
714system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution
715system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution
716system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution
717system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
718system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
719system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
720system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes)
721system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes)
722system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes)
723system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes)
724system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes)
725system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
726system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
727system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
728system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes)
729system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes)
730system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes)
731system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes)
732system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes)
733system.membus.snoops 0 # Total snoops (count)
734system.membus.snoop_fanout::samples 3924997 # Request fanout histogram
735system.membus.snoop_fanout::mean 1 # Request fanout histogram
736system.membus.snoop_fanout::stdev 0 # Request fanout histogram
737system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
738system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
739system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram
740system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
741system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
742system.membus.snoop_fanout::min_value 1 # Request fanout histogram
743system.membus.snoop_fanout::max_value 1 # Request fanout histogram
744system.membus.snoop_fanout::total 3924997 # Request fanout histogram
| 743system.membus.trans_dist::ReadReq 76679 # Transaction distribution
744system.membus.trans_dist::ReadResp 524946 # Transaction distribution
745system.membus.trans_dist::WriteReq 33606 # Transaction distribution
746system.membus.trans_dist::WriteResp 33606 # Transaction distribution
747system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution
748system.membus.trans_dist::CleanEvict 226320 # Transaction distribution
749system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution
750system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
751system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution
752system.membus.trans_dist::ReadExReq 827042 # Transaction distribution
753system.membus.trans_dist::ReadExResp 827042 # Transaction distribution
754system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution
755system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution
756system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution
757system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
758system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
759system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
760system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes)
761system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes)
762system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes)
763system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes)
764system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes)
765system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
766system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
767system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
768system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes)
769system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes)
770system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes)
771system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes)
772system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes)
773system.membus.snoops 0 # Total snoops (count)
774system.membus.snoop_fanout::samples 3924997 # Request fanout histogram
775system.membus.snoop_fanout::mean 1 # Request fanout histogram
776system.membus.snoop_fanout::stdev 0 # Request fanout histogram
777system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
778system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
779system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram
780system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
781system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
782system.membus.snoop_fanout::min_value 1 # Request fanout histogram
783system.membus.snoop_fanout::max_value 1 # Request fanout histogram
784system.membus.snoop_fanout::total 3924997 # Request fanout histogram
|
| 785system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
786system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
787system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
788system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
789system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
790system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
791system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
745system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
746system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
747system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
748system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
749system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
750system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
| 792system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
793system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
794system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
795system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
796system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
797system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
| 798system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
799system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
751system.realview.ethernet.txBytes 966 # Bytes Transmitted
752system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
753system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
754system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
755system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
756system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
757system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
758system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
759system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
760system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
761system.realview.ethernet.totPackets 3 # Total Packets
762system.realview.ethernet.totBytes 966 # Total Bytes
763system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
764system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
765system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
766system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
767system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
768system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
769system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
770system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
771system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
772system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
773system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
774system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
775system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
776system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
777system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
778system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
779system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
780system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
781system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
782system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
783system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
784system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
785system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
786system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
787system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
788system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
789system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
790system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
791system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
792system.realview.ethernet.droppedPackets 0 # number of packets dropped
| 800system.realview.ethernet.txBytes 966 # Bytes Transmitted
801system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
802system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
803system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
804system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
805system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
806system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
807system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
808system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
809system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
810system.realview.ethernet.totPackets 3 # Total Packets
811system.realview.ethernet.totBytes 966 # Total Bytes
812system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
813system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
814system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
815system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
816system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
817system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
818system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
819system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
820system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
821system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
822system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
823system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
824system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
825system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
826system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
827system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
828system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
829system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
830system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
831system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
832system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
833system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
834system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
835system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
836system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
837system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
838system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
839system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
840system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
841system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
| 842system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
843system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
844system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
845system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
846system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
847system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
848system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
793system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
794system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
795system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
796system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
| 849system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
850system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
851system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
852system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
| 853system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
854system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
855system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
856system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
857system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
858system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
859system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
860system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
861system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
862system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
863system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
864system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
797
798---------- End Simulation Statistics ----------
| 865
866---------- End Simulation Statistics ----------
|