| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.216815 # Number of seconds simulated 4sim_ticks 47216814802000 # Number of ticks simulated 5final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.216815 # Number of seconds simulated 4sim_ticks 47216814802000 # Number of ticks simulated 5final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1563637 # Simulator instruction rate (inst/s) 8host_op_rate 1839381 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75563871924 # Simulator tick rate (ticks/s) 10host_mem_usage 737620 # Number of bytes of host memory used 11host_seconds 624.86 # Real time elapsed on the host | 7host_inst_rate 917426 # Simulator instruction rate (inst/s) 8host_op_rate 1079212 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44335256452 # Simulator tick rate (ticks/s) 10host_mem_usage 692848 # Number of bytes of host memory used 11host_seconds 1064.99 # Real time elapsed on the host |
| 12sim_insts 977053655 # Number of instructions simulated 13sim_ops 1149354696 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory --- 144 unchanged lines hidden (view full) --- 164system.cpu0.dtb.read_hits 91801710 # DTB read hits 165system.cpu0.dtb.read_misses 88193 # DTB read misses 166system.cpu0.dtb.write_hits 84999619 # DTB write hits 167system.cpu0.dtb.write_misses 36227 # DTB write misses 168system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 169system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 170system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 171system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 12sim_insts 977053655 # Number of instructions simulated 13sim_ops 1149354696 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory --- 144 unchanged lines hidden (view full) --- 164system.cpu0.dtb.read_hits 91801710 # DTB read hits 165system.cpu0.dtb.read_misses 88193 # DTB read misses 166system.cpu0.dtb.write_hits 84999619 # DTB write hits 167system.cpu0.dtb.write_misses 36227 # DTB write misses 168system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 169system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 170system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 171system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 172system.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB | 172system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB |
| 173system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch 175system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 177system.cpu0.dtb.read_accesses 91889903 # DTB read accesses 178system.cpu0.dtb.write_accesses 85035846 # DTB write accesses 179system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 180system.cpu0.dtb.hits 176801329 # DTB hits --- 53 unchanged lines hidden (view full) --- 234system.cpu0.itb.read_hits 0 # DTB read hits 235system.cpu0.itb.read_misses 0 # DTB read misses 236system.cpu0.itb.write_hits 0 # DTB write hits 237system.cpu0.itb.write_misses 0 # DTB write misses 238system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 239system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 240system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 241system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 173system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch 175system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 177system.cpu0.dtb.read_accesses 91889903 # DTB read accesses 178system.cpu0.dtb.write_accesses 85035846 # DTB write accesses 179system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 180system.cpu0.dtb.hits 176801329 # DTB hits --- 53 unchanged lines hidden (view full) --- 234system.cpu0.itb.read_hits 0 # DTB read hits 235system.cpu0.itb.read_misses 0 # DTB read misses 236system.cpu0.itb.write_hits 0 # DTB write hits 237system.cpu0.itb.write_misses 0 # DTB write misses 238system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 239system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 240system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 241system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 242system.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB | 242system.cpu0.itb.flush_entries 25053 # Number of entries that have been flushed from TLB |
| 243system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 244system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 245system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 246system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 247system.cpu0.itb.read_accesses 0 # DTB read accesses 248system.cpu0.itb.write_accesses 0 # DTB write accesses 249system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 250system.cpu0.itb.hits 493637993 # DTB hits --- 469 unchanged lines hidden (view full) --- 720system.cpu1.dtb.read_hits 91325952 # DTB read hits 721system.cpu1.dtb.read_misses 111931 # DTB read misses 722system.cpu1.dtb.write_hits 82141676 # DTB write hits 723system.cpu1.dtb.write_misses 32424 # DTB write misses 724system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 725system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 726system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 727system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 243system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 244system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 245system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 246system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 247system.cpu0.itb.read_accesses 0 # DTB read accesses 248system.cpu0.itb.write_accesses 0 # DTB write accesses 249system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 250system.cpu0.itb.hits 493637993 # DTB hits --- 469 unchanged lines hidden (view full) --- 720system.cpu1.dtb.read_hits 91325952 # DTB read hits 721system.cpu1.dtb.read_misses 111931 # DTB read misses 722system.cpu1.dtb.write_hits 82141676 # DTB write hits 723system.cpu1.dtb.write_misses 32424 # DTB write misses 724system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 725system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 726system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 727system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 728system.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB | 728system.cpu1.dtb.flush_entries 44794 # Number of entries that have been flushed from TLB |
| 729system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 730system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch 731system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 732system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 733system.cpu1.dtb.read_accesses 91437883 # DTB read accesses 734system.cpu1.dtb.write_accesses 82174100 # DTB write accesses 735system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 736system.cpu1.dtb.hits 173467628 # DTB hits --- 53 unchanged lines hidden (view full) --- 790system.cpu1.itb.read_hits 0 # DTB read hits 791system.cpu1.itb.read_misses 0 # DTB read misses 792system.cpu1.itb.write_hits 0 # DTB write hits 793system.cpu1.itb.write_misses 0 # DTB write misses 794system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 795system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 796system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 797system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 729system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 730system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch 731system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 732system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 733system.cpu1.dtb.read_accesses 91437883 # DTB read accesses 734system.cpu1.dtb.write_accesses 82174100 # DTB write accesses 735system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 736system.cpu1.dtb.hits 173467628 # DTB hits --- 53 unchanged lines hidden (view full) --- 790system.cpu1.itb.read_hits 0 # DTB read hits 791system.cpu1.itb.read_misses 0 # DTB read misses 792system.cpu1.itb.write_hits 0 # DTB write hits 793system.cpu1.itb.write_misses 0 # DTB write misses 794system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 795system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 796system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 797system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 798system.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB | 798system.cpu1.itb.flush_entries 31448 # Number of entries that have been flushed from TLB |
| 799system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 800system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 801system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 802system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 803system.cpu1.itb.read_accesses 0 # DTB read accesses 804system.cpu1.itb.write_accesses 0 # DTB write accesses 805system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 806system.cpu1.itb.hits 483902380 # DTB hits --- 901 unchanged lines hidden --- | 799system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 800system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 801system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 802system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 803system.cpu1.itb.read_accesses 0 # DTB read accesses 804system.cpu1.itb.write_accesses 0 # DTB write accesses 805system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 806system.cpu1.itb.hits 483902380 # DTB hits --- 901 unchanged lines hidden --- |