| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.216815 # Number of seconds simulated 4sim_ticks 47216814802000 # Number of ticks simulated 5final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.216815 # Number of seconds simulated 4sim_ticks 47216814802000 # Number of ticks simulated 5final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1112312 # Simulator instruction rate (inst/s) 8host_op_rate 1308465 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53753255119 # Simulator tick rate (ticks/s) 10host_mem_usage 687512 # Number of bytes of host memory used 11host_seconds 878.40 # Real time elapsed on the host | 7host_inst_rate 1563637 # Simulator instruction rate (inst/s) 8host_op_rate 1839381 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 75563871924 # Simulator tick rate (ticks/s) 10host_mem_usage 737620 # Number of bytes of host memory used 11host_seconds 624.86 # Real time elapsed on the host |
| 12sim_insts 977053655 # Number of instructions simulated 13sim_ops 1149354696 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 977053655 # Number of instructions simulated 13sim_ops 1149354696 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory --- 43 unchanged lines hidden (view full) --- 67system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory --- 43 unchanged lines hidden (view full) --- 68system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) |
| 76system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 93system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 94system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 95system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 96system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 97system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 98system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 99system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 100system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) | 77system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 80system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 81system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 82system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 83system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 84system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 95system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 96system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 97system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 98system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 99system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 100system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 101system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 102system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) |
| 103system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 104system.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 105system.bridge.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 101system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 102system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 103system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 104system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 105system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 106system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 107system.cpu_clk_domain.clock 500 # Clock period in ticks | 106system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 107system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 108system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 109system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 110system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 111system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 112system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 113system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 108system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 109system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 110system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 111system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 112system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 113system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 114system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 114system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 116system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 117system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 118system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 119system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 120system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 121system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 135system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 136system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 137system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 138system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 140system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 141system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 142system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 143system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 137system.cpu0.dtb.walker.walks 124420 # Table walker walks requested 138system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors 139system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency 140system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency 142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 169system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 170system.cpu0.dtb.read_accesses 91889903 # DTB read accesses 171system.cpu0.dtb.write_accesses 85035846 # DTB write accesses 172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 173system.cpu0.dtb.hits 176801329 # DTB hits 174system.cpu0.dtb.misses 124420 # DTB misses 175system.cpu0.dtb.accesses 176925749 # DTB accesses | 144system.cpu0.dtb.walker.walks 124420 # Table walker walks requested 145system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors 146system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency 147system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency 149system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 150system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 151system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 175system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 177system.cpu0.dtb.read_accesses 91889903 # DTB read accesses 178system.cpu0.dtb.write_accesses 85035846 # DTB write accesses 179system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 180system.cpu0.dtb.hits 176801329 # DTB hits 181system.cpu0.dtb.misses 124420 # DTB misses 182system.cpu0.dtb.accesses 176925749 # DTB accesses |
| 183system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 184system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 185system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 186system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 187system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 188system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 189system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 190system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 191system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 205system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 208system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 209system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 210system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 211system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 212system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 213system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 205system.cpu0.itb.walker.walks 60852 # Table walker walks requested 206system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors 207system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency 208system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency 209system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency 210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 238system.cpu0.itb.read_accesses 0 # DTB read accesses 239system.cpu0.itb.write_accesses 0 # DTB write accesses 240system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 241system.cpu0.itb.hits 493637993 # DTB hits 242system.cpu0.itb.misses 60852 # DTB misses 243system.cpu0.itb.accesses 493698845 # DTB accesses | 214system.cpu0.itb.walker.walks 60852 # Table walker walks requested 215system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors 216system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency 217system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency 218system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency 219system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 220system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 221system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 245system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 246system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 247system.cpu0.itb.read_accesses 0 # DTB read accesses 248system.cpu0.itb.write_accesses 0 # DTB write accesses 249system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 250system.cpu0.itb.hits 493637993 # DTB hits 251system.cpu0.itb.misses 60852 # DTB misses 252system.cpu0.itb.accesses 493698845 # DTB accesses |
| 253system.cpu0.numPwrStateTransitions 26456 # Number of power state transitions 254system.cpu0.pwrStateClkGateDist::samples 13226 # Distribution of time spent in the clock gated state 255system.cpu0.pwrStateClkGateDist::mean 3548051502.510434 # Distribution of time spent in the clock gated state 256system.cpu0.pwrStateClkGateDist::stdev 89670925641.729767 # Distribution of time spent in the clock gated state 257system.cpu0.pwrStateClkGateDist::underflows 3168 23.95% 23.95% # Distribution of time spent in the clock gated state 258system.cpu0.pwrStateClkGateDist::1000-5e+10 10031 75.84% 99.80% # Distribution of time spent in the clock gated state 259system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state 260system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state 261system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 262system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 263system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 264system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state 265system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 266system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 267system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 268system.cpu0.pwrStateClkGateDist::max_value 7470356053852 # Distribution of time spent in the clock gated state 269system.cpu0.pwrStateClkGateDist::total 13226 # Distribution of time spent in the clock gated state 270system.cpu0.pwrStateResidencyTicks::ON 290285629797 # Cumulative time (in ticks) in various power states 271system.cpu0.pwrStateResidencyTicks::CLK_GATED 46926529172203 # Cumulative time (in ticks) in various power states |
|
| 244system.cpu0.numCycles 94433642835 # number of cpu cycles simulated 245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu0.kern.inst.arm 0 # number of arm instructions executed 248system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed 249system.cpu0.committedInsts 493402150 # Number of instructions committed 250system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed 251system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 298system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 299system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 300system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 301system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction 302system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction 303system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 305system.cpu0.op_class::total 580566843 # Class of executed instruction | 272system.cpu0.numCycles 94433642835 # number of cpu cycles simulated 273system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 274system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 275system.cpu0.kern.inst.arm 0 # number of arm instructions executed 276system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed 277system.cpu0.committedInsts 493402150 # Number of instructions committed 278system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed 279system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 326system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 327system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 328system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 329system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction 330system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction 331system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 332system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 333system.cpu0.op_class::total 580566843 # Class of executed instruction |
| 334system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 306system.cpu0.dcache.tags.replacements 6218107 # number of replacements 307system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use 308system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. 311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 320system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses | 335system.cpu0.dcache.tags.replacements 6218107 # number of replacements 336system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use 337system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. 338system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. 339system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. 340system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 341system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor 342system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy 343system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy 344system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 345system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 346system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 347system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 348system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 349system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses 350system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses |
| 351system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 322system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits --- 56 unchanged lines hidden (view full) --- 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks 393system.cpu0.dcache.writebacks::total 6218107 # number of writebacks | 352system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits 353system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits 354system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits 355system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits 356system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits 357system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits 358system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits 359system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits --- 56 unchanged lines hidden (view full) --- 416system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 417system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 418system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 419system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 420system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 421system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 422system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks 423system.cpu0.dcache.writebacks::total 6218107 # number of writebacks |
| 424system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 394system.cpu0.icache.tags.replacements 5488502 # number of replacements 395system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 396system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. 397system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. 398system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. 399system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 400system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 401system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 402system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 403system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 404system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 405system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 406system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 408system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 409system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses 410system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses | 425system.cpu0.icache.tags.replacements 5488502 # number of replacements 426system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 427system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. 428system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. 429system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. 430system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 431system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 432system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 433system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 434system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 435system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 436system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 437system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 438system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 439system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 440system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses 441system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses |
| 442system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 411system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits 412system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits 413system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits 414system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits 415system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits 416system.cpu0.icache.overall_hits::total 488204417 # number of overall hits 417system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses 418system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 435system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 436system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 437system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 440system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 441system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks 442system.cpu0.icache.writebacks::total 5488502 # number of writebacks | 443system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits 444system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits 445system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits 446system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits 447system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits 448system.cpu0.icache.overall_hits::total 488204417 # number of overall hits 449system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses 450system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 467system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 473system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks 474system.cpu0.icache.writebacks::total 5488502 # number of writebacks |
| 475system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 443system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 444system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 445system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 446system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 447system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 448system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 476system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 477system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 478system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 479system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 480system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 481system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 482system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 449system.cpu0.l2cache.tags.replacements 2643580 # number of replacements 450system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use 451system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. 452system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. 453system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. 454system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 455system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor 456system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor --- 11 unchanged lines hidden (view full) --- 468system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id 471system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id 472system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 473system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id 474system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses 475system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses | 483system.cpu0.l2cache.tags.replacements 2643580 # number of replacements 484system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use 485system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. 486system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. 487system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. 488system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 489system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor 490system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor --- 11 unchanged lines hidden (view full) --- 502system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id 503system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id 504system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id 505system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id 506system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 507system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id 508system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses 509system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses |
| 510system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 476system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits 477system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits 478system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits 479system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits 480system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits 481system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits 482system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits 483system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits --- 104 unchanged lines hidden (view full) --- 588system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks 589system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks 590system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. 591system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. 592system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 593system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. 594system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 595system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 511system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits 512system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits 513system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits 514system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits 515system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits 516system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits 517system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits 518system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits --- 104 unchanged lines hidden (view full) --- 623system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks 624system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks 625system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. 626system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. 627system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 628system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. 629system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 630system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 631system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 596system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution --- 21 unchanged lines hidden (view full) --- 625system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram 627system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram 628system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram 629system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 630system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 631system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 632system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram | 632system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution 633system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution 634system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution 635system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution 636system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution 637system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution 638system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution 639system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution --- 21 unchanged lines hidden (view full) --- 661system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 662system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram 663system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram 664system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram 665system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 666system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 667system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 668system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram |
| 669system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 654system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 655system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 656system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 657system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 658system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 659system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 660system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 661system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 670system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 674system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 675system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 676system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 677system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 691system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 692system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 693system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 694system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 695system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 696system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 697system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 698system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 699system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 662system.cpu1.dtb.walker.walks 144355 # Table walker walks requested 663system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors 664system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency 665system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency 666system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency 667system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 668system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 669system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 693system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 694system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 695system.cpu1.dtb.read_accesses 91437883 # DTB read accesses 696system.cpu1.dtb.write_accesses 82174100 # DTB write accesses 697system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 698system.cpu1.dtb.hits 173467628 # DTB hits 699system.cpu1.dtb.misses 144355 # DTB misses 700system.cpu1.dtb.accesses 173611983 # DTB accesses | 700system.cpu1.dtb.walker.walks 144355 # Table walker walks requested 701system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors 702system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency 703system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency 704system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency 705system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 706system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 707system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 731system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 732system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 733system.cpu1.dtb.read_accesses 91437883 # DTB read accesses 734system.cpu1.dtb.write_accesses 82174100 # DTB write accesses 735system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 736system.cpu1.dtb.hits 173467628 # DTB hits 737system.cpu1.dtb.misses 144355 # DTB misses 738system.cpu1.dtb.accesses 173611983 # DTB accesses |
| 739system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 701system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 702system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 722system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 723system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 724system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 725system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 726system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 727system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 728system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 729system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 740system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 741system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 742system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 743system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 744system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 761system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 762system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 763system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 764system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 765system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 766system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 767system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 768system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 769system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 730system.cpu1.itb.walker.walks 61638 # Table walker walks requested 731system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors 732system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency 733system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency 734system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency 735system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 736system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 737system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 761system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 762system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 763system.cpu1.itb.read_accesses 0 # DTB read accesses 764system.cpu1.itb.write_accesses 0 # DTB write accesses 765system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 766system.cpu1.itb.hits 483902380 # DTB hits 767system.cpu1.itb.misses 61638 # DTB misses 768system.cpu1.itb.accesses 483964018 # DTB accesses | 770system.cpu1.itb.walker.walks 61638 # Table walker walks requested 771system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors 772system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency 773system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency 774system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency 775system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 776system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 777system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 801system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 802system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 803system.cpu1.itb.read_accesses 0 # DTB read accesses 804system.cpu1.itb.write_accesses 0 # DTB write accesses 805system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 806system.cpu1.itb.hits 483902380 # DTB hits 807system.cpu1.itb.misses 61638 # DTB misses 808system.cpu1.itb.accesses 483964018 # DTB accesses |
| 809system.cpu1.numPwrStateTransitions 12326 # Number of power state transitions 810system.cpu1.pwrStateClkGateDist::samples 6163 # Distribution of time spent in the clock gated state 811system.cpu1.pwrStateClkGateDist::mean 7615138435.844394 # Distribution of time spent in the clock gated state 812system.cpu1.pwrStateClkGateDist::stdev 188025849317.388916 # Distribution of time spent in the clock gated state 813system.cpu1.pwrStateClkGateDist::underflows 4489 72.84% 72.84% # Distribution of time spent in the clock gated state 814system.cpu1.pwrStateClkGateDist::1000-5e+10 1652 26.81% 99.64% # Distribution of time spent in the clock gated state 815system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.10% 99.74% # Distribution of time spent in the clock gated state 816system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.77% # Distribution of time spent in the clock gated state 817system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.81% # Distribution of time spent in the clock gated state 818system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 819system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 820system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state 821system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 822system.cpu1.pwrStateClkGateDist::max_value 11813542449500 # Distribution of time spent in the clock gated state 823system.cpu1.pwrStateClkGateDist::total 6163 # Distribution of time spent in the clock gated state 824system.cpu1.pwrStateResidencyTicks::ON 284716621891 # Cumulative time (in ticks) in various power states 825system.cpu1.pwrStateResidencyTicks::CLK_GATED 46932098180109 # Cumulative time (in ticks) in various power states |
|
| 769system.cpu1.numCycles 94433635768 # number of cpu cycles simulated 770system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 771system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 772system.cpu1.kern.inst.arm 0 # number of arm instructions executed 773system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed 774system.cpu1.committedInsts 483651505 # Number of instructions committed 775system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed 776system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 823system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 824system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 825system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 826system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction 827system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction 828system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 829system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 830system.cpu1.op_class::total 569428445 # Class of executed instruction | 826system.cpu1.numCycles 94433635768 # number of cpu cycles simulated 827system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 828system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 829system.cpu1.kern.inst.arm 0 # number of arm instructions executed 830system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed 831system.cpu1.committedInsts 483651505 # Number of instructions committed 832system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed 833system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 880system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 881system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 882system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 883system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction 884system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction 885system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 886system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 887system.cpu1.op_class::total 569428445 # Class of executed instruction |
| 888system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 831system.cpu1.dcache.tags.replacements 6003966 # number of replacements 832system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use 833system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. 834system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. 835system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. 836system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 837system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor 838system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy 839system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy 840system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 841system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id 842system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id 843system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 844system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses 845system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses | 889system.cpu1.dcache.tags.replacements 6003966 # number of replacements 890system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use 891system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. 892system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. 893system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. 894system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 895system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor 896system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy 897system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy 898system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 899system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id 900system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id 901system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 902system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses 903system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses |
| 904system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 846system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits 847system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits 848system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits 849system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits 850system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits 851system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits 852system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits 853system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits --- 56 unchanged lines hidden (view full) --- 910system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 911system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 912system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 913system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 914system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 915system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 916system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks 917system.cpu1.dcache.writebacks::total 6003966 # number of writebacks | 905system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits 906system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits 907system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits 908system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits 909system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits 910system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits 911system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits 912system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits --- 56 unchanged lines hidden (view full) --- 969system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 970system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 971system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 973system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 974system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 975system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks 976system.cpu1.dcache.writebacks::total 6003966 # number of writebacks |
| 977system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 918system.cpu1.icache.tags.replacements 4799154 # number of replacements 919system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 920system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. 921system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. 922system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. 923system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 924system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 925system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 926system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 927system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 928system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 929system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 930system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id 931system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 932system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses 933system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses | 978system.cpu1.icache.tags.replacements 4799154 # number of replacements 979system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 980system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. 981system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. 982system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. 983system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 984system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 985system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 986system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 987system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 988system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 989system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 990system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id 991system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 992system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses 993system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses |
| 994system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 934system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits 935system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits 936system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits 937system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits 938system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits 939system.cpu1.icache.overall_hits::total 479157890 # number of overall hits 940system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses 941system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 958system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 959system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 960system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 961system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 962system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 963system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 964system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks 965system.cpu1.icache.writebacks::total 4799154 # number of writebacks | 995system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits 996system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits 997system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits 998system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits 999system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits 1000system.cpu1.icache.overall_hits::total 479157890 # number of overall hits 1001system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses 1002system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 1019system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1020system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1021system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1022system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1023system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1024system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1025system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks 1026system.cpu1.icache.writebacks::total 4799154 # number of writebacks |
| 1027system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 966system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 967system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 968system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 969system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 970system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 971system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 1028system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1029system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 1030system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1031system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1032system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1033system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 1034system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 972system.cpu1.l2cache.tags.replacements 2283161 # number of replacements 973system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use 974system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. 975system.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks. 976system.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks. 977system.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit. 978system.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor 979system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor --- 12 unchanged lines hidden (view full) --- 992system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id 993system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id 994system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id 995system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id 996system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 997system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id 998system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses 999system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses | 1035system.cpu1.l2cache.tags.replacements 2283161 # number of replacements 1036system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use 1037system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. 1038system.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks. 1039system.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks. 1040system.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit. 1041system.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor 1042system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor --- 12 unchanged lines hidden (view full) --- 1055system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id 1056system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id 1057system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id 1058system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id 1059system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 1060system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id 1061system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses 1062system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses |
| 1063system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1000system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits 1001system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits 1002system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits 1003system.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits 1004system.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits 1005system.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits 1006system.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits 1007system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits --- 104 unchanged lines hidden (view full) --- 1112system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks 1113system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks 1114system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. 1115system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1116system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1117system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. 1118system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1119system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1064system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits 1065system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits 1066system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits 1067system.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits 1068system.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits 1069system.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits 1070system.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits 1071system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits --- 104 unchanged lines hidden (view full) --- 1176system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks 1177system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks 1178system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. 1179system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1180system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1181system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. 1182system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1183system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1184system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1120system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution 1121system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution 1122system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution 1123system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution 1124system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution 1127system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution --- 21 unchanged lines hidden (view full) --- 1149system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1150system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram 1152system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram 1153system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1154system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1155system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1156system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram | 1185system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution 1186system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution 1187system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution 1188system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution 1189system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution 1190system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution 1191system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution 1192system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution --- 21 unchanged lines hidden (view full) --- 1214system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1215system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram 1216system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram 1217system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram 1218system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1219system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1220system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1221system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram |
| 1222system.iobus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1157system.iobus.trans_dist::ReadReq 40301 # Transaction distribution 1158system.iobus.trans_dist::ReadResp 40301 # Transaction distribution 1159system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1160system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 1161system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 1191system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) | 1223system.iobus.trans_dist::ReadReq 40301 # Transaction distribution 1224system.iobus.trans_dist::ReadResp 40301 # Transaction distribution 1225system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1226system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 1227system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 1228system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1229system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1230system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 26 unchanged lines hidden (view full) --- 1257system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) |
| 1265system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1199system.iocache.tags.replacements 115590 # number of replacements 1200system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use 1201system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1202system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 1203system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1204system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. 1205system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor 1206system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor 1207system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy 1208system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy 1209system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy 1210system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1211system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1212system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1213system.iocache.tags.tag_accesses 1040838 # Number of tag accesses 1214system.iocache.tags.data_accesses 1040838 # Number of data accesses | 1266system.iocache.tags.replacements 115590 # number of replacements 1267system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use 1268system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1269system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 1270system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1271system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. 1272system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor 1273system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor 1274system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy 1275system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy 1276system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy 1277system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1278system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1279system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1280system.iocache.tags.tag_accesses 1040838 # Number of tag accesses 1281system.iocache.tags.data_accesses 1040838 # Number of data accesses |
| 1282system.iocache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1215system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1216system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 1217system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 1218system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1219system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1220system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1221system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1222system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 31 unchanged lines hidden (view full) --- 1254system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1255system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1256system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1257system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1258system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1259system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1260system.iocache.writebacks::writebacks 106694 # number of writebacks 1261system.iocache.writebacks::total 106694 # number of writebacks | 1283system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1284system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 1285system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 1286system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1287system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1288system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1289system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1290system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 31 unchanged lines hidden (view full) --- 1322system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1323system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1324system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1325system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1326system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1327system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1328system.iocache.writebacks::writebacks 106694 # number of writebacks 1329system.iocache.writebacks::total 106694 # number of writebacks |
| 1330system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1262system.l2c.tags.replacements 1772279 # number of replacements 1263system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use 1264system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. 1265system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. 1266system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. 1267system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 1268system.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor 1269system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor --- 22 unchanged lines hidden (view full) --- 1292system.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 1293system.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id 1294system.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id 1295system.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id 1296system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id 1297system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id 1298system.l2c.tags.tag_accesses 73419992 # Number of tag accesses 1299system.l2c.tags.data_accesses 73419992 # Number of data accesses | 1331system.l2c.tags.replacements 1772279 # number of replacements 1332system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use 1333system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. 1334system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. 1335system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. 1336system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 1337system.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor 1338system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor --- 22 unchanged lines hidden (view full) --- 1361system.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 1362system.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id 1363system.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id 1364system.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id 1365system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id 1366system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id 1367system.l2c.tags.tag_accesses 73419992 # Number of tag accesses 1368system.l2c.tags.data_accesses 73419992 # Number of data accesses |
| 1369system.l2c.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1300system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits 1301system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits 1302system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits 1303system.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits 1304system.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits 1305system.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits 1306system.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits 1307system.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits --- 158 unchanged lines hidden (view full) --- 1466system.l2c.writebacks::writebacks 1477304 # number of writebacks 1467system.l2c.writebacks::total 1477304 # number of writebacks 1468system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. 1469system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1470system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1471system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1472system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1473system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1370system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits 1371system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits 1372system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits 1373system.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits 1374system.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits 1375system.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits 1376system.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits 1377system.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits --- 158 unchanged lines hidden (view full) --- 1536system.l2c.writebacks::writebacks 1477304 # number of writebacks 1537system.l2c.writebacks::total 1477304 # number of writebacks 1538system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. 1539system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1540system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1541system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1542system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1543system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1544system.membus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1474system.membus.trans_dist::ReadReq 82119 # Transaction distribution 1475system.membus.trans_dist::ReadResp 569484 # Transaction distribution 1476system.membus.trans_dist::WriteReq 38800 # Transaction distribution 1477system.membus.trans_dist::WriteResp 38800 # Transaction distribution 1478system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution 1479system.membus.trans_dist::CleanEvict 246737 # Transaction distribution 1480system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution 1481system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 1508system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1509system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram 1510system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram 1511system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1512system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1513system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1514system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1515system.membus.snoop_fanout::total 4612344 # Request fanout histogram | 1545system.membus.trans_dist::ReadReq 82119 # Transaction distribution 1546system.membus.trans_dist::ReadResp 569484 # Transaction distribution 1547system.membus.trans_dist::WriteReq 38800 # Transaction distribution 1548system.membus.trans_dist::WriteResp 38800 # Transaction distribution 1549system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution 1550system.membus.trans_dist::CleanEvict 246737 # Transaction distribution 1551system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution 1552system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 1579system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1580system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram 1581system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram 1582system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1583system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1584system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1585system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1586system.membus.snoop_fanout::total 4612344 # Request fanout histogram |
| 1587system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1588system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1589system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1590system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1591system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1592system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1593system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1516system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1517system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1518system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1519system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1520system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1521system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1594system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1595system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1596system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1597system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1598system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1599system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1600system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1601system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1522system.realview.ethernet.txBytes 966 # Bytes Transmitted 1523system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1524system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1525system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1526system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1527system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1528system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1529system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1556system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1557system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1558system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1559system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1560system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1561system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1562system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1563system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1602system.realview.ethernet.txBytes 966 # Bytes Transmitted 1603system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1604system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1605system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1606system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1607system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1608system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1609system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1636system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1637system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1638system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1639system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1640system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1641system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1642system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1643system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1644system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1645system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1646system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1647system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1648system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1649system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1650system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1564system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1565system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1566system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1567system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1651system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1652system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1653system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1654system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1655system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1656system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1657system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1658system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1659system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1660system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1661system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1662system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1663system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1664system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1665system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states 1666system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1568system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. 1569system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1570system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1571system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. 1572system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1573system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1667system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. 1668system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1669system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1670system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. 1671system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1672system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1673system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states |
|
| 1574system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution 1575system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution 1576system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution 1577system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution 1578system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution 1579system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution 1580system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution 1581system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution --- 26 unchanged lines hidden --- | 1674system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution 1675system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution 1676system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution 1677system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution 1678system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution 1679system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution 1680system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution 1681system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution --- 26 unchanged lines hidden --- |