| stats.txt (11456:c0fb4435b80f) | stats.txt (11502:e273e86a873d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.256536 # Number of seconds simulated 4sim_ticks 47256535705500 # Number of ticks simulated 5final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.216815 # Number of seconds simulated 4sim_ticks 47216814802000 # Number of ticks simulated 5final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1118024 # Simulator instruction rate (inst/s) 8host_op_rate 1315296 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54153885278 # Simulator tick rate (ticks/s) 10host_mem_usage 690972 # Number of bytes of host memory used 11host_seconds 872.63 # Real time elapsed on the host 12sim_insts 975625723 # Number of instructions simulated 13sim_ops 1147772483 # Number of ops (including micro ops) simulated | 7host_inst_rate 1112312 # Simulator instruction rate (inst/s) 8host_op_rate 1308465 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53753255119 # Simulator tick rate (ticks/s) 10host_mem_usage 687512 # Number of bytes of host memory used 11host_seconds 878.40 # Real time elapsed on the host 12sim_insts 977053655 # Number of instructions simulated 13sim_ops 1149354696 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 217792 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 214080 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2613000 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 38038064 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 430464 # Number of bytes read from this memory 25system.physmem.bytes_read::total 81291956 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3883124 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2613000 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6496124 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 101151552 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory 25system.physmem.bytes_read::total 81375732 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory |
| 30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::total 101172136 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2451 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 101081 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 556375 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3403 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3345 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 40935 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 594361 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6726 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1310730 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1580493 # Number of write requests responded to by this memory | 32system.physmem.bytes_written::total 101396456 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory |
| 44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::total 1583067 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3319 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 82171 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 753487 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4609 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4530 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 55294 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 804927 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 9109 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 1720227 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 82171 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 55294 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 137465 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2140478 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) | 46system.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_write::total 2140913 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2140478 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3319 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 82171 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 753922 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4609 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4530 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 55294 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 804927 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 9109 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3861140 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) |
| 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 46 unchanged lines hidden (view full) --- 129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 46 unchanged lines hidden (view full) --- 129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 137system.cpu0.dtb.walker.walks 124170 # Table walker walks requested 138system.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors 139system.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency 140system.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141system.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency | 137system.cpu0.dtb.walker.walks 124420 # Table walker walks requested 138system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors 139system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency 140system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency |
| 142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution | 142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution |
| 145system.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated 146system.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated 147system.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated 148system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst | 145system.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated 146system.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated 147system.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated 148system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst |
| 149system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 149system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 150system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst 151system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst | 150system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst 151system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst |
| 152system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 152system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 153system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst 154system.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst | 153system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst 154system.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst |
| 155system.cpu0.dtb.inst_hits 0 # ITB inst hits 156system.cpu0.dtb.inst_misses 0 # ITB inst misses | 155system.cpu0.dtb.inst_hits 0 # ITB inst hits 156system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 157system.cpu0.dtb.read_hits 91996645 # DTB read hits 158system.cpu0.dtb.read_misses 87944 # DTB read misses 159system.cpu0.dtb.write_hits 85085804 # DTB write hits 160system.cpu0.dtb.write_misses 36226 # DTB write misses | 157system.cpu0.dtb.read_hits 91801710 # DTB read hits 158system.cpu0.dtb.read_misses 88193 # DTB read misses 159system.cpu0.dtb.write_hits 84999619 # DTB write hits 160system.cpu0.dtb.write_misses 36227 # DTB write misses |
| 161system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 162system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 161system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 162system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 163system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID | 163system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID |
| 164system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 164system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 165system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB | 165system.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB |
| 166system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 166system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 167system.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch | 167system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch |
| 168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 169system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions 170system.cpu0.dtb.read_accesses 92084589 # DTB read accesses 171system.cpu0.dtb.write_accesses 85122030 # DTB write accesses | 169system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions 170system.cpu0.dtb.read_accesses 91889903 # DTB read accesses 171system.cpu0.dtb.write_accesses 85035846 # DTB write accesses |
| 172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 173system.cpu0.dtb.hits 177082449 # DTB hits 174system.cpu0.dtb.misses 124170 # DTB misses 175system.cpu0.dtb.accesses 177206619 # DTB accesses | 173system.cpu0.dtb.hits 176801329 # DTB hits 174system.cpu0.dtb.misses 124420 # DTB misses 175system.cpu0.dtb.accesses 176925749 # DTB accesses |
| 176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 205system.cpu0.itb.walker.walks 60706 # Table walker walks requested 206system.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors 207system.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency 208system.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency 209system.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency | 205system.cpu0.itb.walker.walks 60852 # Table walker walks requested 206system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors 207system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency 208system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency 209system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency |
| 210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution | 210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution |
| 213system.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated 214system.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated 215system.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated | 213system.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated 214system.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated 215system.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated |
| 216system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 216system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 217system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst 218system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst | 217system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst 218system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst |
| 219system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 219system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 220system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst 221system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst 222system.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst 223system.cpu0.itb.inst_hits 494456191 # ITB inst hits 224system.cpu0.itb.inst_misses 60706 # ITB inst misses | 220system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst 221system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst 222system.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst 223system.cpu0.itb.inst_hits 493637993 # ITB inst hits 224system.cpu0.itb.inst_misses 60852 # ITB inst misses |
| 225system.cpu0.itb.read_hits 0 # DTB read hits 226system.cpu0.itb.read_misses 0 # DTB read misses 227system.cpu0.itb.write_hits 0 # DTB write hits 228system.cpu0.itb.write_misses 0 # DTB write misses 229system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 230system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 225system.cpu0.itb.read_hits 0 # DTB read hits 226system.cpu0.itb.read_misses 0 # DTB read misses 227system.cpu0.itb.write_hits 0 # DTB write hits 228system.cpu0.itb.write_misses 0 # DTB write misses 229system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 230system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 231system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID | 231system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID |
| 232system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 232system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 233system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB | 233system.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB |
| 234system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 235system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 238system.cpu0.itb.read_accesses 0 # DTB read accesses 239system.cpu0.itb.write_accesses 0 # DTB write accesses | 234system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 235system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 238system.cpu0.itb.read_accesses 0 # DTB read accesses 239system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 240system.cpu0.itb.inst_accesses 494516897 # ITB inst accesses 241system.cpu0.itb.hits 494456191 # DTB hits 242system.cpu0.itb.misses 60706 # DTB misses 243system.cpu0.itb.accesses 494516897 # DTB accesses 244system.cpu0.numCycles 94513084765 # number of cpu cycles simulated | 240system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses 241system.cpu0.itb.hits 493637993 # DTB hits 242system.cpu0.itb.misses 60852 # DTB misses 243system.cpu0.itb.accesses 493698845 # DTB accesses 244system.cpu0.numCycles 94433642835 # number of cpu cycles simulated |
| 245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 248system.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed 249system.cpu0.committedInsts 494222683 # Number of instructions committed 250system.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed 251system.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses 252system.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses 253system.cpu0.num_func_calls 28754621 # number of times a function call or return occured 254system.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls 255system.cpu0.num_int_insts 532690974 # number of integer instructions 256system.cpu0.num_fp_insts 523276 # number of float instructions 257system.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read 258system.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written 259system.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read 260system.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written 261system.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read 262system.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written 263system.cpu0.num_mem_refs 177183712 # number of memory refs 264system.cpu0.num_load_insts 92070454 # Number of load instructions 265system.cpu0.num_store_insts 85113258 # Number of store instructions 266system.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles 267system.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles 268system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles 269system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles 270system.cpu0.Branches 110567658 # Number of branches fetched | 248system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed 249system.cpu0.committedInsts 493402150 # Number of instructions committed 250system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed 251system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses 252system.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses 253system.cpu0.num_func_calls 28738017 # number of times a function call or return occured 254system.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls 255system.cpu0.num_int_insts 531778274 # number of integer instructions 256system.cpu0.num_fp_insts 521057 # number of float instructions 257system.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read 258system.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written 259system.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read 260system.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written 261system.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read 262system.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written 263system.cpu0.num_mem_refs 176902115 # number of memory refs 264system.cpu0.num_load_insts 91875039 # Number of load instructions 265system.cpu0.num_store_insts 85027076 # Number of store instructions 266system.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles 267system.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles 268system.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles 269system.cpu0.idle_fraction 0.993852 # Percentage of idle cycles 270system.cpu0.Branches 110403926 # Number of branches fetched |
| 271system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 271system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
| 272system.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction 273system.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction 274system.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction | 272system.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction 273system.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction 274system.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction |
| 275system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 276system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 277system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 278system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 279system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 280system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 281system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 282system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction --- 6 unchanged lines hidden (view full) --- 289system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 290system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 291system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 292system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 293system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 294system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 295system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 296system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction | 275system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 276system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 277system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 278system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 279system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 280system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 281system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 282system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction --- 6 unchanged lines hidden (view full) --- 289system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 290system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 291system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 292system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 293system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 294system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 295system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 296system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction |
| 297system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction | 297system.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction |
| 298system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 299system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 300system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction | 298system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 299system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 300system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction |
| 301system.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction 302system.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction | 301system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction 302system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction |
| 303system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 303system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 305system.cpu0.op_class::total 581576758 # Class of executed instruction 306system.cpu0.dcache.tags.replacements 6248192 # number of replacements 307system.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use 308system.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks. | 305system.cpu0.op_class::total 580566843 # Class of executed instruction 306system.cpu0.dcache.tags.replacements 6218107 # number of replacements 307system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use 308system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. |
| 311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. | 311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. |
| 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy | 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy |
| 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id | 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id |
| 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id | 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id |
| 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 320system.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses 322system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80310144 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80310144 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits 334system.cpu0.dcache.demand_hits::cpu0.data 166131177 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 166131177 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 166345589 # number of overall hits 337system.cpu0.dcache.overall_hits::total 166345589 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses 344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses 345system.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses 350system.cpu0.dcache.demand_misses::cpu0.data 5600711 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 5600711 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 6375269 # number of overall misses 353system.cpu0.dcache.overall_misses::total 6375269 # number of overall misses 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) 361system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) 366system.cpu0.dcache.demand_accesses::cpu0.data 171731888 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 171731888 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 172720858 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 172720858 # number of overall (read+write) accesses 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses 376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses 377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032613 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.032613 # miss rate for demand accesses 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036911 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.036911 # miss rate for overall accesses | 320system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses 322system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits 334system.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits 337system.cpu0.dcache.overall_hits::total 166105825 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses 344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses 345system.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses 350system.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses 353system.cpu0.dcache.overall_misses::total 6341132 # number of overall misses 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses) 361system.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses) 366system.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses 376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses 377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses |
| 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 392system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks 393system.cpu0.dcache.writebacks::total 6248192 # number of writebacks 394system.cpu0.icache.tags.replacements 5479450 # number of replacements 395system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use 396system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. 397system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. 398system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. | 392system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks 393system.cpu0.dcache.writebacks::total 6218107 # number of writebacks 394system.cpu0.icache.tags.replacements 5488502 # number of replacements 395system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 396system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. 397system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. 398system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. |
| 399system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. | 399system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. |
| 400system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor | 400system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor |
| 401system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 402system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 403system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 401system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 402system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 403system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 404system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 405system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 406system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id | 404system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 405system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 406system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
| 407system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 408system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 408system.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses 409system.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses 410system.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits 411system.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits 412system.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits 413system.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits 414system.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits 415system.cpu0.icache.overall_hits::total 489031557 # number of overall hits 416system.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses 417system.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses 418system.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses 419system.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses 420system.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses 421system.cpu0.icache.overall_misses::total 5479967 # number of overall misses 422system.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses) 423system.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses) 424system.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses 425system.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses 426system.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses 427system.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses 428system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses 429system.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses 430system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses 431system.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses 432system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses 433system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses | 409system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses 410system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses 411system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits 412system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits 413system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits 414system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits 415system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits 416system.cpu0.icache.overall_hits::total 488204417 # number of overall hits 417system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses 418system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses 419system.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses 420system.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses 421system.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses 422system.cpu0.icache.overall_misses::total 5489019 # number of overall misses 423system.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses) 424system.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses) 425system.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses 426system.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses 427system.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses 428system.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses 429system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses 430system.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses 431system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses 432system.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses 433system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses 434system.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses |
| 434system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 435system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 436system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 437system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 438system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 439system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 435system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 436system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 437system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 440system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 440system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks 441system.cpu0.icache.writebacks::total 5479450 # number of writebacks | 441system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks 442system.cpu0.icache.writebacks::total 5488502 # number of writebacks |
| 442system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 443system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 444system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 445system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 446system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 447system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 443system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 444system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 445system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 446system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 447system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 448system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 448system.cpu0.l2cache.tags.replacements 2651590 # number of replacements 449system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use 450system.cpu0.l2cache.tags.total_refs 15457113 # Total number of references to valid blocks. 451system.cpu0.l2cache.tags.sampled_refs 2667587 # Sample count of references to valid blocks. 452system.cpu0.l2cache.tags.avg_refs 5.794418 # Average number of references to valid blocks. | 449system.cpu0.l2cache.tags.replacements 2643580 # number of replacements 450system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use 451system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. 452system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. 453system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. |
| 453system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. | 454system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. |
| 454system.cpu0.l2cache.tags.occ_blocks::writebacks 15991.608429 # Average occupied blocks per requestor 455system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.291374 # Average occupied blocks per requestor 456system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.584847 # Average occupied blocks per requestor 457system.cpu0.l2cache.tags.occ_percent::writebacks 0.976050 # Average percentage of cache occupancy 458system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003009 # Average percentage of cache occupancy 459system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003148 # Average percentage of cache occupancy 460system.cpu0.l2cache.tags.occ_percent::total 0.982207 # Average percentage of cache occupancy 461system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 462system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15920 # Occupied blocks per task id 463system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 464system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 465system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 466system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 467system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1478 # Occupied blocks per task id 468system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4821 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4797 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4598 # Occupied blocks per task id 471system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 472system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971680 # Percentage of cache occupancy per task id 473system.cpu0.l2cache.tags.tag_accesses 394865177 # Number of tag accesses 474system.cpu0.l2cache.tags.data_accesses 394865177 # Number of data accesses 475system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294372 # number of ReadReq hits 476system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156640 # number of ReadReq hits 477system.cpu0.l2cache.ReadReq_hits::total 451012 # number of ReadReq hits 478system.cpu0.l2cache.WritebackDirty_hits::writebacks 4430802 # number of WritebackDirty hits 479system.cpu0.l2cache.WritebackDirty_hits::total 4430802 # number of WritebackDirty hits 480system.cpu0.l2cache.WritebackClean_hits::writebacks 7295441 # number of WritebackClean hits 481system.cpu0.l2cache.WritebackClean_hits::total 7295441 # number of WritebackClean hits 482system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 774 # number of UpgradeReq hits 483system.cpu0.l2cache.UpgradeReq_hits::total 774 # number of UpgradeReq hits 484system.cpu0.l2cache.ReadExReq_hits::cpu0.data 631554 # number of ReadExReq hits 485system.cpu0.l2cache.ReadExReq_hits::total 631554 # number of ReadExReq hits 486system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4983798 # number of ReadCleanReq hits 487system.cpu0.l2cache.ReadCleanReq_hits::total 4983798 # number of ReadCleanReq hits 488system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2949332 # number of ReadSharedReq hits 489system.cpu0.l2cache.ReadSharedReq_hits::total 2949332 # number of ReadSharedReq hits 490system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218231 # number of InvalidateReq hits 491system.cpu0.l2cache.InvalidateReq_hits::total 218231 # number of InvalidateReq hits 492system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294372 # number of demand (read+write) hits 493system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156640 # number of demand (read+write) hits 494system.cpu0.l2cache.demand_hits::cpu0.inst 4983798 # number of demand (read+write) hits 495system.cpu0.l2cache.demand_hits::cpu0.data 3580886 # number of demand (read+write) hits 496system.cpu0.l2cache.demand_hits::total 9015696 # number of demand (read+write) hits 497system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294372 # number of overall hits 498system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156640 # number of overall hits 499system.cpu0.l2cache.overall_hits::cpu0.inst 4983798 # number of overall hits 500system.cpu0.l2cache.overall_hits::cpu0.data 3580886 # number of overall hits 501system.cpu0.l2cache.overall_hits::total 9015696 # number of overall hits 502system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11531 # number of ReadReq misses 503system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8761 # number of ReadReq misses 504system.cpu0.l2cache.ReadReq_misses::total 20292 # number of ReadReq misses 505system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140614 # number of UpgradeReq misses 506system.cpu0.l2cache.UpgradeReq_misses::total 140614 # number of UpgradeReq misses 507system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156654 # number of SCUpgradeReq misses 508system.cpu0.l2cache.SCUpgradeReq_misses::total 156654 # number of SCUpgradeReq misses 509system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712280 # number of ReadExReq misses 510system.cpu0.l2cache.ReadExReq_misses::total 712280 # number of ReadExReq misses 511system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 496169 # number of ReadCleanReq misses 512system.cpu0.l2cache.ReadCleanReq_misses::total 496169 # number of ReadCleanReq misses 513system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236248 # number of ReadSharedReq misses 514system.cpu0.l2cache.ReadSharedReq_misses::total 1236248 # number of ReadSharedReq misses 515system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604597 # number of InvalidateReq misses 516system.cpu0.l2cache.InvalidateReq_misses::total 604597 # number of InvalidateReq misses 517system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11531 # number of demand (read+write) misses 518system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8761 # number of demand (read+write) misses 519system.cpu0.l2cache.demand_misses::cpu0.inst 496169 # number of demand (read+write) misses 520system.cpu0.l2cache.demand_misses::cpu0.data 1948528 # number of demand (read+write) misses 521system.cpu0.l2cache.demand_misses::total 2464989 # number of demand (read+write) misses 522system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11531 # number of overall misses 523system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8761 # number of overall misses 524system.cpu0.l2cache.overall_misses::cpu0.inst 496169 # number of overall misses 525system.cpu0.l2cache.overall_misses::cpu0.data 1948528 # number of overall misses 526system.cpu0.l2cache.overall_misses::total 2464989 # number of overall misses 527system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305903 # number of ReadReq accesses(hits+misses) 528system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165401 # number of ReadReq accesses(hits+misses) 529system.cpu0.l2cache.ReadReq_accesses::total 471304 # number of ReadReq accesses(hits+misses) 530system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4430802 # number of WritebackDirty accesses(hits+misses) 531system.cpu0.l2cache.WritebackDirty_accesses::total 4430802 # number of WritebackDirty accesses(hits+misses) 532system.cpu0.l2cache.WritebackClean_accesses::writebacks 7295441 # number of WritebackClean accesses(hits+misses) 533system.cpu0.l2cache.WritebackClean_accesses::total 7295441 # number of WritebackClean accesses(hits+misses) 534system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141388 # number of UpgradeReq accesses(hits+misses) 535system.cpu0.l2cache.UpgradeReq_accesses::total 141388 # number of UpgradeReq accesses(hits+misses) 536system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156654 # number of SCUpgradeReq accesses(hits+misses) 537system.cpu0.l2cache.SCUpgradeReq_accesses::total 156654 # number of SCUpgradeReq accesses(hits+misses) 538system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) 539system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) 540system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) 541system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses) 542system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses) 543system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) 544system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) 545system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) 546system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305903 # number of demand (read+write) accesses 547system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165401 # number of demand (read+write) accesses 548system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses 549system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses 550system.cpu0.l2cache.demand_accesses::total 11480685 # number of demand (read+write) accesses 551system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305903 # number of overall (read+write) accesses 552system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165401 # number of overall (read+write) accesses 553system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses 554system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses 555system.cpu0.l2cache.overall_accesses::total 11480685 # number of overall (read+write) accesses 556system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for ReadReq accesses 557system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052968 # miss rate for ReadReq accesses 558system.cpu0.l2cache.ReadReq_miss_rate::total 0.043055 # miss rate for ReadReq accesses 559system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994526 # miss rate for UpgradeReq accesses 560system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994526 # miss rate for UpgradeReq accesses | 455system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor 456system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor 457system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor 458system.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy 459system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy 460system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy 461system.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy 462system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id 463system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id 464system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 465system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 466system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 467system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id 468system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id 471system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id 472system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 473system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id 474system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses 475system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses 476system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits 477system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits 478system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits 479system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits 480system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits 481system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits 482system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits 483system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits 484system.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits 485system.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits 486system.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits 487system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits 488system.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits 489system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits 490system.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits 491system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits 492system.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits 493system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits 494system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits 495system.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits 496system.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits 497system.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits 498system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits 499system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits 500system.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits 501system.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits 502system.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits 503system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses 504system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses 505system.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses 506system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses 507system.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses 508system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses 509system.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses 510system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses 511system.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses 512system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses 513system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses 514system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses 515system.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses 516system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses 517system.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses 518system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses 519system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses 520system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses 521system.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses 522system.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses 523system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses 524system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses 525system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses 526system.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses 527system.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses 528system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses) 529system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses) 530system.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses) 531system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses) 532system.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses) 533system.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses) 534system.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses) 535system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses) 536system.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses) 537system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses) 538system.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses) 539system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses) 540system.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses) 541system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses) 542system.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses) 543system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses) 544system.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses) 545system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses) 546system.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses) 547system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses 548system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses 549system.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses 550system.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses 551system.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses 552system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses 553system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses 554system.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses 555system.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses 556system.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses 557system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses 558system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses 559system.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses 560system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses 561system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses |
| 561system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 562system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 562system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 563system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 563system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530036 # miss rate for ReadExReq accesses 564system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530036 # miss rate for ReadExReq accesses 565system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090542 # miss rate for ReadCleanReq accesses 566system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090542 # miss rate for ReadCleanReq accesses 567system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295359 # miss rate for ReadSharedReq accesses 568system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295359 # miss rate for ReadSharedReq accesses 569system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734779 # miss rate for InvalidateReq accesses 570system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734779 # miss rate for InvalidateReq accesses 571system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for demand accesses 572system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052968 # miss rate for demand accesses 573system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090542 # miss rate for demand accesses 574system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352393 # miss rate for demand accesses 575system.cpu0.l2cache.demand_miss_rate::total 0.214707 # miss rate for demand accesses 576system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for overall accesses 577system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052968 # miss rate for overall accesses 578system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090542 # miss rate for overall accesses 579system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses 580system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses | 564system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses 565system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses 566system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses 567system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses 568system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses 569system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses 570system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses 571system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses 572system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses 573system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses 574system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses 575system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses 576system.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses 577system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses 578system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses 579system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses 580system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses 581system.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses |
| 581system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 582system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 587system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks 588system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks 589system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. 590system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. 591system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 592system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. 593system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 594system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 595system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::WritebackDirty 4430802 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::WritebackClean 7296840 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::UpgradeReq 141388 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156654 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::UpgradeResp 298042 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution 609system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution 610system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) 611system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681390 # Packet count per connected master and slave (bytes) 612system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) 613system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) 614system.cpu0.toL2Bus.pkt_count::total 37292106 # Packet count per connected master and slave (bytes) 615system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) 616system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) 617system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) 618system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) 619system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) 620system.cpu0.toL2Bus.snoops 6124419 # Total snoops (count) 621system.cpu0.toL2Bus.snoop_fanout::samples 30450834 # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::mean 0.067260 # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::stdev 0.250516 # Request fanout histogram | 588system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks 589system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks 590system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. 591system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. 592system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 593system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. 594system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 595system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 596system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution 609system.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution 610system.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution 611system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes) 612system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes) 613system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes) 614system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes) 615system.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes) 616system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes) 617system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes) 618system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes) 619system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes) 620system.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes) 621system.cpu0.toL2Bus.snoops 6073545 # Total snoops (count) 622system.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram 624system.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram |
| 624system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 625system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 625system.cpu0.toL2Bus.snoop_fanout::0 28403043 93.28% 93.28% # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::1 2047457 6.72% 100.00% # Request fanout histogram 627system.cpu0.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram | 626system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram 627system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram 628system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram |
| 628system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 629system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 630system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 629system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 630system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 631system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 631system.cpu0.toL2Bus.snoop_fanout::total 30450834 # Request fanout histogram | 632system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram |
| 632system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 653system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 654system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 655system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 656system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 657system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 658system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 659system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 660system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 654system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 655system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 656system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 657system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 658system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 659system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 660system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 661system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 661system.cpu1.dtb.walker.walks 145097 # Table walker walks requested 662system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors 663system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency 664system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency 665system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency | 662system.cpu1.dtb.walker.walks 144355 # Table walker walks requested 663system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors 664system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency 665system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency 666system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency |
| 666system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 667system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 668system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution | 667system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 668system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 669system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution |
| 669system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated 670system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated 671system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated 672system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst | 670system.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated 671system.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated 672system.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated 673system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst |
| 673system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 674system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 674system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst 675system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst | 675system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst 676system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst |
| 676system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 677system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 677system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst 678system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst | 678system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst 679system.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst |
| 679system.cpu1.dtb.inst_hits 0 # ITB inst hits 680system.cpu1.dtb.inst_misses 0 # ITB inst misses | 680system.cpu1.dtb.inst_hits 0 # ITB inst hits 681system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 681system.cpu1.dtb.read_hits 90839106 # DTB read hits 682system.cpu1.dtb.read_misses 112437 # DTB read misses 683system.cpu1.dtb.write_hits 81787747 # DTB write hits 684system.cpu1.dtb.write_misses 32660 # DTB write misses | 682system.cpu1.dtb.read_hits 91325952 # DTB read hits 683system.cpu1.dtb.read_misses 111931 # DTB read misses 684system.cpu1.dtb.write_hits 82141676 # DTB write hits 685system.cpu1.dtb.write_misses 32424 # DTB write misses |
| 685system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 686system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 686system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 687system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 687system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID | 688system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID |
| 688system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 689system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 689system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB | 690system.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB |
| 690system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 691system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 691system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch | 692system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch |
| 692system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 693system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 693system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions 694system.cpu1.dtb.read_accesses 90951543 # DTB read accesses 695system.cpu1.dtb.write_accesses 81820407 # DTB write accesses | 694system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions 695system.cpu1.dtb.read_accesses 91437883 # DTB read accesses 696system.cpu1.dtb.write_accesses 82174100 # DTB write accesses |
| 696system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 697system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 697system.cpu1.dtb.hits 172626853 # DTB hits 698system.cpu1.dtb.misses 145097 # DTB misses 699system.cpu1.dtb.accesses 172771950 # DTB accesses | 698system.cpu1.dtb.hits 173467628 # DTB hits 699system.cpu1.dtb.misses 144355 # DTB misses 700system.cpu1.dtb.accesses 173611983 # DTB accesses |
| 700system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 701system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 702system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 721system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 722system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 723system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 724system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 725system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 726system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 727system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 728system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 701system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 702system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 722system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 723system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 724system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 725system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 726system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 727system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 728system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 729system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 729system.cpu1.itb.walker.walks 61573 # Table walker walks requested 730system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors 731system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency 732system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency 733system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency | 730system.cpu1.itb.walker.walks 61638 # Table walker walks requested 731system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors 732system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency 733system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency 734system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency |
| 734system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 735system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 736system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution | 735system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 736system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 737system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution |
| 737system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated 738system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated 739system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated | 738system.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated 739system.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated 740system.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated |
| 740system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 741system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 741system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst 742system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst | 742system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst 743system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst |
| 743system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 744system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 744system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst 745system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst 746system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst 747system.cpu1.itb.inst_hits 481656543 # ITB inst hits 748system.cpu1.itb.inst_misses 61573 # ITB inst misses | 745system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst 746system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst 747system.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst 748system.cpu1.itb.inst_hits 483902380 # ITB inst hits 749system.cpu1.itb.inst_misses 61638 # ITB inst misses |
| 749system.cpu1.itb.read_hits 0 # DTB read hits 750system.cpu1.itb.read_misses 0 # DTB read misses 751system.cpu1.itb.write_hits 0 # DTB write hits 752system.cpu1.itb.write_misses 0 # DTB write misses 753system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 754system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 750system.cpu1.itb.read_hits 0 # DTB read hits 751system.cpu1.itb.read_misses 0 # DTB read misses 752system.cpu1.itb.write_hits 0 # DTB write hits 753system.cpu1.itb.write_misses 0 # DTB write misses 754system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 755system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 755system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID | 756system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID |
| 756system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 757system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 757system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB | 758system.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB |
| 758system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 759system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 760system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 761system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 762system.cpu1.itb.read_accesses 0 # DTB read accesses 763system.cpu1.itb.write_accesses 0 # DTB write accesses | 759system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 760system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 761system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 762system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 763system.cpu1.itb.read_accesses 0 # DTB read accesses 764system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 764system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses 765system.cpu1.itb.hits 481656543 # DTB hits 766system.cpu1.itb.misses 61573 # DTB misses 767system.cpu1.itb.accesses 481718116 # DTB accesses 768system.cpu1.numCycles 94513077683 # number of cpu cycles simulated | 765system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses 766system.cpu1.itb.hits 483902380 # DTB hits 767system.cpu1.itb.misses 61638 # DTB misses 768system.cpu1.itb.accesses 483964018 # DTB accesses 769system.cpu1.numCycles 94433635768 # number of cpu cycles simulated |
| 769system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 770system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 771system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 770system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 771system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 772system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 772system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed 773system.cpu1.committedInsts 481403040 # Number of instructions committed 774system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed 775system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses 776system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses 777system.cpu1.num_func_calls 28379648 # number of times a function call or return occured 778system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls 779system.cpu1.num_int_insts 519926686 # number of integer instructions 780system.cpu1.num_fp_insts 376275 # number of float instructions 781system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read 782system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written 783system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read 784system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written 785system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read 786system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written 787system.cpu1.num_mem_refs 172748485 # number of memory refs 788system.cpu1.num_load_insts 90938541 # Number of load instructions 789system.cpu1.num_store_insts 81809944 # Number of store instructions 790system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles 791system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles 792system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles 793system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles 794system.cpu1.Branches 107246711 # Number of branches fetched | 773system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed 774system.cpu1.committedInsts 483651505 # Number of instructions committed 775system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed 776system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses 777system.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses 778system.cpu1.num_func_calls 28525698 # number of times a function call or return occured 779system.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls 780system.cpu1.num_int_insts 522328734 # number of integer instructions 781system.cpu1.num_fp_insts 379089 # number of float instructions 782system.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read 783system.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written 784system.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read 785system.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written 786system.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read 787system.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written 788system.cpu1.num_mem_refs 173588529 # number of memory refs 789system.cpu1.num_load_insts 91424864 # Number of load instructions 790system.cpu1.num_store_insts 82163665 # Number of store instructions 791system.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles 792system.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles 793system.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles 794system.cpu1.idle_fraction 0.993970 # Percentage of idle cycles 795system.cpu1.Branches 107756231 # Number of branches fetched |
| 795system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction | 796system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction |
| 796system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction 797system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction 798system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction 799system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 800system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 801system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 802system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 803system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 804system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 805system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 806system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 807system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 808system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 809system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 810system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 811system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 812system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 813system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 814system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 815system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 816system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 817system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 818system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 819system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 820system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 821system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction | 797system.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction 798system.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction 799system.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction 800system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 801system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 802system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction 803system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction 804system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction 805system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 806system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 807system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 808system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 809system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 810system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 811system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 812system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 813system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 814system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 815system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 816system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 817system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction 818system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 819system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction 820system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction 821system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 822system.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction |
| 822system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 823system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 824system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction | 823system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 824system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 825system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction |
| 825system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction 826system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction | 826system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction 827system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction |
| 827system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 828system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 828system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 829system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 829system.cpu1.op_class::total 566836400 # Class of executed instruction 830system.cpu1.dcache.tags.replacements 5963482 # number of replacements 831system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use 832system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks. 833system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks. 834system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks. | 830system.cpu1.op_class::total 569428445 # Class of executed instruction 831system.cpu1.dcache.tags.replacements 6003966 # number of replacements 832system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use 833system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. 834system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. 835system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. |
| 835system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. | 836system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. |
| 836system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor 837system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy 838system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy | 837system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor 838system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy 839system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy |
| 839system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 840system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 840system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id 841system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id | 841system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id 842system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id |
| 842system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 843system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 843system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses 844system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses 845system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits 846system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits 847system.cpu1.dcache.WriteReq_hits::cpu1.data 77626026 # number of WriteReq hits 848system.cpu1.dcache.WriteReq_hits::total 77626026 # number of WriteReq hits 849system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits 850system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits 851system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits 852system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits 853system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits 854system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits 855system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits 856system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits 857system.cpu1.dcache.demand_hits::cpu1.data 162066607 # number of demand (read+write) hits 858system.cpu1.dcache.demand_hits::total 162066607 # number of demand (read+write) hits 859system.cpu1.dcache.overall_hits::cpu1.data 162254892 # number of overall hits 860system.cpu1.dcache.overall_hits::total 162254892 # number of overall hits 861system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses 862system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses 863system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses 864system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses 865system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses 866system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses 867system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses 868system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses 869system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses 870system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses 871system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses 872system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses 873system.cpu1.dcache.demand_misses::cpu1.data 5269627 # number of demand (read+write) misses 874system.cpu1.dcache.demand_misses::total 5269627 # number of demand (read+write) misses 875system.cpu1.dcache.overall_misses::cpu1.data 6059925 # number of overall misses 876system.cpu1.dcache.overall_misses::total 6059925 # number of overall misses 877system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) 878system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) 879system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) 880system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) 881system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) 882system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) 883system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) 884system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) 885system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) 886system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) 887system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) 888system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) 889system.cpu1.dcache.demand_accesses::cpu1.data 167336234 # number of demand (read+write) accesses 890system.cpu1.dcache.demand_accesses::total 167336234 # number of demand (read+write) accesses 891system.cpu1.dcache.overall_accesses::cpu1.data 168314817 # number of overall (read+write) accesses 892system.cpu1.dcache.overall_accesses::total 168314817 # number of overall (read+write) accesses 893system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses 894system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses 895system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses 896system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses 897system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses 898system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses 899system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses 900system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses 901system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses 902system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses 903system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses 904system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses 905system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031491 # miss rate for demand accesses 906system.cpu1.dcache.demand_miss_rate::total 0.031491 # miss rate for demand accesses 907system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036004 # miss rate for overall accesses 908system.cpu1.dcache.overall_miss_rate::total 0.036004 # miss rate for overall accesses | 844system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses 845system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses 846system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits 847system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits 848system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits 849system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits 850system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits 851system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits 852system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits 853system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits 854system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits 855system.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits 856system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits 857system.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits 858system.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits 859system.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits 860system.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits 861system.cpu1.dcache.overall_hits::total 163048661 # number of overall hits 862system.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses 863system.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses 864system.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses 865system.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses 866system.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses 867system.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses 868system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses 869system.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses 870system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses 871system.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses 872system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses 873system.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses 874system.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses 875system.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses 876system.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses 877system.cpu1.dcache.overall_misses::total 6091594 # number of overall misses 878system.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses) 879system.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses) 880system.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses) 881system.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses) 882system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses) 883system.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses) 884system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses) 885system.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses) 886system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses) 887system.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses) 888system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses) 889system.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses) 890system.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses 891system.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses 892system.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses 893system.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses 894system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses 895system.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses 896system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses 897system.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses 898system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses 899system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses 900system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses 901system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses 902system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses 903system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses 904system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses 905system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses 906system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses 907system.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses 908system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses 909system.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses |
| 909system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 912system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 913system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 910system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 911system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 912system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 913system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 914system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 915system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 915system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks 916system.cpu1.dcache.writebacks::total 5963482 # number of writebacks 917system.cpu1.icache.tags.replacements 4804881 # number of replacements 918system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use 919system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. 920system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. 921system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. | 916system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks 917system.cpu1.dcache.writebacks::total 6003966 # number of writebacks 918system.cpu1.icache.tags.replacements 4799154 # number of replacements 919system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 920system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. 921system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. 922system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. |
| 922system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. | 923system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. |
| 923system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor 924system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy 925system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy | 924system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 925system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 926system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy |
| 926system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 927system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 927system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 928system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id 929system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id | 928system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 929system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 930system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id |
| 930system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 931system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 931system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses 932system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses 933system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits 934system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits 935system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits 936system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits 937system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits 938system.cpu1.icache.overall_hits::total 476906226 # number of overall hits 939system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses 940system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses 941system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses 942system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses 943system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses 944system.cpu1.icache.overall_misses::total 4805393 # number of overall misses 945system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses) 946system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses) 947system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses 948system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses 949system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses 950system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses 951system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses 952system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses 953system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses 954system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses 955system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses 956system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses | 932system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses 933system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses 934system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits 935system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits 936system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits 937system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits 938system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits 939system.cpu1.icache.overall_hits::total 479157890 # number of overall hits 940system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses 941system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses 942system.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses 943system.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses 944system.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses 945system.cpu1.icache.overall_misses::total 4799666 # number of overall misses 946system.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses) 947system.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses) 948system.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses 949system.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses 950system.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses 951system.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses 952system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses 953system.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses 954system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses 955system.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses 956system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses 957system.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses |
| 957system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 958system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 959system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 960system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 961system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 962system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 958system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 959system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 960system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 961system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 962system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 963system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 963system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 964system.cpu1.icache.writebacks::total 4804881 # number of writebacks | 964system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks 965system.cpu1.icache.writebacks::total 4799154 # number of writebacks |
| 965system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 966system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 967system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 968system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 969system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 970system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 966system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 967system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 968system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 969system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 970system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 971system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 971system.cpu1.l2cache.tags.replacements 2274505 # number of replacements 972system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use 973system.cpu1.l2cache.tags.total_refs 14355408 # Total number of references to valid blocks. 974system.cpu1.l2cache.tags.sampled_refs 2290637 # Sample count of references to valid blocks. 975system.cpu1.l2cache.tags.avg_refs 6.266994 # Average number of references to valid blocks. 976system.cpu1.l2cache.tags.warmup_cycle 9713557342500 # Cycle when the warmup percentage was hit. 977system.cpu1.l2cache.tags.occ_blocks::writebacks 13266.664229 # Average occupied blocks per requestor 978system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.449121 # Average occupied blocks per requestor 979system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.160502 # Average occupied blocks per requestor 980system.cpu1.l2cache.tags.occ_percent::writebacks 0.809733 # Average percentage of cache occupancy 981system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002713 # Average percentage of cache occupancy 982system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003611 # Average percentage of cache occupancy 983system.cpu1.l2cache.tags.occ_percent::total 0.816057 # Average percentage of cache occupancy 984system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id 985system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id 986system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 987system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id 988system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 989system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 990system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id 991system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id 992system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5867 # Occupied blocks per task id 993system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4427 # Occupied blocks per task id 994system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3923 # Occupied blocks per task id 995system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id 996system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id 997system.cpu1.l2cache.tags.tag_accesses 364664430 # Number of tag accesses 998system.cpu1.l2cache.tags.data_accesses 364664430 # Number of data accesses 999system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349739 # number of ReadReq hits 1000system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155441 # number of ReadReq hits 1001system.cpu1.l2cache.ReadReq_hits::total 505180 # number of ReadReq hits 1002system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030758 # number of WritebackDirty hits 1003system.cpu1.l2cache.WritebackDirty_hits::total 4030758 # number of WritebackDirty hits 1004system.cpu1.l2cache.WritebackClean_hits::writebacks 6737219 # number of WritebackClean hits 1005system.cpu1.l2cache.WritebackClean_hits::total 6737219 # number of WritebackClean hits 1006system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1036 # number of UpgradeReq hits 1007system.cpu1.l2cache.UpgradeReq_hits::total 1036 # number of UpgradeReq hits 1008system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606945 # number of ReadExReq hits 1009system.cpu1.l2cache.ReadExReq_hits::total 606945 # number of ReadExReq hits 1010system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338204 # number of ReadCleanReq hits 1011system.cpu1.l2cache.ReadCleanReq_hits::total 4338204 # number of ReadCleanReq hits 1012system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3075973 # number of ReadSharedReq hits 1013system.cpu1.l2cache.ReadSharedReq_hits::total 3075973 # number of ReadSharedReq hits 1014system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 162958 # number of InvalidateReq hits 1015system.cpu1.l2cache.InvalidateReq_hits::total 162958 # number of InvalidateReq hits 1016system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349739 # number of demand (read+write) hits 1017system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155441 # number of demand (read+write) hits 1018system.cpu1.l2cache.demand_hits::cpu1.inst 4338204 # number of demand (read+write) hits 1019system.cpu1.l2cache.demand_hits::cpu1.data 3682918 # number of demand (read+write) hits 1020system.cpu1.l2cache.demand_hits::total 8526302 # number of demand (read+write) hits 1021system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349739 # number of overall hits 1022system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155441 # number of overall hits 1023system.cpu1.l2cache.overall_hits::cpu1.inst 4338204 # number of overall hits 1024system.cpu1.l2cache.overall_hits::cpu1.data 3682918 # number of overall hits 1025system.cpu1.l2cache.overall_hits::total 8526302 # number of overall hits 1026system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12351 # number of ReadReq misses 1027system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9805 # number of ReadReq misses 1028system.cpu1.l2cache.ReadReq_misses::total 22156 # number of ReadReq misses 1029system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147585 # number of UpgradeReq misses 1030system.cpu1.l2cache.UpgradeReq_misses::total 147585 # number of UpgradeReq misses 1031system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158992 # number of SCUpgradeReq misses 1032system.cpu1.l2cache.SCUpgradeReq_misses::total 158992 # number of SCUpgradeReq misses 1033system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708546 # number of ReadExReq misses 1034system.cpu1.l2cache.ReadExReq_misses::total 708546 # number of ReadExReq misses 1035system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467189 # number of ReadCleanReq misses 1036system.cpu1.l2cache.ReadCleanReq_misses::total 467189 # number of ReadCleanReq misses 1037system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230120 # number of ReadSharedReq misses 1038system.cpu1.l2cache.ReadSharedReq_misses::total 1230120 # number of ReadSharedReq misses 1039system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272650 # number of InvalidateReq misses 1040system.cpu1.l2cache.InvalidateReq_misses::total 272650 # number of InvalidateReq misses 1041system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12351 # number of demand (read+write) misses 1042system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9805 # number of demand (read+write) misses 1043system.cpu1.l2cache.demand_misses::cpu1.inst 467189 # number of demand (read+write) misses 1044system.cpu1.l2cache.demand_misses::cpu1.data 1938666 # number of demand (read+write) misses 1045system.cpu1.l2cache.demand_misses::total 2428011 # number of demand (read+write) misses 1046system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12351 # number of overall misses 1047system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9805 # number of overall misses 1048system.cpu1.l2cache.overall_misses::cpu1.inst 467189 # number of overall misses 1049system.cpu1.l2cache.overall_misses::cpu1.data 1938666 # number of overall misses 1050system.cpu1.l2cache.overall_misses::total 2428011 # number of overall misses 1051system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362090 # number of ReadReq accesses(hits+misses) 1052system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165246 # number of ReadReq accesses(hits+misses) 1053system.cpu1.l2cache.ReadReq_accesses::total 527336 # number of ReadReq accesses(hits+misses) 1054system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030758 # number of WritebackDirty accesses(hits+misses) 1055system.cpu1.l2cache.WritebackDirty_accesses::total 4030758 # number of WritebackDirty accesses(hits+misses) 1056system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737219 # number of WritebackClean accesses(hits+misses) 1057system.cpu1.l2cache.WritebackClean_accesses::total 6737219 # number of WritebackClean accesses(hits+misses) 1058system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148621 # number of UpgradeReq accesses(hits+misses) 1059system.cpu1.l2cache.UpgradeReq_accesses::total 148621 # number of UpgradeReq accesses(hits+misses) 1060system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158992 # number of SCUpgradeReq accesses(hits+misses) 1061system.cpu1.l2cache.SCUpgradeReq_accesses::total 158992 # number of SCUpgradeReq accesses(hits+misses) 1062system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses) 1063system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses) 1064system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses) 1065system.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses) 1066system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses) 1067system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses) 1068system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses) 1069system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses) 1070system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362090 # number of demand (read+write) accesses 1071system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165246 # number of demand (read+write) accesses 1072system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses 1073system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses 1074system.cpu1.l2cache.demand_accesses::total 10954313 # number of demand (read+write) accesses 1075system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362090 # number of overall (read+write) accesses 1076system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165246 # number of overall (read+write) accesses 1077system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses 1078system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses 1079system.cpu1.l2cache.overall_accesses::total 10954313 # number of overall (read+write) accesses 1080system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for ReadReq accesses 1081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059336 # miss rate for ReadReq accesses 1082system.cpu1.l2cache.ReadReq_miss_rate::total 0.042015 # miss rate for ReadReq accesses 1083system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993029 # miss rate for UpgradeReq accesses 1084system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993029 # miss rate for UpgradeReq accesses | 972system.cpu1.l2cache.tags.replacements 2283161 # number of replacements 973system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use 974system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. 975system.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks. 976system.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks. 977system.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit. 978system.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor 979system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor 980system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor 981system.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy 982system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy 983system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy 984system.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy 985system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id 986system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id 987system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 988system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id 989system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 990system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 991system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id 992system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id 993system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id 994system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id 995system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id 996system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 997system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id 998system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses 999system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses 1000system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits 1001system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits 1002system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits 1003system.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits 1004system.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits 1005system.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits 1006system.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits 1007system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits 1008system.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits 1009system.cpu1.l2cache.ReadExReq_hits::cpu1.data 615614 # number of ReadExReq hits 1010system.cpu1.l2cache.ReadExReq_hits::total 615614 # number of ReadExReq hits 1011system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4333068 # number of ReadCleanReq hits 1012system.cpu1.l2cache.ReadCleanReq_hits::total 4333068 # number of ReadCleanReq hits 1013system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3106952 # number of ReadSharedReq hits 1014system.cpu1.l2cache.ReadSharedReq_hits::total 3106952 # number of ReadSharedReq hits 1015system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166128 # number of InvalidateReq hits 1016system.cpu1.l2cache.InvalidateReq_hits::total 166128 # number of InvalidateReq hits 1017system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 347777 # number of demand (read+write) hits 1018system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155733 # number of demand (read+write) hits 1019system.cpu1.l2cache.demand_hits::cpu1.inst 4333068 # number of demand (read+write) hits 1020system.cpu1.l2cache.demand_hits::cpu1.data 3722566 # number of demand (read+write) hits 1021system.cpu1.l2cache.demand_hits::total 8559144 # number of demand (read+write) hits 1022system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 347777 # number of overall hits 1023system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155733 # number of overall hits 1024system.cpu1.l2cache.overall_hits::cpu1.inst 4333068 # number of overall hits 1025system.cpu1.l2cache.overall_hits::cpu1.data 3722566 # number of overall hits 1026system.cpu1.l2cache.overall_hits::total 8559144 # number of overall hits 1027system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12333 # number of ReadReq misses 1028system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9620 # number of ReadReq misses 1029system.cpu1.l2cache.ReadReq_misses::total 21953 # number of ReadReq misses 1030system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143903 # number of UpgradeReq misses 1031system.cpu1.l2cache.UpgradeReq_misses::total 143903 # number of UpgradeReq misses 1032system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157576 # number of SCUpgradeReq misses 1033system.cpu1.l2cache.SCUpgradeReq_misses::total 157576 # number of SCUpgradeReq misses 1034system.cpu1.l2cache.ReadExReq_misses::cpu1.data 709038 # number of ReadExReq misses 1035system.cpu1.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses 1036system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 466598 # number of ReadCleanReq misses 1037system.cpu1.l2cache.ReadCleanReq_misses::total 466598 # number of ReadCleanReq misses 1038system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1225336 # number of ReadSharedReq misses 1039system.cpu1.l2cache.ReadSharedReq_misses::total 1225336 # number of ReadSharedReq misses 1040system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272085 # number of InvalidateReq misses 1041system.cpu1.l2cache.InvalidateReq_misses::total 272085 # number of InvalidateReq misses 1042system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12333 # number of demand (read+write) misses 1043system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9620 # number of demand (read+write) misses 1044system.cpu1.l2cache.demand_misses::cpu1.inst 466598 # number of demand (read+write) misses 1045system.cpu1.l2cache.demand_misses::cpu1.data 1934374 # number of demand (read+write) misses 1046system.cpu1.l2cache.demand_misses::total 2422925 # number of demand (read+write) misses 1047system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12333 # number of overall misses 1048system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9620 # number of overall misses 1049system.cpu1.l2cache.overall_misses::cpu1.inst 466598 # number of overall misses 1050system.cpu1.l2cache.overall_misses::cpu1.data 1934374 # number of overall misses 1051system.cpu1.l2cache.overall_misses::total 2422925 # number of overall misses 1052system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360110 # number of ReadReq accesses(hits+misses) 1053system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165353 # number of ReadReq accesses(hits+misses) 1054system.cpu1.l2cache.ReadReq_accesses::total 525463 # number of ReadReq accesses(hits+misses) 1055system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4070389 # number of WritebackDirty accesses(hits+misses) 1056system.cpu1.l2cache.WritebackDirty_accesses::total 4070389 # number of WritebackDirty accesses(hits+misses) 1057system.cpu1.l2cache.WritebackClean_accesses::writebacks 6732353 # number of WritebackClean accesses(hits+misses) 1058system.cpu1.l2cache.WritebackClean_accesses::total 6732353 # number of WritebackClean accesses(hits+misses) 1059system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144957 # number of UpgradeReq accesses(hits+misses) 1060system.cpu1.l2cache.UpgradeReq_accesses::total 144957 # number of UpgradeReq accesses(hits+misses) 1061system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157576 # number of SCUpgradeReq accesses(hits+misses) 1062system.cpu1.l2cache.SCUpgradeReq_accesses::total 157576 # number of SCUpgradeReq accesses(hits+misses) 1063system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1324652 # number of ReadExReq accesses(hits+misses) 1064system.cpu1.l2cache.ReadExReq_accesses::total 1324652 # number of ReadExReq accesses(hits+misses) 1065system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4799666 # number of ReadCleanReq accesses(hits+misses) 1066system.cpu1.l2cache.ReadCleanReq_accesses::total 4799666 # number of ReadCleanReq accesses(hits+misses) 1067system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4332288 # number of ReadSharedReq accesses(hits+misses) 1068system.cpu1.l2cache.ReadSharedReq_accesses::total 4332288 # number of ReadSharedReq accesses(hits+misses) 1069system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 438213 # number of InvalidateReq accesses(hits+misses) 1070system.cpu1.l2cache.InvalidateReq_accesses::total 438213 # number of InvalidateReq accesses(hits+misses) 1071system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360110 # number of demand (read+write) accesses 1072system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165353 # number of demand (read+write) accesses 1073system.cpu1.l2cache.demand_accesses::cpu1.inst 4799666 # number of demand (read+write) accesses 1074system.cpu1.l2cache.demand_accesses::cpu1.data 5656940 # number of demand (read+write) accesses 1075system.cpu1.l2cache.demand_accesses::total 10982069 # number of demand (read+write) accesses 1076system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360110 # number of overall (read+write) accesses 1077system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165353 # number of overall (read+write) accesses 1078system.cpu1.l2cache.overall_accesses::cpu1.inst 4799666 # number of overall (read+write) accesses 1079system.cpu1.l2cache.overall_accesses::cpu1.data 5656940 # number of overall (read+write) accesses 1080system.cpu1.l2cache.overall_accesses::total 10982069 # number of overall (read+write) accesses 1081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for ReadReq accesses 1082system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058179 # miss rate for ReadReq accesses 1083system.cpu1.l2cache.ReadReq_miss_rate::total 0.041778 # miss rate for ReadReq accesses 1084system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992729 # miss rate for UpgradeReq accesses 1085system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992729 # miss rate for UpgradeReq accesses |
| 1085system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1086system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1086system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1087system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1087system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538617 # miss rate for ReadExReq accesses 1088system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538617 # miss rate for ReadExReq accesses 1089system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097222 # miss rate for ReadCleanReq accesses 1090system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097222 # miss rate for ReadCleanReq accesses 1091system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285670 # miss rate for ReadSharedReq accesses 1092system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285670 # miss rate for ReadSharedReq accesses 1093system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625907 # miss rate for InvalidateReq accesses 1094system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625907 # miss rate for InvalidateReq accesses 1095system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for demand accesses 1096system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059336 # miss rate for demand accesses 1097system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097222 # miss rate for demand accesses 1098system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344861 # miss rate for demand accesses 1099system.cpu1.l2cache.demand_miss_rate::total 0.221649 # miss rate for demand accesses 1100system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for overall accesses 1101system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059336 # miss rate for overall accesses 1102system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097222 # miss rate for overall accesses 1103system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses 1104system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses | 1088system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses 1089system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses 1090system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses 1091system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses 1092system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses 1093system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses 1094system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses 1095system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses 1096system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses 1097system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses 1098system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses 1099system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses 1100system.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses 1101system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses 1102system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses 1103system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses 1104system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses 1105system.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses |
| 1105system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1106system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1107system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1108system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1109system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1110system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1106system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1107system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1108system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1109system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1110system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1111system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1111system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks 1112system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks 1113system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. 1114system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1115system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1116system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. 1117system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1118system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1119system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution 1120system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution 1121system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution 1122system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution 1123system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030758 # Transaction distribution 1124system.cpu1.toL2Bus.trans_dist::WritebackClean 6737605 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::UpgradeReq 148621 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158992 # Transaction distribution 1127system.cpu1.toL2Bus.trans_dist::UpgradeResp 307613 # Transaction distribution 1128system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution 1129system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution 1130system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution 1131system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution 1132system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution 1133system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution 1134system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) 1135system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18716020 # Packet count per connected master and slave (bytes) 1136system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) 1137system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) 1138system.cpu1.toL2Bus.pkt_count::total 34341155 # Packet count per connected master and slave (bytes) 1139system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) 1144system.cpu1.toL2Bus.snoops 5725702 # Total snoops (count) 1145system.cpu1.toL2Bus.snoop_fanout::samples 28118123 # Request fanout histogram 1146system.cpu1.toL2Bus.snoop_fanout::mean 0.072932 # Request fanout histogram 1147system.cpu1.toL2Bus.snoop_fanout::stdev 0.260049 # Request fanout histogram | 1112system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks 1113system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks 1114system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. 1115system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1116system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1117system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. 1118system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1119system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1120system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution 1121system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution 1122system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution 1123system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution 1124system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution 1127system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution 1128system.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution 1129system.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution 1130system.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution 1131system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution 1132system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution 1133system.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution 1134system.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution 1135system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes) 1136system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes) 1137system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes) 1138system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes) 1139system.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes) 1140system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes) 1143system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes) 1144system.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes) 1145system.cpu1.toL2Bus.snoops 5687998 # Total snoops (count) 1146system.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram 1147system.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram 1148system.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram |
| 1148system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1149system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1149system.cpu1.toL2Bus.snoop_fanout::0 26067606 92.71% 92.71% # Request fanout histogram 1150system.cpu1.toL2Bus.snoop_fanout::1 2050333 7.29% 100.00% # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::2 184 0.00% 100.00% # Request fanout histogram | 1150system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram 1152system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram |
| 1152system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1153system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1154system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1153system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1154system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1155system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1155system.cpu1.toL2Bus.snoop_fanout::total 28118123 # Request fanout histogram 1156system.iobus.trans_dist::ReadReq 40311 # Transaction distribution 1157system.iobus.trans_dist::ReadResp 40311 # Transaction distribution | 1156system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram 1157system.iobus.trans_dist::ReadReq 40301 # Transaction distribution 1158system.iobus.trans_dist::ReadResp 40301 # Transaction distribution |
| 1158system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1159system.iobus.trans_dist::WriteResp 136636 # Transaction distribution | 1159system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1160system.iobus.trans_dist::WriteResp 136636 # Transaction distribution |
| 1160system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) | 1161system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) |
| 1161system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) | 1162system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) |
| 1173system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) | 1174system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) |
| 1176system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 1177system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 1178system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) | 1179system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) |
| 1180system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) | 1181system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) |
| 1192system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) | 1193system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) |
| 1195system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 1196system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 1197system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes) 1198system.iocache.tags.replacements 115596 # number of replacements 1199system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use | 1198system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) 1199system.iocache.tags.replacements 115590 # number of replacements 1200system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use |
| 1200system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 1201system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 1201system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. | 1202system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. |
| 1202system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 1203system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 1203system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 1204system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor 1205system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor 1206system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy 1207system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy 1208system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy | 1204system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. 1205system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor 1206system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor 1207system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy 1208system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy 1209system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy |
| 1209system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1210system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1211system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1210system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1211system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1212system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1212system.iocache.tags.tag_accesses 1040892 # Number of tag accesses 1213system.iocache.tags.data_accesses 1040892 # Number of data accesses | 1213system.iocache.tags.tag_accesses 1040838 # Number of tag accesses 1214system.iocache.tags.data_accesses 1040838 # Number of data accesses |
| 1214system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 1215system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 1215system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses 1216system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses | 1216system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 1217system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses |
| 1217system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1218system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1219system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1220system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1221system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1218system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1219system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1220system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1221system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1222system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1222system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses 1223system.iocache.demand_misses::total 115655 # number of demand (read+write) misses | 1223system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses 1224system.iocache.demand_misses::total 115649 # number of demand (read+write) misses |
| 1224system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1225system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1225system.iocache.overall_misses::realview.ide 115615 # number of overall misses 1226system.iocache.overall_misses::total 115655 # number of overall misses | 1226system.iocache.overall_misses::realview.ide 115609 # number of overall misses 1227system.iocache.overall_misses::total 115649 # number of overall misses |
| 1227system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 1228system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 1228system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) 1229system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) | 1229system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 1230system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) |
| 1230system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1231system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1232system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1233system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1234system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1231system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1232system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1233system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1234system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1235system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1235system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses 1236system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses | 1236system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses 1237system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses |
| 1237system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1238system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1238system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses 1239system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses | 1239system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses 1240system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses |
| 1240system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1241system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1242system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1243system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1244system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1245system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1246system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1247system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1253system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1254system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1255system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1256system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1257system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1258system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1259system.iocache.writebacks::writebacks 106694 # number of writebacks 1260system.iocache.writebacks::total 106694 # number of writebacks | 1241system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1242system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1243system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1244system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1245system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1246system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1247system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1248system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1254system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1255system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1256system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1257system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1258system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1259system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1260system.iocache.writebacks::writebacks 106694 # number of writebacks 1261system.iocache.writebacks::total 106694 # number of writebacks |
| 1261system.l2c.tags.replacements 1766126 # number of replacements 1262system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use 1263system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. 1264system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. 1265system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. | 1262system.l2c.tags.replacements 1772279 # number of replacements 1263system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use 1264system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. 1265system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. 1266system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. |
| 1266system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. | 1267system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. |
| 1267system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor 1268system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor 1269system.l2c.tags.occ_blocks::cpu0.itb.walker 102.298868 # Average occupied blocks per requestor 1270system.l2c.tags.occ_blocks::cpu0.inst 3405.442592 # Average occupied blocks per requestor 1271system.l2c.tags.occ_blocks::cpu0.data 8003.318713 # Average occupied blocks per requestor 1272system.l2c.tags.occ_blocks::cpu1.dtb.walker 244.723732 # Average occupied blocks per requestor 1273system.l2c.tags.occ_blocks::cpu1.itb.walker 389.512702 # Average occupied blocks per requestor 1274system.l2c.tags.occ_blocks::cpu1.inst 2881.151775 # Average occupied blocks per requestor 1275system.l2c.tags.occ_blocks::cpu1.data 13153.170652 # Average occupied blocks per requestor 1276system.l2c.tags.occ_percent::writebacks 0.531906 # Average percentage of cache occupancy 1277system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001038 # Average percentage of cache occupancy 1278system.l2c.tags.occ_percent::cpu0.itb.walker 0.001561 # Average percentage of cache occupancy 1279system.l2c.tags.occ_percent::cpu0.inst 0.051963 # Average percentage of cache occupancy 1280system.l2c.tags.occ_percent::cpu0.data 0.122121 # Average percentage of cache occupancy 1281system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003734 # Average percentage of cache occupancy 1282system.l2c.tags.occ_percent::cpu1.itb.walker 0.005943 # Average percentage of cache occupancy 1283system.l2c.tags.occ_percent::cpu1.inst 0.043963 # Average percentage of cache occupancy 1284system.l2c.tags.occ_percent::cpu1.data 0.200701 # Average percentage of cache occupancy 1285system.l2c.tags.occ_percent::total 0.962930 # Average percentage of cache occupancy 1286system.l2c.tags.occ_task_id_blocks::1023 203 # Occupied blocks per task id 1287system.l2c.tags.occ_task_id_blocks::1024 59170 # Occupied blocks per task id 1288system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1289system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id 1290system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1291system.l2c.tags.age_task_id_blocks_1024::1 472 # Occupied blocks per task id 1292system.l2c.tags.age_task_id_blocks_1024::2 3156 # Occupied blocks per task id 1293system.l2c.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id 1294system.l2c.tags.age_task_id_blocks_1024::4 50220 # Occupied blocks per task id 1295system.l2c.tags.occ_task_id_percent::1023 0.003098 # Percentage of cache occupancy per task id 1296system.l2c.tags.occ_task_id_percent::1024 0.902863 # Percentage of cache occupancy per task id 1297system.l2c.tags.tag_accesses 73355182 # Number of tag accesses 1298system.l2c.tags.data_accesses 73355182 # Number of data accesses 1299system.l2c.WritebackDirty_hits::writebacks 2757627 # number of WritebackDirty hits 1300system.l2c.WritebackDirty_hits::total 2757627 # number of WritebackDirty hits 1301system.l2c.UpgradeReq_hits::cpu0.data 19019 # number of UpgradeReq hits 1302system.l2c.UpgradeReq_hits::cpu1.data 16164 # number of UpgradeReq hits 1303system.l2c.UpgradeReq_hits::total 35183 # number of UpgradeReq hits 1304system.l2c.SCUpgradeReq_hits::cpu0.data 2641 # number of SCUpgradeReq hits 1305system.l2c.SCUpgradeReq_hits::cpu1.data 2463 # number of SCUpgradeReq hits 1306system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits 1307system.l2c.ReadExReq_hits::cpu0.data 198159 # number of ReadExReq hits 1308system.l2c.ReadExReq_hits::cpu1.data 177179 # number of ReadExReq hits 1309system.l2c.ReadExReq_hits::total 375338 # number of ReadExReq hits 1310system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6315 # number of ReadSharedReq hits 1311system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4649 # number of ReadSharedReq hits 1312system.l2c.ReadSharedReq_hits::cpu0.inst 438189 # number of ReadSharedReq hits 1313system.l2c.ReadSharedReq_hits::cpu0.data 723007 # number of ReadSharedReq hits 1314system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5487 # number of ReadSharedReq hits 1315system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3779 # number of ReadSharedReq hits 1316system.l2c.ReadSharedReq_hits::cpu1.inst 426355 # number of ReadSharedReq hits 1317system.l2c.ReadSharedReq_hits::cpu1.data 685222 # number of ReadSharedReq hits 1318system.l2c.ReadSharedReq_hits::total 2293003 # number of ReadSharedReq hits 1319system.l2c.InvalidateReq_hits::cpu0.data 118931 # number of InvalidateReq hits 1320system.l2c.InvalidateReq_hits::cpu1.data 103897 # number of InvalidateReq hits 1321system.l2c.InvalidateReq_hits::total 222828 # number of InvalidateReq hits 1322system.l2c.demand_hits::cpu0.dtb.walker 6315 # number of demand (read+write) hits 1323system.l2c.demand_hits::cpu0.itb.walker 4649 # number of demand (read+write) hits 1324system.l2c.demand_hits::cpu0.inst 438189 # number of demand (read+write) hits 1325system.l2c.demand_hits::cpu0.data 921166 # number of demand (read+write) hits 1326system.l2c.demand_hits::cpu1.dtb.walker 5487 # number of demand (read+write) hits 1327system.l2c.demand_hits::cpu1.itb.walker 3779 # number of demand (read+write) hits 1328system.l2c.demand_hits::cpu1.inst 426355 # number of demand (read+write) hits 1329system.l2c.demand_hits::cpu1.data 862401 # number of demand (read+write) hits 1330system.l2c.demand_hits::total 2668341 # number of demand (read+write) hits 1331system.l2c.overall_hits::cpu0.dtb.walker 6315 # number of overall hits 1332system.l2c.overall_hits::cpu0.itb.walker 4649 # number of overall hits 1333system.l2c.overall_hits::cpu0.inst 438189 # number of overall hits 1334system.l2c.overall_hits::cpu0.data 921166 # number of overall hits 1335system.l2c.overall_hits::cpu1.dtb.walker 5487 # number of overall hits 1336system.l2c.overall_hits::cpu1.itb.walker 3779 # number of overall hits 1337system.l2c.overall_hits::cpu1.inst 426355 # number of overall hits 1338system.l2c.overall_hits::cpu1.data 862401 # number of overall hits 1339system.l2c.overall_hits::total 2668341 # number of overall hits 1340system.l2c.UpgradeReq_misses::cpu0.data 65379 # number of UpgradeReq misses 1341system.l2c.UpgradeReq_misses::cpu1.data 61938 # number of UpgradeReq misses 1342system.l2c.UpgradeReq_misses::total 127317 # number of UpgradeReq misses 1343system.l2c.SCUpgradeReq_misses::cpu0.data 6666 # number of SCUpgradeReq misses 1344system.l2c.SCUpgradeReq_misses::cpu1.data 6353 # number of SCUpgradeReq misses 1345system.l2c.SCUpgradeReq_misses::total 13019 # number of SCUpgradeReq misses 1346system.l2c.ReadExReq_misses::cpu0.data 385718 # number of ReadExReq misses 1347system.l2c.ReadExReq_misses::cpu1.data 415753 # number of ReadExReq misses 1348system.l2c.ReadExReq_misses::total 801471 # number of ReadExReq misses 1349system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2451 # number of ReadSharedReq misses 1350system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses 1351system.l2c.ReadSharedReq_misses::cpu0.inst 57980 # number of ReadSharedReq misses 1352system.l2c.ReadSharedReq_misses::cpu0.data 180523 # number of ReadSharedReq misses 1353system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3403 # number of ReadSharedReq misses 1354system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3345 # number of ReadSharedReq misses 1355system.l2c.ReadSharedReq_misses::cpu1.inst 40834 # number of ReadSharedReq misses 1356system.l2c.ReadSharedReq_misses::cpu1.data 186956 # number of ReadSharedReq misses 1357system.l2c.ReadSharedReq_misses::total 477545 # number of ReadSharedReq misses 1358system.l2c.InvalidateReq_misses::cpu0.data 477269 # number of InvalidateReq misses 1359system.l2c.InvalidateReq_misses::cpu1.data 162394 # number of InvalidateReq misses 1360system.l2c.InvalidateReq_misses::total 639663 # number of InvalidateReq misses 1361system.l2c.demand_misses::cpu0.dtb.walker 2451 # number of demand (read+write) misses 1362system.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses 1363system.l2c.demand_misses::cpu0.inst 57980 # number of demand (read+write) misses 1364system.l2c.demand_misses::cpu0.data 566241 # number of demand (read+write) misses 1365system.l2c.demand_misses::cpu1.dtb.walker 3403 # number of demand (read+write) misses 1366system.l2c.demand_misses::cpu1.itb.walker 3345 # number of demand (read+write) misses 1367system.l2c.demand_misses::cpu1.inst 40834 # number of demand (read+write) misses 1368system.l2c.demand_misses::cpu1.data 602709 # number of demand (read+write) misses 1369system.l2c.demand_misses::total 1279016 # number of demand (read+write) misses 1370system.l2c.overall_misses::cpu0.dtb.walker 2451 # number of overall misses 1371system.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses 1372system.l2c.overall_misses::cpu0.inst 57980 # number of overall misses 1373system.l2c.overall_misses::cpu0.data 566241 # number of overall misses 1374system.l2c.overall_misses::cpu1.dtb.walker 3403 # number of overall misses 1375system.l2c.overall_misses::cpu1.itb.walker 3345 # number of overall misses 1376system.l2c.overall_misses::cpu1.inst 40834 # number of overall misses 1377system.l2c.overall_misses::cpu1.data 602709 # number of overall misses 1378system.l2c.overall_misses::total 1279016 # number of overall misses 1379system.l2c.WritebackDirty_accesses::writebacks 2757627 # number of WritebackDirty accesses(hits+misses) 1380system.l2c.WritebackDirty_accesses::total 2757627 # number of WritebackDirty accesses(hits+misses) 1381system.l2c.UpgradeReq_accesses::cpu0.data 84398 # number of UpgradeReq accesses(hits+misses) 1382system.l2c.UpgradeReq_accesses::cpu1.data 78102 # number of UpgradeReq accesses(hits+misses) 1383system.l2c.UpgradeReq_accesses::total 162500 # number of UpgradeReq accesses(hits+misses) 1384system.l2c.SCUpgradeReq_accesses::cpu0.data 9307 # number of SCUpgradeReq accesses(hits+misses) 1385system.l2c.SCUpgradeReq_accesses::cpu1.data 8816 # number of SCUpgradeReq accesses(hits+misses) 1386system.l2c.SCUpgradeReq_accesses::total 18123 # number of SCUpgradeReq accesses(hits+misses) 1387system.l2c.ReadExReq_accesses::cpu0.data 583877 # number of ReadExReq accesses(hits+misses) 1388system.l2c.ReadExReq_accesses::cpu1.data 592932 # number of ReadExReq accesses(hits+misses) 1389system.l2c.ReadExReq_accesses::total 1176809 # number of ReadExReq accesses(hits+misses) 1390system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8766 # number of ReadSharedReq accesses(hits+misses) 1391system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6702 # number of ReadSharedReq accesses(hits+misses) 1392system.l2c.ReadSharedReq_accesses::cpu0.inst 496169 # number of ReadSharedReq accesses(hits+misses) 1393system.l2c.ReadSharedReq_accesses::cpu0.data 903530 # number of ReadSharedReq accesses(hits+misses) 1394system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8890 # number of ReadSharedReq accesses(hits+misses) 1395system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7124 # number of ReadSharedReq accesses(hits+misses) 1396system.l2c.ReadSharedReq_accesses::cpu1.inst 467189 # number of ReadSharedReq accesses(hits+misses) 1397system.l2c.ReadSharedReq_accesses::cpu1.data 872178 # number of ReadSharedReq accesses(hits+misses) 1398system.l2c.ReadSharedReq_accesses::total 2770548 # number of ReadSharedReq accesses(hits+misses) 1399system.l2c.InvalidateReq_accesses::cpu0.data 596200 # number of InvalidateReq accesses(hits+misses) 1400system.l2c.InvalidateReq_accesses::cpu1.data 266291 # number of InvalidateReq accesses(hits+misses) 1401system.l2c.InvalidateReq_accesses::total 862491 # number of InvalidateReq accesses(hits+misses) 1402system.l2c.demand_accesses::cpu0.dtb.walker 8766 # number of demand (read+write) accesses 1403system.l2c.demand_accesses::cpu0.itb.walker 6702 # number of demand (read+write) accesses 1404system.l2c.demand_accesses::cpu0.inst 496169 # number of demand (read+write) accesses 1405system.l2c.demand_accesses::cpu0.data 1487407 # number of demand (read+write) accesses 1406system.l2c.demand_accesses::cpu1.dtb.walker 8890 # number of demand (read+write) accesses 1407system.l2c.demand_accesses::cpu1.itb.walker 7124 # number of demand (read+write) accesses 1408system.l2c.demand_accesses::cpu1.inst 467189 # number of demand (read+write) accesses 1409system.l2c.demand_accesses::cpu1.data 1465110 # number of demand (read+write) accesses 1410system.l2c.demand_accesses::total 3947357 # number of demand (read+write) accesses 1411system.l2c.overall_accesses::cpu0.dtb.walker 8766 # number of overall (read+write) accesses 1412system.l2c.overall_accesses::cpu0.itb.walker 6702 # number of overall (read+write) accesses 1413system.l2c.overall_accesses::cpu0.inst 496169 # number of overall (read+write) accesses 1414system.l2c.overall_accesses::cpu0.data 1487407 # number of overall (read+write) accesses 1415system.l2c.overall_accesses::cpu1.dtb.walker 8890 # number of overall (read+write) accesses 1416system.l2c.overall_accesses::cpu1.itb.walker 7124 # number of overall (read+write) accesses 1417system.l2c.overall_accesses::cpu1.inst 467189 # number of overall (read+write) accesses 1418system.l2c.overall_accesses::cpu1.data 1465110 # number of overall (read+write) accesses 1419system.l2c.overall_accesses::total 3947357 # number of overall (read+write) accesses 1420system.l2c.UpgradeReq_miss_rate::cpu0.data 0.774651 # miss rate for UpgradeReq accesses 1421system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793040 # miss rate for UpgradeReq accesses 1422system.l2c.UpgradeReq_miss_rate::total 0.783489 # miss rate for UpgradeReq accesses 1423system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.716235 # miss rate for SCUpgradeReq accesses 1424system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720622 # miss rate for SCUpgradeReq accesses 1425system.l2c.SCUpgradeReq_miss_rate::total 0.718369 # miss rate for SCUpgradeReq accesses 1426system.l2c.ReadExReq_miss_rate::cpu0.data 0.660615 # miss rate for ReadExReq accesses 1427system.l2c.ReadExReq_miss_rate::cpu1.data 0.701182 # miss rate for ReadExReq accesses 1428system.l2c.ReadExReq_miss_rate::total 0.681054 # miss rate for ReadExReq accesses 1429system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for ReadSharedReq accesses 1430system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.306326 # miss rate for ReadSharedReq accesses 1431system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.116855 # miss rate for ReadSharedReq accesses 1432system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.199797 # miss rate for ReadSharedReq accesses 1433system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for ReadSharedReq accesses 1434system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.469540 # miss rate for ReadSharedReq accesses 1435system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087404 # miss rate for ReadSharedReq accesses 1436system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.214355 # miss rate for ReadSharedReq accesses 1437system.l2c.ReadSharedReq_miss_rate::total 0.172365 # miss rate for ReadSharedReq accesses 1438system.l2c.InvalidateReq_miss_rate::cpu0.data 0.800518 # miss rate for InvalidateReq accesses 1439system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609837 # miss rate for InvalidateReq accesses 1440system.l2c.InvalidateReq_miss_rate::total 0.741646 # miss rate for InvalidateReq accesses 1441system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for demand accesses 1442system.l2c.demand_miss_rate::cpu0.itb.walker 0.306326 # miss rate for demand accesses 1443system.l2c.demand_miss_rate::cpu0.inst 0.116855 # miss rate for demand accesses 1444system.l2c.demand_miss_rate::cpu0.data 0.380690 # miss rate for demand accesses 1445system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for demand accesses 1446system.l2c.demand_miss_rate::cpu1.itb.walker 0.469540 # miss rate for demand accesses 1447system.l2c.demand_miss_rate::cpu1.inst 0.087404 # miss rate for demand accesses 1448system.l2c.demand_miss_rate::cpu1.data 0.411375 # miss rate for demand accesses 1449system.l2c.demand_miss_rate::total 0.324018 # miss rate for demand accesses 1450system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for overall accesses 1451system.l2c.overall_miss_rate::cpu0.itb.walker 0.306326 # miss rate for overall accesses 1452system.l2c.overall_miss_rate::cpu0.inst 0.116855 # miss rate for overall accesses 1453system.l2c.overall_miss_rate::cpu0.data 0.380690 # miss rate for overall accesses 1454system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for overall accesses 1455system.l2c.overall_miss_rate::cpu1.itb.walker 0.469540 # miss rate for overall accesses 1456system.l2c.overall_miss_rate::cpu1.inst 0.087404 # miss rate for overall accesses 1457system.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses 1458system.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses | 1268system.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor 1269system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor 1270system.l2c.tags.occ_blocks::cpu0.itb.walker 43.277467 # Average occupied blocks per requestor 1271system.l2c.tags.occ_blocks::cpu0.inst 3264.617227 # Average occupied blocks per requestor 1272system.l2c.tags.occ_blocks::cpu0.data 6940.607740 # Average occupied blocks per requestor 1273system.l2c.tags.occ_blocks::cpu1.dtb.walker 274.307726 # Average occupied blocks per requestor 1274system.l2c.tags.occ_blocks::cpu1.itb.walker 426.439632 # Average occupied blocks per requestor 1275system.l2c.tags.occ_blocks::cpu1.inst 2871.138387 # Average occupied blocks per requestor 1276system.l2c.tags.occ_blocks::cpu1.data 14482.680343 # Average occupied blocks per requestor 1277system.l2c.tags.occ_percent::writebacks 0.531803 # Average percentage of cache occupancy 1278system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000545 # Average percentage of cache occupancy 1279system.l2c.tags.occ_percent::cpu0.itb.walker 0.000660 # Average percentage of cache occupancy 1280system.l2c.tags.occ_percent::cpu0.inst 0.049814 # Average percentage of cache occupancy 1281system.l2c.tags.occ_percent::cpu0.data 0.105905 # Average percentage of cache occupancy 1282system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004186 # Average percentage of cache occupancy 1283system.l2c.tags.occ_percent::cpu1.itb.walker 0.006507 # Average percentage of cache occupancy 1284system.l2c.tags.occ_percent::cpu1.inst 0.043810 # Average percentage of cache occupancy 1285system.l2c.tags.occ_percent::cpu1.data 0.220988 # Average percentage of cache occupancy 1286system.l2c.tags.occ_percent::total 0.964219 # Average percentage of cache occupancy 1287system.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id 1288system.l2c.tags.occ_task_id_blocks::1024 59404 # Occupied blocks per task id 1289system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 1290system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id 1291system.l2c.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 1292system.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 1293system.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id 1294system.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id 1295system.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id 1296system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id 1297system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id 1298system.l2c.tags.tag_accesses 73419992 # Number of tag accesses 1299system.l2c.tags.data_accesses 73419992 # Number of data accesses 1300system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits 1301system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits 1302system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits 1303system.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits 1304system.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits 1305system.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits 1306system.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits 1307system.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits 1308system.l2c.ReadExReq_hits::cpu0.data 200286 # number of ReadExReq hits 1309system.l2c.ReadExReq_hits::cpu1.data 176214 # number of ReadExReq hits 1310system.l2c.ReadExReq_hits::total 376500 # number of ReadExReq hits 1311system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6410 # number of ReadSharedReq hits 1312system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4846 # number of ReadSharedReq hits 1313system.l2c.ReadSharedReq_hits::cpu0.inst 439050 # number of ReadSharedReq hits 1314system.l2c.ReadSharedReq_hits::cpu0.data 727042 # number of ReadSharedReq hits 1315system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5703 # number of ReadSharedReq hits 1316system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3689 # number of ReadSharedReq hits 1317system.l2c.ReadSharedReq_hits::cpu1.inst 424901 # number of ReadSharedReq hits 1318system.l2c.ReadSharedReq_hits::cpu1.data 685160 # number of ReadSharedReq hits 1319system.l2c.ReadSharedReq_hits::total 2296801 # number of ReadSharedReq hits 1320system.l2c.InvalidateReq_hits::cpu0.data 115689 # number of InvalidateReq hits 1321system.l2c.InvalidateReq_hits::cpu1.data 102800 # number of InvalidateReq hits 1322system.l2c.InvalidateReq_hits::total 218489 # number of InvalidateReq hits 1323system.l2c.demand_hits::cpu0.dtb.walker 6410 # number of demand (read+write) hits 1324system.l2c.demand_hits::cpu0.itb.walker 4846 # number of demand (read+write) hits 1325system.l2c.demand_hits::cpu0.inst 439050 # number of demand (read+write) hits 1326system.l2c.demand_hits::cpu0.data 927328 # number of demand (read+write) hits 1327system.l2c.demand_hits::cpu1.dtb.walker 5703 # number of demand (read+write) hits 1328system.l2c.demand_hits::cpu1.itb.walker 3689 # number of demand (read+write) hits 1329system.l2c.demand_hits::cpu1.inst 424901 # number of demand (read+write) hits 1330system.l2c.demand_hits::cpu1.data 861374 # number of demand (read+write) hits 1331system.l2c.demand_hits::total 2673301 # number of demand (read+write) hits 1332system.l2c.overall_hits::cpu0.dtb.walker 6410 # number of overall hits 1333system.l2c.overall_hits::cpu0.itb.walker 4846 # number of overall hits 1334system.l2c.overall_hits::cpu0.inst 439050 # number of overall hits 1335system.l2c.overall_hits::cpu0.data 927328 # number of overall hits 1336system.l2c.overall_hits::cpu1.dtb.walker 5703 # number of overall hits 1337system.l2c.overall_hits::cpu1.itb.walker 3689 # number of overall hits 1338system.l2c.overall_hits::cpu1.inst 424901 # number of overall hits 1339system.l2c.overall_hits::cpu1.data 861374 # number of overall hits 1340system.l2c.overall_hits::total 2673301 # number of overall hits 1341system.l2c.UpgradeReq_misses::cpu0.data 64906 # number of UpgradeReq misses 1342system.l2c.UpgradeReq_misses::cpu1.data 60031 # number of UpgradeReq misses 1343system.l2c.UpgradeReq_misses::total 124937 # number of UpgradeReq misses 1344system.l2c.SCUpgradeReq_misses::cpu0.data 6479 # number of SCUpgradeReq misses 1345system.l2c.SCUpgradeReq_misses::cpu1.data 6386 # number of SCUpgradeReq misses 1346system.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses 1347system.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses 1348system.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses 1349system.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses 1350system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses 1351system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses 1352system.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses 1353system.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses 1354system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses 1355system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses 1356system.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses 1357system.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses 1358system.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses 1359system.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses 1360system.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses 1361system.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses 1362system.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses 1363system.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses 1364system.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses 1365system.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses 1366system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses 1367system.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses 1368system.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses 1369system.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses 1370system.l2c.demand_misses::total 1278569 # number of demand (read+write) misses 1371system.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses 1372system.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses 1373system.l2c.overall_misses::cpu0.inst 58179 # number of overall misses 1374system.l2c.overall_misses::cpu0.data 555623 # number of overall misses 1375system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses 1376system.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses 1377system.l2c.overall_misses::cpu1.inst 41697 # number of overall misses 1378system.l2c.overall_misses::cpu1.data 611829 # number of overall misses 1379system.l2c.overall_misses::total 1278569 # number of overall misses 1380system.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses) 1381system.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses) 1382system.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses) 1383system.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses) 1384system.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses) 1385system.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses) 1386system.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses) 1387system.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses) 1388system.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses) 1389system.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses) 1390system.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses) 1391system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses) 1392system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses) 1393system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) 1394system.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses) 1395system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses) 1396system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses) 1397system.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses) 1398system.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses) 1399system.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses) 1400system.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses) 1401system.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses) 1402system.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses) 1403system.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses 1404system.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses 1405system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses 1406system.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses 1407system.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses 1408system.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses 1409system.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses 1410system.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses 1411system.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses 1412system.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses 1413system.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses 1414system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses 1415system.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses 1416system.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses 1417system.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses 1418system.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses 1419system.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses 1420system.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses 1421system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses 1422system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses 1423system.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses 1424system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses 1425system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses 1426system.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses 1427system.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses 1428system.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses 1429system.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses 1430system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses 1431system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses 1432system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses 1433system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses 1434system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses 1435system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses 1436system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses 1437system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses 1438system.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses 1439system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses 1440system.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses 1441system.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses 1442system.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses 1443system.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses 1444system.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses 1445system.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses 1446system.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses 1447system.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses 1448system.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses 1449system.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses 1450system.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses 1451system.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses 1452system.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses 1453system.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses 1454system.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses 1455system.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses 1456system.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses 1457system.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses 1458system.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses 1459system.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses |
| 1459system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1460system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1461system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1462system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1463system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1464system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1460system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1461system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1462system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1463system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1464system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1465system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1465system.l2c.writebacks::writebacks 1473799 # number of writebacks 1466system.l2c.writebacks::total 1473799 # number of writebacks 1467system.membus.trans_dist::ReadReq 82185 # Transaction distribution 1468system.membus.trans_dist::ReadResp 568654 # Transaction distribution 1469system.membus.trans_dist::WriteReq 38847 # Transaction distribution 1470system.membus.trans_dist::WriteResp 38847 # Transaction distribution 1471system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution 1472system.membus.trans_dist::CleanEvict 246676 # Transaction distribution 1473system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution 1474system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution 1475system.membus.trans_dist::UpgradeResp 162598 # Transaction distribution 1476system.membus.trans_dist::ReadExReq 787734 # Transaction distribution 1477system.membus.trans_dist::ReadExResp 783864 # Transaction distribution 1478system.membus.trans_dist::ReadSharedReq 486469 # Transaction distribution 1479system.membus.trans_dist::InvalidateReq 741739 # Transaction distribution 1480system.membus.trans_dist::InvalidateResp 741739 # Transaction distribution 1481system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) | 1466system.l2c.writebacks::writebacks 1477304 # number of writebacks 1467system.l2c.writebacks::total 1477304 # number of writebacks 1468system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. 1469system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1470system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1471system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1472system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1473system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1474system.membus.trans_dist::ReadReq 82119 # Transaction distribution 1475system.membus.trans_dist::ReadResp 569484 # Transaction distribution 1476system.membus.trans_dist::WriteReq 38800 # Transaction distribution 1477system.membus.trans_dist::WriteResp 38800 # Transaction distribution 1478system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution 1479system.membus.trans_dist::CleanEvict 246737 # Transaction distribution 1480system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution 1481system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution 1482system.membus.trans_dist::UpgradeResp 157952 # Transaction distribution 1483system.membus.trans_dist::ReadExReq 787861 # Transaction distribution 1484system.membus.trans_dist::ReadExResp 784470 # Transaction distribution 1485system.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution 1486system.membus.trans_dist::InvalidateReq 742728 # Transaction distribution 1487system.membus.trans_dist::InvalidateResp 742728 # Transaction distribution 1488system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) |
| 1482system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) | 1489system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) |
| 1483system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) 1484system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6419962 # Packet count per connected master and slave (bytes) 1485system.membus.pkt_count_system.l2c.mem_side::total 6570380 # Packet count per connected master and slave (bytes) 1486system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) 1487system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) 1488system.membus.pkt_count::total 6917286 # Packet count per connected master and slave (bytes) 1489system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) | 1490system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes) 1491system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes) 1492system.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes) 1493system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) 1494system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) 1495system.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes) 1496system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) |
| 1490system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) | 1497system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) |
| 1491system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) 1492system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175247068 # Cumulative packet size per connected master and slave (bytes) 1493system.membus.pkt_size_system.l2c.mem_side::total 175458447 # Cumulative packet size per connected master and slave (bytes) 1494system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) 1495system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) 1496system.membus.pkt_size::total 182857999 # Cumulative packet size per connected master and slave (bytes) | 1498system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes) 1499system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes) 1500system.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes) 1501system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) 1502system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) 1503system.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes) |
| 1497system.membus.snoops 0 # Total snoops (count) | 1504system.membus.snoops 0 # Total snoops (count) |
| 1498system.membus.snoop_fanout::samples 4621584 # Request fanout histogram 1499system.membus.snoop_fanout::mean 1 # Request fanout histogram 1500system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1505system.membus.snoop_fanout::samples 4612344 # Request fanout histogram 1506system.membus.snoop_fanout::mean 0.007156 # Request fanout histogram 1507system.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram |
| 1501system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1508system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1502system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1503system.membus.snoop_fanout::1 4621584 100.00% 100.00% # Request fanout histogram | 1509system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram 1510system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram |
| 1504system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1505system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1511system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1512system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1506system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1513system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1507system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1514system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1508system.membus.snoop_fanout::total 4621584 # Request fanout histogram | 1515system.membus.snoop_fanout::total 4612344 # Request fanout histogram |
| 1509system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1510system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1511system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1512system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1513system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1514system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1515system.realview.ethernet.txBytes 966 # Bytes Transmitted 1516system.realview.ethernet.txPackets 3 # Number of Packets Transmitted --- 36 unchanged lines hidden (view full) --- 1553system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1554system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1555system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1556system.realview.ethernet.droppedPackets 0 # number of packets dropped 1557system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1558system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1559system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1560system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1516system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1517system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1518system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1519system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1520system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1521system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1522system.realview.ethernet.txBytes 966 # Bytes Transmitted 1523system.realview.ethernet.txPackets 3 # Number of Packets Transmitted --- 36 unchanged lines hidden (view full) --- 1560system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1561system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1562system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1563system.realview.ethernet.droppedPackets 0 # number of packets dropped 1564system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1565system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1566system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1567system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1561system.toL2Bus.snoop_filter.tot_requests 11149977 # Total number of requests made to the snoop filter. 1562system.toL2Bus.snoop_filter.hit_single_requests 5745476 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1563system.toL2Bus.snoop_filter.hit_multi_requests 1663139 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1564system.toL2Bus.snoop_filter.tot_snoops 131712 # Total number of snoops made to the snoop filter. 1565system.toL2Bus.snoop_filter.hit_single_snoops 118684 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1566system.toL2Bus.snoop_filter.hit_multi_snoops 13028 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1567system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution 1568system.toL2Bus.trans_dist::ReadResp 3554361 # Transaction distribution 1569system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution 1570system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution 1571system.toL2Bus.trans_dist::WritebackDirty 2757627 # Transaction distribution 1572system.toL2Bus.trans_dist::CleanEvict 2018256 # Transaction distribution 1573system.toL2Bus.trans_dist::UpgradeReq 359820 # Transaction distribution 1574system.toL2Bus.trans_dist::SCUpgradeReq 315646 # Transaction distribution 1575system.toL2Bus.trans_dist::UpgradeResp 675466 # Transaction distribution 1576system.toL2Bus.trans_dist::ReadExReq 1363961 # Transaction distribution 1577system.toL2Bus.trans_dist::ReadExResp 1363961 # Transaction distribution 1578system.toL2Bus.trans_dist::ReadSharedReq 3472174 # Transaction distribution 1579system.toL2Bus.trans_dist::InvalidateReq 862491 # Transaction distribution 1580system.toL2Bus.trans_dist::InvalidateResp 862491 # Transaction distribution 1581system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9530168 # Packet count per connected master and slave (bytes) 1582system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8235967 # Packet count per connected master and slave (bytes) 1583system.toL2Bus.pkt_count::total 17766135 # Packet count per connected master and slave (bytes) 1584system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255951612 # Cumulative packet size per connected master and slave (bytes) 1585system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 230454307 # Cumulative packet size per connected master and slave (bytes) 1586system.toL2Bus.pkt_size::total 486405919 # Cumulative packet size per connected master and slave (bytes) 1587system.toL2Bus.snoops 1999071 # Total snoops (count) 1588system.toL2Bus.snoop_fanout::samples 13268387 # Request fanout histogram 1589system.toL2Bus.snoop_fanout::mean 0.283691 # Request fanout histogram 1590system.toL2Bus.snoop_fanout::stdev 0.452962 # Request fanout histogram | 1568system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. 1569system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1570system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1571system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. 1572system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1573system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1574system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution 1575system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution 1576system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution 1577system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution 1578system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution 1579system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution 1580system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution 1581system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution 1582system.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution 1583system.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution 1584system.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution 1585system.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution 1586system.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution 1587system.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution 1588system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes) 1589system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes) 1590system.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes) 1591system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes) 1592system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes) 1593system.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes) 1594system.toL2Bus.snoops 1806287 # Total snoops (count) 1595system.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram 1596system.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram 1597system.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram |
| 1591system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1598system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1592system.toL2Bus.snoop_fanout::0 9517290 71.73% 71.73% # Request fanout histogram 1593system.toL2Bus.snoop_fanout::1 3738069 28.17% 99.90% # Request fanout histogram 1594system.toL2Bus.snoop_fanout::2 13028 0.10% 100.00% # Request fanout histogram | 1599system.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram 1600system.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram 1601system.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram |
| 1595system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1596system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1597system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1602system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1603system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1604system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1598system.toL2Bus.snoop_fanout::total 13268387 # Request fanout histogram | 1605system.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram |
| 1599 1600---------- End Simulation Statistics ---------- | 1606 1607---------- End Simulation Statistics ---------- |