| stats.txt (11353:31c5786945b4) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.256536 # Number of seconds simulated 4sim_ticks 47256535705500 # Number of ticks simulated 5final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.256536 # Number of seconds simulated 4sim_ticks 47256535705500 # Number of ticks simulated 5final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1671940 # Simulator instruction rate (inst/s) 8host_op_rate 1966949 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 80984002716 # Simulator tick rate (ticks/s) 10host_mem_usage 693668 # Number of bytes of host memory used 11host_seconds 583.53 # Real time elapsed on the host | 7host_inst_rate 1118024 # Simulator instruction rate (inst/s) 8host_op_rate 1315296 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54153885278 # Simulator tick rate (ticks/s) 10host_mem_usage 690972 # Number of bytes of host memory used 11host_seconds 872.63 # Real time elapsed on the host |
| 12sim_insts 975625723 # Number of instructions simulated 13sim_ops 1147772483 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory --- 306 unchanged lines hidden (view full) --- 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits | 12sim_insts 975625723 # Number of instructions simulated 13sim_ops 1147772483 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory --- 306 unchanged lines hidden (view full) --- 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits |
| 334system.cpu0.dcache.demand_hits::cpu0.data 165871488 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 165871488 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 166085900 # number of overall hits 337system.cpu0.dcache.overall_hits::total 166085900 # number of overall hits | 334system.cpu0.dcache.demand_hits::cpu0.data 166131177 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 166131177 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 166345589 # number of overall hits 337system.cpu0.dcache.overall_hits::total 166345589 # number of overall hits |
| 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses 344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses 345system.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses | 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses 344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses 345system.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses |
| 350system.cpu0.dcache.demand_misses::cpu0.data 4777518 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 4777518 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 5552076 # number of overall misses 353system.cpu0.dcache.overall_misses::total 5552076 # number of overall misses | 350system.cpu0.dcache.demand_misses::cpu0.data 5600711 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 5600711 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 6375269 # number of overall misses 353system.cpu0.dcache.overall_misses::total 6375269 # number of overall misses |
| 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) 361system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) | 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) 361system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) |
| 366system.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses | 366system.cpu0.dcache.demand_accesses::cpu0.data 171731888 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 171731888 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 172720858 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 172720858 # number of overall (read+write) accesses |
| 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses 376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses 377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses | 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses 376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses 377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses |
| 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032348 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.032348 # miss rate for overall accesses | 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032613 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.032613 # miss rate for demand accesses 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036911 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.036911 # miss rate for overall accesses |
| 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 392system.cpu0.dcache.fast_writes 0 # number of fast writes performed 393system.cpu0.dcache.cache_copies 0 # number of cache copies performed | |
| 394system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks 395system.cpu0.dcache.writebacks::total 6248192 # number of writebacks | 392system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks 393system.cpu0.dcache.writebacks::total 6248192 # number of writebacks |
| 396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 397system.cpu0.icache.tags.replacements 5479450 # number of replacements 398system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use 399system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. 400system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. 401system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. 402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor 404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 435system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses 436system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses 437system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 394system.cpu0.icache.tags.replacements 5479450 # number of replacements 395system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use 396system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. 397system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. 398system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. 399system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 400system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor 401system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 432system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses 433system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses 434system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 435system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 436system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 437system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 438system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 439system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 443system.cpu0.icache.fast_writes 0 # number of fast writes performed 444system.cpu0.icache.cache_copies 0 # number of cache copies performed | |
| 445system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks 446system.cpu0.icache.writebacks::total 5479450 # number of writebacks | 440system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks 441system.cpu0.icache.writebacks::total 5479450 # number of writebacks |
| 447system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 448system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 449system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 450system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 451system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 452system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 453system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 454system.cpu0.l2cache.tags.replacements 2651590 # number of replacements 455system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use --- 129 unchanged lines hidden (view full) --- 585system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses 586system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses 587system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 588system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 589system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 590system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 591system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 592system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 442system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 443system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 444system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 445system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 446system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 447system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 448system.cpu0.l2cache.tags.replacements 2651590 # number of replacements 449system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use --- 129 unchanged lines hidden (view full) --- 579system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses 580system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses 581system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 593system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 594system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | |
| 595system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks 596system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks | 587system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks 588system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks |
| 597system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 598system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. 599system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. 600system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 601system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. 602system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 603system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution --- 252 unchanged lines hidden (view full) --- 858system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits 859system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits 860system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits 861system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits 862system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits 863system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits 864system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits 865system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits | 589system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter. 590system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data. 591system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 592system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter. 593system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 594system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 595system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution --- 252 unchanged lines hidden (view full) --- 849system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits 850system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits 851system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits 852system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits 853system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits 854system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits 855system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits 856system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits |
| 866system.cpu1.dcache.demand_hits::cpu1.data 162001697 # number of demand (read+write) hits 867system.cpu1.dcache.demand_hits::total 162001697 # number of demand (read+write) hits 868system.cpu1.dcache.overall_hits::cpu1.data 162189982 # number of overall hits 869system.cpu1.dcache.overall_hits::total 162189982 # number of overall hits | 857system.cpu1.dcache.demand_hits::cpu1.data 162066607 # number of demand (read+write) hits 858system.cpu1.dcache.demand_hits::total 162066607 # number of demand (read+write) hits 859system.cpu1.dcache.overall_hits::cpu1.data 162254892 # number of overall hits 860system.cpu1.dcache.overall_hits::total 162254892 # number of overall hits |
| 870system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses 871system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses 872system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses 873system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses 874system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses 875system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses 876system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses 877system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses 878system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses 879system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses 880system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses 881system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses | 861system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses 862system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses 863system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses 864system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses 865system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses 866system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses 867system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses 868system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses 869system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses 870system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses 871system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses 872system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses |
| 882system.cpu1.dcache.demand_misses::cpu1.data 4833784 # number of demand (read+write) misses 883system.cpu1.dcache.demand_misses::total 4833784 # number of demand (read+write) misses 884system.cpu1.dcache.overall_misses::cpu1.data 5624082 # number of overall misses 885system.cpu1.dcache.overall_misses::total 5624082 # number of overall misses | 873system.cpu1.dcache.demand_misses::cpu1.data 5269627 # number of demand (read+write) misses 874system.cpu1.dcache.demand_misses::total 5269627 # number of demand (read+write) misses 875system.cpu1.dcache.overall_misses::cpu1.data 6059925 # number of overall misses 876system.cpu1.dcache.overall_misses::total 6059925 # number of overall misses |
| 886system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) 887system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) 888system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) 889system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) 890system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) 891system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) 892system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) 893system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) 894system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) 895system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) 896system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) 897system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) | 877system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) 878system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) 879system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) 880system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) 881system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) 882system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) 883system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) 884system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) 885system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) 886system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) 887system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) 888system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) |
| 898system.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses 899system.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses 900system.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses 901system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses | 889system.cpu1.dcache.demand_accesses::cpu1.data 167336234 # number of demand (read+write) accesses 890system.cpu1.dcache.demand_accesses::total 167336234 # number of demand (read+write) accesses 891system.cpu1.dcache.overall_accesses::cpu1.data 168314817 # number of overall (read+write) accesses 892system.cpu1.dcache.overall_accesses::total 168314817 # number of overall (read+write) accesses |
| 902system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses 903system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses 904system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses 905system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses 906system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses 907system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses 908system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses 909system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses 910system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses 911system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses 912system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses 913system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses | 893system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses 894system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses 895system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses 896system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses 897system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses 898system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses 899system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses 900system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses 901system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses 902system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses 903system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses 904system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses |
| 914system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses 915system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses 916system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033514 # miss rate for overall accesses 917system.cpu1.dcache.overall_miss_rate::total 0.033514 # miss rate for overall accesses | 905system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031491 # miss rate for demand accesses 906system.cpu1.dcache.demand_miss_rate::total 0.031491 # miss rate for demand accesses 907system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036004 # miss rate for overall accesses 908system.cpu1.dcache.overall_miss_rate::total 0.036004 # miss rate for overall accesses |
| 918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 909system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 910system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 911system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 912system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 913system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 914system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 924system.cpu1.dcache.fast_writes 0 # number of fast writes performed 925system.cpu1.dcache.cache_copies 0 # number of cache copies performed | |
| 926system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks 927system.cpu1.dcache.writebacks::total 5963482 # number of writebacks | 915system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks 916system.cpu1.dcache.writebacks::total 5963482 # number of writebacks |
| 928system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 929system.cpu1.icache.tags.replacements 4804881 # number of replacements 930system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use 931system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. 932system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. 933system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. 934system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 935system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor 936system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 967system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses 968system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses 969system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 970system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 971system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 973system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 974system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 917system.cpu1.icache.tags.replacements 4804881 # number of replacements 918system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use 919system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. 920system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. 921system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. 922system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 923system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor 924system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 955system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses 956system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses 957system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 958system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 959system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 960system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 961system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 962system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 975system.cpu1.icache.fast_writes 0 # number of fast writes performed 976system.cpu1.icache.cache_copies 0 # number of cache copies performed | |
| 977system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 978system.cpu1.icache.writebacks::total 4804881 # number of writebacks | 963system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 964system.cpu1.icache.writebacks::total 4804881 # number of writebacks |
| 979system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 980system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 981system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 982system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 983system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 984system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 985system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 986system.cpu1.l2cache.tags.replacements 2274505 # number of replacements 987system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use --- 130 unchanged lines hidden (view full) --- 1118system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses 1119system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses 1120system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1121system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1122system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1123system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1124system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1125system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 965system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 966system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 967system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 968system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 969system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 970system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 971system.cpu1.l2cache.tags.replacements 2274505 # number of replacements 972system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use --- 130 unchanged lines hidden (view full) --- 1103system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses 1104system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses 1105system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1106system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1107system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1108system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1109system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1110system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1126system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1127system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | |
| 1128system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks 1129system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks | 1111system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks 1112system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks |
| 1130system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1131system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. 1132system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1133system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1134system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. 1135system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1136system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1137system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution 1138system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution --- 93 unchanged lines hidden (view full) --- 1232system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1233system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses 1234system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses 1235system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1236system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1237system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1238system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1239system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1113system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter. 1114system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1115system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1116system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter. 1117system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1118system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1119system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution 1120system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution --- 93 unchanged lines hidden (view full) --- 1214system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1215system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses 1216system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses 1217system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1218system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1219system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1220system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1221system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1240system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses 1241system.iocache.demand_misses::total 8927 # number of demand (read+write) misses | 1222system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses 1223system.iocache.demand_misses::total 115655 # number of demand (read+write) misses |
| 1242system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1224system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1243system.iocache.overall_misses::realview.ide 8887 # number of overall misses 1244system.iocache.overall_misses::total 8927 # number of overall misses | 1225system.iocache.overall_misses::realview.ide 115615 # number of overall misses 1226system.iocache.overall_misses::total 115655 # number of overall misses |
| 1245system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1246system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) 1247system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) 1248system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1249system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1250system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1251system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1252system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1227system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1228system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) 1229system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) 1230system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1231system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1232system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1233system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1234system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1253system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses 1254system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses | 1235system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses 1236system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses |
| 1255system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1237system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1256system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses 1257system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses | 1238system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses 1239system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses |
| 1258system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1259system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1260system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1261system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1262system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1263system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1264system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1265system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1266system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1267system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1268system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1269system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1270system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1271system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1272system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1273system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1274system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1275system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1276system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1240system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1241system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1242system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1243system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1244system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1245system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1246system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1247system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1248system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1249system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1250system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1251system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1252system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1253system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1254system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1255system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1256system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1257system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1258system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1277system.iocache.fast_writes 0 # number of fast writes performed 1278system.iocache.cache_copies 0 # number of cache copies performed | |
| 1279system.iocache.writebacks::writebacks 106694 # number of writebacks 1280system.iocache.writebacks::total 106694 # number of writebacks | 1259system.iocache.writebacks::writebacks 106694 # number of writebacks 1260system.iocache.writebacks::total 106694 # number of writebacks |
| 1281system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1282system.l2c.tags.replacements 1766126 # number of replacements 1283system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use 1284system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. 1285system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. 1286system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. 1287system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 1288system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor 1289system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor --- 188 unchanged lines hidden (view full) --- 1478system.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses 1479system.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses 1480system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1481system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1482system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1483system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1484system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1485system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1261system.l2c.tags.replacements 1766126 # number of replacements 1262system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use 1263system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks. 1264system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks. 1265system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks. 1266system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. 1267system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor 1268system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor --- 188 unchanged lines hidden (view full) --- 1457system.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses 1458system.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses 1459system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1460system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1461system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1462system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1463system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1464system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1486system.l2c.fast_writes 0 # number of fast writes performed 1487system.l2c.cache_copies 0 # number of cache copies performed | |
| 1488system.l2c.writebacks::writebacks 1473799 # number of writebacks 1489system.l2c.writebacks::total 1473799 # number of writebacks | 1465system.l2c.writebacks::writebacks 1473799 # number of writebacks 1466system.l2c.writebacks::total 1473799 # number of writebacks |
| 1490system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1491system.membus.trans_dist::ReadReq 82185 # Transaction distribution 1492system.membus.trans_dist::ReadResp 568654 # Transaction distribution 1493system.membus.trans_dist::WriteReq 38847 # Transaction distribution 1494system.membus.trans_dist::WriteResp 38847 # Transaction distribution 1495system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution 1496system.membus.trans_dist::CleanEvict 246676 # Transaction distribution 1497system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution 1498system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution --- 126 unchanged lines hidden --- | 1467system.membus.trans_dist::ReadReq 82185 # Transaction distribution 1468system.membus.trans_dist::ReadResp 568654 # Transaction distribution 1469system.membus.trans_dist::WriteReq 38847 # Transaction distribution 1470system.membus.trans_dist::WriteResp 38847 # Transaction distribution 1471system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution 1472system.membus.trans_dist::CleanEvict 246676 # Transaction distribution 1473system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution 1474system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution --- 126 unchanged lines hidden --- |