| stats.txt (11245:1c5102c0a7a9) | stats.txt (11336:b318499f676c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.216814 # Number of seconds simulated 4sim_ticks 47216814145000 # Number of ticks simulated 5final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.256536 # Number of seconds simulated 4sim_ticks 47256535705500 # Number of ticks simulated 5final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 919960 # Simulator instruction rate (inst/s) 8host_op_rate 1082251 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44530469299 # Simulator tick rate (ticks/s) 10host_mem_usage 691012 # Number of bytes of host memory used 11host_seconds 1060.33 # Real time elapsed on the host 12sim_insts 975457230 # Number of instructions simulated 13sim_ops 1147538415 # Number of ops (including micro ops) simulated | 7host_inst_rate 1053178 # Simulator instruction rate (inst/s) 8host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51012949173 # Simulator tick rate (ticks/s) 10host_mem_usage 689744 # Number of bytes of host memory used 11host_seconds 926.36 # Real time elapsed on the host 12sim_insts 975625723 # Number of instructions simulated 13sim_ops 1147772483 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 152064 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 126912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3862964 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 62933832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 221952 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 220096 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2661000 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 46409840 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 419200 # Number of bytes read from this memory 25system.physmem.bytes_read::total 117007860 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3862964 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2661000 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6523964 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 100926976 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 155968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3922036 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 63542792 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 217344 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 214144 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2638472 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 46092656 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 429440 # Number of bytes read from this memory 25system.physmem.bytes_read::total 117344244 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3922036 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2638472 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 101301760 # Number of bytes written to this memory |
| 30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::total 100947560 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2376 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 1983 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 100766 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 983354 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3468 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3439 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 41685 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 725170 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6550 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1868791 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1576984 # Number of write requests responded to by this memory | 32system.physmem.bytes_written::total 101322344 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2437 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.inst 101689 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 992869 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3396 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3346 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 41333 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 720214 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6710 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1874047 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1582840 # Number of write requests responded to by this memory |
| 44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::total 1579558 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3221 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 2688 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 81813 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 1332869 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4661 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 982909 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 8878 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 2478097 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 81813 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 138170 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2137522 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) | 46system.physmem.num_writes::total 1585414 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3300 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.inst 82995 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 1344635 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4599 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4532 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 55833 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 975371 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 9087 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 2483133 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 82995 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 55833 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 138828 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2143656 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_write::total 2137958 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2137522 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3221 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 2688 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 81813 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 1333305 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4661 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 982909 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 8878 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 4616055 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_write::total 2144092 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2143656 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3300 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.inst 82995 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 1345070 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4599 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4532 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 55833 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 975371 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 9087 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 4627224 # Total bandwidth to/from this memory (bytes/s) |
| 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 46 unchanged lines hidden (view full) --- 129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 46 unchanged lines hidden (view full) --- 129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 137system.cpu0.dtb.walker.walks 125229 # Table walker walks requested 138system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors 139system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency 140system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency | 137system.cpu0.dtb.walker.walks 124170 # Table walker walks requested 138system.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors 139system.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency 140system.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency 141system.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency |
| 142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution | 142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution |
| 145system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated 146system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated 147system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated 148system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst | 145system.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated 146system.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated 147system.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated 148system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst |
| 149system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 149system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 150system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst 151system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst | 150system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst 151system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst |
| 152system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 152system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 153system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst 154system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst | 153system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst 154system.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst |
| 155system.cpu0.dtb.inst_hits 0 # ITB inst hits 156system.cpu0.dtb.inst_misses 0 # ITB inst misses | 155system.cpu0.dtb.inst_hits 0 # ITB inst hits 156system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 157system.cpu0.dtb.read_hits 92662773 # DTB read hits 158system.cpu0.dtb.read_misses 88786 # DTB read misses 159system.cpu0.dtb.write_hits 85694958 # DTB write hits 160system.cpu0.dtb.write_misses 36443 # DTB write misses | 157system.cpu0.dtb.read_hits 91996645 # DTB read hits 158system.cpu0.dtb.read_misses 87944 # DTB read misses 159system.cpu0.dtb.write_hits 85085804 # DTB write hits 160system.cpu0.dtb.write_misses 36226 # DTB write misses |
| 161system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 162system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 161system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 162system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 163system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID | 163system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID |
| 164system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 164system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 165system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB | 165system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB |
| 166system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 166system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 167system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch | 167system.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch |
| 168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 169system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions 170system.cpu0.dtb.read_accesses 92751559 # DTB read accesses 171system.cpu0.dtb.write_accesses 85731401 # DTB write accesses | 169system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions 170system.cpu0.dtb.read_accesses 92084589 # DTB read accesses 171system.cpu0.dtb.write_accesses 85122030 # DTB write accesses |
| 172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 173system.cpu0.dtb.hits 178357731 # DTB hits 174system.cpu0.dtb.misses 125229 # DTB misses 175system.cpu0.dtb.accesses 178482960 # DTB accesses | 173system.cpu0.dtb.hits 177082449 # DTB hits 174system.cpu0.dtb.misses 124170 # DTB misses 175system.cpu0.dtb.accesses 177206619 # DTB accesses |
| 176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 205system.cpu0.itb.walker.walks 61377 # Table walker walks requested 206system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors 207system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency 208system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency 209system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency | 205system.cpu0.itb.walker.walks 60706 # Table walker walks requested 206system.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors 207system.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency 208system.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency 209system.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency |
| 210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution | 210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution |
| 213system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated 214system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated 215system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated | 213system.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated 214system.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated 215system.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated |
| 216system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 216system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 217system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst 218system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst | 217system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst 218system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst |
| 219system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 219system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 220system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst 221system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst 222system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst 223system.cpu0.itb.inst_hits 497696393 # ITB inst hits 224system.cpu0.itb.inst_misses 61377 # ITB inst misses | 220system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst 221system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst 222system.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst 223system.cpu0.itb.inst_hits 494456191 # ITB inst hits 224system.cpu0.itb.inst_misses 60706 # ITB inst misses |
| 225system.cpu0.itb.read_hits 0 # DTB read hits 226system.cpu0.itb.read_misses 0 # DTB read misses 227system.cpu0.itb.write_hits 0 # DTB write hits 228system.cpu0.itb.write_misses 0 # DTB write misses 229system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 230system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 225system.cpu0.itb.read_hits 0 # DTB read hits 226system.cpu0.itb.read_misses 0 # DTB read misses 227system.cpu0.itb.write_hits 0 # DTB write hits 228system.cpu0.itb.write_misses 0 # DTB write misses 229system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 230system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 231system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID | 231system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID |
| 232system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 232system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 233system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB | 233system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB |
| 234system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 235system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 238system.cpu0.itb.read_accesses 0 # DTB read accesses 239system.cpu0.itb.write_accesses 0 # DTB write accesses | 234system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 235system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 238system.cpu0.itb.read_accesses 0 # DTB read accesses 239system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 240system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses 241system.cpu0.itb.hits 497696393 # DTB hits 242system.cpu0.itb.misses 61377 # DTB misses 243system.cpu0.itb.accesses 497757770 # DTB accesses 244system.cpu0.numCycles 94433641544 # number of cpu cycles simulated | 240system.cpu0.itb.inst_accesses 494516897 # ITB inst accesses 241system.cpu0.itb.hits 494456191 # DTB hits 242system.cpu0.itb.misses 60706 # DTB misses 243system.cpu0.itb.accesses 494516897 # DTB accesses 244system.cpu0.numCycles 94513084765 # number of cpu cycles simulated |
| 245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 247system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 248system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed 249system.cpu0.committedInsts 497466384 # Number of instructions committed 250system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed 251system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses 252system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses 253system.cpu0.num_func_calls 28869117 # number of times a function call or return occured 254system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls 255system.cpu0.num_int_insts 536103359 # number of integer instructions 256system.cpu0.num_fp_insts 526132 # number of float instructions 257system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read 258system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written 259system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read 260system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written 261system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read 262system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written 263system.cpu0.num_mem_refs 178459396 # number of memory refs 264system.cpu0.num_load_insts 92737001 # Number of load instructions 265system.cpu0.num_store_insts 85722395 # Number of store instructions 266system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles 267system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles 268system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles 269system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles 270system.cpu0.Branches 111287587 # Number of branches fetched | 248system.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed 249system.cpu0.committedInsts 494222683 # Number of instructions committed 250system.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed 251system.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses 252system.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses 253system.cpu0.num_func_calls 28754621 # number of times a function call or return occured 254system.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls 255system.cpu0.num_int_insts 532690974 # number of integer instructions 256system.cpu0.num_fp_insts 523276 # number of float instructions 257system.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read 258system.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written 259system.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read 260system.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written 261system.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read 262system.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written 263system.cpu0.num_mem_refs 177183712 # number of memory refs 264system.cpu0.num_load_insts 92070454 # Number of load instructions 265system.cpu0.num_store_insts 85113258 # Number of store instructions 266system.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles 267system.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles 268system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles 269system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles 270system.cpu0.Branches 110567658 # Number of branches fetched |
| 271system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction | 271system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction |
| 272system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction 273system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction 274system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction 275system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 276system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 277system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 278system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 279system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 280system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 281system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 282system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 283system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 284system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 285system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 286system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 287system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 288system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 289system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 290system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 291system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 292system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction 293system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 294system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction 295system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction 296system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 297system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction 298system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 299system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 300system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 301system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 302system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction | 272system.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction 273system.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction 274system.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction 275system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 276system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 277system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 278system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 279system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 280system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 281system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 282system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 283system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 284system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 285system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 286system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 287system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 288system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 289system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 290system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 291system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 292system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction 293system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 294system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction 295system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction 296system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 297system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction 298system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction 299system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction 300system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction 301system.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction 302system.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction |
| 303system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 303system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 304system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 305system.cpu0.op_class::total 585300003 # Class of executed instruction 306system.cpu0.dcache.tags.replacements 6272771 # number of replacements 307system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use 308system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks. | 305system.cpu0.op_class::total 581576758 # Class of executed instruction 306system.cpu0.dcache.tags.replacements 6248192 # number of replacements 307system.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use 308system.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks. |
| 311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. | 311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. |
| 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy | 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy |
| 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id | 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id |
| 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 320system.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses 322system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80912298 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80912298 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262024 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 262024 # number of WriteLineReq hits 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036634 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2036634 # number of StoreCondReq hits 334system.cpu0.dcache.demand_hits::cpu0.data 167127209 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 167127209 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 167342863 # number of overall hits 337system.cpu0.dcache.overall_hits::total 167342863 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1483144 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1483144 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses 344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831696 # number of WriteLineReq misses 345system.cpu0.dcache.WriteLineReq_misses::total 831696 # number of WriteLineReq misses 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158509 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 158509 # number of StoreCondReq misses 350system.cpu0.dcache.demand_misses::cpu0.data 4792526 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 4792526 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 5564665 # number of overall misses 353system.cpu0.dcache.overall_misses::total 5564665 # number of overall misses 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses) 361system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) 366system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018000 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.018000 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses 376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteLineReq accesses 377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760429 # miss rate for WriteLineReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072209 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072209 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027877 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.027877 # miss rate for demand accesses 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032183 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.032183 # miss rate for overall accesses | 320system.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses 322system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80310172 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80310172 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits 328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259684 # number of WriteLineReq hits 329system.cpu0.dcache.WriteLineReq_hits::total 259684 # number of WriteLineReq hits 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039916 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2039916 # number of StoreCondReq hits 334system.cpu0.dcache.demand_hits::cpu0.data 165871516 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 165871516 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 166085928 # number of overall hits 337system.cpu0.dcache.overall_hits::total 166085928 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1484829 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1484829 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses 344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823198 # number of WriteLineReq misses 345system.cpu0.dcache.WriteLineReq_misses::total 823198 # number of WriteLineReq misses 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156543 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 156543 # number of StoreCondReq misses 350system.cpu0.dcache.demand_misses::cpu0.data 4777490 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 4777490 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 5552048 # number of overall misses 353system.cpu0.dcache.overall_misses::total 5552048 # number of overall misses 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) 361system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) 366system.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses 376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760192 # miss rate for WriteLineReq accesses 377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760192 # miss rate for WriteLineReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071271 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071271 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032347 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.032347 # miss rate for overall accesses |
| 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu0.dcache.fast_writes 0 # number of fast writes performed 393system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu0.dcache.fast_writes 0 # number of fast writes performed 393system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 394system.cpu0.dcache.writebacks::writebacks 6272771 # number of writebacks 395system.cpu0.dcache.writebacks::total 6272771 # number of writebacks | 394system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks 395system.cpu0.dcache.writebacks::total 6248192 # number of writebacks |
| 396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 397system.cpu0.icache.tags.replacements 5539081 # number of replacements 398system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 399system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. 400system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. 401system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. | 397system.cpu0.icache.tags.replacements 5479450 # number of replacements 398system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use 399system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. 400system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. 401system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. |
| 402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. | 402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. |
| 403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor | 403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor |
| 404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 406system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 406system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 407system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 409system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 410system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 407system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 409system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id |
| 411system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 410system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 412system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses 413system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses 414system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits 415system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits 416system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits 417system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits 418system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits 419system.cpu0.icache.overall_hits::total 492212891 # number of overall hits 420system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses 421system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses 422system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses 423system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses 424system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses 425system.cpu0.icache.overall_misses::total 5539598 # number of overall misses 426system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 427system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 428system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 429system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 430system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 431system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 432system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 433system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses 434system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses 435system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses 436system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses 437system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses | 411system.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses 412system.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses 413system.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits 414system.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits 415system.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits 416system.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits 417system.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits 418system.cpu0.icache.overall_hits::total 489031557 # number of overall hits 419system.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses 420system.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses 421system.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses 422system.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses 423system.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses 424system.cpu0.icache.overall_misses::total 5479967 # number of overall misses 425system.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses) 426system.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses) 427system.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses 428system.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses 429system.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses 430system.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses 431system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses 432system.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses 433system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses 434system.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses 435system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses 436system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses |
| 438system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 439system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 441system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 443system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 444system.cpu0.icache.fast_writes 0 # number of fast writes performed 445system.cpu0.icache.cache_copies 0 # number of cache copies performed | 437system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu0.icache.fast_writes 0 # number of fast writes performed 444system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 446system.cpu0.icache.writebacks::writebacks 5539081 # number of writebacks 447system.cpu0.icache.writebacks::total 5539081 # number of writebacks | 445system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks 446system.cpu0.icache.writebacks::total 5479450 # number of writebacks |
| 448system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 449system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 450system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 451system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 452system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 453system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 454system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 447system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 448system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 449system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 450system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 451system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 452system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 453system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 455system.cpu0.l2cache.tags.replacements 2670833 # number of replacements 456system.cpu0.l2cache.tags.tagsinuse 16144.496707 # Cycle average of tags in use 457system.cpu0.l2cache.tags.total_refs 15583793 # Total number of references to valid blocks. 458system.cpu0.l2cache.tags.sampled_refs 2686790 # Sample count of references to valid blocks. 459system.cpu0.l2cache.tags.avg_refs 5.800153 # Average number of references to valid blocks. | 454system.cpu0.l2cache.tags.replacements 2651661 # number of replacements 455system.cpu0.l2cache.tags.tagsinuse 16083.621220 # Cycle average of tags in use 456system.cpu0.l2cache.tags.total_refs 15456673 # Total number of references to valid blocks. 457system.cpu0.l2cache.tags.sampled_refs 2667641 # Sample count of references to valid blocks. 458system.cpu0.l2cache.tags.avg_refs 5.794135 # Average number of references to valid blocks. |
| 460system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. | 459system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. |
| 461system.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.665572 # Average occupied blocks per requestor 463system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 43.728993 # Average occupied blocks per requestor 464system.cpu0.l2cache.tags.occ_percent::writebacks 0.980170 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002543 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002669 # Average percentage of cache occupancy 467system.cpu0.l2cache.tags.occ_percent::total 0.985382 # Average percentage of cache occupancy 468system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id 469system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15907 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id | 460system.cpu0.l2cache.tags.occ_blocks::writebacks 15982.700506 # Average occupied blocks per requestor 461system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 46.812729 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.107985 # Average occupied blocks per requestor 463system.cpu0.l2cache.tags.occ_percent::writebacks 0.975507 # Average percentage of cache occupancy 464system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002857 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003302 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy 467system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id 468system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15898 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 67 # Occupied blocks per task id |
| 471system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id | 470system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 471system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id |
| 473system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4378 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5313 # Occupied blocks per task id 477system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4509 # Occupied blocks per task id 478system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id 479system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970886 # Percentage of cache occupancy per task id 480system.cpu0.l2cache.tags.tag_accesses 397685392 # Number of tag accesses 481system.cpu0.l2cache.tags.data_accesses 397685392 # Number of data accesses 482system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 298097 # number of ReadReq hits 483system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 159313 # number of ReadReq hits 484system.cpu0.l2cache.ReadReq_hits::total 457410 # number of ReadReq hits 485system.cpu0.l2cache.WritebackDirty_hits::writebacks 4459579 # number of WritebackDirty hits 486system.cpu0.l2cache.WritebackDirty_hits::total 4459579 # number of WritebackDirty hits 487system.cpu0.l2cache.WritebackClean_hits::writebacks 7350874 # number of WritebackClean hits 488system.cpu0.l2cache.WritebackClean_hits::total 7350874 # number of WritebackClean hits 489system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 760 # number of UpgradeReq hits 490system.cpu0.l2cache.UpgradeReq_hits::total 760 # number of UpgradeReq hits 491system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635944 # number of ReadExReq hits 492system.cpu0.l2cache.ReadExReq_hits::total 635944 # number of ReadExReq hits 493system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5035825 # number of ReadCleanReq hits 494system.cpu0.l2cache.ReadCleanReq_hits::total 5035825 # number of ReadCleanReq hits 495system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2962064 # number of ReadSharedReq hits 496system.cpu0.l2cache.ReadSharedReq_hits::total 2962064 # number of ReadSharedReq hits 497system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223971 # number of InvalidateReq hits 498system.cpu0.l2cache.InvalidateReq_hits::total 223971 # number of InvalidateReq hits 499system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 298097 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.itb.walker 159313 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::cpu0.inst 5035825 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::cpu0.data 3598008 # number of demand (read+write) hits 503system.cpu0.l2cache.demand_hits::total 9091243 # number of demand (read+write) hits 504system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 298097 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.itb.walker 159313 # number of overall hits 506system.cpu0.l2cache.overall_hits::cpu0.inst 5035825 # number of overall hits 507system.cpu0.l2cache.overall_hits::cpu0.data 3598008 # number of overall hits 508system.cpu0.l2cache.overall_hits::total 9091243 # number of overall hits 509system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11326 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8418 # number of ReadReq misses 511system.cpu0.l2cache.ReadReq_misses::total 19744 # number of ReadReq misses 512system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138515 # number of UpgradeReq misses 513system.cpu0.l2cache.UpgradeReq_misses::total 138515 # number of UpgradeReq misses 514system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158509 # number of SCUpgradeReq misses 515system.cpu0.l2cache.SCUpgradeReq_misses::total 158509 # number of SCUpgradeReq misses 516system.cpu0.l2cache.ReadExReq_misses::cpu0.data 708286 # number of ReadExReq misses 517system.cpu0.l2cache.ReadExReq_misses::total 708286 # number of ReadExReq misses 518system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 503773 # number of ReadCleanReq misses 519system.cpu0.l2cache.ReadCleanReq_misses::total 503773 # number of ReadCleanReq misses 520system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1239273 # number of ReadSharedReq misses 521system.cpu0.l2cache.ReadSharedReq_misses::total 1239273 # number of ReadSharedReq misses 522system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607364 # number of InvalidateReq misses 523system.cpu0.l2cache.InvalidateReq_misses::total 607364 # number of InvalidateReq misses 524system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11326 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8418 # number of demand (read+write) misses 526system.cpu0.l2cache.demand_misses::cpu0.inst 503773 # number of demand (read+write) misses 527system.cpu0.l2cache.demand_misses::cpu0.data 1947559 # number of demand (read+write) misses 528system.cpu0.l2cache.demand_misses::total 2471076 # number of demand (read+write) misses 529system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11326 # number of overall misses 530system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8418 # number of overall misses 531system.cpu0.l2cache.overall_misses::cpu0.inst 503773 # number of overall misses 532system.cpu0.l2cache.overall_misses::cpu0.data 1947559 # number of overall misses 533system.cpu0.l2cache.overall_misses::total 2471076 # number of overall misses 534system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 309423 # number of ReadReq accesses(hits+misses) 535system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 167731 # number of ReadReq accesses(hits+misses) 536system.cpu0.l2cache.ReadReq_accesses::total 477154 # number of ReadReq accesses(hits+misses) 537system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4459579 # number of WritebackDirty accesses(hits+misses) 538system.cpu0.l2cache.WritebackDirty_accesses::total 4459579 # number of WritebackDirty accesses(hits+misses) 539system.cpu0.l2cache.WritebackClean_accesses::writebacks 7350874 # number of WritebackClean accesses(hits+misses) 540system.cpu0.l2cache.WritebackClean_accesses::total 7350874 # number of WritebackClean accesses(hits+misses) 541system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139275 # number of UpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.UpgradeReq_accesses::total 139275 # number of UpgradeReq accesses(hits+misses) 543system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158509 # number of SCUpgradeReq accesses(hits+misses) 544system.cpu0.l2cache.SCUpgradeReq_accesses::total 158509 # number of SCUpgradeReq accesses(hits+misses) 545system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) 546system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) 547system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) 548system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) 549system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) 550system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) 551system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses) 552system.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses) 553system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 309423 # number of demand (read+write) accesses 554system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 167731 # number of demand (read+write) accesses 555system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses 556system.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses 557system.cpu0.l2cache.demand_accesses::total 11562319 # number of demand (read+write) accesses 558system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 309423 # number of overall (read+write) accesses 559system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 167731 # number of overall (read+write) accesses 560system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses 561system.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses 562system.cpu0.l2cache.overall_accesses::total 11562319 # number of overall (read+write) accesses 563system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for ReadReq accesses 564system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050188 # miss rate for ReadReq accesses 565system.cpu0.l2cache.ReadReq_miss_rate::total 0.041379 # miss rate for ReadReq accesses 566system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994543 # miss rate for UpgradeReq accesses 567system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994543 # miss rate for UpgradeReq accesses | 472system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4776 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4826 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4604 # Occupied blocks per task id 477system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id 478system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970337 # Percentage of cache occupancy per task id 479system.cpu0.l2cache.tags.tag_accesses 394866118 # Number of tag accesses 480system.cpu0.l2cache.tags.data_accesses 394866118 # Number of data accesses 481system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294519 # number of ReadReq hits 482system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156806 # number of ReadReq hits 483system.cpu0.l2cache.ReadReq_hits::total 451325 # number of ReadReq hits 484system.cpu0.l2cache.WritebackDirty_hits::writebacks 4431483 # number of WritebackDirty hits 485system.cpu0.l2cache.WritebackDirty_hits::total 4431483 # number of WritebackDirty hits 486system.cpu0.l2cache.WritebackClean_hits::writebacks 7294760 # number of WritebackClean hits 487system.cpu0.l2cache.WritebackClean_hits::total 7294760 # number of WritebackClean hits 488system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 771 # number of UpgradeReq hits 489system.cpu0.l2cache.UpgradeReq_hits::total 771 # number of UpgradeReq hits 490system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630855 # number of ReadExReq hits 491system.cpu0.l2cache.ReadExReq_hits::total 630855 # number of ReadExReq hits 492system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4984424 # number of ReadCleanReq hits 493system.cpu0.l2cache.ReadCleanReq_hits::total 4984424 # number of ReadCleanReq hits 494system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2948651 # number of ReadSharedReq hits 495system.cpu0.l2cache.ReadSharedReq_hits::total 2948651 # number of ReadSharedReq hits 496system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218371 # number of InvalidateReq hits 497system.cpu0.l2cache.InvalidateReq_hits::total 218371 # number of InvalidateReq hits 498system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294519 # number of demand (read+write) hits 499system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156806 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.inst 4984424 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::cpu0.data 3579506 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::total 9015255 # number of demand (read+write) hits 503system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294519 # number of overall hits 504system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156806 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.inst 4984424 # number of overall hits 506system.cpu0.l2cache.overall_hits::cpu0.data 3579506 # number of overall hits 507system.cpu0.l2cache.overall_hits::total 9015255 # number of overall hits 508system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11443 # number of ReadReq misses 509system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8713 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::total 20156 # number of ReadReq misses 511system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140594 # number of UpgradeReq misses 512system.cpu0.l2cache.UpgradeReq_misses::total 140594 # number of UpgradeReq misses 513system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156543 # number of SCUpgradeReq misses 514system.cpu0.l2cache.SCUpgradeReq_misses::total 156543 # number of SCUpgradeReq misses 515system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712979 # number of ReadExReq misses 516system.cpu0.l2cache.ReadExReq_misses::total 712979 # number of ReadExReq misses 517system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 495543 # number of ReadCleanReq misses 518system.cpu0.l2cache.ReadCleanReq_misses::total 495543 # number of ReadCleanReq misses 519system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236929 # number of ReadSharedReq misses 520system.cpu0.l2cache.ReadSharedReq_misses::total 1236929 # number of ReadSharedReq misses 521system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604457 # number of InvalidateReq misses 522system.cpu0.l2cache.InvalidateReq_misses::total 604457 # number of InvalidateReq misses 523system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11443 # number of demand (read+write) misses 524system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8713 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::cpu0.inst 495543 # number of demand (read+write) misses 526system.cpu0.l2cache.demand_misses::cpu0.data 1949908 # number of demand (read+write) misses 527system.cpu0.l2cache.demand_misses::total 2465607 # number of demand (read+write) misses 528system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11443 # number of overall misses 529system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8713 # number of overall misses 530system.cpu0.l2cache.overall_misses::cpu0.inst 495543 # number of overall misses 531system.cpu0.l2cache.overall_misses::cpu0.data 1949908 # number of overall misses 532system.cpu0.l2cache.overall_misses::total 2465607 # number of overall misses 533system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305962 # number of ReadReq accesses(hits+misses) 534system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165519 # number of ReadReq accesses(hits+misses) 535system.cpu0.l2cache.ReadReq_accesses::total 471481 # number of ReadReq accesses(hits+misses) 536system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4431483 # number of WritebackDirty accesses(hits+misses) 537system.cpu0.l2cache.WritebackDirty_accesses::total 4431483 # number of WritebackDirty accesses(hits+misses) 538system.cpu0.l2cache.WritebackClean_accesses::writebacks 7294760 # number of WritebackClean accesses(hits+misses) 539system.cpu0.l2cache.WritebackClean_accesses::total 7294760 # number of WritebackClean accesses(hits+misses) 540system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141365 # number of UpgradeReq accesses(hits+misses) 541system.cpu0.l2cache.UpgradeReq_accesses::total 141365 # number of UpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156543 # number of SCUpgradeReq accesses(hits+misses) 543system.cpu0.l2cache.SCUpgradeReq_accesses::total 156543 # number of SCUpgradeReq accesses(hits+misses) 544system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) 545system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) 546system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) 547system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses) 548system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses) 549system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) 550system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) 551system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) 552system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305962 # number of demand (read+write) accesses 553system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165519 # number of demand (read+write) accesses 554system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses 555system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses 556system.cpu0.l2cache.demand_accesses::total 11480862 # number of demand (read+write) accesses 557system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305962 # number of overall (read+write) accesses 558system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165519 # number of overall (read+write) accesses 559system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses 560system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses 561system.cpu0.l2cache.overall_accesses::total 11480862 # number of overall (read+write) accesses 562system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for ReadReq accesses 563system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052640 # miss rate for ReadReq accesses 564system.cpu0.l2cache.ReadReq_miss_rate::total 0.042750 # miss rate for ReadReq accesses 565system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994546 # miss rate for UpgradeReq accesses 566system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994546 # miss rate for UpgradeReq accesses |
| 568system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 569system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 567system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 568system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 570system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526908 # miss rate for ReadExReq accesses 571system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526908 # miss rate for ReadExReq accesses 572system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090940 # miss rate for ReadCleanReq accesses 573system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090940 # miss rate for ReadCleanReq accesses 574system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294971 # miss rate for ReadSharedReq accesses 575system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294971 # miss rate for ReadSharedReq accesses 576system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730589 # miss rate for InvalidateReq accesses 577system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730589 # miss rate for InvalidateReq accesses 578system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for demand accesses 579system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050188 # miss rate for demand accesses 580system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090940 # miss rate for demand accesses 581system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.351192 # miss rate for demand accesses 582system.cpu0.l2cache.demand_miss_rate::total 0.213718 # miss rate for demand accesses 583system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for overall accesses 584system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050188 # miss rate for overall accesses 585system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090940 # miss rate for overall accesses 586system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.351192 # miss rate for overall accesses 587system.cpu0.l2cache.overall_miss_rate::total 0.213718 # miss rate for overall accesses | 569system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530556 # miss rate for ReadExReq accesses 570system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530556 # miss rate for ReadExReq accesses 571system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090428 # miss rate for ReadCleanReq accesses 572system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090428 # miss rate for ReadCleanReq accesses 573system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295522 # miss rate for ReadSharedReq accesses 574system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295522 # miss rate for ReadSharedReq accesses 575system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734609 # miss rate for InvalidateReq accesses 576system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734609 # miss rate for InvalidateReq accesses 577system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for demand accesses 578system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052640 # miss rate for demand accesses 579system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090428 # miss rate for demand accesses 580system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352643 # miss rate for demand accesses 581system.cpu0.l2cache.demand_miss_rate::total 0.214758 # miss rate for demand accesses 582system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for overall accesses 583system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052640 # miss rate for overall accesses 584system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090428 # miss rate for overall accesses 585system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352643 # miss rate for overall accesses 586system.cpu0.l2cache.overall_miss_rate::total 0.214758 # miss rate for overall accesses |
| 588system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 589system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 590system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 591system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 592system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 593system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 594system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 595system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 587system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 588system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 589system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 590system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 591system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 592system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 593system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 594system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 596system.cpu0.l2cache.writebacks::writebacks 1567377 # number of writebacks 597system.cpu0.l2cache.writebacks::total 1567377 # number of writebacks | 595system.cpu0.l2cache.writebacks::writebacks 1559370 # number of writebacks 596system.cpu0.l2cache.writebacks::total 1559370 # number of writebacks |
| 598system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 597system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 599system.cpu0.toL2Bus.snoop_filter.tot_requests 24282502 # Total number of requests made to the snoop filter. 600system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12366009 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 598system.cpu0.toL2Bus.snoop_filter.tot_requests 24116923 # Total number of requests made to the snoop filter. 599system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284721 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 601system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 600system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 602system.cpu0.toL2Bus.snoop_filter.tot_snoops 1791227 # Total number of snoops made to the snoop filter. 603system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1790958 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 604system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 605system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution 609system.cpu0.toL2Bus.trans_dist::WritebackDirty 4459579 # Transaction distribution 610system.cpu0.toL2Bus.trans_dist::WritebackClean 7350874 # Transaction distribution 611system.cpu0.toL2Bus.trans_dist::UpgradeReq 139275 # Transaction distribution 612system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158509 # Transaction distribution 613system.cpu0.toL2Bus.trans_dist::UpgradeResp 297784 # Transaction distribution 614system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution 615system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution 616system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution 617system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution 618system.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution 619system.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution 620system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes) 621system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19751529 # Packet count per connected master and slave (bytes) 622system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 623system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) 624system.cpu0.toL2Bus.pkt_count::total 37549877 # Packet count per connected master and slave (bytes) 625system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 709149780 # Cumulative packet size per connected master and slave (bytes) 626system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 756535625 # Cumulative packet size per connected master and slave (bytes) 627system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 628system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) 629system.cpu0.toL2Bus.pkt_size::total 1470064325 # Cumulative packet size per connected master and slave (bytes) 630system.cpu0.toL2Bus.snoops 6119333 # Total snoops (count) 631system.cpu0.toL2Bus.snoop_fanout::samples 30615399 # Request fanout histogram 632system.cpu0.toL2Bus.snoop_fanout::mean 0.066982 # Request fanout histogram 633system.cpu0.toL2Bus.snoop_fanout::stdev 0.250025 # Request fanout histogram | 601system.cpu0.toL2Bus.snoop_filter.tot_snoops 1786138 # Total number of snoops made to the snoop filter. 602system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 603system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 271 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 604system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::WritebackDirty 4431483 # Transaction distribution 609system.cpu0.toL2Bus.trans_dist::WritebackClean 7296159 # Transaction distribution 610system.cpu0.toL2Bus.trans_dist::UpgradeReq 141365 # Transaction distribution 611system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156543 # Transaction distribution 612system.cpu0.toL2Bus.trans_dist::UpgradeResp 297908 # Transaction distribution 613system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution 614system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution 615system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution 616system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution 617system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution 618system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution 619system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) 620system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681122 # Packet count per connected master and slave (bytes) 621system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) 622system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) 623system.cpu0.toL2Bus.pkt_count::total 37291838 # Packet count per connected master and slave (bytes) 624system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) 625system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) 626system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) 627system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) 628system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) 629system.cpu0.toL2Bus.snoops 6128014 # Total snoops (count) 630system.cpu0.toL2Bus.snoop_fanout::samples 30453385 # Request fanout histogram 631system.cpu0.toL2Bus.snoop_fanout::mean 0.067263 # Request fanout histogram 632system.cpu0.toL2Bus.snoop_fanout::stdev 0.250512 # Request fanout histogram |
| 634system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 633system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 635system.cpu0.toL2Bus.snoop_fanout::0 28565001 93.30% 93.30% # Request fanout histogram 636system.cpu0.toL2Bus.snoop_fanout::1 2050129 6.70% 100.00% # Request fanout histogram 637system.cpu0.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram | 634system.cpu0.toL2Bus.snoop_fanout::0 28405278 93.27% 93.27% # Request fanout histogram 635system.cpu0.toL2Bus.snoop_fanout::1 2047836 6.72% 100.00% # Request fanout histogram 636system.cpu0.toL2Bus.snoop_fanout::2 271 0.00% 100.00% # Request fanout histogram |
| 638system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 639system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 640system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 637system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 638system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 639system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 641system.cpu0.toL2Bus.snoop_fanout::total 30615399 # Request fanout histogram | 640system.cpu0.toL2Bus.snoop_fanout::total 30453385 # Request fanout histogram |
| 642system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 643system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 644system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 645system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 646system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 647system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 648system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 649system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 663system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 664system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 665system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 666system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 667system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 668system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 669system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 670system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 641system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 642system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 643system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 644system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 645system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 646system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 647system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 648system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 662system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 663system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 664system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 665system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 666system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 667system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 668system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 669system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 671system.cpu1.dtb.walker.walks 144041 # Table walker walks requested 672system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors 673system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency 674system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency 675system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency | 670system.cpu1.dtb.walker.walks 145097 # Table walker walks requested 671system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors 672system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency 673system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency 674system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency |
| 676system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 677system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 678system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution | 675system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 676system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 677system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution |
| 679system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated 680system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated 681system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated 682system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst | 678system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated 679system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated 680system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated 681system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst |
| 683system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 682system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 684system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst 685system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst | 683system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst 684system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst |
| 686system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 685system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 687system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst 688system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst | 686system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst 687system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst |
| 689system.cpu1.dtb.inst_hits 0 # ITB inst hits 690system.cpu1.dtb.inst_misses 0 # ITB inst misses | 688system.cpu1.dtb.inst_hits 0 # ITB inst hits 689system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 691system.cpu1.dtb.read_hits 90153061 # DTB read hits 692system.cpu1.dtb.read_misses 111753 # DTB read misses 693system.cpu1.dtb.write_hits 81132787 # DTB write hits 694system.cpu1.dtb.write_misses 32288 # DTB write misses | 690system.cpu1.dtb.read_hits 90839106 # DTB read hits 691system.cpu1.dtb.read_misses 112437 # DTB read misses 692system.cpu1.dtb.write_hits 81787747 # DTB write hits 693system.cpu1.dtb.write_misses 32660 # DTB write misses |
| 695system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 696system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 694system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 695system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 697system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID | 696system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID |
| 698system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 697system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 699system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB | 698system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB |
| 700system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 699system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 701system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch | 700system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch |
| 702system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 701system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 703system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions 704system.cpu1.dtb.read_accesses 90264814 # DTB read accesses 705system.cpu1.dtb.write_accesses 81165075 # DTB write accesses | 702system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions 703system.cpu1.dtb.read_accesses 90951543 # DTB read accesses 704system.cpu1.dtb.write_accesses 81820407 # DTB write accesses |
| 706system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 705system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 707system.cpu1.dtb.hits 171285848 # DTB hits 708system.cpu1.dtb.misses 144041 # DTB misses 709system.cpu1.dtb.accesses 171429889 # DTB accesses | 706system.cpu1.dtb.hits 172626853 # DTB hits 707system.cpu1.dtb.misses 145097 # DTB misses 708system.cpu1.dtb.accesses 172771950 # DTB accesses |
| 710system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 711system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 712system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 714system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 715system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 716system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 717system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 731system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 732system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 733system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 734system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 735system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 736system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 737system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 738system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 709system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 710system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 711system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 712system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 714system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 715system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 716system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 730system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 731system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 732system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 733system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 734system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 735system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 736system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 737system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 739system.cpu1.itb.walker.walks 60885 # Table walker walks requested 740system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors 741system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency 742system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency 743system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency | 738system.cpu1.itb.walker.walks 61573 # Table walker walks requested 739system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors 740system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency 741system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency 742system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency |
| 744system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 745system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 746system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution | 743system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 744system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 745system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution |
| 747system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated 748system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated 749system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated | 746system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated 747system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated 748system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated |
| 750system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 749system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 751system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst 752system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst | 750system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst 751system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst |
| 753system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 752system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 754system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst 755system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst 756system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst 757system.cpu1.itb.inst_hits 478248118 # ITB inst hits 758system.cpu1.itb.inst_misses 60885 # ITB inst misses | 753system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst 754system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst 755system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst 756system.cpu1.itb.inst_hits 481656543 # ITB inst hits 757system.cpu1.itb.inst_misses 61573 # ITB inst misses |
| 759system.cpu1.itb.read_hits 0 # DTB read hits 760system.cpu1.itb.read_misses 0 # DTB read misses 761system.cpu1.itb.write_hits 0 # DTB write hits 762system.cpu1.itb.write_misses 0 # DTB write misses 763system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 764system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 758system.cpu1.itb.read_hits 0 # DTB read hits 759system.cpu1.itb.read_misses 0 # DTB read misses 760system.cpu1.itb.write_hits 0 # DTB write hits 761system.cpu1.itb.write_misses 0 # DTB write misses 762system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 763system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 765system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID | 764system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID |
| 766system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID | 765system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID |
| 767system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB | 766system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB |
| 768system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 769system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 770system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 771system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 772system.cpu1.itb.read_accesses 0 # DTB read accesses 773system.cpu1.itb.write_accesses 0 # DTB write accesses | 767system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 768system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 769system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 770system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 771system.cpu1.itb.read_accesses 0 # DTB read accesses 772system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 774system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses 775system.cpu1.itb.hits 478248118 # DTB hits 776system.cpu1.itb.misses 60885 # DTB misses 777system.cpu1.itb.accesses 478309003 # DTB accesses 778system.cpu1.numCycles 94433634550 # number of cpu cycles simulated | 773system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses 774system.cpu1.itb.hits 481656543 # DTB hits 775system.cpu1.itb.misses 61573 # DTB misses 776system.cpu1.itb.accesses 481718116 # DTB accesses 777system.cpu1.numCycles 94513077683 # number of cpu cycles simulated |
| 779system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 780system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 781system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 778system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 779system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 780system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 782system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed 783system.cpu1.committedInsts 477990846 # Number of instructions committed 784system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed 785system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses 786system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses 787system.cpu1.num_func_calls 28237407 # number of times a function call or return occured 788system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls 789system.cpu1.num_int_insts 516282159 # number of integer instructions 790system.cpu1.num_fp_insts 374678 # number of float instructions 791system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read 792system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written 793system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read 794system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written 795system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read 796system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written 797system.cpu1.num_mem_refs 171406825 # number of memory refs 798system.cpu1.num_load_insts 90251973 # Number of load instructions 799system.cpu1.num_store_insts 81154852 # Number of store instructions 800system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles 801system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles 802system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles 803system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles 804system.cpu1.Branches 106497601 # Number of branches fetched | 781system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed 782system.cpu1.committedInsts 481403040 # Number of instructions committed 783system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed 784system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses 785system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses 786system.cpu1.num_func_calls 28379648 # number of times a function call or return occured 787system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls 788system.cpu1.num_int_insts 519926686 # number of integer instructions 789system.cpu1.num_fp_insts 376275 # number of float instructions 790system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read 791system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written 792system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read 793system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written 794system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read 795system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written 796system.cpu1.num_mem_refs 172748485 # number of memory refs 797system.cpu1.num_load_insts 90938541 # Number of load instructions 798system.cpu1.num_store_insts 81809944 # Number of store instructions 799system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles 800system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles 801system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles 802system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles 803system.cpu1.Branches 107246711 # Number of branches fetched |
| 805system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction | 804system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction |
| 806system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction 807system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction 808system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction 809system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 810system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 811system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 812system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 813system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 814system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 815system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 816system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 817system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 818system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 819system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 820system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 821system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 822system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 823system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 824system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 825system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 826system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 827system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 828system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 829system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 830system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 831system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction 832system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 833system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 834system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 835system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction 836system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction | 805system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction 806system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction 807system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction 808system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 809system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 810system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 811system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction 812system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction 813system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 814system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 815system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 816system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 817system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 818system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 819system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 820system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 821system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 822system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 823system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 824system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 825system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 826system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 827system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 828system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 829system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 830system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction 831system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 832system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 833system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction 834system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction 835system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction |
| 837system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 838system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 836system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 837system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 839system.cpu1.op_class::total 562879339 # Class of executed instruction 840system.cpu1.dcache.tags.replacements 5945049 # number of replacements 841system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use 842system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. 843system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. 844system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. | 838system.cpu1.op_class::total 566836400 # Class of executed instruction 839system.cpu1.dcache.tags.replacements 5963482 # number of replacements 840system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use 841system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks. 842system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks. 843system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks. |
| 845system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. | 844system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. |
| 846system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor 847system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy 848system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy | 845system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor 846system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy 847system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy |
| 849system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 848system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 850system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 851system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 852system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id | 849system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id 850system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id |
| 853system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 851system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 854system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 855system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 856system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 857system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits 858system.cpu1.dcache.WriteReq_hits::cpu1.data 76981821 # number of WriteReq hits 859system.cpu1.dcache.WriteReq_hits::total 76981821 # number of WriteReq hits 860system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 861system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits 862system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63451 # number of WriteLineReq hits 863system.cpu1.dcache.WriteLineReq_hits::total 63451 # number of WriteLineReq hits 864system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 865system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits 866system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048602 # number of StoreCondReq hits 867system.cpu1.dcache.StoreCondReq_hits::total 2048602 # number of StoreCondReq hits 868system.cpu1.dcache.demand_hits::cpu1.data 160679385 # number of demand (read+write) hits 869system.cpu1.dcache.demand_hits::total 160679385 # number of demand (read+write) hits 870system.cpu1.dcache.overall_hits::cpu1.data 160867239 # number of overall hits 871system.cpu1.dcache.overall_hits::total 160867239 # number of overall hits 872system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 873system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses 874system.cpu1.dcache.WriteReq_misses::cpu1.data 1461655 # number of WriteReq misses 875system.cpu1.dcache.WriteReq_misses::total 1461655 # number of WriteReq misses 876system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 877system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses 878system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427048 # number of WriteLineReq misses 879system.cpu1.dcache.WriteLineReq_misses::total 427048 # number of WriteLineReq misses 880system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 881system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses 882system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159147 # number of StoreCondReq misses 883system.cpu1.dcache.StoreCondReq_misses::total 159147 # number of StoreCondReq misses 884system.cpu1.dcache.demand_misses::cpu1.data 4819877 # number of demand (read+write) misses 885system.cpu1.dcache.demand_misses::total 4819877 # number of demand (read+write) misses 886system.cpu1.dcache.overall_misses::cpu1.data 5612228 # number of overall misses 887system.cpu1.dcache.overall_misses::total 5612228 # number of overall misses 888system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 889system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 890system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 891system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 892system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 893system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 894system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses) 895system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses) 896system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) 897system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) 898system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) 899system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) 900system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses 901system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses 902system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 903system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 904system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 905system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 906system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018633 # miss rate for WriteReq accesses 907system.cpu1.dcache.WriteReq_miss_rate::total 0.018633 # miss rate for WriteReq accesses 908system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 909system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses 910system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870640 # miss rate for WriteLineReq accesses 911system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870640 # miss rate for WriteLineReq accesses 912system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 913system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses 914system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072086 # miss rate for StoreCondReq accesses 915system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072086 # miss rate for StoreCondReq accesses 916system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029123 # miss rate for demand accesses 917system.cpu1.dcache.demand_miss_rate::total 0.029123 # miss rate for demand accesses 918system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033711 # miss rate for overall accesses 919system.cpu1.dcache.overall_miss_rate::total 0.033711 # miss rate for overall accesses | 852system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses 853system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses 854system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits 855system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits 856system.cpu1.dcache.WriteReq_hits::cpu1.data 77626077 # number of WriteReq hits 857system.cpu1.dcache.WriteReq_hits::total 77626077 # number of WriteReq hits 858system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits 859system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits 860system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64906 # number of WriteLineReq hits 861system.cpu1.dcache.WriteLineReq_hits::total 64906 # number of WriteLineReq hits 862system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits 863system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits 864system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047972 # number of StoreCondReq hits 865system.cpu1.dcache.StoreCondReq_hits::total 2047972 # number of StoreCondReq hits 866system.cpu1.dcache.demand_hits::cpu1.data 162001748 # number of demand (read+write) hits 867system.cpu1.dcache.demand_hits::total 162001748 # number of demand (read+write) hits 868system.cpu1.dcache.overall_hits::cpu1.data 162190033 # number of overall hits 869system.cpu1.dcache.overall_hits::total 162190033 # number of overall hits 870system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses 871system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses 872system.cpu1.dcache.WriteReq_misses::cpu1.data 1463826 # number of WriteReq misses 873system.cpu1.dcache.WriteReq_misses::total 1463826 # number of WriteReq misses 874system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses 875system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses 876system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435847 # number of WriteLineReq misses 877system.cpu1.dcache.WriteLineReq_misses::total 435847 # number of WriteLineReq misses 878system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses 879system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses 880system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159002 # number of StoreCondReq misses 881system.cpu1.dcache.StoreCondReq_misses::total 159002 # number of StoreCondReq misses 882system.cpu1.dcache.demand_misses::cpu1.data 4833733 # number of demand (read+write) misses 883system.cpu1.dcache.demand_misses::total 4833733 # number of demand (read+write) misses 884system.cpu1.dcache.overall_misses::cpu1.data 5624031 # number of overall misses 885system.cpu1.dcache.overall_misses::total 5624031 # number of overall misses 886system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) 887system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) 888system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) 889system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) 890system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) 891system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) 892system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) 893system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) 894system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) 895system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) 896system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) 897system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) 898system.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses 899system.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses 900system.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses 901system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses 902system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses 903system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses 904system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018508 # miss rate for WriteReq accesses 905system.cpu1.dcache.WriteReq_miss_rate::total 0.018508 # miss rate for WriteReq accesses 906system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses 907system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses 908system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870383 # miss rate for WriteLineReq accesses 909system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870383 # miss rate for WriteLineReq accesses 910system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses 911system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses 912system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072045 # miss rate for StoreCondReq accesses 913system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072045 # miss rate for StoreCondReq accesses 914system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses 915system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses 916system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033513 # miss rate for overall accesses 917system.cpu1.dcache.overall_miss_rate::total 0.033513 # miss rate for overall accesses |
| 920system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu1.dcache.fast_writes 0 # number of fast writes performed 927system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.dcache.fast_writes 0 # number of fast writes performed 925system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 928system.cpu1.dcache.writebacks::writebacks 5945049 # number of writebacks 929system.cpu1.dcache.writebacks::total 5945049 # number of writebacks | 926system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks 927system.cpu1.dcache.writebacks::total 5963482 # number of writebacks |
| 930system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 928system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 931system.cpu1.icache.tags.replacements 4741297 # number of replacements 932system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 933system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 934system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 935system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. | 929system.cpu1.icache.tags.replacements 4804881 # number of replacements 930system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use 931system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. 932system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. 933system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. |
| 936system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. | 934system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. |
| 937system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 938system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 939system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy | 935system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor 936system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy 937system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy |
| 940system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 938system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 941system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 942system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 943system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id | 939system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 940system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id 941system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id |
| 944system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 942system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 945system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses 946system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses 947system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits 948system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits 949system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits 950system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits 951system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits 952system.cpu1.icache.overall_hits::total 473560604 # number of overall hits 953system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses 954system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses 955system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses 956system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses 957system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses 958system.cpu1.icache.overall_misses::total 4741809 # number of overall misses 959system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) 960system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) 961system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses 962system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses 963system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses 964system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses 965system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses 966system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses 967system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses 968system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses 969system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses 970system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses | 943system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses 944system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses 945system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits 946system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits 947system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits 948system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits 949system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits 950system.cpu1.icache.overall_hits::total 476906226 # number of overall hits 951system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses 952system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses 953system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses 954system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses 955system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses 956system.cpu1.icache.overall_misses::total 4805393 # number of overall misses 957system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses) 958system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses) 959system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses 960system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses 961system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses 962system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses 963system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses 964system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses 965system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses 966system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses 967system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses 968system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses |
| 971system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 973system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 974system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 975system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 976system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 977system.cpu1.icache.fast_writes 0 # number of fast writes performed 978system.cpu1.icache.cache_copies 0 # number of cache copies performed | 969system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 970system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 971system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 973system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 974system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 975system.cpu1.icache.fast_writes 0 # number of fast writes performed 976system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 979system.cpu1.icache.writebacks::writebacks 4741297 # number of writebacks 980system.cpu1.icache.writebacks::total 4741297 # number of writebacks | 977system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 978system.cpu1.icache.writebacks::total 4804881 # number of writebacks |
| 981system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 982system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 983system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 984system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 985system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 986system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 987system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 979system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 980system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 981system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 982system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 983system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 984system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 985system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 988system.cpu1.l2cache.tags.replacements 2235881 # number of replacements 989system.cpu1.l2cache.tags.tagsinuse 13334.612647 # Cycle average of tags in use 990system.cpu1.l2cache.tags.total_refs 14249550 # Total number of references to valid blocks. 991system.cpu1.l2cache.tags.sampled_refs 2251891 # Sample count of references to valid blocks. 992system.cpu1.l2cache.tags.avg_refs 6.327815 # Average number of references to valid blocks. 993system.cpu1.l2cache.tags.warmup_cycle 9713557375000 # Cycle when the warmup percentage was hit. 994system.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748 # Average occupied blocks per requestor 995system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.246601 # Average occupied blocks per requestor 996system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.385297 # Average occupied blocks per requestor 997system.cpu1.l2cache.tags.occ_percent::writebacks 0.807067 # Average percentage of cache occupancy 998system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002823 # Average percentage of cache occupancy 999system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003991 # Average percentage of cache occupancy 1000system.cpu1.l2cache.tags.occ_percent::total 0.813880 # Average percentage of cache occupancy 1001system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 1004system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id 1005system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id 1006system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 1007system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1627 # Occupied blocks per task id 1008system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6185 # Occupied blocks per task id 1009system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4247 # Occupied blocks per task id 1010system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3746 # Occupied blocks per task id 1011system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id 1012system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id 1013system.cpu1.l2cache.tags.tag_accesses 361919913 # Number of tag accesses 1014system.cpu1.l2cache.tags.data_accesses 361919913 # Number of data accesses 1015system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 346945 # number of ReadReq hits 1016system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153602 # number of ReadReq hits 1017system.cpu1.l2cache.ReadReq_hits::total 500547 # number of ReadReq hits 1018system.cpu1.l2cache.WritebackDirty_hits::writebacks 4020160 # number of WritebackDirty hits 1019system.cpu1.l2cache.WritebackDirty_hits::total 4020160 # number of WritebackDirty hits 1020system.cpu1.l2cache.WritebackClean_hits::writebacks 6665818 # number of WritebackClean hits 1021system.cpu1.l2cache.WritebackClean_hits::total 6665818 # number of WritebackClean hits 1022system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1056 # number of UpgradeReq hits 1023system.cpu1.l2cache.UpgradeReq_hits::total 1056 # number of UpgradeReq hits 1024system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614983 # number of ReadExReq hits 1025system.cpu1.l2cache.ReadExReq_hits::total 614983 # number of ReadExReq hits 1026system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4283593 # number of ReadCleanReq hits 1027system.cpu1.l2cache.ReadCleanReq_hits::total 4283593 # number of ReadCleanReq hits 1028system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3077520 # number of ReadSharedReq hits 1029system.cpu1.l2cache.ReadSharedReq_hits::total 3077520 # number of ReadSharedReq hits 1030system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161463 # number of InvalidateReq hits 1031system.cpu1.l2cache.InvalidateReq_hits::total 161463 # number of InvalidateReq hits 1032system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 346945 # number of demand (read+write) hits 1033system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153602 # number of demand (read+write) hits 1034system.cpu1.l2cache.demand_hits::cpu1.inst 4283593 # number of demand (read+write) hits 1035system.cpu1.l2cache.demand_hits::cpu1.data 3692503 # number of demand (read+write) hits 1036system.cpu1.l2cache.demand_hits::total 8476643 # number of demand (read+write) hits 1037system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 346945 # number of overall hits 1038system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153602 # number of overall hits 1039system.cpu1.l2cache.overall_hits::cpu1.inst 4283593 # number of overall hits 1040system.cpu1.l2cache.overall_hits::cpu1.data 3692503 # number of overall hits 1041system.cpu1.l2cache.overall_hits::total 8476643 # number of overall hits 1042system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12460 # number of ReadReq misses 1043system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9763 # number of ReadReq misses 1044system.cpu1.l2cache.ReadReq_misses::total 22223 # number of ReadReq misses 1045system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144911 # number of UpgradeReq misses 1046system.cpu1.l2cache.UpgradeReq_misses::total 144911 # number of UpgradeReq misses 1047system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159147 # number of SCUpgradeReq misses 1048system.cpu1.l2cache.SCUpgradeReq_misses::total 159147 # number of SCUpgradeReq misses 1049system.cpu1.l2cache.ReadExReq_misses::cpu1.data 700907 # number of ReadExReq misses 1050system.cpu1.l2cache.ReadExReq_misses::total 700907 # number of ReadExReq misses 1051system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458216 # number of ReadCleanReq misses 1052system.cpu1.l2cache.ReadCleanReq_misses::total 458216 # number of ReadCleanReq misses 1053system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1219873 # number of ReadSharedReq misses 1054system.cpu1.l2cache.ReadSharedReq_misses::total 1219873 # number of ReadSharedReq misses 1055system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265383 # number of InvalidateReq misses 1056system.cpu1.l2cache.InvalidateReq_misses::total 265383 # number of InvalidateReq misses 1057system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12460 # number of demand (read+write) misses 1058system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9763 # number of demand (read+write) misses 1059system.cpu1.l2cache.demand_misses::cpu1.inst 458216 # number of demand (read+write) misses 1060system.cpu1.l2cache.demand_misses::cpu1.data 1920780 # number of demand (read+write) misses 1061system.cpu1.l2cache.demand_misses::total 2401219 # number of demand (read+write) misses 1062system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12460 # number of overall misses 1063system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9763 # number of overall misses 1064system.cpu1.l2cache.overall_misses::cpu1.inst 458216 # number of overall misses 1065system.cpu1.l2cache.overall_misses::cpu1.data 1920780 # number of overall misses 1066system.cpu1.l2cache.overall_misses::total 2401219 # number of overall misses 1067system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 359405 # number of ReadReq accesses(hits+misses) 1068system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163365 # number of ReadReq accesses(hits+misses) 1069system.cpu1.l2cache.ReadReq_accesses::total 522770 # number of ReadReq accesses(hits+misses) 1070system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4020160 # number of WritebackDirty accesses(hits+misses) 1071system.cpu1.l2cache.WritebackDirty_accesses::total 4020160 # number of WritebackDirty accesses(hits+misses) 1072system.cpu1.l2cache.WritebackClean_accesses::writebacks 6665818 # number of WritebackClean accesses(hits+misses) 1073system.cpu1.l2cache.WritebackClean_accesses::total 6665818 # number of WritebackClean accesses(hits+misses) 1074system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145967 # number of UpgradeReq accesses(hits+misses) 1075system.cpu1.l2cache.UpgradeReq_accesses::total 145967 # number of UpgradeReq accesses(hits+misses) 1076system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159147 # number of SCUpgradeReq accesses(hits+misses) 1077system.cpu1.l2cache.SCUpgradeReq_accesses::total 159147 # number of SCUpgradeReq accesses(hits+misses) 1078system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 1079system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) 1080system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) 1081system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses) 1082system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses) 1083system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) 1084system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) 1085system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) 1086system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 359405 # number of demand (read+write) accesses 1087system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163365 # number of demand (read+write) accesses 1088system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 1089system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses 1090system.cpu1.l2cache.demand_accesses::total 10877862 # number of demand (read+write) accesses 1091system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 359405 # number of overall (read+write) accesses 1092system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163365 # number of overall (read+write) accesses 1093system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 1094system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses 1095system.cpu1.l2cache.overall_accesses::total 10877862 # number of overall (read+write) accesses 1096system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for ReadReq accesses 1097system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059762 # miss rate for ReadReq accesses 1098system.cpu1.l2cache.ReadReq_miss_rate::total 0.042510 # miss rate for ReadReq accesses 1099system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992765 # miss rate for UpgradeReq accesses 1100system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992765 # miss rate for UpgradeReq accesses | 986system.cpu1.l2cache.tags.replacements 2273518 # number of replacements 987system.cpu1.l2cache.tags.tagsinuse 13372.591247 # Cycle average of tags in use 988system.cpu1.l2cache.tags.total_refs 14355328 # Total number of references to valid blocks. 989system.cpu1.l2cache.tags.sampled_refs 2289651 # Sample count of references to valid blocks. 990system.cpu1.l2cache.tags.avg_refs 6.269658 # Average number of references to valid blocks. 991system.cpu1.l2cache.tags.warmup_cycle 9713557312500 # Cycle when the warmup percentage was hit. 992system.cpu1.l2cache.tags.occ_blocks::writebacks 13267.841352 # Average occupied blocks per requestor 993system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.789421 # Average occupied blocks per requestor 994system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.960475 # Average occupied blocks per requestor 995system.cpu1.l2cache.tags.occ_percent::writebacks 0.809805 # Average percentage of cache occupancy 996system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002917 # Average percentage of cache occupancy 997system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003477 # Average percentage of cache occupancy 998system.cpu1.l2cache.tags.occ_percent::total 0.816198 # Average percentage of cache occupancy 999system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id 1000system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16058 # Occupied blocks per task id 1001system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id 1004system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 1005system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 1006system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 317 # Occupied blocks per task id 1007system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id 1008system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5907 # Occupied blocks per task id 1009system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id 1010system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3824 # Occupied blocks per task id 1011system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id 1012system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980103 # Percentage of cache occupancy per task id 1013system.cpu1.l2cache.tags.tag_accesses 364667597 # Number of tag accesses 1014system.cpu1.l2cache.tags.data_accesses 364667597 # Number of data accesses 1015system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349833 # number of ReadReq hits 1016system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155576 # number of ReadReq hits 1017system.cpu1.l2cache.ReadReq_hits::total 505409 # number of ReadReq hits 1018system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030572 # number of WritebackDirty hits 1019system.cpu1.l2cache.WritebackDirty_hits::total 4030572 # number of WritebackDirty hits 1020system.cpu1.l2cache.WritebackClean_hits::writebacks 6737405 # number of WritebackClean hits 1021system.cpu1.l2cache.WritebackClean_hits::total 6737405 # number of WritebackClean hits 1022system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1033 # number of UpgradeReq hits 1023system.cpu1.l2cache.UpgradeReq_hits::total 1033 # number of UpgradeReq hits 1024system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606896 # number of ReadExReq hits 1025system.cpu1.l2cache.ReadExReq_hits::total 606896 # number of ReadExReq hits 1026system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338388 # number of ReadCleanReq hits 1027system.cpu1.l2cache.ReadCleanReq_hits::total 4338388 # number of ReadCleanReq hits 1028system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3076039 # number of ReadSharedReq hits 1029system.cpu1.l2cache.ReadSharedReq_hits::total 3076039 # number of ReadSharedReq hits 1030system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 163041 # number of InvalidateReq hits 1031system.cpu1.l2cache.InvalidateReq_hits::total 163041 # number of InvalidateReq hits 1032system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349833 # number of demand (read+write) hits 1033system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155576 # number of demand (read+write) hits 1034system.cpu1.l2cache.demand_hits::cpu1.inst 4338388 # number of demand (read+write) hits 1035system.cpu1.l2cache.demand_hits::cpu1.data 3682935 # number of demand (read+write) hits 1036system.cpu1.l2cache.demand_hits::total 8526732 # number of demand (read+write) hits 1037system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349833 # number of overall hits 1038system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155576 # number of overall hits 1039system.cpu1.l2cache.overall_hits::cpu1.inst 4338388 # number of overall hits 1040system.cpu1.l2cache.overall_hits::cpu1.data 3682935 # number of overall hits 1041system.cpu1.l2cache.overall_hits::total 8526732 # number of overall hits 1042system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12358 # number of ReadReq misses 1043system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9778 # number of ReadReq misses 1044system.cpu1.l2cache.ReadReq_misses::total 22136 # number of ReadReq misses 1045system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147541 # number of UpgradeReq misses 1046system.cpu1.l2cache.UpgradeReq_misses::total 147541 # number of UpgradeReq misses 1047system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159002 # number of SCUpgradeReq misses 1048system.cpu1.l2cache.SCUpgradeReq_misses::total 159002 # number of SCUpgradeReq misses 1049system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708595 # number of ReadExReq misses 1050system.cpu1.l2cache.ReadExReq_misses::total 708595 # number of ReadExReq misses 1051system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467005 # number of ReadCleanReq misses 1052system.cpu1.l2cache.ReadCleanReq_misses::total 467005 # number of ReadCleanReq misses 1053system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230054 # number of ReadSharedReq misses 1054system.cpu1.l2cache.ReadSharedReq_misses::total 1230054 # number of ReadSharedReq misses 1055system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272567 # number of InvalidateReq misses 1056system.cpu1.l2cache.InvalidateReq_misses::total 272567 # number of InvalidateReq misses 1057system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12358 # number of demand (read+write) misses 1058system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9778 # number of demand (read+write) misses 1059system.cpu1.l2cache.demand_misses::cpu1.inst 467005 # number of demand (read+write) misses 1060system.cpu1.l2cache.demand_misses::cpu1.data 1938649 # number of demand (read+write) misses 1061system.cpu1.l2cache.demand_misses::total 2427790 # number of demand (read+write) misses 1062system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12358 # number of overall misses 1063system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9778 # number of overall misses 1064system.cpu1.l2cache.overall_misses::cpu1.inst 467005 # number of overall misses 1065system.cpu1.l2cache.overall_misses::cpu1.data 1938649 # number of overall misses 1066system.cpu1.l2cache.overall_misses::total 2427790 # number of overall misses 1067system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362191 # number of ReadReq accesses(hits+misses) 1068system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165354 # number of ReadReq accesses(hits+misses) 1069system.cpu1.l2cache.ReadReq_accesses::total 527545 # number of ReadReq accesses(hits+misses) 1070system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030572 # number of WritebackDirty accesses(hits+misses) 1071system.cpu1.l2cache.WritebackDirty_accesses::total 4030572 # number of WritebackDirty accesses(hits+misses) 1072system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737405 # number of WritebackClean accesses(hits+misses) 1073system.cpu1.l2cache.WritebackClean_accesses::total 6737405 # number of WritebackClean accesses(hits+misses) 1074system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148574 # number of UpgradeReq accesses(hits+misses) 1075system.cpu1.l2cache.UpgradeReq_accesses::total 148574 # number of UpgradeReq accesses(hits+misses) 1076system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159002 # number of SCUpgradeReq accesses(hits+misses) 1077system.cpu1.l2cache.SCUpgradeReq_accesses::total 159002 # number of SCUpgradeReq accesses(hits+misses) 1078system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses) 1079system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses) 1080system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses) 1081system.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses) 1082system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses) 1083system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses) 1084system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses) 1085system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses) 1086system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362191 # number of demand (read+write) accesses 1087system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165354 # number of demand (read+write) accesses 1088system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses 1089system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses 1090system.cpu1.l2cache.demand_accesses::total 10954522 # number of demand (read+write) accesses 1091system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362191 # number of overall (read+write) accesses 1092system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165354 # number of overall (read+write) accesses 1093system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses 1094system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses 1095system.cpu1.l2cache.overall_accesses::total 10954522 # number of overall (read+write) accesses 1096system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for ReadReq accesses 1097system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059134 # miss rate for ReadReq accesses 1098system.cpu1.l2cache.ReadReq_miss_rate::total 0.041960 # miss rate for ReadReq accesses 1099system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993047 # miss rate for UpgradeReq accesses 1100system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993047 # miss rate for UpgradeReq accesses |
| 1101system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1102system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1101system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1102system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1103system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532649 # miss rate for ReadExReq accesses 1104system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532649 # miss rate for ReadExReq accesses 1105system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096633 # miss rate for ReadCleanReq accesses 1106system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096633 # miss rate for ReadCleanReq accesses 1107system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283863 # miss rate for ReadSharedReq accesses 1108system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283863 # miss rate for ReadSharedReq accesses 1109system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.621730 # miss rate for InvalidateReq accesses 1110system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.621730 # miss rate for InvalidateReq accesses 1111system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for demand accesses 1112system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059762 # miss rate for demand accesses 1113system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096633 # miss rate for demand accesses 1114system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342185 # miss rate for demand accesses 1115system.cpu1.l2cache.demand_miss_rate::total 0.220744 # miss rate for demand accesses 1116system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for overall accesses 1117system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059762 # miss rate for overall accesses 1118system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096633 # miss rate for overall accesses 1119system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342185 # miss rate for overall accesses 1120system.cpu1.l2cache.overall_miss_rate::total 0.220744 # miss rate for overall accesses | 1103system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538654 # miss rate for ReadExReq accesses 1104system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538654 # miss rate for ReadExReq accesses 1105system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097184 # miss rate for ReadCleanReq accesses 1106system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097184 # miss rate for ReadCleanReq accesses 1107system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285654 # miss rate for ReadSharedReq accesses 1108system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285654 # miss rate for ReadSharedReq accesses 1109system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625716 # miss rate for InvalidateReq accesses 1110system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625716 # miss rate for InvalidateReq accesses 1111system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for demand accesses 1112system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059134 # miss rate for demand accesses 1113system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097184 # miss rate for demand accesses 1114system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344858 # miss rate for demand accesses 1115system.cpu1.l2cache.demand_miss_rate::total 0.221624 # miss rate for demand accesses 1116system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for overall accesses 1117system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059134 # miss rate for overall accesses 1118system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097184 # miss rate for overall accesses 1119system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344858 # miss rate for overall accesses 1120system.cpu1.l2cache.overall_miss_rate::total 0.221624 # miss rate for overall accesses |
| 1121system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1125system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1128system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1121system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1125system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1128system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1129system.cpu1.l2cache.writebacks::writebacks 1179503 # number of writebacks 1130system.cpu1.l2cache.writebacks::total 1179503 # number of writebacks | 1129system.cpu1.l2cache.writebacks::writebacks 1197492 # number of writebacks 1130system.cpu1.l2cache.writebacks::total 1197492 # number of writebacks |
| 1131system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1131system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1132system.cpu1.toL2Bus.snoop_filter.tot_requests 22049015 # Total number of requests made to the snoop filter. 1133system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11267078 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1134system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760820 # Total number of snoops made to the snoop filter. 1136system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760650 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1137system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1138system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution 1139system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 1140system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 1141system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution 1142system.cpu1.toL2Bus.trans_dist::WritebackDirty 4020160 # Transaction distribution 1143system.cpu1.toL2Bus.trans_dist::WritebackClean 6665818 # Transaction distribution 1144system.cpu1.toL2Bus.trans_dist::UpgradeReq 145967 # Transaction distribution 1145system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159147 # Transaction distribution 1146system.cpu1.toL2Bus.trans_dist::UpgradeResp 305114 # Transaction distribution 1147system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 1148system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 1149system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution 1150system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution 1151system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution 1152system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution 1153system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes) 1154system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18660714 # Packet count per connected master and slave (bytes) 1155system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 1156system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) 1157system.cpu1.toL2Bus.pkt_count::total 34085270 # Packet count per connected master and slave (bytes) 1158system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 606915272 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 739752124 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu1.toL2Bus.pkt_size::total 1351465172 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu1.toL2Bus.snoops 5690396 # Total snoops (count) 1164system.cpu1.toL2Bus.snoop_fanout::samples 27910438 # Request fanout histogram 1165system.cpu1.toL2Bus.snoop_fanout::mean 0.072996 # Request fanout histogram 1166system.cpu1.toL2Bus.snoop_fanout::stdev 0.260153 # Request fanout histogram | 1132system.cpu1.toL2Bus.snoop_filter.tot_requests 22219563 # Total number of requests made to the snoop filter. 1133system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11356978 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1134system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu1.toL2Bus.snoop_filter.tot_snoops 1770232 # Total number of snoops made to the snoop filter. 1136system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1770046 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1137system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1138system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution 1139system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution 1140system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution 1141system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution 1142system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030572 # Transaction distribution 1143system.cpu1.toL2Bus.trans_dist::WritebackClean 6737791 # Transaction distribution 1144system.cpu1.toL2Bus.trans_dist::UpgradeReq 148574 # Transaction distribution 1145system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159002 # Transaction distribution 1146system.cpu1.toL2Bus.trans_dist::UpgradeResp 307576 # Transaction distribution 1147system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution 1148system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution 1149system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution 1150system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution 1151system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution 1152system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution 1153system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) 1154system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18715946 # Packet count per connected master and slave (bytes) 1155system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) 1156system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) 1157system.cpu1.toL2Bus.pkt_count::total 34341081 # Packet count per connected master and slave (bytes) 1158system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu1.toL2Bus.snoops 5728933 # Total snoops (count) 1164system.cpu1.toL2Bus.snoop_fanout::samples 28119998 # Request fanout histogram 1165system.cpu1.toL2Bus.snoop_fanout::mean 0.072981 # Request fanout histogram 1166system.cpu1.toL2Bus.snoop_fanout::stdev 0.260131 # Request fanout histogram |
| 1167system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1167system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1168system.cpu1.toL2Bus.snoop_fanout::0 25873264 92.70% 92.70% # Request fanout histogram 1169system.cpu1.toL2Bus.snoop_fanout::1 2037004 7.30% 100.00% # Request fanout histogram 1170system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram | 1168system.cpu1.toL2Bus.snoop_fanout::0 26067955 92.70% 92.70% # Request fanout histogram 1169system.cpu1.toL2Bus.snoop_fanout::1 2051857 7.30% 100.00% # Request fanout histogram 1170system.cpu1.toL2Bus.snoop_fanout::2 186 0.00% 100.00% # Request fanout histogram |
| 1171system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1172system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1173system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1171system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1172system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1173system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1174system.cpu1.toL2Bus.snoop_fanout::total 27910438 # Request fanout histogram 1175system.iobus.trans_dist::ReadReq 40295 # Transaction distribution 1176system.iobus.trans_dist::ReadResp 40295 # Transaction distribution 1177system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 1178system.iobus.trans_dist::WriteResp 136634 # Transaction distribution 1179system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) | 1174system.cpu1.toL2Bus.snoop_fanout::total 28119998 # Request fanout histogram 1175system.iobus.trans_dist::ReadReq 40311 # Transaction distribution 1176system.iobus.trans_dist::ReadResp 40311 # Transaction distribution 1177system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1178system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 1179system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) |
| 1180system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) | 1180system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1185system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) |
| 1192system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) | 1192system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) |
| 1195system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 1195system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 1197system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) | 1197system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) |
| 1199system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) | 1199system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) |
| 1211system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) | 1211system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) |
| 1214system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 1214system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 1216system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) 1217system.iocache.tags.replacements 115585 # number of replacements 1218system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use | 1216system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes) 1217system.iocache.tags.replacements 115596 # number of replacements 1218system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use |
| 1219system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 1219system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 1220system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. | 1220system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. |
| 1221system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1222system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. | 1221system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1222system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. |
| 1223system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor 1224system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor 1225system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy 1226system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy 1227system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy | 1223system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor 1224system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor 1225system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy 1226system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy 1227system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy |
| 1228system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1229system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1230system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1228system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1229system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1230system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1231system.iocache.tags.tag_accesses 1040793 # Number of tag accesses 1232system.iocache.tags.data_accesses 1040793 # Number of data accesses | 1231system.iocache.tags.tag_accesses 1040892 # Number of tag accesses 1232system.iocache.tags.data_accesses 1040892 # Number of data accesses |
| 1233system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 1233system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 1234system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses 1235system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses | 1234system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses 1235system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses |
| 1236system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1237system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1238system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1239system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1240system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1236system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1237system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1238system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1239system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1240system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1241system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses 1242system.iocache.demand_misses::total 8916 # number of demand (read+write) misses | 1241system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses 1242system.iocache.demand_misses::total 8927 # number of demand (read+write) misses |
| 1243system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1243system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1244system.iocache.overall_misses::realview.ide 8876 # number of overall misses 1245system.iocache.overall_misses::total 8916 # number of overall misses | 1244system.iocache.overall_misses::realview.ide 8887 # number of overall misses 1245system.iocache.overall_misses::total 8927 # number of overall misses |
| 1246system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 1246system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 1247system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) 1248system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) | 1247system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) 1248system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) |
| 1249system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1250system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1251system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1252system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1253system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1249system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1250system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1251system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1252system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1253system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1254system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses 1255system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses | 1254system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses 1255system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses |
| 1256system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1256system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1257system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses 1258system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses | 1257system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses 1258system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses |
| 1259system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1260system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1261system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1262system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1263system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1264system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1265system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1266system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 8 unchanged lines hidden (view full) --- 1275system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1276system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1277system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1278system.iocache.fast_writes 0 # number of fast writes performed 1279system.iocache.cache_copies 0 # number of cache copies performed 1280system.iocache.writebacks::writebacks 106694 # number of writebacks 1281system.iocache.writebacks::total 106694 # number of writebacks 1282system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1259system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1260system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1261system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1262system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1263system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1264system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1265system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1266system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 8 unchanged lines hidden (view full) --- 1275system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1276system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1277system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1278system.iocache.fast_writes 0 # number of fast writes performed 1279system.iocache.cache_copies 0 # number of cache copies performed 1280system.iocache.writebacks::writebacks 106694 # number of writebacks 1281system.iocache.writebacks::total 106694 # number of writebacks 1282system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1283system.l2c.tags.replacements 1759418 # number of replacements 1284system.l2c.tags.tagsinuse 62296.253449 # Cycle average of tags in use 1285system.l2c.tags.total_refs 4473392 # Total number of references to valid blocks. 1286system.l2c.tags.sampled_refs 1817492 # Sample count of references to valid blocks. 1287system.l2c.tags.avg_refs 2.461299 # Average number of references to valid blocks. | 1283system.l2c.tags.replacements 1772759 # number of replacements 1284system.l2c.tags.tagsinuse 62623.636789 # Cycle average of tags in use 1285system.l2c.tags.total_refs 4610700 # Total number of references to valid blocks. 1286system.l2c.tags.sampled_refs 1831680 # Sample count of references to valid blocks. 1287system.l2c.tags.avg_refs 2.517197 # Average number of references to valid blocks. |
| 1288system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1288system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1289system.l2c.tags.occ_blocks::writebacks 34373.643780 # Average occupied blocks per requestor 1290system.l2c.tags.occ_blocks::cpu0.dtb.walker 42.521667 # Average occupied blocks per requestor 1291system.l2c.tags.occ_blocks::cpu0.itb.walker 58.768031 # Average occupied blocks per requestor 1292system.l2c.tags.occ_blocks::cpu0.inst 3224.697109 # Average occupied blocks per requestor 1293system.l2c.tags.occ_blocks::cpu0.data 7016.159468 # Average occupied blocks per requestor 1294system.l2c.tags.occ_blocks::cpu1.dtb.walker 270.222583 # Average occupied blocks per requestor 1295system.l2c.tags.occ_blocks::cpu1.itb.walker 416.861208 # Average occupied blocks per requestor 1296system.l2c.tags.occ_blocks::cpu1.inst 2985.929949 # Average occupied blocks per requestor 1297system.l2c.tags.occ_blocks::cpu1.data 13907.449654 # Average occupied blocks per requestor 1298system.l2c.tags.occ_percent::writebacks 0.524500 # Average percentage of cache occupancy 1299system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000649 # Average percentage of cache occupancy 1300system.l2c.tags.occ_percent::cpu0.itb.walker 0.000897 # Average percentage of cache occupancy 1301system.l2c.tags.occ_percent::cpu0.inst 0.049205 # Average percentage of cache occupancy 1302system.l2c.tags.occ_percent::cpu0.data 0.107058 # Average percentage of cache occupancy 1303system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004123 # Average percentage of cache occupancy 1304system.l2c.tags.occ_percent::cpu1.itb.walker 0.006361 # Average percentage of cache occupancy 1305system.l2c.tags.occ_percent::cpu1.inst 0.045562 # Average percentage of cache occupancy 1306system.l2c.tags.occ_percent::cpu1.data 0.212211 # Average percentage of cache occupancy 1307system.l2c.tags.occ_percent::total 0.950565 # Average percentage of cache occupancy 1308system.l2c.tags.occ_task_id_blocks::1023 212 # Occupied blocks per task id 1309system.l2c.tags.occ_task_id_blocks::1024 57862 # Occupied blocks per task id 1310system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id | 1289system.l2c.tags.occ_blocks::writebacks 34513.616341 # Average occupied blocks per requestor 1290system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.391588 # Average occupied blocks per requestor 1291system.l2c.tags.occ_blocks::cpu0.itb.walker 102.836315 # Average occupied blocks per requestor 1292system.l2c.tags.occ_blocks::cpu0.inst 3358.057391 # Average occupied blocks per requestor 1293system.l2c.tags.occ_blocks::cpu0.data 7927.916069 # Average occupied blocks per requestor 1294system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.822259 # Average occupied blocks per requestor 1295system.l2c.tags.occ_blocks::cpu1.itb.walker 388.027254 # Average occupied blocks per requestor 1296system.l2c.tags.occ_blocks::cpu1.inst 2900.077291 # Average occupied blocks per requestor 1297system.l2c.tags.occ_blocks::cpu1.data 13121.892282 # Average occupied blocks per requestor 1298system.l2c.tags.occ_percent::writebacks 0.526636 # Average percentage of cache occupancy 1299system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001059 # Average percentage of cache occupancy 1300system.l2c.tags.occ_percent::cpu0.itb.walker 0.001569 # Average percentage of cache occupancy 1301system.l2c.tags.occ_percent::cpu0.inst 0.051240 # Average percentage of cache occupancy 1302system.l2c.tags.occ_percent::cpu0.data 0.120970 # Average percentage of cache occupancy 1303system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003690 # Average percentage of cache occupancy 1304system.l2c.tags.occ_percent::cpu1.itb.walker 0.005921 # Average percentage of cache occupancy 1305system.l2c.tags.occ_percent::cpu1.inst 0.044252 # Average percentage of cache occupancy 1306system.l2c.tags.occ_percent::cpu1.data 0.200224 # Average percentage of cache occupancy 1307system.l2c.tags.occ_percent::total 0.955561 # Average percentage of cache occupancy 1308system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id 1309system.l2c.tags.occ_task_id_blocks::1024 58727 # Occupied blocks per task id 1310system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 1311system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1312system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id |
| 1311system.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id | 1313system.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id |
| 1312system.l2c.tags.age_task_id_blocks_1024::1 539 # Occupied blocks per task id 1313system.l2c.tags.age_task_id_blocks_1024::2 3515 # Occupied blocks per task id 1314system.l2c.tags.age_task_id_blocks_1024::3 5475 # Occupied blocks per task id 1315system.l2c.tags.age_task_id_blocks_1024::4 48284 # Occupied blocks per task id 1316system.l2c.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 1317system.l2c.tags.occ_task_id_percent::1024 0.882904 # Percentage of cache occupancy per task id 1318system.l2c.tags.tag_accesses 73042126 # Number of tag accesses 1319system.l2c.tags.data_accesses 73042126 # Number of data accesses 1320system.l2c.WritebackDirty_hits::writebacks 2746880 # number of WritebackDirty hits 1321system.l2c.WritebackDirty_hits::total 2746880 # number of WritebackDirty hits 1322system.l2c.UpgradeReq_hits::cpu0.data 14674 # number of UpgradeReq hits 1323system.l2c.UpgradeReq_hits::cpu1.data 12828 # number of UpgradeReq hits 1324system.l2c.UpgradeReq_hits::total 27502 # number of UpgradeReq hits 1325system.l2c.SCUpgradeReq_hits::cpu0.data 1473 # number of SCUpgradeReq hits 1326system.l2c.SCUpgradeReq_hits::cpu1.data 1269 # number of SCUpgradeReq hits 1327system.l2c.SCUpgradeReq_hits::total 2742 # number of SCUpgradeReq hits 1328system.l2c.ReadExReq_hits::cpu0.data 316195 # number of ReadExReq hits 1329system.l2c.ReadExReq_hits::cpu1.data 262623 # number of ReadExReq hits 1330system.l2c.ReadExReq_hits::total 578818 # number of ReadExReq hits 1331system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits 1332system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4560 # number of ReadSharedReq hits 1333system.l2c.ReadSharedReq_hits::cpu0.inst 446108 # number of ReadSharedReq hits 1334system.l2c.ReadSharedReq_hits::cpu0.data 731335 # number of ReadSharedReq hits 1335system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits 1336system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3622 # number of ReadSharedReq hits 1337system.l2c.ReadSharedReq_hits::cpu1.inst 416632 # number of ReadSharedReq hits 1338system.l2c.ReadSharedReq_hits::cpu1.data 676220 # number of ReadSharedReq hits 1339system.l2c.ReadSharedReq_hits::total 2290398 # number of ReadSharedReq hits 1340system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits 1341system.l2c.demand_hits::cpu0.itb.walker 4560 # number of demand (read+write) hits 1342system.l2c.demand_hits::cpu0.inst 446108 # number of demand (read+write) hits 1343system.l2c.demand_hits::cpu0.data 1047530 # number of demand (read+write) hits 1344system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits 1345system.l2c.demand_hits::cpu1.itb.walker 3622 # number of demand (read+write) hits 1346system.l2c.demand_hits::cpu1.inst 416632 # number of demand (read+write) hits 1347system.l2c.demand_hits::cpu1.data 938843 # number of demand (read+write) hits 1348system.l2c.demand_hits::total 2869216 # number of demand (read+write) hits 1349system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits 1350system.l2c.overall_hits::cpu0.itb.walker 4560 # number of overall hits 1351system.l2c.overall_hits::cpu0.inst 446108 # number of overall hits 1352system.l2c.overall_hits::cpu0.data 1047530 # number of overall hits 1353system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits 1354system.l2c.overall_hits::cpu1.itb.walker 3622 # number of overall hits 1355system.l2c.overall_hits::cpu1.inst 416632 # number of overall hits 1356system.l2c.overall_hits::cpu1.data 938843 # number of overall hits 1357system.l2c.overall_hits::total 2869216 # number of overall hits 1358system.l2c.UpgradeReq_misses::cpu0.data 68066 # number of UpgradeReq misses 1359system.l2c.UpgradeReq_misses::cpu1.data 63332 # number of UpgradeReq misses 1360system.l2c.UpgradeReq_misses::total 131398 # number of UpgradeReq misses 1361system.l2c.SCUpgradeReq_misses::cpu0.data 7840 # number of SCUpgradeReq misses 1362system.l2c.SCUpgradeReq_misses::cpu1.data 7476 # number of SCUpgradeReq misses 1363system.l2c.SCUpgradeReq_misses::total 15316 # number of SCUpgradeReq misses 1364system.l2c.ReadExReq_misses::cpu0.data 815697 # number of ReadExReq misses 1365system.l2c.ReadExReq_misses::cpu1.data 546954 # number of ReadExReq misses 1366system.l2c.ReadExReq_misses::total 1362651 # number of ReadExReq misses 1367system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2376 # number of ReadSharedReq misses 1368system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1983 # number of ReadSharedReq misses 1369system.l2c.ReadSharedReq_misses::cpu0.inst 57665 # number of ReadSharedReq misses 1370system.l2c.ReadSharedReq_misses::cpu0.data 181479 # number of ReadSharedReq misses 1371system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3468 # number of ReadSharedReq misses 1372system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3439 # number of ReadSharedReq misses 1373system.l2c.ReadSharedReq_misses::cpu1.inst 41584 # number of ReadSharedReq misses 1374system.l2c.ReadSharedReq_misses::cpu1.data 187193 # number of ReadSharedReq misses 1375system.l2c.ReadSharedReq_misses::total 479187 # number of ReadSharedReq misses 1376system.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses 1377system.l2c.demand_misses::cpu0.itb.walker 1983 # number of demand (read+write) misses 1378system.l2c.demand_misses::cpu0.inst 57665 # number of demand (read+write) misses 1379system.l2c.demand_misses::cpu0.data 997176 # number of demand (read+write) misses 1380system.l2c.demand_misses::cpu1.dtb.walker 3468 # number of demand (read+write) misses 1381system.l2c.demand_misses::cpu1.itb.walker 3439 # number of demand (read+write) misses 1382system.l2c.demand_misses::cpu1.inst 41584 # number of demand (read+write) misses 1383system.l2c.demand_misses::cpu1.data 734147 # number of demand (read+write) misses 1384system.l2c.demand_misses::total 1841838 # number of demand (read+write) misses 1385system.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses 1386system.l2c.overall_misses::cpu0.itb.walker 1983 # number of overall misses 1387system.l2c.overall_misses::cpu0.inst 57665 # number of overall misses 1388system.l2c.overall_misses::cpu0.data 997176 # number of overall misses 1389system.l2c.overall_misses::cpu1.dtb.walker 3468 # number of overall misses 1390system.l2c.overall_misses::cpu1.itb.walker 3439 # number of overall misses 1391system.l2c.overall_misses::cpu1.inst 41584 # number of overall misses 1392system.l2c.overall_misses::cpu1.data 734147 # number of overall misses 1393system.l2c.overall_misses::total 1841838 # number of overall misses 1394system.l2c.WritebackDirty_accesses::writebacks 2746880 # number of WritebackDirty accesses(hits+misses) 1395system.l2c.WritebackDirty_accesses::total 2746880 # number of WritebackDirty accesses(hits+misses) 1396system.l2c.UpgradeReq_accesses::cpu0.data 82740 # number of UpgradeReq accesses(hits+misses) 1397system.l2c.UpgradeReq_accesses::cpu1.data 76160 # number of UpgradeReq accesses(hits+misses) 1398system.l2c.UpgradeReq_accesses::total 158900 # number of UpgradeReq accesses(hits+misses) 1399system.l2c.SCUpgradeReq_accesses::cpu0.data 9313 # number of SCUpgradeReq accesses(hits+misses) 1400system.l2c.SCUpgradeReq_accesses::cpu1.data 8745 # number of SCUpgradeReq accesses(hits+misses) 1401system.l2c.SCUpgradeReq_accesses::total 18058 # number of SCUpgradeReq accesses(hits+misses) 1402system.l2c.ReadExReq_accesses::cpu0.data 1131892 # number of ReadExReq accesses(hits+misses) 1403system.l2c.ReadExReq_accesses::cpu1.data 809577 # number of ReadExReq accesses(hits+misses) 1404system.l2c.ReadExReq_accesses::total 1941469 # number of ReadExReq accesses(hits+misses) 1405system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8724 # number of ReadSharedReq accesses(hits+misses) 1406system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6543 # number of ReadSharedReq accesses(hits+misses) 1407system.l2c.ReadSharedReq_accesses::cpu0.inst 503773 # number of ReadSharedReq accesses(hits+misses) 1408system.l2c.ReadSharedReq_accesses::cpu0.data 912814 # number of ReadSharedReq accesses(hits+misses) 1409system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9041 # number of ReadSharedReq accesses(hits+misses) 1410system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7061 # number of ReadSharedReq accesses(hits+misses) 1411system.l2c.ReadSharedReq_accesses::cpu1.inst 458216 # number of ReadSharedReq accesses(hits+misses) 1412system.l2c.ReadSharedReq_accesses::cpu1.data 863413 # number of ReadSharedReq accesses(hits+misses) 1413system.l2c.ReadSharedReq_accesses::total 2769585 # number of ReadSharedReq accesses(hits+misses) 1414system.l2c.demand_accesses::cpu0.dtb.walker 8724 # number of demand (read+write) accesses 1415system.l2c.demand_accesses::cpu0.itb.walker 6543 # number of demand (read+write) accesses 1416system.l2c.demand_accesses::cpu0.inst 503773 # number of demand (read+write) accesses 1417system.l2c.demand_accesses::cpu0.data 2044706 # number of demand (read+write) accesses 1418system.l2c.demand_accesses::cpu1.dtb.walker 9041 # number of demand (read+write) accesses 1419system.l2c.demand_accesses::cpu1.itb.walker 7061 # number of demand (read+write) accesses 1420system.l2c.demand_accesses::cpu1.inst 458216 # number of demand (read+write) accesses 1421system.l2c.demand_accesses::cpu1.data 1672990 # number of demand (read+write) accesses 1422system.l2c.demand_accesses::total 4711054 # number of demand (read+write) accesses 1423system.l2c.overall_accesses::cpu0.dtb.walker 8724 # number of overall (read+write) accesses 1424system.l2c.overall_accesses::cpu0.itb.walker 6543 # number of overall (read+write) accesses 1425system.l2c.overall_accesses::cpu0.inst 503773 # number of overall (read+write) accesses 1426system.l2c.overall_accesses::cpu0.data 2044706 # number of overall (read+write) accesses 1427system.l2c.overall_accesses::cpu1.dtb.walker 9041 # number of overall (read+write) accesses 1428system.l2c.overall_accesses::cpu1.itb.walker 7061 # number of overall (read+write) accesses 1429system.l2c.overall_accesses::cpu1.inst 458216 # number of overall (read+write) accesses 1430system.l2c.overall_accesses::cpu1.data 1672990 # number of overall (read+write) accesses 1431system.l2c.overall_accesses::total 4711054 # number of overall (read+write) accesses 1432system.l2c.UpgradeReq_miss_rate::cpu0.data 0.822649 # miss rate for UpgradeReq accesses 1433system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831565 # miss rate for UpgradeReq accesses 1434system.l2c.UpgradeReq_miss_rate::total 0.826923 # miss rate for UpgradeReq accesses 1435system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.841834 # miss rate for SCUpgradeReq accesses 1436system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.854889 # miss rate for SCUpgradeReq accesses 1437system.l2c.SCUpgradeReq_miss_rate::total 0.848156 # miss rate for SCUpgradeReq accesses 1438system.l2c.ReadExReq_miss_rate::cpu0.data 0.720649 # miss rate for ReadExReq accesses 1439system.l2c.ReadExReq_miss_rate::cpu1.data 0.675605 # miss rate for ReadExReq accesses 1440system.l2c.ReadExReq_miss_rate::total 0.701866 # miss rate for ReadExReq accesses 1441system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for ReadSharedReq accesses 1442system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303072 # miss rate for ReadSharedReq accesses 1443system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.114466 # miss rate for ReadSharedReq accesses 1444system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198813 # miss rate for ReadSharedReq accesses 1445system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for ReadSharedReq accesses 1446system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.487041 # miss rate for ReadSharedReq accesses 1447system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090752 # miss rate for ReadSharedReq accesses 1448system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.216806 # miss rate for ReadSharedReq accesses 1449system.l2c.ReadSharedReq_miss_rate::total 0.173018 # miss rate for ReadSharedReq accesses 1450system.l2c.demand_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for demand accesses 1451system.l2c.demand_miss_rate::cpu0.itb.walker 0.303072 # miss rate for demand accesses 1452system.l2c.demand_miss_rate::cpu0.inst 0.114466 # miss rate for demand accesses 1453system.l2c.demand_miss_rate::cpu0.data 0.487687 # miss rate for demand accesses 1454system.l2c.demand_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for demand accesses 1455system.l2c.demand_miss_rate::cpu1.itb.walker 0.487041 # miss rate for demand accesses 1456system.l2c.demand_miss_rate::cpu1.inst 0.090752 # miss rate for demand accesses 1457system.l2c.demand_miss_rate::cpu1.data 0.438823 # miss rate for demand accesses 1458system.l2c.demand_miss_rate::total 0.390961 # miss rate for demand accesses 1459system.l2c.overall_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for overall accesses 1460system.l2c.overall_miss_rate::cpu0.itb.walker 0.303072 # miss rate for overall accesses 1461system.l2c.overall_miss_rate::cpu0.inst 0.114466 # miss rate for overall accesses 1462system.l2c.overall_miss_rate::cpu0.data 0.487687 # miss rate for overall accesses 1463system.l2c.overall_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for overall accesses 1464system.l2c.overall_miss_rate::cpu1.itb.walker 0.487041 # miss rate for overall accesses 1465system.l2c.overall_miss_rate::cpu1.inst 0.090752 # miss rate for overall accesses 1466system.l2c.overall_miss_rate::cpu1.data 0.438823 # miss rate for overall accesses 1467system.l2c.overall_miss_rate::total 0.390961 # miss rate for overall accesses | 1314system.l2c.tags.age_task_id_blocks_1024::1 457 # Occupied blocks per task id 1315system.l2c.tags.age_task_id_blocks_1024::2 3184 # Occupied blocks per task id 1316system.l2c.tags.age_task_id_blocks_1024::3 5196 # Occupied blocks per task id 1317system.l2c.tags.age_task_id_blocks_1024::4 49841 # Occupied blocks per task id 1318system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id 1319system.l2c.tags.occ_task_id_percent::1024 0.896103 # Percentage of cache occupancy per task id 1320system.l2c.tags.tag_accesses 73222946 # Number of tag accesses 1321system.l2c.tags.data_accesses 73222946 # Number of data accesses 1322system.l2c.WritebackDirty_hits::writebacks 2756862 # number of WritebackDirty hits 1323system.l2c.WritebackDirty_hits::total 2756862 # number of WritebackDirty hits 1324system.l2c.UpgradeReq_hits::cpu0.data 19292 # number of UpgradeReq hits 1325system.l2c.UpgradeReq_hits::cpu1.data 16576 # number of UpgradeReq hits 1326system.l2c.UpgradeReq_hits::total 35868 # number of UpgradeReq hits 1327system.l2c.SCUpgradeReq_hits::cpu0.data 2708 # number of SCUpgradeReq hits 1328system.l2c.SCUpgradeReq_hits::cpu1.data 2412 # number of SCUpgradeReq hits 1329system.l2c.SCUpgradeReq_hits::total 5120 # number of SCUpgradeReq hits 1330system.l2c.ReadExReq_hits::cpu0.data 311775 # number of ReadExReq hits 1331system.l2c.ReadExReq_hits::cpu1.data 276099 # number of ReadExReq hits 1332system.l2c.ReadExReq_hits::total 587874 # number of ReadExReq hits 1333system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6229 # number of ReadSharedReq hits 1334system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4594 # number of ReadSharedReq hits 1335system.l2c.ReadSharedReq_hits::cpu0.inst 436955 # number of ReadSharedReq hits 1336system.l2c.ReadSharedReq_hits::cpu0.data 721918 # number of ReadSharedReq hits 1337system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5484 # number of ReadSharedReq hits 1338system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3754 # number of ReadSharedReq hits 1339system.l2c.ReadSharedReq_hits::cpu1.inst 425773 # number of ReadSharedReq hits 1340system.l2c.ReadSharedReq_hits::cpu1.data 684534 # number of ReadSharedReq hits 1341system.l2c.ReadSharedReq_hits::total 2289241 # number of ReadSharedReq hits 1342system.l2c.demand_hits::cpu0.dtb.walker 6229 # number of demand (read+write) hits 1343system.l2c.demand_hits::cpu0.itb.walker 4594 # number of demand (read+write) hits 1344system.l2c.demand_hits::cpu0.inst 436955 # number of demand (read+write) hits 1345system.l2c.demand_hits::cpu0.data 1033693 # number of demand (read+write) hits 1346system.l2c.demand_hits::cpu1.dtb.walker 5484 # number of demand (read+write) hits 1347system.l2c.demand_hits::cpu1.itb.walker 3754 # number of demand (read+write) hits 1348system.l2c.demand_hits::cpu1.inst 425773 # number of demand (read+write) hits 1349system.l2c.demand_hits::cpu1.data 960633 # number of demand (read+write) hits 1350system.l2c.demand_hits::total 2877115 # number of demand (read+write) hits 1351system.l2c.overall_hits::cpu0.dtb.walker 6229 # number of overall hits 1352system.l2c.overall_hits::cpu0.itb.walker 4594 # number of overall hits 1353system.l2c.overall_hits::cpu0.inst 436955 # number of overall hits 1354system.l2c.overall_hits::cpu0.data 1033693 # number of overall hits 1355system.l2c.overall_hits::cpu1.dtb.walker 5484 # number of overall hits 1356system.l2c.overall_hits::cpu1.itb.walker 3754 # number of overall hits 1357system.l2c.overall_hits::cpu1.inst 425773 # number of overall hits 1358system.l2c.overall_hits::cpu1.data 960633 # number of overall hits 1359system.l2c.overall_hits::total 2877115 # number of overall hits 1360system.l2c.UpgradeReq_misses::cpu0.data 65194 # number of UpgradeReq misses 1361system.l2c.UpgradeReq_misses::cpu1.data 61685 # number of UpgradeReq misses 1362system.l2c.UpgradeReq_misses::total 126879 # number of UpgradeReq misses 1363system.l2c.SCUpgradeReq_misses::cpu0.data 6603 # number of SCUpgradeReq misses 1364system.l2c.SCUpgradeReq_misses::cpu1.data 6332 # number of SCUpgradeReq misses 1365system.l2c.SCUpgradeReq_misses::total 12935 # number of SCUpgradeReq misses 1366system.l2c.ReadExReq_misses::cpu0.data 822855 # number of ReadExReq misses 1367system.l2c.ReadExReq_misses::cpu1.data 542831 # number of ReadExReq misses 1368system.l2c.ReadExReq_misses::total 1365686 # number of ReadExReq misses 1369system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2437 # number of ReadSharedReq misses 1370system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses 1371system.l2c.ReadSharedReq_misses::cpu0.inst 58588 # number of ReadSharedReq misses 1372system.l2c.ReadSharedReq_misses::cpu0.data 182243 # number of ReadSharedReq misses 1373system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3396 # number of ReadSharedReq misses 1374system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3346 # number of ReadSharedReq misses 1375system.l2c.ReadSharedReq_misses::cpu1.inst 41232 # number of ReadSharedReq misses 1376system.l2c.ReadSharedReq_misses::cpu1.data 187565 # number of ReadSharedReq misses 1377system.l2c.ReadSharedReq_misses::total 480860 # number of ReadSharedReq misses 1378system.l2c.demand_misses::cpu0.dtb.walker 2437 # number of demand (read+write) misses 1379system.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses 1380system.l2c.demand_misses::cpu0.inst 58588 # number of demand (read+write) misses 1381system.l2c.demand_misses::cpu0.data 1005098 # number of demand (read+write) misses 1382system.l2c.demand_misses::cpu1.dtb.walker 3396 # number of demand (read+write) misses 1383system.l2c.demand_misses::cpu1.itb.walker 3346 # number of demand (read+write) misses 1384system.l2c.demand_misses::cpu1.inst 41232 # number of demand (read+write) misses 1385system.l2c.demand_misses::cpu1.data 730396 # number of demand (read+write) misses 1386system.l2c.demand_misses::total 1846546 # number of demand (read+write) misses 1387system.l2c.overall_misses::cpu0.dtb.walker 2437 # number of overall misses 1388system.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses 1389system.l2c.overall_misses::cpu0.inst 58588 # number of overall misses 1390system.l2c.overall_misses::cpu0.data 1005098 # number of overall misses 1391system.l2c.overall_misses::cpu1.dtb.walker 3396 # number of overall misses 1392system.l2c.overall_misses::cpu1.itb.walker 3346 # number of overall misses 1393system.l2c.overall_misses::cpu1.inst 41232 # number of overall misses 1394system.l2c.overall_misses::cpu1.data 730396 # number of overall misses 1395system.l2c.overall_misses::total 1846546 # number of overall misses 1396system.l2c.WritebackDirty_accesses::writebacks 2756862 # number of WritebackDirty accesses(hits+misses) 1397system.l2c.WritebackDirty_accesses::total 2756862 # number of WritebackDirty accesses(hits+misses) 1398system.l2c.UpgradeReq_accesses::cpu0.data 84486 # number of UpgradeReq accesses(hits+misses) 1399system.l2c.UpgradeReq_accesses::cpu1.data 78261 # number of UpgradeReq accesses(hits+misses) 1400system.l2c.UpgradeReq_accesses::total 162747 # number of UpgradeReq accesses(hits+misses) 1401system.l2c.SCUpgradeReq_accesses::cpu0.data 9311 # number of SCUpgradeReq accesses(hits+misses) 1402system.l2c.SCUpgradeReq_accesses::cpu1.data 8744 # number of SCUpgradeReq accesses(hits+misses) 1403system.l2c.SCUpgradeReq_accesses::total 18055 # number of SCUpgradeReq accesses(hits+misses) 1404system.l2c.ReadExReq_accesses::cpu0.data 1134630 # number of ReadExReq accesses(hits+misses) 1405system.l2c.ReadExReq_accesses::cpu1.data 818930 # number of ReadExReq accesses(hits+misses) 1406system.l2c.ReadExReq_accesses::total 1953560 # number of ReadExReq accesses(hits+misses) 1407system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8666 # number of ReadSharedReq accesses(hits+misses) 1408system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6647 # number of ReadSharedReq accesses(hits+misses) 1409system.l2c.ReadSharedReq_accesses::cpu0.inst 495543 # number of ReadSharedReq accesses(hits+misses) 1410system.l2c.ReadSharedReq_accesses::cpu0.data 904161 # number of ReadSharedReq accesses(hits+misses) 1411system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8880 # number of ReadSharedReq accesses(hits+misses) 1412system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7100 # number of ReadSharedReq accesses(hits+misses) 1413system.l2c.ReadSharedReq_accesses::cpu1.inst 467005 # number of ReadSharedReq accesses(hits+misses) 1414system.l2c.ReadSharedReq_accesses::cpu1.data 872099 # number of ReadSharedReq accesses(hits+misses) 1415system.l2c.ReadSharedReq_accesses::total 2770101 # number of ReadSharedReq accesses(hits+misses) 1416system.l2c.demand_accesses::cpu0.dtb.walker 8666 # number of demand (read+write) accesses 1417system.l2c.demand_accesses::cpu0.itb.walker 6647 # number of demand (read+write) accesses 1418system.l2c.demand_accesses::cpu0.inst 495543 # number of demand (read+write) accesses 1419system.l2c.demand_accesses::cpu0.data 2038791 # number of demand (read+write) accesses 1420system.l2c.demand_accesses::cpu1.dtb.walker 8880 # number of demand (read+write) accesses 1421system.l2c.demand_accesses::cpu1.itb.walker 7100 # number of demand (read+write) accesses 1422system.l2c.demand_accesses::cpu1.inst 467005 # number of demand (read+write) accesses 1423system.l2c.demand_accesses::cpu1.data 1691029 # number of demand (read+write) accesses 1424system.l2c.demand_accesses::total 4723661 # number of demand (read+write) accesses 1425system.l2c.overall_accesses::cpu0.dtb.walker 8666 # number of overall (read+write) accesses 1426system.l2c.overall_accesses::cpu0.itb.walker 6647 # number of overall (read+write) accesses 1427system.l2c.overall_accesses::cpu0.inst 495543 # number of overall (read+write) accesses 1428system.l2c.overall_accesses::cpu0.data 2038791 # number of overall (read+write) accesses 1429system.l2c.overall_accesses::cpu1.dtb.walker 8880 # number of overall (read+write) accesses 1430system.l2c.overall_accesses::cpu1.itb.walker 7100 # number of overall (read+write) accesses 1431system.l2c.overall_accesses::cpu1.inst 467005 # number of overall (read+write) accesses 1432system.l2c.overall_accesses::cpu1.data 1691029 # number of overall (read+write) accesses 1433system.l2c.overall_accesses::total 4723661 # number of overall (read+write) accesses 1434system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771654 # miss rate for UpgradeReq accesses 1435system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788196 # miss rate for UpgradeReq accesses 1436system.l2c.UpgradeReq_miss_rate::total 0.779609 # miss rate for UpgradeReq accesses 1437system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.709161 # miss rate for SCUpgradeReq accesses 1438system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.724154 # miss rate for SCUpgradeReq accesses 1439system.l2c.SCUpgradeReq_miss_rate::total 0.716422 # miss rate for SCUpgradeReq accesses 1440system.l2c.ReadExReq_miss_rate::cpu0.data 0.725219 # miss rate for ReadExReq accesses 1441system.l2c.ReadExReq_miss_rate::cpu1.data 0.662854 # miss rate for ReadExReq accesses 1442system.l2c.ReadExReq_miss_rate::total 0.699076 # miss rate for ReadExReq accesses 1443system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for ReadSharedReq accesses 1444system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.308861 # miss rate for ReadSharedReq accesses 1445system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.118230 # miss rate for ReadSharedReq accesses 1446system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201560 # miss rate for ReadSharedReq accesses 1447system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for ReadSharedReq accesses 1448system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.471268 # miss rate for ReadSharedReq accesses 1449system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.088290 # miss rate for ReadSharedReq accesses 1450system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215073 # miss rate for ReadSharedReq accesses 1451system.l2c.ReadSharedReq_miss_rate::total 0.173589 # miss rate for ReadSharedReq accesses 1452system.l2c.demand_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for demand accesses 1453system.l2c.demand_miss_rate::cpu0.itb.walker 0.308861 # miss rate for demand accesses 1454system.l2c.demand_miss_rate::cpu0.inst 0.118230 # miss rate for demand accesses 1455system.l2c.demand_miss_rate::cpu0.data 0.492987 # miss rate for demand accesses 1456system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for demand accesses 1457system.l2c.demand_miss_rate::cpu1.itb.walker 0.471268 # miss rate for demand accesses 1458system.l2c.demand_miss_rate::cpu1.inst 0.088290 # miss rate for demand accesses 1459system.l2c.demand_miss_rate::cpu1.data 0.431924 # miss rate for demand accesses 1460system.l2c.demand_miss_rate::total 0.390914 # miss rate for demand accesses 1461system.l2c.overall_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for overall accesses 1462system.l2c.overall_miss_rate::cpu0.itb.walker 0.308861 # miss rate for overall accesses 1463system.l2c.overall_miss_rate::cpu0.inst 0.118230 # miss rate for overall accesses 1464system.l2c.overall_miss_rate::cpu0.data 0.492987 # miss rate for overall accesses 1465system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for overall accesses 1466system.l2c.overall_miss_rate::cpu1.itb.walker 0.471268 # miss rate for overall accesses 1467system.l2c.overall_miss_rate::cpu1.inst 0.088290 # miss rate for overall accesses 1468system.l2c.overall_miss_rate::cpu1.data 0.431924 # miss rate for overall accesses 1469system.l2c.overall_miss_rate::total 0.390914 # miss rate for overall accesses |
| 1468system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1469system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1470system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1471system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1472system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1473system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1474system.l2c.fast_writes 0 # number of fast writes performed 1475system.l2c.cache_copies 0 # number of cache copies performed | 1470system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1471system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1472system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1473system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1474system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1475system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1476system.l2c.fast_writes 0 # number of fast writes performed 1477system.l2c.cache_copies 0 # number of cache copies performed |
| 1476system.l2c.writebacks::writebacks 1470290 # number of writebacks 1477system.l2c.writebacks::total 1470290 # number of writebacks | 1478system.l2c.writebacks::writebacks 1476146 # number of writebacks 1479system.l2c.writebacks::total 1476146 # number of writebacks |
| 1478system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 1480system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1479system.membus.trans_dist::ReadReq 82131 # Transaction distribution 1480system.membus.trans_dist::ReadResp 570231 # Transaction distribution 1481system.membus.trans_dist::WriteReq 38802 # Transaction distribution 1482system.membus.trans_dist::WriteResp 38802 # Transaction distribution 1483system.membus.trans_dist::WritebackDirty 1576984 # Transaction distribution 1484system.membus.trans_dist::CleanEvict 244820 # Transaction distribution 1485system.membus.trans_dist::UpgradeReq 347427 # Transaction distribution 1486system.membus.trans_dist::SCUpgradeReq 314914 # Transaction distribution 1487system.membus.trans_dist::UpgradeResp 168909 # Transaction distribution 1488system.membus.trans_dist::ReadExReq 1611622 # Transaction distribution 1489system.membus.trans_dist::ReadExResp 1340459 # Transaction distribution 1490system.membus.trans_dist::ReadSharedReq 488100 # Transaction distribution | 1481system.membus.trans_dist::ReadReq 82185 # Transaction distribution 1482system.membus.trans_dist::ReadResp 571969 # Transaction distribution 1483system.membus.trans_dist::WriteReq 38847 # Transaction distribution 1484system.membus.trans_dist::WriteResp 38847 # Transaction distribution 1485system.membus.trans_dist::WritebackDirty 1582840 # Transaction distribution 1486system.membus.trans_dist::CleanEvict 248395 # Transaction distribution 1487system.membus.trans_dist::UpgradeReq 346027 # Transaction distribution 1488system.membus.trans_dist::SCUpgradeReq 310425 # Transaction distribution 1489system.membus.trans_dist::UpgradeResp 161621 # Transaction distribution 1490system.membus.trans_dist::ReadExReq 1349349 # Transaction distribution 1491system.membus.trans_dist::ReadExResp 1343882 # Transaction distribution 1492system.membus.trans_dist::ReadSharedReq 489784 # Transaction distribution |
| 1491system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 1492system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution | 1493system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 1494system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution |
| 1493system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) | 1495system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) |
| 1494system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) | 1496system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) |
| 1495system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) 1496system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6542117 # Packet count per connected master and slave (bytes) 1497system.membus.pkt_count_system.l2c.mem_side::total 6692337 # Packet count per connected master and slave (bytes) 1498system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344320 # Packet count per connected master and slave (bytes) 1499system.membus.pkt_count_system.iocache.mem_side::total 344320 # Packet count per connected master and slave (bytes) 1500system.membus.pkt_count::total 7036657 # Packet count per connected master and slave (bytes) 1501system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) | 1497system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) 1498system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6280303 # Packet count per connected master and slave (bytes) 1499system.membus.pkt_count_system.l2c.mem_side::total 6430721 # Packet count per connected master and slave (bytes) 1500system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) 1501system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) 1502system.membus.pkt_count::total 6777627 # Packet count per connected master and slave (bytes) 1503system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) |
| 1502system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) | 1504system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) |
| 1503system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) 1504system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210749660 # Cumulative packet size per connected master and slave (bytes) 1505system.membus.pkt_size_system.l2c.mem_side::total 210960657 # Cumulative packet size per connected master and slave (bytes) 1506system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) 1507system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) 1508system.membus.pkt_size::total 218359505 # Cumulative packet size per connected master and slave (bytes) | 1505system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) 1506system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211450588 # Cumulative packet size per connected master and slave (bytes) 1507system.membus.pkt_size_system.l2c.mem_side::total 211661967 # Cumulative packet size per connected master and slave (bytes) 1508system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) 1509system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) 1510system.membus.pkt_size::total 219061519 # Cumulative packet size per connected master and slave (bytes) |
| 1509system.membus.snoops 0 # Total snoops (count) | 1511system.membus.snoops 0 # Total snoops (count) |
| 1510system.membus.snoop_fanout::samples 4814081 # Request fanout histogram | 1512system.membus.snoop_fanout::samples 4554580 # Request fanout histogram |
| 1511system.membus.snoop_fanout::mean 1 # Request fanout histogram 1512system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1513system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1514system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1513system.membus.snoop_fanout::mean 1 # Request fanout histogram 1514system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1515system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1516system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1515system.membus.snoop_fanout::1 4814081 100.00% 100.00% # Request fanout histogram | 1517system.membus.snoop_fanout::1 4554580 100.00% 100.00% # Request fanout histogram |
| 1516system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1517system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1518system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1519system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1518system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1519system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1520system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1521system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1520system.membus.snoop_fanout::total 4814081 # Request fanout histogram | 1522system.membus.snoop_fanout::total 4554580 # Request fanout histogram |
| 1521system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1522system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1523system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1524system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1525system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1526system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1527system.realview.ethernet.txBytes 966 # Bytes Transmitted 1528system.realview.ethernet.txPackets 3 # Number of Packets Transmitted --- 36 unchanged lines hidden (view full) --- 1565system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1566system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1567system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1568system.realview.ethernet.droppedPackets 0 # number of packets dropped 1569system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1570system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1571system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1572system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1523system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1524system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1525system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1526system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1527system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1528system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1529system.realview.ethernet.txBytes 966 # Bytes Transmitted 1530system.realview.ethernet.txPackets 3 # Number of Packets Transmitted --- 36 unchanged lines hidden (view full) --- 1567system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1568system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1569system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1570system.realview.ethernet.droppedPackets 0 # number of packets dropped 1571system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1572system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1573system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1574system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1573system.toL2Bus.snoop_filter.tot_requests 11103531 # Total number of requests made to the snoop filter. 1574system.toL2Bus.snoop_filter.hit_single_requests 5720804 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1575system.toL2Bus.snoop_filter.hit_multi_requests 1657088 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1576system.toL2Bus.snoop_filter.tot_snoops 128474 # Total number of snoops made to the snoop filter. 1577system.toL2Bus.snoop_filter.hit_single_snoops 115294 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1578system.toL2Bus.snoop_filter.hit_multi_snoops 13180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1579system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution 1580system.toL2Bus.trans_dist::ReadResp 3545235 # Transaction distribution 1581system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution 1582system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution 1583system.toL2Bus.trans_dist::WritebackDirty 2746880 # Transaction distribution 1584system.toL2Bus.trans_dist::CleanEvict 1000532 # Transaction distribution 1585system.toL2Bus.trans_dist::UpgradeReq 352734 # Transaction distribution 1586system.toL2Bus.trans_dist::SCUpgradeReq 317656 # Transaction distribution 1587system.toL2Bus.trans_dist::UpgradeResp 670390 # Transaction distribution 1588system.toL2Bus.trans_dist::ReadExReq 2212632 # Transaction distribution 1589system.toL2Bus.trans_dist::ReadExResp 2212632 # Transaction distribution 1590system.toL2Bus.trans_dist::ReadSharedReq 3463102 # Transaction distribution 1591system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9045879 # Packet count per connected master and slave (bytes) 1592system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7635651 # Packet count per connected master and slave (bytes) 1593system.toL2Bus.pkt_count::total 16681530 # Packet count per connected master and slave (bytes) 1594system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295373981 # Cumulative packet size per connected master and slave (bytes) 1595system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 244078084 # Cumulative packet size per connected master and slave (bytes) 1596system.toL2Bus.pkt_size::total 539452065 # Cumulative packet size per connected master and slave (bytes) 1597system.toL2Bus.snoops 1992317 # Total snoops (count) 1598system.toL2Bus.snoop_fanout::samples 13215112 # Request fanout histogram 1599system.toL2Bus.snoop_fanout::mean 0.283607 # Request fanout histogram 1600system.toL2Bus.snoop_fanout::stdev 0.452956 # Request fanout histogram | 1575system.toL2Bus.snoop_filter.tot_requests 11149388 # Total number of requests made to the snoop filter. 1576system.toL2Bus.snoop_filter.hit_single_requests 5745365 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1577system.toL2Bus.snoop_filter.hit_multi_requests 1662887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1578system.toL2Bus.snoop_filter.tot_snoops 135292 # Total number of snoops made to the snoop filter. 1579system.toL2Bus.snoop_filter.hit_single_snoops 121804 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1580system.toL2Bus.snoop_filter.hit_multi_snoops 13488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1581system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution 1582system.toL2Bus.trans_dist::ReadResp 3554010 # Transaction distribution 1583system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution 1584system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution 1585system.toL2Bus.trans_dist::WritebackDirty 2756862 # Transaction distribution 1586system.toL2Bus.trans_dist::CleanEvict 2018423 # Transaction distribution 1587system.toL2Bus.trans_dist::UpgradeReq 360088 # Transaction distribution 1588system.toL2Bus.trans_dist::SCUpgradeReq 315545 # Transaction distribution 1589system.toL2Bus.trans_dist::UpgradeResp 675633 # Transaction distribution 1590system.toL2Bus.trans_dist::ReadExReq 2226645 # Transaction distribution 1591system.toL2Bus.trans_dist::ReadExResp 2226645 # Transaction distribution 1592system.toL2Bus.trans_dist::ReadSharedReq 3471823 # Transaction distribution 1593system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9531217 # Packet count per connected master and slave (bytes) 1594system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8234338 # Packet count per connected master and slave (bytes) 1595system.toL2Bus.pkt_count::total 17765555 # Packet count per connected master and slave (bytes) 1596system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294166716 # Cumulative packet size per connected master and slave (bytes) 1597system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 247379555 # Cumulative packet size per connected master and slave (bytes) 1598system.toL2Bus.pkt_size::total 541546271 # Cumulative packet size per connected master and slave (bytes) 1599system.toL2Bus.snoops 2005695 # Total snoops (count) 1600system.toL2Bus.snoop_fanout::samples 13274431 # Request fanout histogram 1601system.toL2Bus.snoop_fanout::mean 0.283856 # Request fanout histogram 1602system.toL2Bus.snoop_fanout::stdev 0.453116 # Request fanout histogram |
| 1601system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1603system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1602system.toL2Bus.snoop_fanout::0 9480390 71.74% 71.74% # Request fanout histogram 1603system.toL2Bus.snoop_fanout::1 3721542 28.16% 99.90% # Request fanout histogram 1604system.toL2Bus.snoop_fanout::2 13180 0.10% 100.00% # Request fanout histogram | 1604system.toL2Bus.snoop_fanout::0 9519891 71.72% 71.72% # Request fanout histogram 1605system.toL2Bus.snoop_fanout::1 3741052 28.18% 99.90% # Request fanout histogram 1606system.toL2Bus.snoop_fanout::2 13488 0.10% 100.00% # Request fanout histogram |
| 1605system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1606system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1607system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1607system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1608system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1609system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1608system.toL2Bus.snoop_fanout::total 13215112 # Request fanout histogram | 1610system.toL2Bus.snoop_fanout::total 13274431 # Request fanout histogram |
| 1609 1610---------- End Simulation Statistics ---------- | 1611 1612---------- End Simulation Statistics ---------- |