| stats.txt (10752:62b24818c8c6) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.216814 # Number of seconds simulated 4sim_ticks 47216814145000 # Number of ticks simulated 5final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.216814 # Number of seconds simulated 4sim_ticks 47216814145000 # Number of ticks simulated 5final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1225013 # Simulator instruction rate (inst/s) 8host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59296512316 # Simulator tick rate (ticks/s) 10host_mem_usage 723320 # Number of bytes of host memory used 11host_seconds 796.28 # Real time elapsed on the host | 7host_inst_rate 1152960 # Simulator instruction rate (inst/s) 8host_op_rate 1356355 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55808802200 # Simulator tick rate (ticks/s) 10host_mem_usage 723640 # Number of bytes of host memory used 11host_seconds 846.05 # Real time elapsed on the host |
| 12sim_insts 975457230 # Number of instructions simulated 13sim_ops 1147538415 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 975457230 # Number of instructions simulated 13sim_ops 1147538415 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 152320 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory 25system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory | 18system.physmem.bytes_read::cpu0.inst 3903156 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 35201416 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 2639368 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 38466864 # Number of bytes read from this memory 24system.physmem.bytes_read::realview.ide 412736 # Number of bytes read from this memory 25system.physmem.bytes_read::total 81348148 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 3903156 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 2639368 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 6542524 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 100538752 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory | 32system.physmem.bytes_written::total 100559336 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 2380 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory | 35system.physmem.num_reads::cpu0.inst 101394 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 550035 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 41347 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 601061 # Number of read requests responded to by this memory 41system.physmem.num_reads::realview.ide 6449 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 1311608 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 1570918 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory |
| 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.num_writes::total 1573492 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 3226 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu0.inst 82665 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 745527 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.itb.walker 4693 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 55899 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 814686 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 8741 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 1722864 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 82665 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 55899 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 138563 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2129300 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_write::total 2129736 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2129300 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 3226 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) |
| 67system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s) | 67system.physmem.bw_total::cpu0.inst 82665 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 745963 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.itb.walker 4693 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 55899 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 814686 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 8741 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 3852600 # Total bandwidth to/from this memory (bytes/s) |
| 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 215 unchanged lines hidden (view full) --- 298system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 299system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 300system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction 301system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 302system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 303system.cpu0.op_class::total 585300003 # Class of executed instruction 304system.cpu0.kern.inst.arm 0 # number of arm instructions executed 305system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed | 75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory --- 215 unchanged lines hidden (view full) --- 298system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 299system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 300system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction 301system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 302system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 303system.cpu0.op_class::total 585300003 # Class of executed instruction 304system.cpu0.kern.inst.arm 0 # number of arm instructions executed 305system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed |
| 306system.cpu0.dcache.tags.replacements 6272759 # number of replacements | 306system.cpu0.dcache.tags.replacements 6272773 # number of replacements |
| 307system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use | 307system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use |
| 308system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks. 311system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. | 308system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks. 309system.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks. 310system.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks. 311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. |
| 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 314system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy 315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 320system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses 322system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits | 320system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses 321system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses 322system.cpu0.dcache.ReadReq_hits::cpu0.data 86214909 # number of ReadReq hits 323system.cpu0.dcache.ReadReq_hits::total 86214909 # number of ReadReq hits 324system.cpu0.dcache.WriteReq_hits::cpu0.data 80919814 # number of WriteReq hits 325system.cpu0.dcache.WriteReq_hits::total 80919814 # number of WriteReq hits 326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits 327system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits |
| 328system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits 329system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits | 328system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits 329system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits |
| 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits 334system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits 337system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses | 330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076465 # number of LoadLockedReq hits 331system.cpu0.dcache.LoadLockedReq_hits::total 2076465 # number of LoadLockedReq hits 332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036713 # number of StoreCondReq hits 333system.cpu0.dcache.StoreCondReq_hits::total 2036713 # number of StoreCondReq hits 334system.cpu0.dcache.demand_hits::cpu0.data 167134723 # number of demand (read+write) hits 335system.cpu0.dcache.demand_hits::total 167134723 # number of demand (read+write) hits 336system.cpu0.dcache.overall_hits::cpu0.data 167350377 # number of overall hits 337system.cpu0.dcache.overall_hits::total 167350377 # number of overall hits 338system.cpu0.dcache.ReadReq_misses::cpu0.data 3309384 # number of ReadReq misses 339system.cpu0.dcache.ReadReq_misses::total 3309384 # number of ReadReq misses 340system.cpu0.dcache.WriteReq_misses::cpu0.data 1475628 # number of WriteReq misses 341system.cpu0.dcache.WriteReq_misses::total 1475628 # number of WriteReq misses 342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses 343system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses |
| 344system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses 345system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses | 344system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses 345system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses |
| 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses 350system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses 353system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses) | 346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119817 # number of LoadLockedReq misses 347system.cpu0.dcache.LoadLockedReq_misses::total 119817 # number of LoadLockedReq misses 348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158430 # number of StoreCondReq misses 349system.cpu0.dcache.StoreCondReq_misses::total 158430 # number of StoreCondReq misses 350system.cpu0.dcache.demand_misses::cpu0.data 4785012 # number of demand (read+write) misses 351system.cpu0.dcache.demand_misses::total 4785012 # number of demand (read+write) misses 352system.cpu0.dcache.overall_misses::cpu0.data 5557151 # number of overall misses 353system.cpu0.dcache.overall_misses::total 5557151 # number of overall misses 354system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) 355system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) 356system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) 357system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) |
| 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) 361system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) | 358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 359system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 360system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) 361system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) 362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 363system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 365system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) |
| 366system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses | 366system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses 367system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses 368system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses 369system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses |
| 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses | 370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 371system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses |
| 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses | 372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses 373system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses 374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses 375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses |
| 376system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses 377system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses | 376system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses 377system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses 378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses |
| 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses | 380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072173 # miss rate for StoreCondReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072173 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses 383system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses |
| 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu0.dcache.fast_writes 0 # number of fast writes performed 393system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses 385system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses 386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu0.dcache.fast_writes 0 # number of fast writes performed 393system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 394system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks 395system.cpu0.dcache.writebacks::total 4469723 # number of writebacks | 394system.cpu0.dcache.writebacks::writebacks 4471084 # number of writebacks 395system.cpu0.dcache.writebacks::total 4471084 # number of writebacks |
| 396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 397system.cpu0.icache.tags.replacements 5539081 # number of replacements | 397system.cpu0.icache.tags.replacements 5539078 # number of replacements |
| 398system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use | 398system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use |
| 399system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. 400system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. 401system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. | 399system.cpu0.icache.tags.total_refs 492212894 # Total number of references to valid blocks. 400system.cpu0.icache.tags.sampled_refs 5539590 # Sample count of references to valid blocks. 401system.cpu0.icache.tags.avg_refs 88.853669 # Average number of references to valid blocks. |
| 402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 406system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 409system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 410system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 411system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 406system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 409system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 410system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 411system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 412system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses 413system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses 414system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits 415system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits 416system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits 417system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits 418system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits 419system.cpu0.icache.overall_hits::total 492212891 # number of overall hits 420system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses 421system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses 422system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses 423system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses 424system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses 425system.cpu0.icache.overall_misses::total 5539598 # number of overall misses | 412system.cpu0.icache.tags.tag_accesses 1001044573 # Number of tag accesses 413system.cpu0.icache.tags.data_accesses 1001044573 # Number of data accesses 414system.cpu0.icache.ReadReq_hits::cpu0.inst 492212894 # number of ReadReq hits 415system.cpu0.icache.ReadReq_hits::total 492212894 # number of ReadReq hits 416system.cpu0.icache.demand_hits::cpu0.inst 492212894 # number of demand (read+write) hits 417system.cpu0.icache.demand_hits::total 492212894 # number of demand (read+write) hits 418system.cpu0.icache.overall_hits::cpu0.inst 492212894 # number of overall hits 419system.cpu0.icache.overall_hits::total 492212894 # number of overall hits 420system.cpu0.icache.ReadReq_misses::cpu0.inst 5539595 # number of ReadReq misses 421system.cpu0.icache.ReadReq_misses::total 5539595 # number of ReadReq misses 422system.cpu0.icache.demand_misses::cpu0.inst 5539595 # number of demand (read+write) misses 423system.cpu0.icache.demand_misses::total 5539595 # number of demand (read+write) misses 424system.cpu0.icache.overall_misses::cpu0.inst 5539595 # number of overall misses 425system.cpu0.icache.overall_misses::total 5539595 # number of overall misses |
| 426system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 427system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 428system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 429system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 430system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 431system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 432system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 433system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses --- 11 unchanged lines hidden (view full) --- 445system.cpu0.icache.cache_copies 0 # number of cache copies performed 446system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 447system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 448system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 449system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 450system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 451system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 452system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 426system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 427system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 428system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 429system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 430system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 431system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 432system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 433system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses --- 11 unchanged lines hidden (view full) --- 445system.cpu0.icache.cache_copies 0 # number of cache copies performed 446system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 447system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 448system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 449system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 450system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 451system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 452system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 453system.cpu0.l2cache.tags.replacements 2710840 # number of replacements 454system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use 455system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks. 456system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks. 457system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks. | 453system.cpu0.l2cache.tags.replacements 2709460 # number of replacements 454system.cpu0.l2cache.tags.tagsinuse 16213.748169 # Cycle average of tags in use 455system.cpu0.l2cache.tags.total_refs 11555205 # Total number of references to valid blocks. 456system.cpu0.l2cache.tags.sampled_refs 2725459 # Sample count of references to valid blocks. 457system.cpu0.l2cache.tags.avg_refs 4.239728 # Average number of references to valid blocks. |
| 458system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. | 458system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. |
| 459system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor 460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor 461system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor 463system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor 464system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy 467system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy 468system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy 469system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy 470system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 471system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id 477system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id 478system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id 479system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id 480system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id 481system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 482system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id 483system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses 484system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses 485system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 269350 # number of ReadReq hits 486system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 141753 # number of ReadReq hits 487system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971397 # number of ReadReq hits 488system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944075 # number of ReadReq hits 489system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits 490system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits 491system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits 492system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222737 # number of WriteInvalidateReq hits 493system.cpu0.l2cache.WriteInvalidateReq_hits::total 222737 # number of WriteInvalidateReq hits 494system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3521 # number of UpgradeReq hits 495system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits 496system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634814 # number of ReadExReq hits 497system.cpu0.l2cache.ReadExReq_hits::total 634814 # number of ReadExReq hits 498system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 269350 # number of demand (read+write) hits 499system.cpu0.l2cache.demand_hits::cpu0.itb.walker 141753 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.inst 4971397 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::cpu0.data 3578889 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::total 8961389 # number of demand (read+write) hits 503system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 269350 # number of overall hits 504system.cpu0.l2cache.overall_hits::cpu0.itb.walker 141753 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.inst 4971397 # number of overall hits 506system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits 507system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits 508system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11316 # number of ReadReq misses 509system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8593 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::cpu0.inst 568201 # number of ReadReq misses 511system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257257 # number of ReadReq misses 512system.cpu0.l2cache.ReadReq_misses::total 1845367 # number of ReadReq misses 513system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses 514system.cpu0.l2cache.WriteInvalidateReq_misses::total 608598 # number of WriteInvalidateReq misses 515system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128143 # number of UpgradeReq misses 516system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses 517system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses 518system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses 519system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses 520system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses 521system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11316 # number of demand (read+write) misses 522system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8593 # number of demand (read+write) misses 523system.cpu0.l2cache.demand_misses::cpu0.inst 568201 # number of demand (read+write) misses 524system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::total 2554776 # number of demand (read+write) misses 526system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses 527system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses 528system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses 529system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses 530system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses 531system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses) 532system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses) 533system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses) 534system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses) 535system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses) 536system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses) 537system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses) 538system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses) 539system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses) 540system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses) 541system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses) 543system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses) 544system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses) 545system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses) 546system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses 547system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses 548system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses 549system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses 550system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses 551system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses 552system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150346 # number of overall (read+write) accesses 553system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses 554system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses 555system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses 556system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses 557system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses 558system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses 559system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses 560system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses 561system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses 562system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses 563system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses 564system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses | 459system.cpu0.l2cache.tags.occ_blocks::writebacks 5709.903296 # Average occupied blocks per requestor 460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.786445 # Average occupied blocks per requestor 461system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.022731 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4531.359232 # Average occupied blocks per requestor 463system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5862.676466 # Average occupied blocks per requestor 464system.cpu0.l2cache.tags.occ_percent::writebacks 0.348505 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003222 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003480 # Average percentage of cache occupancy 467system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276572 # Average percentage of cache occupancy 468system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357829 # Average percentage of cache occupancy 469system.cpu0.l2cache.tags.occ_percent::total 0.989609 # Average percentage of cache occupancy 470system.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id 471system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15951 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 234 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id 477system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4590 # Occupied blocks per task id 478system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5333 # Occupied blocks per task id 479system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4627 # Occupied blocks per task id 480system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id 481system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973572 # Percentage of cache occupancy per task id 482system.cpu0.l2cache.tags.tag_accesses 278732920 # Number of tag accesses 483system.cpu0.l2cache.tags.data_accesses 278732920 # Number of data accesses 484system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271204 # number of ReadReq hits 485system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 143552 # number of ReadReq hits 486system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971662 # number of ReadReq hits 487system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944246 # number of ReadReq hits 488system.cpu0.l2cache.ReadReq_hits::total 8330664 # number of ReadReq hits 489system.cpu0.l2cache.Writeback_hits::writebacks 4471084 # number of Writeback hits 490system.cpu0.l2cache.Writeback_hits::total 4471084 # number of Writeback hits 491system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 223142 # number of WriteInvalidateReq hits 492system.cpu0.l2cache.WriteInvalidateReq_hits::total 223142 # number of WriteInvalidateReq hits 493system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3523 # number of UpgradeReq hits 494system.cpu0.l2cache.UpgradeReq_hits::total 3523 # number of UpgradeReq hits 495system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635192 # number of ReadExReq hits 496system.cpu0.l2cache.ReadExReq_hits::total 635192 # number of ReadExReq hits 497system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271204 # number of demand (read+write) hits 498system.cpu0.l2cache.demand_hits::cpu0.itb.walker 143552 # number of demand (read+write) hits 499system.cpu0.l2cache.demand_hits::cpu0.inst 4971662 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.data 3579438 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::total 8965856 # number of demand (read+write) hits 502system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271204 # number of overall hits 503system.cpu0.l2cache.overall_hits::cpu0.itb.walker 143552 # number of overall hits 504system.cpu0.l2cache.overall_hits::cpu0.inst 4971662 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.data 3579438 # number of overall hits 506system.cpu0.l2cache.overall_hits::total 8965856 # number of overall hits 507system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11221 # number of ReadReq misses 508system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8442 # number of ReadReq misses 509system.cpu0.l2cache.ReadReq_misses::cpu0.inst 567933 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257094 # number of ReadReq misses 511system.cpu0.l2cache.ReadReq_misses::total 1844690 # number of ReadReq misses 512system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608192 # number of WriteInvalidateReq misses 513system.cpu0.l2cache.WriteInvalidateReq_misses::total 608192 # number of WriteInvalidateReq misses 514system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128237 # number of UpgradeReq misses 515system.cpu0.l2cache.UpgradeReq_misses::total 128237 # number of UpgradeReq misses 516system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158430 # number of SCUpgradeReq misses 517system.cpu0.l2cache.SCUpgradeReq_misses::total 158430 # number of SCUpgradeReq misses 518system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709038 # number of ReadExReq misses 519system.cpu0.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses 520system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11221 # number of demand (read+write) misses 521system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8442 # number of demand (read+write) misses 522system.cpu0.l2cache.demand_misses::cpu0.inst 567933 # number of demand (read+write) misses 523system.cpu0.l2cache.demand_misses::cpu0.data 1966132 # number of demand (read+write) misses 524system.cpu0.l2cache.demand_misses::total 2553728 # number of demand (read+write) misses 525system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11221 # number of overall misses 526system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8442 # number of overall misses 527system.cpu0.l2cache.overall_misses::cpu0.inst 567933 # number of overall misses 528system.cpu0.l2cache.overall_misses::cpu0.data 1966132 # number of overall misses 529system.cpu0.l2cache.overall_misses::total 2553728 # number of overall misses 530system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282425 # number of ReadReq accesses(hits+misses) 531system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151994 # number of ReadReq accesses(hits+misses) 532system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539595 # number of ReadReq accesses(hits+misses) 533system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201340 # number of ReadReq accesses(hits+misses) 534system.cpu0.l2cache.ReadReq_accesses::total 10175354 # number of ReadReq accesses(hits+misses) 535system.cpu0.l2cache.Writeback_accesses::writebacks 4471084 # number of Writeback accesses(hits+misses) 536system.cpu0.l2cache.Writeback_accesses::total 4471084 # number of Writeback accesses(hits+misses) 537system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831334 # number of WriteInvalidateReq accesses(hits+misses) 538system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831334 # number of WriteInvalidateReq accesses(hits+misses) 539system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131760 # number of UpgradeReq accesses(hits+misses) 540system.cpu0.l2cache.UpgradeReq_accesses::total 131760 # number of UpgradeReq accesses(hits+misses) 541system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158430 # number of SCUpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.SCUpgradeReq_accesses::total 158430 # number of SCUpgradeReq accesses(hits+misses) 543system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) 544system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) 545system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282425 # number of demand (read+write) accesses 546system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151994 # number of demand (read+write) accesses 547system.cpu0.l2cache.demand_accesses::cpu0.inst 5539595 # number of demand (read+write) accesses 548system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses 549system.cpu0.l2cache.demand_accesses::total 11519584 # number of demand (read+write) accesses 550system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282425 # number of overall (read+write) accesses 551system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151994 # number of overall (read+write) accesses 552system.cpu0.l2cache.overall_accesses::cpu0.inst 5539595 # number of overall (read+write) accesses 553system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses 554system.cpu0.l2cache.overall_accesses::total 11519584 # number of overall (read+write) accesses 555system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for ReadReq accesses 556system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.055542 # miss rate for ReadReq accesses 557system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102522 # miss rate for ReadReq accesses 558system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299213 # miss rate for ReadReq accesses 559system.cpu0.l2cache.ReadReq_miss_rate::total 0.181290 # miss rate for ReadReq accesses 560system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731586 # miss rate for WriteInvalidateReq accesses 561system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731586 # miss rate for WriteInvalidateReq accesses 562system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973262 # miss rate for UpgradeReq accesses 563system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973262 # miss rate for UpgradeReq accesses |
| 565system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 566system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 564system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 565system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 567system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses 568system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses 569system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses 570system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses 571system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses 572system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses 573system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses 574system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses 575system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses 576system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses 577system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses 578system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses | 566system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527468 # miss rate for ReadExReq accesses 567system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527468 # miss rate for ReadExReq accesses 568system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for demand accesses 569system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.055542 # miss rate for demand accesses 570system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102522 # miss rate for demand accesses 571system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354541 # miss rate for demand accesses 572system.cpu0.l2cache.demand_miss_rate::total 0.221686 # miss rate for demand accesses 573system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for overall accesses 574system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.055542 # miss rate for overall accesses 575system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102522 # miss rate for overall accesses 576system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354541 # miss rate for overall accesses 577system.cpu0.l2cache.overall_miss_rate::total 0.221686 # miss rate for overall accesses |
| 579system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 578system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 579system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 581system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 583system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 584system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 585system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 587system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks 588system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks | 586system.cpu0.l2cache.writebacks::writebacks 1573136 # number of writebacks 587system.cpu0.l2cache.writebacks::total 1573136 # number of writebacks |
| 589system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 588system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 590system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution 591system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution 592system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution 593system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution 594system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution 595system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution 602system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes) 603system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes) | 589system.cpu0.toL2Bus.trans_dist::ReadReq 10363944 # Transaction distribution 590system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution 591system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution 592system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution 593system.cpu0.toL2Bus.trans_dist::Writeback 4471084 # Transaction distribution 594system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831334 # Transaction distribution 595system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831334 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::UpgradeReq 131760 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158430 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::UpgradeResp 290190 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution 601system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165440 # Packet count per connected master and slave (bytes) 602system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17935148 # Packet count per connected master and slave (bytes) |
| 604system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 605system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) | 603system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 604system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) |
| 606system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes) 607system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) 608system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes) | 605system.cpu0.toL2Bus.pkt_count::total 30195318 # Packet count per connected master and slave (bytes) 606system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706580 # Cumulative packet size per connected master and slave (bytes) 607system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694464585 # Cumulative packet size per connected master and slave (bytes) |
| 609system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 610system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) | 608system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 609system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) |
| 611system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes) 612system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count) 613system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram 614system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram 615system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram | 610system.cpu0.toL2Bus.pkt_size::total 1053550085 # Cumulative packet size per connected master and slave (bytes) 611system.cpu0.toL2Bus.snoops 3357578 # Total snoops (count) 612system.cpu0.toL2Bus.snoop_fanout::samples 20506010 # Request fanout histogram 613system.cpu0.toL2Bus.snoop_fanout::mean 1.181419 # Request fanout histogram 614system.cpu0.toL2Bus.snoop_fanout::stdev 0.385365 # Request fanout histogram |
| 616system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 617system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 615system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 616system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 618system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 619system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 620system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram 621system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram | 617system.cpu0.toL2Bus.snoop_fanout::1 16785836 81.86% 81.86% # Request fanout histogram 618system.cpu0.toL2Bus.snoop_fanout::2 3720174 18.14% 100.00% # Request fanout histogram |
| 622system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 619system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 623system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 624system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 625system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram | 620system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 621system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::total 20506010 # Request fanout histogram |
| 626system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 627system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 628system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 631system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 200 unchanged lines hidden (view full) --- 834system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 835system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 836system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 837system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 838system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 839system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 840system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 841system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits | 623system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 624system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 625system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 626system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 627system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 628system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 200 unchanged lines hidden (view full) --- 831system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 832system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 833system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 834system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 835system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 836system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 837system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 838system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits |
| 842system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits 843system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits | 839system.cpu1.dcache.WriteReq_hits::cpu1.data 76990302 # number of WriteReq hits 840system.cpu1.dcache.WriteReq_hits::total 76990302 # number of WriteReq hits |
| 844system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 845system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits | 841system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 842system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits |
| 846system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits 847system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits | 843system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63438 # number of WriteInvalidateReq hits 844system.cpu1.dcache.WriteInvalidateReq_hits::total 63438 # number of WriteInvalidateReq hits |
| 848system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 849system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits | 845system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 846system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits |
| 850system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits 851system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits 852system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits 853system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits 854system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits 855system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits | 847system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048921 # number of StoreCondReq hits 848system.cpu1.dcache.StoreCondReq_hits::total 2048921 # number of StoreCondReq hits 849system.cpu1.dcache.demand_hits::cpu1.data 160687866 # number of demand (read+write) hits 850system.cpu1.dcache.demand_hits::total 160687866 # number of demand (read+write) hits 851system.cpu1.dcache.overall_hits::cpu1.data 160875720 # number of overall hits 852system.cpu1.dcache.overall_hits::total 160875720 # number of overall hits |
| 856system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 857system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses | 853system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 854system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses |
| 858system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses 859system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses | 855system.cpu1.dcache.WriteReq_misses::cpu1.data 1453174 # number of WriteReq misses 856system.cpu1.dcache.WriteReq_misses::total 1453174 # number of WriteReq misses |
| 860system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 861system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses | 857system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 858system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses |
| 862system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses 863system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses | 859system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427061 # number of WriteInvalidateReq misses 860system.cpu1.dcache.WriteInvalidateReq_misses::total 427061 # number of WriteInvalidateReq misses |
| 864system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 865system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses | 861system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 862system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses |
| 866system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses 867system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses 868system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses 869system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses 870system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses 871system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses | 863system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158828 # number of StoreCondReq misses 864system.cpu1.dcache.StoreCondReq_misses::total 158828 # number of StoreCondReq misses 865system.cpu1.dcache.demand_misses::cpu1.data 4811396 # number of demand (read+write) misses 866system.cpu1.dcache.demand_misses::total 4811396 # number of demand (read+write) misses 867system.cpu1.dcache.overall_misses::cpu1.data 5603747 # number of overall misses 868system.cpu1.dcache.overall_misses::total 5603747 # number of overall misses |
| 872system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 873system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 874system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 875system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 876system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 877system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 878system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) 879system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 886system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 887system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 888system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 889system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 890system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses 891system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses 892system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 893system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses | 869system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 870system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 871system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 872system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 873system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 874system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 875system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) 876system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 883system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 884system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 885system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 886system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 887system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses 888system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses 889system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 890system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses |
| 894system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses 895system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses | 891system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870666 # miss rate for WriteInvalidateReq accesses 892system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870666 # miss rate for WriteInvalidateReq accesses |
| 896system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 897system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses | 893system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 894system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses |
| 898system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses 899system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses | 895system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071941 # miss rate for StoreCondReq accesses 896system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071941 # miss rate for StoreCondReq accesses |
| 900system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses 901system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses 902system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses 903system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses 904system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 905system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 906system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 907system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 908system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 909system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 910system.cpu1.dcache.fast_writes 0 # number of fast writes performed 911system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 897system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses 898system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses 899system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses 900system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses 901system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu1.dcache.fast_writes 0 # number of fast writes performed 908system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 912system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks 913system.cpu1.dcache.writebacks::total 4030826 # number of writebacks | 909system.cpu1.dcache.writebacks::writebacks 4032690 # number of writebacks 910system.cpu1.dcache.writebacks::total 4032690 # number of writebacks |
| 914system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 915system.cpu1.icache.tags.replacements 4741297 # number of replacements 916system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 917system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 918system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 919system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. 920system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 921system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor --- 40 unchanged lines hidden (view full) --- 962system.cpu1.icache.cache_copies 0 # number of cache copies performed 963system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 964system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 965system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 966system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 967system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 968system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 969system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 911system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 912system.cpu1.icache.tags.replacements 4741297 # number of replacements 913system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 914system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 915system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 916system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. 917system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 918system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor --- 40 unchanged lines hidden (view full) --- 959system.cpu1.icache.cache_copies 0 # number of cache copies performed 960system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 961system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 962system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 963system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 964system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 965system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 966system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 970system.cpu1.l2cache.tags.replacements 2278914 # number of replacements 971system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use 972system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks. 973system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks. 974system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks. 975system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. 976system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor 977system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor 978system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor 979system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor 980system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor 981system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy 982system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy 983system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005597 # Average percentage of cache occupancy 984system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy 985system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322423 # Average percentage of cache occupancy 986system.cpu1.l2cache.tags.occ_percent::total 0.821041 # Average percentage of cache occupancy 987system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id 988system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id 989system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id 990system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id 991system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 992system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 993system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 994system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id 995system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id 996system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id 997system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id 998system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id 999system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id 1000system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses 1001system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses 1002system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits 1003system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits 1004system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits 1005system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # number of ReadReq hits 1006system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits 1007system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits 1008system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits 1009system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits 1010system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits 1011system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits 1012system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits 1013system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits 1014system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits 1015system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 325118 # number of demand (read+write) hits 1016system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141158 # number of demand (read+write) hits 1017system.cpu1.l2cache.demand_hits::cpu1.inst 4217165 # number of demand (read+write) hits 1018system.cpu1.l2cache.demand_hits::cpu1.data 3672082 # number of demand (read+write) hits 1019system.cpu1.l2cache.demand_hits::total 8355523 # number of demand (read+write) hits 1020system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 325118 # number of overall hits 1021system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141158 # number of overall hits 1022system.cpu1.l2cache.overall_hits::cpu1.inst 4217165 # number of overall hits 1023system.cpu1.l2cache.overall_hits::cpu1.data 3672082 # number of overall hits 1024system.cpu1.l2cache.overall_hits::total 8355523 # number of overall hits 1025system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12489 # number of ReadReq misses 1026system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9780 # number of ReadReq misses 1027system.cpu1.l2cache.ReadReq_misses::cpu1.inst 524644 # number of ReadReq misses 1028system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239502 # number of ReadReq misses 1029system.cpu1.l2cache.ReadReq_misses::total 1786415 # number of ReadReq misses 1030system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses 1031system.cpu1.l2cache.WriteInvalidateReq_misses::total 265480 # number of WriteInvalidateReq misses 1032system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133591 # number of UpgradeReq misses 1033system.cpu1.l2cache.UpgradeReq_misses::total 133591 # number of UpgradeReq misses 1034system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158842 # number of SCUpgradeReq misses 1035system.cpu1.l2cache.SCUpgradeReq_misses::total 158842 # number of SCUpgradeReq misses 1036system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701699 # number of ReadExReq misses 1037system.cpu1.l2cache.ReadExReq_misses::total 701699 # number of ReadExReq misses 1038system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12489 # number of demand (read+write) misses 1039system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9780 # number of demand (read+write) misses 1040system.cpu1.l2cache.demand_misses::cpu1.inst 524644 # number of demand (read+write) misses 1041system.cpu1.l2cache.demand_misses::cpu1.data 1941201 # number of demand (read+write) misses 1042system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses 1043system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12489 # number of overall misses 1044system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9780 # number of overall misses 1045system.cpu1.l2cache.overall_misses::cpu1.inst 524644 # number of overall misses 1046system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses 1047system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses 1048system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses) 1049system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses) | 967system.cpu1.l2cache.tags.replacements 2276750 # number of replacements 968system.cpu1.l2cache.tags.tagsinuse 13455.535871 # Cycle average of tags in use 969system.cpu1.l2cache.tags.total_refs 10863007 # Total number of references to valid blocks. 970system.cpu1.l2cache.tags.sampled_refs 2292767 # Sample count of references to valid blocks. 971system.cpu1.l2cache.tags.avg_refs 4.737946 # Average number of references to valid blocks. 972system.cpu1.l2cache.tags.warmup_cycle 9713557209000 # Cycle when the warmup percentage was hit. 973system.cpu1.l2cache.tags.occ_blocks::writebacks 5167.508425 # Average occupied blocks per requestor 974system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.262953 # Average occupied blocks per requestor 975system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.675159 # Average occupied blocks per requestor 976system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.798557 # Average occupied blocks per requestor 977system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5285.290777 # Average occupied blocks per requestor 978system.cpu1.l2cache.tags.occ_percent::writebacks 0.315400 # Average percentage of cache occupancy 979system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004044 # Average percentage of cache occupancy 980system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005290 # Average percentage of cache occupancy 981system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173938 # Average percentage of cache occupancy 982system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322589 # Average percentage of cache occupancy 983system.cpu1.l2cache.tags.occ_percent::total 0.821261 # Average percentage of cache occupancy 984system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id 985system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id 986system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id 987system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 988system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id 989system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 990system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id 991system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 992system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1571 # Occupied blocks per task id 993system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5986 # Occupied blocks per task id 994system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id 995system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3831 # Occupied blocks per task id 996system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id 997system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id 998system.cpu1.l2cache.tags.tag_accesses 254014080 # Number of tag accesses 999system.cpu1.l2cache.tags.data_accesses 254014080 # Number of data accesses 1000system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324472 # number of ReadReq hits 1001system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140015 # number of ReadReq hits 1002system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4218186 # number of ReadReq hits 1003system.cpu1.l2cache.ReadReq_hits::cpu1.data 3058286 # number of ReadReq hits 1004system.cpu1.l2cache.ReadReq_hits::total 7740959 # number of ReadReq hits 1005system.cpu1.l2cache.Writeback_hits::writebacks 4032690 # number of Writeback hits 1006system.cpu1.l2cache.Writeback_hits::total 4032690 # number of Writeback hits 1007system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161150 # number of WriteInvalidateReq hits 1008system.cpu1.l2cache.WriteInvalidateReq_hits::total 161150 # number of WriteInvalidateReq hits 1009system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3831 # number of UpgradeReq hits 1010system.cpu1.l2cache.UpgradeReq_hits::total 3831 # number of UpgradeReq hits 1011system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614491 # number of ReadExReq hits 1012system.cpu1.l2cache.ReadExReq_hits::total 614491 # number of ReadExReq hits 1013system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324472 # number of demand (read+write) hits 1014system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140015 # number of demand (read+write) hits 1015system.cpu1.l2cache.demand_hits::cpu1.inst 4218186 # number of demand (read+write) hits 1016system.cpu1.l2cache.demand_hits::cpu1.data 3672777 # number of demand (read+write) hits 1017system.cpu1.l2cache.demand_hits::total 8355450 # number of demand (read+write) hits 1018system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324472 # number of overall hits 1019system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140015 # number of overall hits 1020system.cpu1.l2cache.overall_hits::cpu1.inst 4218186 # number of overall hits 1021system.cpu1.l2cache.overall_hits::cpu1.data 3672777 # number of overall hits 1022system.cpu1.l2cache.overall_hits::total 8355450 # number of overall hits 1023system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12267 # number of ReadReq misses 1024system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9705 # number of ReadReq misses 1025system.cpu1.l2cache.ReadReq_misses::cpu1.inst 523623 # number of ReadReq misses 1026system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239107 # number of ReadReq misses 1027system.cpu1.l2cache.ReadReq_misses::total 1784702 # number of ReadReq misses 1028system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265696 # number of WriteInvalidateReq misses 1029system.cpu1.l2cache.WriteInvalidateReq_misses::total 265696 # number of WriteInvalidateReq misses 1030system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133668 # number of UpgradeReq misses 1031system.cpu1.l2cache.UpgradeReq_misses::total 133668 # number of UpgradeReq misses 1032system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158828 # number of SCUpgradeReq misses 1033system.cpu1.l2cache.SCUpgradeReq_misses::total 158828 # number of SCUpgradeReq misses 1034system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701399 # number of ReadExReq misses 1035system.cpu1.l2cache.ReadExReq_misses::total 701399 # number of ReadExReq misses 1036system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12267 # number of demand (read+write) misses 1037system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9705 # number of demand (read+write) misses 1038system.cpu1.l2cache.demand_misses::cpu1.inst 523623 # number of demand (read+write) misses 1039system.cpu1.l2cache.demand_misses::cpu1.data 1940506 # number of demand (read+write) misses 1040system.cpu1.l2cache.demand_misses::total 2486101 # number of demand (read+write) misses 1041system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12267 # number of overall misses 1042system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9705 # number of overall misses 1043system.cpu1.l2cache.overall_misses::cpu1.inst 523623 # number of overall misses 1044system.cpu1.l2cache.overall_misses::cpu1.data 1940506 # number of overall misses 1045system.cpu1.l2cache.overall_misses::total 2486101 # number of overall misses 1046system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336739 # number of ReadReq accesses(hits+misses) 1047system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149720 # number of ReadReq accesses(hits+misses) |
| 1050system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) 1051system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) | 1048system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) 1049system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) |
| 1052system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses) 1053system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses) 1054system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses) | 1050system.cpu1.l2cache.ReadReq_accesses::total 9525661 # number of ReadReq accesses(hits+misses) 1051system.cpu1.l2cache.Writeback_accesses::writebacks 4032690 # number of Writeback accesses(hits+misses) 1052system.cpu1.l2cache.Writeback_accesses::total 4032690 # number of Writeback accesses(hits+misses) |
| 1055system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) 1056system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) | 1053system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) 1054system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) |
| 1057system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses) 1058system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses) 1059system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses) 1060system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses) | 1055system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137499 # number of UpgradeReq accesses(hits+misses) 1056system.cpu1.l2cache.UpgradeReq_accesses::total 137499 # number of UpgradeReq accesses(hits+misses) 1057system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158828 # number of SCUpgradeReq accesses(hits+misses) 1058system.cpu1.l2cache.SCUpgradeReq_accesses::total 158828 # number of SCUpgradeReq accesses(hits+misses) |
| 1061system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 1062system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) | 1059system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 1060system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) |
| 1063system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses 1064system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses | 1061system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336739 # number of demand (read+write) accesses 1062system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149720 # number of demand (read+write) accesses |
| 1065system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 1066system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses | 1063system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 1064system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses |
| 1067system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses 1068system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses 1069system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses | 1065system.cpu1.l2cache.demand_accesses::total 10841551 # number of demand (read+write) accesses 1066system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336739 # number of overall (read+write) accesses 1067system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149720 # number of overall (read+write) accesses |
| 1070system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 1071system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses | 1068system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 1069system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses |
| 1072system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses 1073system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses 1074system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses 1075system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses 1076system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses 1077system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses 1078system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses 1079system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses 1080system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses 1081system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses | 1070system.cpu1.l2cache.overall_accesses::total 10841551 # number of overall (read+write) accesses 1071system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for ReadReq accesses 1072system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064821 # miss rate for ReadReq accesses 1073system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110427 # miss rate for ReadReq accesses 1074system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288339 # miss rate for ReadReq accesses 1075system.cpu1.l2cache.ReadReq_miss_rate::total 0.187357 # miss rate for ReadReq accesses 1076system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.622463 # miss rate for WriteInvalidateReq accesses 1077system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.622463 # miss rate for WriteInvalidateReq accesses 1078system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972138 # miss rate for UpgradeReq accesses 1079system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972138 # miss rate for UpgradeReq accesses |
| 1082system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1083system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1080system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1081system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1084system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses 1085system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses 1086system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses 1087system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses 1088system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses 1089system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses 1090system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses 1091system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses 1092system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses 1093system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses 1094system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses 1095system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses | 1082system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533023 # miss rate for ReadExReq accesses 1083system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533023 # miss rate for ReadExReq accesses 1084system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for demand accesses 1085system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064821 # miss rate for demand accesses 1086system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110427 # miss rate for demand accesses 1087system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345699 # miss rate for demand accesses 1088system.cpu1.l2cache.demand_miss_rate::total 0.229312 # miss rate for demand accesses 1089system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for overall accesses 1090system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064821 # miss rate for overall accesses 1091system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110427 # miss rate for overall accesses 1092system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345699 # miss rate for overall accesses 1093system.cpu1.l2cache.overall_miss_rate::total 0.229312 # miss rate for overall accesses |
| 1096system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1097system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1098system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1099system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1100system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1101system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1102system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1103system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1094system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1095system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1096system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1097system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1098system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1099system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1100system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1101system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1104system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks 1105system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks | 1102system.cpu1.l2cache.writebacks::writebacks 1183004 # number of writebacks 1103system.cpu1.l2cache.writebacks::total 1183004 # number of writebacks |
| 1106system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1107system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution 1108system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 1109system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 1110system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution | 1104system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1105system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution 1106system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 1107system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 1108system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution |
| 1111system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution | 1109system.cpu1.toL2Bus.trans_dist::Writeback 4032690 # Transaction distribution |
| 1112system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution 1113system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution | 1110system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution 1111system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution |
| 1114system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution 1115system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution 1116system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution | 1112system.cpu1.toL2Bus.trans_dist::UpgradeReq 137499 # Transaction distribution 1113system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158828 # Transaction distribution 1114system.cpu1.toL2Bus.trans_dist::UpgradeResp 296327 # Transaction distribution |
| 1117system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 1118system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 1119system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) | 1115system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 1116system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 1117system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) |
| 1120system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes) | 1118system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16731086 # Packet count per connected master and slave (bytes) |
| 1121system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 1122system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) | 1119system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 1120system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) |
| 1123system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes) | 1121system.cpu1.toL2Bus.pkt_count::total 27414408 # Packet count per connected master and slave (bytes) |
| 1124system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) | 1122system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) |
| 1125system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes) | 1123system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644698812 # Cumulative packet size per connected master and slave (bytes) |
| 1126system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) | 1124system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 1125system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) |
| 1128system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes) 1129system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count) 1130system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram 1131system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram 1132system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram | 1126system.cpu1.toL2Bus.pkt_size::total 952972884 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu1.toL2Bus.snoops 3837128 # Total snoops (count) 1128system.cpu1.toL2Bus.snoop_fanout::samples 19395843 # Request fanout histogram 1129system.cpu1.toL2Bus.snoop_fanout::mean 1.220254 # Request fanout histogram 1130system.cpu1.toL2Bus.snoop_fanout::stdev 0.414418 # Request fanout histogram |
| 1133system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1134system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1131system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1132system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1135system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1136system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1137system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram 1138system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram | 1133system.cpu1.toL2Bus.snoop_fanout::1 15123827 77.97% 77.97% # Request fanout histogram 1134system.cpu1.toL2Bus.snoop_fanout::2 4272016 22.03% 100.00% # Request fanout histogram |
| 1139system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1135system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1140system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1141system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1142system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram | 1136system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1137system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1138system.cpu1.toL2Bus.snoop_fanout::total 19395843 # Request fanout histogram |
| 1143system.iobus.trans_dist::ReadReq 40295 # Transaction distribution 1144system.iobus.trans_dist::ReadResp 40295 # Transaction distribution 1145system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 1146system.iobus.trans_dist::WriteResp 29906 # Transaction distribution 1147system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 1148system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) 1149system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1150system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 97 unchanged lines hidden (view full) --- 1248system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1249system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1250system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1251system.iocache.fast_writes 0 # number of fast writes performed 1252system.iocache.cache_copies 0 # number of cache copies performed 1253system.iocache.writebacks::writebacks 106694 # number of writebacks 1254system.iocache.writebacks::total 106694 # number of writebacks 1255system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1139system.iobus.trans_dist::ReadReq 40295 # Transaction distribution 1140system.iobus.trans_dist::ReadResp 40295 # Transaction distribution 1141system.iobus.trans_dist::WriteReq 136634 # Transaction distribution 1142system.iobus.trans_dist::WriteResp 29906 # Transaction distribution 1143system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 1144system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) 1145system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1146system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 97 unchanged lines hidden (view full) --- 1244system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1245system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1247system.iocache.fast_writes 0 # number of fast writes performed 1248system.iocache.cache_copies 0 # number of cache copies performed 1249system.iocache.writebacks::writebacks 106694 # number of writebacks 1250system.iocache.writebacks::total 106694 # number of writebacks 1251system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1256system.l2c.tags.replacements 1759966 # number of replacements 1257system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use 1258system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks. 1259system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks. 1260system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks. 1261system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. 1262system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor 1263system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor 1264system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor 1265system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor 1266system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor 1267system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor 1268system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor 1269system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor 1270system.l2c.tags.occ_blocks::cpu1.data 13514.968494 # Average occupied blocks per requestor 1271system.l2c.tags.occ_percent::writebacks 0.537404 # Average percentage of cache occupancy 1272system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000716 # Average percentage of cache occupancy 1273system.l2c.tags.occ_percent::cpu0.itb.walker 0.000883 # Average percentage of cache occupancy 1274system.l2c.tags.occ_percent::cpu0.inst 0.050948 # Average percentage of cache occupancy 1275system.l2c.tags.occ_percent::cpu0.data 0.106280 # Average percentage of cache occupancy 1276system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004723 # Average percentage of cache occupancy 1277system.l2c.tags.occ_percent::cpu1.itb.walker 0.006565 # Average percentage of cache occupancy 1278system.l2c.tags.occ_percent::cpu1.inst 0.045154 # Average percentage of cache occupancy 1279system.l2c.tags.occ_percent::cpu1.data 0.206222 # Average percentage of cache occupancy 1280system.l2c.tags.occ_percent::total 0.958896 # Average percentage of cache occupancy 1281system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id 1282system.l2c.tags.occ_task_id_blocks::1024 58508 # Occupied blocks per task id | 1252system.l2c.tags.replacements 1759191 # number of replacements 1253system.l2c.tags.tagsinuse 62867.167491 # Cycle average of tags in use 1254system.l2c.tags.total_refs 3704436 # Total number of references to valid blocks. 1255system.l2c.tags.sampled_refs 1817948 # Sample count of references to valid blocks. 1256system.l2c.tags.avg_refs 2.037702 # Average number of references to valid blocks. 1257system.l2c.tags.warmup_cycle 483416500 # Cycle when the warmup percentage was hit. 1258system.l2c.tags.occ_blocks::writebacks 35264.935108 # Average occupied blocks per requestor 1259system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.422401 # Average occupied blocks per requestor 1260system.l2c.tags.occ_blocks::cpu0.itb.walker 57.110376 # Average occupied blocks per requestor 1261system.l2c.tags.occ_blocks::cpu0.inst 3318.609191 # Average occupied blocks per requestor 1262system.l2c.tags.occ_blocks::cpu0.data 6952.273283 # Average occupied blocks per requestor 1263system.l2c.tags.occ_blocks::cpu1.dtb.walker 314.594733 # Average occupied blocks per requestor 1264system.l2c.tags.occ_blocks::cpu1.itb.walker 425.085194 # Average occupied blocks per requestor 1265system.l2c.tags.occ_blocks::cpu1.inst 2976.403767 # Average occupied blocks per requestor 1266system.l2c.tags.occ_blocks::cpu1.data 13512.733438 # Average occupied blocks per requestor 1267system.l2c.tags.occ_percent::writebacks 0.538100 # Average percentage of cache occupancy 1268system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000693 # Average percentage of cache occupancy 1269system.l2c.tags.occ_percent::cpu0.itb.walker 0.000871 # Average percentage of cache occupancy 1270system.l2c.tags.occ_percent::cpu0.inst 0.050638 # Average percentage of cache occupancy 1271system.l2c.tags.occ_percent::cpu0.data 0.106083 # Average percentage of cache occupancy 1272system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004800 # Average percentage of cache occupancy 1273system.l2c.tags.occ_percent::cpu1.itb.walker 0.006486 # Average percentage of cache occupancy 1274system.l2c.tags.occ_percent::cpu1.inst 0.045416 # Average percentage of cache occupancy 1275system.l2c.tags.occ_percent::cpu1.data 0.206188 # Average percentage of cache occupancy 1276system.l2c.tags.occ_percent::total 0.959277 # Average percentage of cache occupancy 1277system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id 1278system.l2c.tags.occ_task_id_blocks::1024 58530 # Occupied blocks per task id |
| 1283system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1284system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 1279system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1280system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 1285system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id 1286system.l2c.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1287system.l2c.tags.age_task_id_blocks_1024::1 549 # Occupied blocks per task id 1288system.l2c.tags.age_task_id_blocks_1024::2 3406 # Occupied blocks per task id 1289system.l2c.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id 1290system.l2c.tags.age_task_id_blocks_1024::4 48840 # Occupied blocks per task id 1291system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id 1292system.l2c.tags.occ_task_id_percent::1024 0.892761 # Percentage of cache occupancy per task id 1293system.l2c.tags.tag_accesses 66406004 # Number of tag accesses 1294system.l2c.tags.data_accesses 66406004 # Number of data accesses 1295system.l2c.ReadReq_hits::cpu0.dtb.walker 6334 # number of ReadReq hits 1296system.l2c.ReadReq_hits::cpu0.itb.walker 4677 # number of ReadReq hits 1297system.l2c.ReadReq_hits::cpu0.inst 509782 # number of ReadReq hits 1298system.l2c.ReadReq_hits::cpu0.data 744386 # number of ReadReq hits 1299system.l2c.ReadReq_hits::cpu1.dtb.walker 5569 # number of ReadReq hits 1300system.l2c.ReadReq_hits::cpu1.itb.walker 3610 # number of ReadReq hits 1301system.l2c.ReadReq_hits::cpu1.inst 483417 # number of ReadReq hits 1302system.l2c.ReadReq_hits::cpu1.data 692017 # number of ReadReq hits 1303system.l2c.ReadReq_hits::total 2449792 # number of ReadReq hits 1304system.l2c.Writeback_hits::writebacks 2756939 # number of Writeback hits 1305system.l2c.Writeback_hits::total 2756939 # number of Writeback hits 1306system.l2c.WriteInvalidateReq_hits::cpu0.data 121538 # number of WriteInvalidateReq hits 1307system.l2c.WriteInvalidateReq_hits::cpu1.data 97977 # number of WriteInvalidateReq hits 1308system.l2c.WriteInvalidateReq_hits::total 219515 # number of WriteInvalidateReq hits 1309system.l2c.UpgradeReq_hits::cpu0.data 13827 # number of UpgradeReq hits 1310system.l2c.UpgradeReq_hits::cpu1.data 10932 # number of UpgradeReq hits 1311system.l2c.UpgradeReq_hits::total 24759 # number of UpgradeReq hits 1312system.l2c.SCUpgradeReq_hits::cpu0.data 1566 # number of SCUpgradeReq hits 1313system.l2c.SCUpgradeReq_hits::cpu1.data 1304 # number of SCUpgradeReq hits 1314system.l2c.SCUpgradeReq_hits::total 2870 # number of SCUpgradeReq hits 1315system.l2c.ReadExReq_hits::cpu0.data 202688 # number of ReadExReq hits 1316system.l2c.ReadExReq_hits::cpu1.data 171255 # number of ReadExReq hits 1317system.l2c.ReadExReq_hits::total 373943 # number of ReadExReq hits 1318system.l2c.demand_hits::cpu0.dtb.walker 6334 # number of demand (read+write) hits 1319system.l2c.demand_hits::cpu0.itb.walker 4677 # number of demand (read+write) hits 1320system.l2c.demand_hits::cpu0.inst 509782 # number of demand (read+write) hits 1321system.l2c.demand_hits::cpu0.data 947074 # number of demand (read+write) hits 1322system.l2c.demand_hits::cpu1.dtb.walker 5569 # number of demand (read+write) hits 1323system.l2c.demand_hits::cpu1.itb.walker 3610 # number of demand (read+write) hits 1324system.l2c.demand_hits::cpu1.inst 483417 # number of demand (read+write) hits 1325system.l2c.demand_hits::cpu1.data 863272 # number of demand (read+write) hits 1326system.l2c.demand_hits::total 2823735 # number of demand (read+write) hits 1327system.l2c.overall_hits::cpu0.dtb.walker 6334 # number of overall hits 1328system.l2c.overall_hits::cpu0.itb.walker 4677 # number of overall hits 1329system.l2c.overall_hits::cpu0.inst 509782 # number of overall hits 1330system.l2c.overall_hits::cpu0.data 947074 # number of overall hits 1331system.l2c.overall_hits::cpu1.dtb.walker 5569 # number of overall hits 1332system.l2c.overall_hits::cpu1.itb.walker 3610 # number of overall hits 1333system.l2c.overall_hits::cpu1.inst 483417 # number of overall hits 1334system.l2c.overall_hits::cpu1.data 863272 # number of overall hits 1335system.l2c.overall_hits::total 2823735 # number of overall hits 1336system.l2c.ReadReq_misses::cpu0.dtb.walker 2407 # number of ReadReq misses | 1281system.l2c.tags.age_task_id_blocks_1023::4 225 # Occupied blocks per task id 1282system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 1283system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id 1284system.l2c.tags.age_task_id_blocks_1024::2 3441 # Occupied blocks per task id 1285system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id 1286system.l2c.tags.age_task_id_blocks_1024::4 48852 # Occupied blocks per task id 1287system.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id 1288system.l2c.tags.occ_task_id_percent::1024 0.893097 # Percentage of cache occupancy per task id 1289system.l2c.tags.tag_accesses 66366738 # Number of tag accesses 1290system.l2c.tags.data_accesses 66366738 # Number of data accesses 1291system.l2c.ReadReq_hits::cpu0.dtb.walker 6239 # number of ReadReq hits 1292system.l2c.ReadReq_hits::cpu0.itb.walker 4535 # number of ReadReq hits 1293system.l2c.ReadReq_hits::cpu0.inst 509640 # number of ReadReq hits 1294system.l2c.ReadReq_hits::cpu0.data 744526 # number of ReadReq hits 1295system.l2c.ReadReq_hits::cpu1.dtb.walker 5366 # number of ReadReq hits 1296system.l2c.ReadReq_hits::cpu1.itb.walker 3579 # number of ReadReq hits 1297system.l2c.ReadReq_hits::cpu1.inst 482377 # number of ReadReq hits 1298system.l2c.ReadReq_hits::cpu1.data 691195 # number of ReadReq hits 1299system.l2c.ReadReq_hits::total 2447457 # number of ReadReq hits 1300system.l2c.Writeback_hits::writebacks 2756140 # number of Writeback hits 1301system.l2c.Writeback_hits::total 2756140 # number of Writeback hits 1302system.l2c.WriteInvalidateReq_hits::cpu0.data 121071 # number of WriteInvalidateReq hits 1303system.l2c.WriteInvalidateReq_hits::cpu1.data 98425 # number of WriteInvalidateReq hits 1304system.l2c.WriteInvalidateReq_hits::total 219496 # number of WriteInvalidateReq hits 1305system.l2c.UpgradeReq_hits::cpu0.data 13420 # number of UpgradeReq hits 1306system.l2c.UpgradeReq_hits::cpu1.data 10778 # number of UpgradeReq hits 1307system.l2c.UpgradeReq_hits::total 24198 # number of UpgradeReq hits 1308system.l2c.SCUpgradeReq_hits::cpu0.data 1497 # number of SCUpgradeReq hits 1309system.l2c.SCUpgradeReq_hits::cpu1.data 1278 # number of SCUpgradeReq hits 1310system.l2c.SCUpgradeReq_hits::total 2775 # number of SCUpgradeReq hits 1311system.l2c.ReadExReq_hits::cpu0.data 202220 # number of ReadExReq hits 1312system.l2c.ReadExReq_hits::cpu1.data 170877 # number of ReadExReq hits 1313system.l2c.ReadExReq_hits::total 373097 # number of ReadExReq hits 1314system.l2c.demand_hits::cpu0.dtb.walker 6239 # number of demand (read+write) hits 1315system.l2c.demand_hits::cpu0.itb.walker 4535 # number of demand (read+write) hits 1316system.l2c.demand_hits::cpu0.inst 509640 # number of demand (read+write) hits 1317system.l2c.demand_hits::cpu0.data 946746 # number of demand (read+write) hits 1318system.l2c.demand_hits::cpu1.dtb.walker 5366 # number of demand (read+write) hits 1319system.l2c.demand_hits::cpu1.itb.walker 3579 # number of demand (read+write) hits 1320system.l2c.demand_hits::cpu1.inst 482377 # number of demand (read+write) hits 1321system.l2c.demand_hits::cpu1.data 862072 # number of demand (read+write) hits 1322system.l2c.demand_hits::total 2820554 # number of demand (read+write) hits 1323system.l2c.overall_hits::cpu0.dtb.walker 6239 # number of overall hits 1324system.l2c.overall_hits::cpu0.itb.walker 4535 # number of overall hits 1325system.l2c.overall_hits::cpu0.inst 509640 # number of overall hits 1326system.l2c.overall_hits::cpu0.data 946746 # number of overall hits 1327system.l2c.overall_hits::cpu1.dtb.walker 5366 # number of overall hits 1328system.l2c.overall_hits::cpu1.itb.walker 3579 # number of overall hits 1329system.l2c.overall_hits::cpu1.inst 482377 # number of overall hits 1330system.l2c.overall_hits::cpu1.data 862072 # number of overall hits 1331system.l2c.overall_hits::total 2820554 # number of overall hits 1332system.l2c.ReadReq_misses::cpu0.dtb.walker 2380 # number of ReadReq misses |
| 1337system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses | 1333system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses |
| 1338system.l2c.ReadReq_misses::cpu0.inst 58419 # number of ReadReq misses 1339system.l2c.ReadReq_misses::cpu0.data 184134 # number of ReadReq misses 1340system.l2c.ReadReq_misses::cpu1.dtb.walker 3483 # number of ReadReq misses 1341system.l2c.ReadReq_misses::cpu1.itb.walker 3456 # number of ReadReq misses 1342system.l2c.ReadReq_misses::cpu1.inst 41227 # number of ReadReq misses 1343system.l2c.ReadReq_misses::cpu1.data 189746 # number of ReadReq misses 1344system.l2c.ReadReq_misses::total 484883 # number of ReadReq misses 1345system.l2c.WriteInvalidateReq_misses::cpu0.data 479213 # number of WriteInvalidateReq misses 1346system.l2c.WriteInvalidateReq_misses::cpu1.data 160846 # number of WriteInvalidateReq misses 1347system.l2c.WriteInvalidateReq_misses::total 640059 # number of WriteInvalidateReq misses 1348system.l2c.UpgradeReq_misses::cpu0.data 58018 # number of UpgradeReq misses 1349system.l2c.UpgradeReq_misses::cpu1.data 53853 # number of UpgradeReq misses 1350system.l2c.UpgradeReq_misses::total 111871 # number of UpgradeReq misses 1351system.l2c.SCUpgradeReq_misses::cpu0.data 7722 # number of SCUpgradeReq misses 1352system.l2c.SCUpgradeReq_misses::cpu1.data 7423 # number of SCUpgradeReq misses 1353system.l2c.SCUpgradeReq_misses::total 15145 # number of SCUpgradeReq misses 1354system.l2c.ReadExReq_misses::cpu0.data 377543 # number of ReadExReq misses 1355system.l2c.ReadExReq_misses::cpu1.data 418309 # number of ReadExReq misses 1356system.l2c.ReadExReq_misses::total 795852 # number of ReadExReq misses 1357system.l2c.demand_misses::cpu0.dtb.walker 2407 # number of demand (read+write) misses | 1334system.l2c.ReadReq_misses::cpu0.inst 58293 # number of ReadReq misses 1335system.l2c.ReadReq_misses::cpu0.data 183599 # number of ReadReq misses 1336system.l2c.ReadReq_misses::cpu1.dtb.walker 3469 # number of ReadReq misses 1337system.l2c.ReadReq_misses::cpu1.itb.walker 3462 # number of ReadReq misses 1338system.l2c.ReadReq_misses::cpu1.inst 41246 # number of ReadReq misses 1339system.l2c.ReadReq_misses::cpu1.data 189649 # number of ReadReq misses 1340system.l2c.ReadReq_misses::total 484109 # number of ReadReq misses 1341system.l2c.WriteInvalidateReq_misses::cpu0.data 479323 # number of WriteInvalidateReq misses 1342system.l2c.WriteInvalidateReq_misses::cpu1.data 160634 # number of WriteInvalidateReq misses 1343system.l2c.WriteInvalidateReq_misses::total 639957 # number of WriteInvalidateReq misses 1344system.l2c.UpgradeReq_misses::cpu0.data 58449 # number of UpgradeReq misses 1345system.l2c.UpgradeReq_misses::cpu1.data 54093 # number of UpgradeReq misses 1346system.l2c.UpgradeReq_misses::total 112542 # number of UpgradeReq misses 1347system.l2c.SCUpgradeReq_misses::cpu0.data 7788 # number of SCUpgradeReq misses 1348system.l2c.SCUpgradeReq_misses::cpu1.data 7462 # number of SCUpgradeReq misses 1349system.l2c.SCUpgradeReq_misses::total 15250 # number of SCUpgradeReq misses 1350system.l2c.ReadExReq_misses::cpu0.data 377640 # number of ReadExReq misses 1351system.l2c.ReadExReq_misses::cpu1.data 418302 # number of ReadExReq misses 1352system.l2c.ReadExReq_misses::total 795942 # number of ReadExReq misses 1353system.l2c.demand_misses::cpu0.dtb.walker 2380 # number of demand (read+write) misses |
| 1358system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses | 1354system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses |
| 1359system.l2c.demand_misses::cpu0.inst 58419 # number of demand (read+write) misses 1360system.l2c.demand_misses::cpu0.data 561677 # number of demand (read+write) misses 1361system.l2c.demand_misses::cpu1.dtb.walker 3483 # number of demand (read+write) misses 1362system.l2c.demand_misses::cpu1.itb.walker 3456 # number of demand (read+write) misses 1363system.l2c.demand_misses::cpu1.inst 41227 # number of demand (read+write) misses 1364system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses 1365system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses 1366system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses | 1355system.l2c.demand_misses::cpu0.inst 58293 # number of demand (read+write) misses 1356system.l2c.demand_misses::cpu0.data 561239 # number of demand (read+write) misses 1357system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses 1358system.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses 1359system.l2c.demand_misses::cpu1.inst 41246 # number of demand (read+write) misses 1360system.l2c.demand_misses::cpu1.data 607951 # number of demand (read+write) misses 1361system.l2c.demand_misses::total 1280051 # number of demand (read+write) misses 1362system.l2c.overall_misses::cpu0.dtb.walker 2380 # number of overall misses |
| 1367system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses | 1363system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses |
| 1368system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses 1369system.l2c.overall_misses::cpu0.data 561677 # number of overall misses 1370system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses 1371system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses 1372system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses 1373system.l2c.overall_misses::cpu1.data 608055 # number of overall misses 1374system.l2c.overall_misses::total 1280735 # number of overall misses 1375system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses) 1376system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses) 1377system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses) 1378system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses) 1379system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses) 1380system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses) 1381system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses) 1382system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses) 1383system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses) 1384system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses) 1385system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses) 1386system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses) 1387system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses) 1388system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses) 1389system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses) 1390system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses) 1391system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses) 1392system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses) 1393system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses) 1394system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses) 1395system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses) 1396system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses) 1397system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses) 1398system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses 1399system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses 1400system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses 1401system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses 1402system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses 1403system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses 1404system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses 1405system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses 1406system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses 1407system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses 1408system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses 1409system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses 1410system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses 1411system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses 1412system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses 1413system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses 1414system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses 1415system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses 1416system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses 1417system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses 1418system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses 1419system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses 1420system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses 1421system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses 1422system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses 1423system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses 1424system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses 1425system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses 1426system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses 1427system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses 1428system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses 1429system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses 1430system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses 1431system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses 1432system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses 1433system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses 1434system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses 1435system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses 1436system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses 1437system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses 1438system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses 1439system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses 1440system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses 1441system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses 1442system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses 1443system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses 1444system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses 1445system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses 1446system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses 1447system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses 1448system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses 1449system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses 1450system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses 1451system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses 1452system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses 1453system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses 1454system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses | 1364system.l2c.overall_misses::cpu0.inst 58293 # number of overall misses 1365system.l2c.overall_misses::cpu0.data 561239 # number of overall misses 1366system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses 1367system.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses 1368system.l2c.overall_misses::cpu1.inst 41246 # number of overall misses 1369system.l2c.overall_misses::cpu1.data 607951 # number of overall misses 1370system.l2c.overall_misses::total 1280051 # number of overall misses 1371system.l2c.ReadReq_accesses::cpu0.dtb.walker 8619 # number of ReadReq accesses(hits+misses) 1372system.l2c.ReadReq_accesses::cpu0.itb.walker 6546 # number of ReadReq accesses(hits+misses) 1373system.l2c.ReadReq_accesses::cpu0.inst 567933 # number of ReadReq accesses(hits+misses) 1374system.l2c.ReadReq_accesses::cpu0.data 928125 # number of ReadReq accesses(hits+misses) 1375system.l2c.ReadReq_accesses::cpu1.dtb.walker 8835 # number of ReadReq accesses(hits+misses) 1376system.l2c.ReadReq_accesses::cpu1.itb.walker 7041 # number of ReadReq accesses(hits+misses) 1377system.l2c.ReadReq_accesses::cpu1.inst 523623 # number of ReadReq accesses(hits+misses) 1378system.l2c.ReadReq_accesses::cpu1.data 880844 # number of ReadReq accesses(hits+misses) 1379system.l2c.ReadReq_accesses::total 2931566 # number of ReadReq accesses(hits+misses) 1380system.l2c.Writeback_accesses::writebacks 2756140 # number of Writeback accesses(hits+misses) 1381system.l2c.Writeback_accesses::total 2756140 # number of Writeback accesses(hits+misses) 1382system.l2c.WriteInvalidateReq_accesses::cpu0.data 600394 # number of WriteInvalidateReq accesses(hits+misses) 1383system.l2c.WriteInvalidateReq_accesses::cpu1.data 259059 # number of WriteInvalidateReq accesses(hits+misses) 1384system.l2c.WriteInvalidateReq_accesses::total 859453 # number of WriteInvalidateReq accesses(hits+misses) 1385system.l2c.UpgradeReq_accesses::cpu0.data 71869 # number of UpgradeReq accesses(hits+misses) 1386system.l2c.UpgradeReq_accesses::cpu1.data 64871 # number of UpgradeReq accesses(hits+misses) 1387system.l2c.UpgradeReq_accesses::total 136740 # number of UpgradeReq accesses(hits+misses) 1388system.l2c.SCUpgradeReq_accesses::cpu0.data 9285 # number of SCUpgradeReq accesses(hits+misses) 1389system.l2c.SCUpgradeReq_accesses::cpu1.data 8740 # number of SCUpgradeReq accesses(hits+misses) 1390system.l2c.SCUpgradeReq_accesses::total 18025 # number of SCUpgradeReq accesses(hits+misses) 1391system.l2c.ReadExReq_accesses::cpu0.data 579860 # number of ReadExReq accesses(hits+misses) 1392system.l2c.ReadExReq_accesses::cpu1.data 589179 # number of ReadExReq accesses(hits+misses) 1393system.l2c.ReadExReq_accesses::total 1169039 # number of ReadExReq accesses(hits+misses) 1394system.l2c.demand_accesses::cpu0.dtb.walker 8619 # number of demand (read+write) accesses 1395system.l2c.demand_accesses::cpu0.itb.walker 6546 # number of demand (read+write) accesses 1396system.l2c.demand_accesses::cpu0.inst 567933 # number of demand (read+write) accesses 1397system.l2c.demand_accesses::cpu0.data 1507985 # number of demand (read+write) accesses 1398system.l2c.demand_accesses::cpu1.dtb.walker 8835 # number of demand (read+write) accesses 1399system.l2c.demand_accesses::cpu1.itb.walker 7041 # number of demand (read+write) accesses 1400system.l2c.demand_accesses::cpu1.inst 523623 # number of demand (read+write) accesses 1401system.l2c.demand_accesses::cpu1.data 1470023 # number of demand (read+write) accesses 1402system.l2c.demand_accesses::total 4100605 # number of demand (read+write) accesses 1403system.l2c.overall_accesses::cpu0.dtb.walker 8619 # number of overall (read+write) accesses 1404system.l2c.overall_accesses::cpu0.itb.walker 6546 # number of overall (read+write) accesses 1405system.l2c.overall_accesses::cpu0.inst 567933 # number of overall (read+write) accesses 1406system.l2c.overall_accesses::cpu0.data 1507985 # number of overall (read+write) accesses 1407system.l2c.overall_accesses::cpu1.dtb.walker 8835 # number of overall (read+write) accesses 1408system.l2c.overall_accesses::cpu1.itb.walker 7041 # number of overall (read+write) accesses 1409system.l2c.overall_accesses::cpu1.inst 523623 # number of overall (read+write) accesses 1410system.l2c.overall_accesses::cpu1.data 1470023 # number of overall (read+write) accesses 1411system.l2c.overall_accesses::total 4100605 # number of overall (read+write) accesses 1412system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for ReadReq accesses 1413system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.307211 # miss rate for ReadReq accesses 1414system.l2c.ReadReq_miss_rate::cpu0.inst 0.102641 # miss rate for ReadReq accesses 1415system.l2c.ReadReq_miss_rate::cpu0.data 0.197817 # miss rate for ReadReq accesses 1416system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for ReadReq accesses 1417system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.491692 # miss rate for ReadReq accesses 1418system.l2c.ReadReq_miss_rate::cpu1.inst 0.078770 # miss rate for ReadReq accesses 1419system.l2c.ReadReq_miss_rate::cpu1.data 0.215304 # miss rate for ReadReq accesses 1420system.l2c.ReadReq_miss_rate::total 0.165137 # miss rate for ReadReq accesses 1421system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.798347 # miss rate for WriteInvalidateReq accesses 1422system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.620067 # miss rate for WriteInvalidateReq accesses 1423system.l2c.WriteInvalidateReq_miss_rate::total 0.744610 # miss rate for WriteInvalidateReq accesses 1424system.l2c.UpgradeReq_miss_rate::cpu0.data 0.813271 # miss rate for UpgradeReq accesses 1425system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833855 # miss rate for UpgradeReq accesses 1426system.l2c.UpgradeReq_miss_rate::total 0.823036 # miss rate for UpgradeReq accesses 1427system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.838772 # miss rate for SCUpgradeReq accesses 1428system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.853776 # miss rate for SCUpgradeReq accesses 1429system.l2c.SCUpgradeReq_miss_rate::total 0.846047 # miss rate for SCUpgradeReq accesses 1430system.l2c.ReadExReq_miss_rate::cpu0.data 0.651261 # miss rate for ReadExReq accesses 1431system.l2c.ReadExReq_miss_rate::cpu1.data 0.709974 # miss rate for ReadExReq accesses 1432system.l2c.ReadExReq_miss_rate::total 0.680852 # miss rate for ReadExReq accesses 1433system.l2c.demand_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for demand accesses 1434system.l2c.demand_miss_rate::cpu0.itb.walker 0.307211 # miss rate for demand accesses 1435system.l2c.demand_miss_rate::cpu0.inst 0.102641 # miss rate for demand accesses 1436system.l2c.demand_miss_rate::cpu0.data 0.372178 # miss rate for demand accesses 1437system.l2c.demand_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for demand accesses 1438system.l2c.demand_miss_rate::cpu1.itb.walker 0.491692 # miss rate for demand accesses 1439system.l2c.demand_miss_rate::cpu1.inst 0.078770 # miss rate for demand accesses 1440system.l2c.demand_miss_rate::cpu1.data 0.413566 # miss rate for demand accesses 1441system.l2c.demand_miss_rate::total 0.312161 # miss rate for demand accesses 1442system.l2c.overall_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for overall accesses 1443system.l2c.overall_miss_rate::cpu0.itb.walker 0.307211 # miss rate for overall accesses 1444system.l2c.overall_miss_rate::cpu0.inst 0.102641 # miss rate for overall accesses 1445system.l2c.overall_miss_rate::cpu0.data 0.372178 # miss rate for overall accesses 1446system.l2c.overall_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for overall accesses 1447system.l2c.overall_miss_rate::cpu1.itb.walker 0.491692 # miss rate for overall accesses 1448system.l2c.overall_miss_rate::cpu1.inst 0.078770 # miss rate for overall accesses 1449system.l2c.overall_miss_rate::cpu1.data 0.413566 # miss rate for overall accesses 1450system.l2c.overall_miss_rate::total 0.312161 # miss rate for overall accesses |
| 1455system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1456system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1457system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1458system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1459system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1460system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1461system.l2c.fast_writes 0 # number of fast writes performed 1462system.l2c.cache_copies 0 # number of cache copies performed | 1451system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1452system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1453system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1454system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1455system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1456system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1457system.l2c.fast_writes 0 # number of fast writes performed 1458system.l2c.cache_copies 0 # number of cache copies performed |
| 1463system.l2c.writebacks::writebacks 1464604 # number of writebacks 1464system.l2c.writebacks::total 1464604 # number of writebacks | 1459system.l2c.writebacks::writebacks 1464224 # number of writebacks 1460system.l2c.writebacks::total 1464224 # number of writebacks |
| 1465system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 1461system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1466system.membus.trans_dist::ReadReq 575939 # Transaction distribution 1467system.membus.trans_dist::ReadResp 575939 # Transaction distribution 1468system.membus.trans_dist::WriteReq 38831 # Transaction distribution 1469system.membus.trans_dist::WriteResp 38831 # Transaction distribution 1470system.membus.trans_dist::Writeback 1571298 # Transaction distribution 1471system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution 1472system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution 1473system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution 1474system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution 1475system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution 1476system.membus.trans_dist::ReadExReq 965776 # Transaction distribution 1477system.membus.trans_dist::ReadExResp 778482 # Transaction distribution | 1462system.membus.trans_dist::ReadReq 575153 # Transaction distribution 1463system.membus.trans_dist::ReadResp 575153 # Transaction distribution 1464system.membus.trans_dist::WriteReq 38802 # Transaction distribution 1465system.membus.trans_dist::WriteResp 38802 # Transaction distribution 1466system.membus.trans_dist::Writeback 1570918 # Transaction distribution 1467system.membus.trans_dist::WriteInvalidateReq 742110 # Transaction distribution 1468system.membus.trans_dist::WriteInvalidateResp 742110 # Transaction distribution 1469system.membus.trans_dist::UpgradeReq 328170 # Transaction distribution 1470system.membus.trans_dist::SCUpgradeReq 314483 # Transaction distribution 1471system.membus.trans_dist::UpgradeResp 149857 # Transaction distribution 1472system.membus.trans_dist::ReadExReq 965890 # Transaction distribution 1473system.membus.trans_dist::ReadExResp 778455 # Transaction distribution |
| 1478system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) 1479system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 1480system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) | 1474system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) 1475system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 1476system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) |
| 1481system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes) 1482system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes) | 1477system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6331701 # Packet count per connected master and slave (bytes) 1478system.membus.pkt_count_system.l2c.mem_side::total 6481921 # Packet count per connected master and slave (bytes) |
| 1483system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) 1484system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) | 1479system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) 1480system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) |
| 1485system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes) | 1481system.membus.pkt_count::total 6819903 # Packet count per connected master and slave (bytes) |
| 1486system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) 1487system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 1488system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) | 1482system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 1484system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) |
| 1489system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes) 1490system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes) | 1485system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215372636 # Cumulative packet size per connected master and slave (bytes) 1486system.membus.pkt_size_system.l2c.mem_side::total 215583633 # Cumulative packet size per connected master and slave (bytes) |
| 1491system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) 1492system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) | 1487system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) 1488system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) |
| 1493system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes) | 1489system.membus.pkt_size::total 229813073 # Cumulative packet size per connected master and slave (bytes) |
| 1494system.membus.snoops 0 # Total snoops (count) | 1490system.membus.snoops 0 # Total snoops (count) |
| 1495system.membus.snoop_fanout::samples 4414869 # Request fanout histogram | 1491system.membus.snoop_fanout::samples 4535526 # Request fanout histogram |
| 1496system.membus.snoop_fanout::mean 1 # Request fanout histogram 1497system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1498system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1499system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1492system.membus.snoop_fanout::mean 1 # Request fanout histogram 1493system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1494system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1495system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1500system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram | 1496system.membus.snoop_fanout::1 4535526 100.00% 100.00% # Request fanout histogram |
| 1501system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1502system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1503system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1504system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1497system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1498system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1499system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1500system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1505system.membus.snoop_fanout::total 4414869 # Request fanout histogram | 1501system.membus.snoop_fanout::total 4535526 # Request fanout histogram |
| 1506system.realview.ethernet.txBytes 966 # Bytes Transmitted 1507system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1508system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1509system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1510system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1511system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1512system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1513system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1540system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1541system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1542system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1543system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1544system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1545system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1546system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1547system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1502system.realview.ethernet.txBytes 966 # Bytes Transmitted 1503system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1504system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1505system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1506system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1507system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1508system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1509system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1536system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1537system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1538system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1539system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1540system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1541system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1542system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1543system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1548system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution 1549system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution 1550system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution 1551system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution 1552system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution 1553system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution 1554system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution 1555system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution 1556system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution 1557system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution 1558system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution 1559system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution 1560system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes) 1561system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes) 1562system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes) 1563system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes) 1564system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes) 1565system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes) 1566system.toL2Bus.snoops 117306 # Total snoops (count) 1567system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram 1568system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram 1569system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram | 1544system.toL2Bus.trans_dist::ReadReq 3711525 # Transaction distribution 1545system.toL2Bus.trans_dist::ReadResp 3711525 # Transaction distribution 1546system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution 1547system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution 1548system.toL2Bus.trans_dist::Writeback 2756140 # Transaction distribution 1549system.toL2Bus.trans_dist::WriteInvalidateReq 859453 # Transaction distribution 1550system.toL2Bus.trans_dist::WriteInvalidateResp 859453 # Transaction distribution 1551system.toL2Bus.trans_dist::UpgradeReq 330303 # Transaction distribution 1552system.toL2Bus.trans_dist::SCUpgradeReq 317258 # Transaction distribution 1553system.toL2Bus.trans_dist::UpgradeResp 647561 # Transaction distribution 1554system.toL2Bus.trans_dist::ReadExReq 1356474 # Transaction distribution 1555system.toL2Bus.trans_dist::ReadExResp 1356474 # Transaction distribution 1556system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8686436 # Packet count per connected master and slave (bytes) 1557system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7297334 # Packet count per connected master and slave (bytes) 1558system.toL2Bus.pkt_count::total 15983770 # Packet count per connected master and slave (bytes) 1559system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301115229 # Cumulative packet size per connected master and slave (bytes) 1560system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249782916 # Cumulative packet size per connected master and slave (bytes) 1561system.toL2Bus.pkt_size::total 550898145 # Cumulative packet size per connected master and slave (bytes) 1562system.toL2Bus.snoops 117325 # Total snoops (count) 1563system.toL2Bus.snoop_fanout::samples 9485599 # Request fanout histogram 1564system.toL2Bus.snoop_fanout::mean 1.012192 # Request fanout histogram 1565system.toL2Bus.snoop_fanout::stdev 0.109740 # Request fanout histogram |
| 1570system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1571system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1566system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1567system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1572system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram 1573system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram | 1568system.toL2Bus.snoop_fanout::1 9369955 98.78% 98.78% # Request fanout histogram 1569system.toL2Bus.snoop_fanout::2 115644 1.22% 100.00% # Request fanout histogram |
| 1574system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1575system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1576system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1570system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1571system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1572system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1577system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram | 1573system.toL2Bus.snoop_fanout::total 9485599 # Request fanout histogram |
| 1578 1579---------- End Simulation Statistics ---------- | 1574 1575---------- End Simulation Statistics ---------- |