Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt

Deleted Added

sdiff udiff text old ( 11245:1c5102c0a7a9 ) new ( 11336:b318499f676c )

full compact

3,5c3,5
< sim_seconds 47.216814 # Number of seconds simulated
< sim_ticks 47216814145000 # Number of ticks simulated
< final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.256536 # Number of seconds simulated
> sim_ticks 47256535705500 # Number of ticks simulated
> final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 919960 # Simulator instruction rate (inst/s)
< host_op_rate 1082251 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 44530469299 # Simulator tick rate (ticks/s)
< host_mem_usage 691012 # Number of bytes of host memory used
< host_seconds 1060.33 # Real time elapsed on the host
< sim_insts 975457230 # Number of instructions simulated
< sim_ops 1147538415 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1053178 # Simulator instruction rate (inst/s)
> host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 51012949173 # Simulator tick rate (ticks/s)
> host_mem_usage 689744 # Number of bytes of host memory used
> host_seconds 926.36 # Real time elapsed on the host
> sim_insts 975625723 # Number of instructions simulated
> sim_ops 1147772483 # Number of ops (including micro ops) simulated
16,29c16,29
< system.physmem.bytes_read::cpu0.dtb.walker 152064 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 126912 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 3862964 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 62933832 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 221952 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 220096 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2661000 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 46409840 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 419200 # Number of bytes read from this memory
< system.physmem.bytes_read::total 117007860 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 3862964 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2661000 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 6523964 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 100926976 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 155968 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 3922036 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 63542792 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 217344 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 214144 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 2638472 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 46092656 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 429440 # Number of bytes read from this memory
> system.physmem.bytes_read::total 117344244 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 3922036 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 2638472 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 101301760 # Number of bytes written to this memory
32,43c32,43
< system.physmem.bytes_written::total 100947560 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 2376 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 1983 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 100766 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 983354 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 3468 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 3439 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 41685 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 725170 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6550 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1868791 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1576984 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 101322344 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 2437 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 101689 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 992869 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 3396 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 3346 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 41333 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 720214 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6710 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1874047 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1582840 # Number of write requests responded to by this memory
46,61c46,61
< system.physmem.num_writes::total 1579558 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 3221 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 2688 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 81813 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 1332869 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 4661 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 982909 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8878 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2478097 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 81813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 138170 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2137522 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1585414 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 3300 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 82995 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 1344635 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 4599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 4532 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 55833 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 975371 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9087 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2483133 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 82995 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 55833 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 138828 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2143656 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
63,74c63,74
< system.physmem.bw_write::total 2137958 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2137522 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 3221 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 2688 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 81813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 1333305 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 4661 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 982909 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8878 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4616055 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2144092 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2143656 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 3300 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 82995 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 1345070 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 4599 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 4532 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 55833 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 975371 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9087 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4627224 # Total bandwidth to/from this memory (bytes/s)
137,141c137,141
< system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
---
> system.cpu0.dtb.walker.walks 124170 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency
145,148c145,148
< system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst
150,151c150,151
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst
153,154c153,154
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst
157,160c157,160
< system.cpu0.dtb.read_hits 92662773 # DTB read hits
< system.cpu0.dtb.read_misses 88786 # DTB read misses
< system.cpu0.dtb.write_hits 85694958 # DTB write hits
< system.cpu0.dtb.write_misses 36443 # DTB write misses
---
> system.cpu0.dtb.read_hits 91996645 # DTB read hits
> system.cpu0.dtb.read_misses 87944 # DTB read misses
> system.cpu0.dtb.write_hits 85085804 # DTB write hits
> system.cpu0.dtb.write_misses 36226 # DTB write misses
163c163
< system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
165c165
< system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB
167c167
< system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch
169,171c169,171
< system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
< system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 92084589 # DTB read accesses
> system.cpu0.dtb.write_accesses 85122030 # DTB write accesses
173,175c173,175
< system.cpu0.dtb.hits 178357731 # DTB hits
< system.cpu0.dtb.misses 125229 # DTB misses
< system.cpu0.dtb.accesses 178482960 # DTB accesses
---
> system.cpu0.dtb.hits 177082449 # DTB hits
> system.cpu0.dtb.misses 124170 # DTB misses
> system.cpu0.dtb.accesses 177206619 # DTB accesses
205,209c205,209
< system.cpu0.itb.walker.walks 61377 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
---
> system.cpu0.itb.walker.walks 60706 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency
213,215c213,215
< system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated
217,218c217,218
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst
220,224c220,224
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 497696393 # ITB inst hits
< system.cpu0.itb.inst_misses 61377 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 494456191 # ITB inst hits
> system.cpu0.itb.inst_misses 60706 # ITB inst misses
231c231
< system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
233c233
< system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB
240,244c240,244
< system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
< system.cpu0.itb.hits 497696393 # DTB hits
< system.cpu0.itb.misses 61377 # DTB misses
< system.cpu0.itb.accesses 497757770 # DTB accesses
< system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 494516897 # ITB inst accesses
> system.cpu0.itb.hits 494456191 # DTB hits
> system.cpu0.itb.misses 60706 # DTB misses
> system.cpu0.itb.accesses 494516897 # DTB accesses
> system.cpu0.numCycles 94513084765 # number of cpu cycles simulated
248,270c248,270
< system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
< system.cpu0.committedInsts 497466384 # Number of instructions committed
< system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
< system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 536103359 # number of integer instructions
< system.cpu0.num_fp_insts 526132 # number of float instructions
< system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
< system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
< system.cpu0.num_mem_refs 178459396 # number of memory refs
< system.cpu0.num_load_insts 92737001 # Number of load instructions
< system.cpu0.num_store_insts 85722395 # Number of store instructions
< system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
< system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
< system.cpu0.Branches 111287587 # Number of branches fetched
---
> system.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed
> system.cpu0.committedInsts 494222683 # Number of instructions committed
> system.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses
> system.cpu0.num_func_calls 28754621 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 532690974 # number of integer instructions
> system.cpu0.num_fp_insts 523276 # number of float instructions
> system.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written
> system.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written
> system.cpu0.num_mem_refs 177183712 # number of memory refs
> system.cpu0.num_load_insts 92070454 # Number of load instructions
> system.cpu0.num_store_insts 85113258 # Number of store instructions
> system.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles
> system.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles
> system.cpu0.Branches 110567658 # Number of branches fetched
272,302c272,302
< system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
< system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
< system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
< system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
< system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction
> system.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction
> system.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction
> system.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction
> system.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction
305,310c305,310
< system.cpu0.op_class::total 585300003 # Class of executed instruction
< system.cpu0.dcache.tags.replacements 6272771 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks.
---
> system.cpu0.op_class::total 581576758 # Class of executed instruction
> system.cpu0.dcache.tags.replacements 6248192 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks.
312,314c312,314
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy
316,318c316,318
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
320,385c320,385
< system.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 80912298 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 80912298 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262024 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 262024 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036634 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 2036634 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 167127209 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 167127209 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 167342863 # number of overall hits
< system.cpu0.dcache.overall_hits::total 167342863 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 1483144 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 1483144 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831696 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 831696 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158509 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 158509 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 4792526 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 4792526 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 5564665 # number of overall misses
< system.cpu0.dcache.overall_misses::total 5564665 # number of overall misses
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018000 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.018000 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760429 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072209 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072209 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027877 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.027877 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032183 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.032183 # miss rate for overall accesses
---
> system.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 80310172 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 80310172 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259684 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 259684 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039916 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 2039916 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 165871516 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 165871516 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 166085928 # number of overall hits
> system.cpu0.dcache.overall_hits::total 166085928 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 1484829 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 1484829 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823198 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 823198 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156543 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 156543 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 4777490 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 4777490 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 5552048 # number of overall misses
> system.cpu0.dcache.overall_misses::total 5552048 # number of overall misses
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760192 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760192 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071271 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071271 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032347 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.032347 # miss rate for overall accesses
394,395c394,395
< system.cpu0.dcache.writebacks::writebacks 6272771 # number of writebacks
< system.cpu0.dcache.writebacks::total 6272771 # number of writebacks
---
> system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks
> system.cpu0.dcache.writebacks::total 6248192 # number of writebacks
397,401c397,401
< system.cpu0.icache.tags.replacements 5539081 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 5479450 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks.
403c403
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor
407,410c407,409
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
412,437c411,436
< system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits
< system.cpu0.icache.overall_hits::total 492212891 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses
< system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
---
> system.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits
> system.cpu0.icache.overall_hits::total 489031557 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses
> system.cpu0.icache.overall_misses::total 5479967 # number of overall misses
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses
446,447c445,446
< system.cpu0.icache.writebacks::writebacks 5539081 # number of writebacks
< system.cpu0.icache.writebacks::total 5539081 # number of writebacks
---
> system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks
> system.cpu0.icache.writebacks::total 5479450 # number of writebacks
455,459c454,458
< system.cpu0.l2cache.tags.replacements 2670833 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16144.496707 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 15583793 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2686790 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 5.800153 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.tags.replacements 2651661 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16083.621220 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 15456673 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2667641 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 5.794135 # Average number of references to valid blocks.
461,470c460,469
< system.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.665572 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 43.728993 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.980170 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002543 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002669 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.985382 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15907 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15982.700506 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 46.812729 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.107985 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.975507 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002857 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003302 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15898 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 67 # Occupied blocks per task id
473,567c472,566
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4378 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5313 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4509 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970886 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 397685392 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 397685392 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 298097 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 159313 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 457410 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 4459579 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 4459579 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 7350874 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 7350874 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 760 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 760 # number of UpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635944 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 635944 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5035825 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 5035825 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2962064 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2962064 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223971 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 223971 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 298097 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 159313 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 5035825 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3598008 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 9091243 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 298097 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 159313 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 5035825 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3598008 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 9091243 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11326 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8418 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 19744 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138515 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 138515 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158509 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 158509 # number of SCUpgradeReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 708286 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 708286 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 503773 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 503773 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1239273 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1239273 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607364 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 607364 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11326 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8418 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 503773 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1947559 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 2471076 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11326 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8418 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 503773 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1947559 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 2471076 # number of overall misses
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 309423 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 167731 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 477154 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4459579 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 4459579 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 7350874 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 7350874 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139275 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 139275 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158509 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 158509 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 309423 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 167731 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 11562319 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 309423 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 167731 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 11562319 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050188 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.041379 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994543 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994543 # miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4776 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4826 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4604 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970337 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 394866118 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 394866118 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294519 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156806 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 451325 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 4431483 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 4431483 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 7294760 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 7294760 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 771 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 771 # number of UpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630855 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 630855 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4984424 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 4984424 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2948651 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2948651 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218371 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 218371 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294519 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156806 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 4984424 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3579506 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 9015255 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294519 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156806 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 4984424 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3579506 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 9015255 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11443 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8713 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 20156 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140594 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 140594 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156543 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 156543 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712979 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 712979 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 495543 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 495543 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236929 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1236929 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604457 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 604457 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11443 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8713 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 495543 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1949908 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2465607 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11443 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8713 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 495543 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1949908 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2465607 # number of overall misses
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305962 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165519 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 471481 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4431483 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 4431483 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 7294760 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 7294760 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141365 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 141365 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156543 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 156543 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305962 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165519 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 11480862 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305962 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165519 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 11480862 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052640 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.042750 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994546 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994546 # miss rate for UpgradeReq accesses
570,587c569,586
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526908 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526908 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090940 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090940 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294971 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294971 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730589 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730589 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050188 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090940 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.351192 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.213718 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050188 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090940 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.351192 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.213718 # miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530556 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530556 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090428 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090428 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295522 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295522 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734609 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734609 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052640 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090428 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352643 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.214758 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052640 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090428 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352643 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.214758 # miss rate for overall accesses
596,597c595,596
< system.cpu0.l2cache.writebacks::writebacks 1567377 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1567377 # number of writebacks
---
> system.cpu0.l2cache.writebacks::writebacks 1559370 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1559370 # number of writebacks
599,600c598,599
< system.cpu0.toL2Bus.snoop_filter.tot_requests 24282502 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12366009 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 24116923 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284721 # Number of requests hitting in the snoop filter with a single holder of the requested data.
602,633c601,632
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 1791227 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1790958 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 4459579 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 7350874 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 139275 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158509 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 297784 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19751529 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 37549877 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 709149780 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 756535625 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1470064325 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 6119333 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 30615399 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.066982 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.250025 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 1786138 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785867 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 271 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 4431483 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 7296159 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 141365 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156543 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 297908 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681122 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 37291838 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 6128014 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 30453385 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.067263 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.250512 # Request fanout histogram
635,637c634,636
< system.cpu0.toL2Bus.snoop_fanout::0 28565001 93.30% 93.30% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 2050129 6.70% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 28405278 93.27% 93.27% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 2047836 6.72% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 271 0.00% 100.00% # Request fanout histogram
641c640
< system.cpu0.toL2Bus.snoop_fanout::total 30615399 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::total 30453385 # Request fanout histogram
671,675c670,674
< system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
---
> system.cpu1.dtb.walker.walks 145097 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency
679,682c678,681
< system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst
684,685c683,684
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst
687,688c686,687
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst
691,694c690,693
< system.cpu1.dtb.read_hits 90153061 # DTB read hits
< system.cpu1.dtb.read_misses 111753 # DTB read misses
< system.cpu1.dtb.write_hits 81132787 # DTB write hits
< system.cpu1.dtb.write_misses 32288 # DTB write misses
---
> system.cpu1.dtb.read_hits 90839106 # DTB read hits
> system.cpu1.dtb.read_misses 112437 # DTB read misses
> system.cpu1.dtb.write_hits 81787747 # DTB write hits
> system.cpu1.dtb.write_misses 32660 # DTB write misses
697c696
< system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
699c698
< system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB
701c700
< system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch
703,705c702,704
< system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
< system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 90951543 # DTB read accesses
> system.cpu1.dtb.write_accesses 81820407 # DTB write accesses
707,709c706,708
< system.cpu1.dtb.hits 171285848 # DTB hits
< system.cpu1.dtb.misses 144041 # DTB misses
< system.cpu1.dtb.accesses 171429889 # DTB accesses
---
> system.cpu1.dtb.hits 172626853 # DTB hits
> system.cpu1.dtb.misses 145097 # DTB misses
> system.cpu1.dtb.accesses 172771950 # DTB accesses
739,743c738,742
< system.cpu1.itb.walker.walks 60885 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
---
> system.cpu1.itb.walker.walks 61573 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency
747,749c746,748
< system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated
751,752c750,751
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst
754,758c753,757
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 478248118 # ITB inst hits
< system.cpu1.itb.inst_misses 60885 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 481656543 # ITB inst hits
> system.cpu1.itb.inst_misses 61573 # ITB inst misses
765c764
< system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
767c766
< system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB
774,778c773,777
< system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
< system.cpu1.itb.hits 478248118 # DTB hits
< system.cpu1.itb.misses 60885 # DTB misses
< system.cpu1.itb.accesses 478309003 # DTB accesses
< system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses
> system.cpu1.itb.hits 481656543 # DTB hits
> system.cpu1.itb.misses 61573 # DTB misses
> system.cpu1.itb.accesses 481718116 # DTB accesses
> system.cpu1.numCycles 94513077683 # number of cpu cycles simulated
782,804c781,803
< system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
< system.cpu1.committedInsts 477990846 # Number of instructions committed
< system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
< system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 516282159 # number of integer instructions
< system.cpu1.num_fp_insts 374678 # number of float instructions
< system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
< system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
< system.cpu1.num_mem_refs 171406825 # number of memory refs
< system.cpu1.num_load_insts 90251973 # Number of load instructions
< system.cpu1.num_store_insts 81154852 # Number of store instructions
< system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
< system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
< system.cpu1.Branches 106497601 # Number of branches fetched
---
> system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed
> system.cpu1.committedInsts 481403040 # Number of instructions committed
> system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses
> system.cpu1.num_func_calls 28379648 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 519926686 # number of integer instructions
> system.cpu1.num_fp_insts 376275 # number of float instructions
> system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written
> system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written
> system.cpu1.num_mem_refs 172748485 # number of memory refs
> system.cpu1.num_load_insts 90938541 # Number of load instructions
> system.cpu1.num_store_insts 81809944 # Number of store instructions
> system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles
> system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles
> system.cpu1.Branches 107246711 # Number of branches fetched
806,836c805,835
< system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
< system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
< system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
< system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
< system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction
> system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction
> system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
> system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction
> system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction
839,844c838,843
< system.cpu1.op_class::total 562879339 # Class of executed instruction
< system.cpu1.dcache.tags.replacements 5945049 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
---
> system.cpu1.op_class::total 566836400 # Class of executed instruction
> system.cpu1.dcache.tags.replacements 5963482 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks.
846,848c845,847
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy
850,852c849,850
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id
854,919c852,917
< system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 76981821 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 76981821 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63451 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 63451 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048602 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 2048602 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 160679385 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 160679385 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 160867239 # number of overall hits
< system.cpu1.dcache.overall_hits::total 160867239 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 1461655 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 1461655 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427048 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 427048 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159147 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 159147 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 4819877 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 4819877 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 5612228 # number of overall misses
< system.cpu1.dcache.overall_misses::total 5612228 # number of overall misses
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018633 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.018633 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870640 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870640 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072086 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072086 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029123 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.029123 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033711 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.033711 # miss rate for overall accesses
---
> system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 77626077 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 77626077 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64906 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 64906 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047972 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 2047972 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 162001748 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 162001748 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 162190033 # number of overall hits
> system.cpu1.dcache.overall_hits::total 162190033 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 1463826 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 1463826 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435847 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 435847 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159002 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 159002 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 4833733 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 4833733 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 5624031 # number of overall misses
> system.cpu1.dcache.overall_misses::total 5624031 # number of overall misses
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018508 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.018508 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870383 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870383 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072045 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072045 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033513 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.033513 # miss rate for overall accesses
928,929c926,927
< system.cpu1.dcache.writebacks::writebacks 5945049 # number of writebacks
< system.cpu1.dcache.writebacks::total 5945049 # number of writebacks
---
> system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks
> system.cpu1.dcache.writebacks::total 5963482 # number of writebacks
931,935c929,933
< system.cpu1.icache.tags.replacements 4741297 # number of replacements
< system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.replacements 4804881 # number of replacements
> system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks.
937,939c935,937
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy
941,943c939,941
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
945,970c943,968
< system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
< system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
< system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
---
> system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits
> system.cpu1.icache.overall_hits::total 476906226 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses
> system.cpu1.icache.overall_misses::total 4805393 # number of overall misses
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses
979,980c977,978
< system.cpu1.icache.writebacks::writebacks 4741297 # number of writebacks
< system.cpu1.icache.writebacks::total 4741297 # number of writebacks
---
> system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks
> system.cpu1.icache.writebacks::total 4804881 # number of writebacks
988,1100c986,1100
< system.cpu1.l2cache.tags.replacements 2235881 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13334.612647 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 14249550 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2251891 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 6.327815 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 9713557375000 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.246601 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.385297 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.807067 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002823 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003991 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.813880 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1627 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6185 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4247 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3746 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 361919913 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 361919913 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 346945 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153602 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 500547 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 4020160 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 4020160 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 6665818 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 6665818 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1056 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 1056 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614983 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 614983 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4283593 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 4283593 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3077520 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 3077520 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161463 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 161463 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 346945 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153602 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 4283593 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3692503 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 8476643 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 346945 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153602 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 4283593 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3692503 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 8476643 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12460 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9763 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 22223 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144911 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 144911 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159147 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 159147 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 700907 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 700907 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458216 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 458216 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1219873 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 1219873 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265383 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 265383 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12460 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9763 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 458216 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1920780 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 2401219 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12460 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9763 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 458216 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1920780 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 2401219 # number of overall misses
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 359405 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163365 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 522770 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4020160 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 4020160 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 6665818 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 6665818 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145967 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 145967 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159147 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 159147 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 359405 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163365 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 10877862 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 359405 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163365 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 10877862 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059762 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.042510 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992765 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992765 # miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.tags.replacements 2273518 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13372.591247 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 14355328 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2289651 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 6.269658 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9713557312500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 13267.841352 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.789421 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 56.960475 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.809805 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002917 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003477 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.816198 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16058 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 317 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5907 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3824 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980103 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 364667597 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 364667597 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349833 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155576 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 505409 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030572 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 4030572 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 6737405 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 6737405 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1033 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1033 # number of UpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606896 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 606896 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338388 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 4338388 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3076039 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 3076039 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 163041 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 163041 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349833 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155576 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 4338388 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3682935 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 8526732 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349833 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155576 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 4338388 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3682935 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 8526732 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12358 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9778 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 22136 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147541 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 147541 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159002 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 159002 # number of SCUpgradeReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708595 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 708595 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467005 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 467005 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230054 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 1230054 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272567 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 272567 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12358 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9778 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 467005 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1938649 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 2427790 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12358 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9778 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 467005 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1938649 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 2427790 # number of overall misses
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362191 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165354 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 527545 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030572 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 4030572 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737405 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 6737405 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148574 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 148574 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159002 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 159002 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362191 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165354 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 10954522 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362191 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165354 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 10954522 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059134 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.041960 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993047 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993047 # miss rate for UpgradeReq accesses
1103,1120c1103,1120
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532649 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532649 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096633 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096633 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283863 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283863 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.621730 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.621730 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059762 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096633 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342185 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.220744 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059762 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096633 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342185 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.220744 # miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538654 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538654 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097184 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097184 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285654 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285654 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625716 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625716 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059134 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097184 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344858 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.221624 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059134 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097184 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344858 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.221624 # miss rate for overall accesses
1129,1130c1129,1130
< system.cpu1.l2cache.writebacks::writebacks 1179503 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1179503 # number of writebacks
---
> system.cpu1.l2cache.writebacks::writebacks 1197492 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1197492 # number of writebacks
1132,1166c1132,1166
< system.cpu1.toL2Bus.snoop_filter.tot_requests 22049015 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11267078 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760820 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760650 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4020160 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 6665818 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 145967 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159147 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 305114 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18660714 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 34085270 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 606915272 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 739752124 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1351465172 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 5690396 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 27910438 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.072996 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.260153 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 22219563 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11356978 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 1770232 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1770046 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030572 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 6737791 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 148574 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159002 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 307576 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18715946 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 34341081 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5728933 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 28119998 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.072981 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.260131 # Request fanout histogram
1168,1170c1168,1170
< system.cpu1.toL2Bus.snoop_fanout::0 25873264 92.70% 92.70% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 2037004 7.30% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 26067955 92.70% 92.70% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 2051857 7.30% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 186 0.00% 100.00% # Request fanout histogram
1174,1179c1174,1179
< system.cpu1.toL2Bus.snoop_fanout::total 27910438 # Request fanout histogram
< system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
---
> system.cpu1.toL2Bus.snoop_fanout::total 28119998 # Request fanout histogram
> system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes)
1192,1194c1192,1194
< system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes)
1197,1198c1197,1198
< system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes)
1211,1213c1211,1213
< system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes)
1216,1218c1216,1218
< system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
< system.iocache.tags.replacements 115585 # number of replacements
< system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
---
> system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes)
> system.iocache.tags.replacements 115596 # number of replacements
> system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use
1220c1220
< system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks.
1223,1227c1223,1227
< system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy
1231,1232c1231,1232
< system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
< system.iocache.tags.data_accesses 1040793 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1040892 # Number of tag accesses
> system.iocache.tags.data_accesses 1040892 # Number of data accesses
1234,1235c1234,1235
< system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses
1241,1242c1241,1242
< system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8927 # number of demand (read+write) misses
1244,1245c1244,1245
< system.iocache.overall_misses::realview.ide 8876 # number of overall misses
< system.iocache.overall_misses::total 8916 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8887 # number of overall misses
> system.iocache.overall_misses::total 8927 # number of overall misses
1247,1248c1247,1248
< system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses)
1254,1255c1254,1255
< system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses
1257,1258c1257,1258
< system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses
1283,1287c1283,1287
< system.l2c.tags.replacements 1759418 # number of replacements
< system.l2c.tags.tagsinuse 62296.253449 # Cycle average of tags in use
< system.l2c.tags.total_refs 4473392 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1817492 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.461299 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 1772759 # number of replacements
> system.l2c.tags.tagsinuse 62623.636789 # Cycle average of tags in use
> system.l2c.tags.total_refs 4610700 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1831680 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.517197 # Average number of references to valid blocks.
1289,1310c1289,1312
< system.l2c.tags.occ_blocks::writebacks 34373.643780 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 42.521667 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 58.768031 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 3224.697109 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 7016.159468 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 270.222583 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 416.861208 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 2985.929949 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 13907.449654 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.524500 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000649 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000897 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.049205 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.107058 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004123 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.006361 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.045562 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.212211 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.950565 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1023 212 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 57862 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id
---
> system.l2c.tags.occ_blocks::writebacks 34513.616341 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.391588 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 102.836315 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 3358.057391 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 7927.916069 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.822259 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 388.027254 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 2900.077291 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 13121.892282 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.526636 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001059 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.001569 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.051240 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.120970 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003690 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.005921 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.044252 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.200224 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.955561 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 58727 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id
1312,1467c1314,1469
< system.l2c.tags.age_task_id_blocks_1024::1 539 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 3515 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5475 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 48284 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.882904 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 73042126 # Number of tag accesses
< system.l2c.tags.data_accesses 73042126 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 2746880 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2746880 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 14674 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 12828 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 27502 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 1473 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 1269 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 2742 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 316195 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 262623 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 578818 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4560 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 446108 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 731335 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3622 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 416632 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 676220 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2290398 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 4560 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 446108 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 1047530 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 3622 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 416632 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 938843 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2869216 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 4560 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 446108 # number of overall hits
< system.l2c.overall_hits::cpu0.data 1047530 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 3622 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 416632 # number of overall hits
< system.l2c.overall_hits::cpu1.data 938843 # number of overall hits
< system.l2c.overall_hits::total 2869216 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 68066 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 63332 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 131398 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 7840 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 7476 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 15316 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 815697 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 546954 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 1362651 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2376 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1983 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 57665 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 181479 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3468 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3439 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 41584 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 187193 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 479187 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1983 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 57665 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 997176 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 3468 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 3439 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 41584 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 734147 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1841838 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1983 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 57665 # number of overall misses
< system.l2c.overall_misses::cpu0.data 997176 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 3468 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 3439 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 41584 # number of overall misses
< system.l2c.overall_misses::cpu1.data 734147 # number of overall misses
< system.l2c.overall_misses::total 1841838 # number of overall misses
< system.l2c.WritebackDirty_accesses::writebacks 2746880 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2746880 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 82740 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 76160 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 158900 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 9313 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 8745 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 18058 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 1131892 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 809577 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 1941469 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8724 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6543 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 503773 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 912814 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9041 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7061 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 458216 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 863413 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 2769585 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 8724 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 6543 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 503773 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 2044706 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 9041 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 7061 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 458216 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 1672990 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4711054 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 8724 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 6543 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 503773 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 2044706 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 9041 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 7061 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 458216 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 1672990 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4711054 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.822649 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831565 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.826923 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.841834 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.854889 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.848156 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.720649 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.675605 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.701866 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303072 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.114466 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198813 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.487041 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090752 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.216806 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.173018 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.303072 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.114466 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.487687 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.487041 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.090752 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.438823 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.390961 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.303072 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.114466 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.487687 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.487041 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.090752 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.438823 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.390961 # miss rate for overall accesses
---
> system.l2c.tags.age_task_id_blocks_1024::1 457 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 3184 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 5196 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 49841 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1023 0.002960 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.896103 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 73222946 # Number of tag accesses
> system.l2c.tags.data_accesses 73222946 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 2756862 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 2756862 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 19292 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 16576 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 35868 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2708 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 2412 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 5120 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 311775 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 276099 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 587874 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6229 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4594 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 436955 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 721918 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5484 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3754 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 425773 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 684534 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2289241 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 6229 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4594 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 436955 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 1033693 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5484 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 3754 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 425773 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 960633 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2877115 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 6229 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4594 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 436955 # number of overall hits
> system.l2c.overall_hits::cpu0.data 1033693 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5484 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 3754 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 425773 # number of overall hits
> system.l2c.overall_hits::cpu1.data 960633 # number of overall hits
> system.l2c.overall_hits::total 2877115 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 65194 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 61685 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 126879 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 6603 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 6332 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 12935 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 822855 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 542831 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 1365686 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2437 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 58588 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 182243 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3396 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3346 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 41232 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 187565 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 480860 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 2437 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 58588 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 1005098 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 3396 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 3346 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 41232 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 730396 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1846546 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 2437 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 58588 # number of overall misses
> system.l2c.overall_misses::cpu0.data 1005098 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 3396 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 3346 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 41232 # number of overall misses
> system.l2c.overall_misses::cpu1.data 730396 # number of overall misses
> system.l2c.overall_misses::total 1846546 # number of overall misses
> system.l2c.WritebackDirty_accesses::writebacks 2756862 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 2756862 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 84486 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 78261 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 162747 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 9311 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 8744 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 18055 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 1134630 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 818930 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 1953560 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8666 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6647 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 495543 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 904161 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8880 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7100 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 467005 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 872099 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 2770101 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 8666 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 6647 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 495543 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 2038791 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 8880 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 7100 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 467005 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 1691029 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4723661 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 8666 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 6647 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 495543 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 2038791 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 8880 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 7100 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 467005 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 1691029 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4723661 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771654 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788196 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.779609 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.709161 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.724154 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.716422 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.725219 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.662854 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.699076 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.308861 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.118230 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201560 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.471268 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.088290 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215073 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.173589 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.308861 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.118230 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.492987 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.471268 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.088290 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.431924 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.390914 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.308861 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.118230 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.492987 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.471268 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.088290 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.431924 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.390914 # miss rate for overall accesses
1476,1477c1478,1479
< system.l2c.writebacks::writebacks 1470290 # number of writebacks
< system.l2c.writebacks::total 1470290 # number of writebacks
---
> system.l2c.writebacks::writebacks 1476146 # number of writebacks
> system.l2c.writebacks::total 1476146 # number of writebacks
1479,1490c1481,1492
< system.membus.trans_dist::ReadReq 82131 # Transaction distribution
< system.membus.trans_dist::ReadResp 570231 # Transaction distribution
< system.membus.trans_dist::WriteReq 38802 # Transaction distribution
< system.membus.trans_dist::WriteResp 38802 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1576984 # Transaction distribution
< system.membus.trans_dist::CleanEvict 244820 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 347427 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 314914 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 168909 # Transaction distribution
< system.membus.trans_dist::ReadExReq 1611622 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1340459 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 488100 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 82185 # Transaction distribution
> system.membus.trans_dist::ReadResp 571969 # Transaction distribution
> system.membus.trans_dist::WriteReq 38847 # Transaction distribution
> system.membus.trans_dist::WriteResp 38847 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1582840 # Transaction distribution
> system.membus.trans_dist::CleanEvict 248395 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 346027 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 310425 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 161621 # Transaction distribution
> system.membus.trans_dist::ReadExReq 1349349 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1343882 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 489784 # Transaction distribution
1493c1495
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
1495,1501c1497,1503
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6542117 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 6692337 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344320 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 344320 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7036657 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6280303 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 6430721 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 6777627 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes)
1503,1508c1505,1510
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210749660 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 210960657 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 218359505 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211450588 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 211661967 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 219061519 # Cumulative packet size per connected master and slave (bytes)
1510c1512
< system.membus.snoop_fanout::samples 4814081 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 4554580 # Request fanout histogram
1515c1517
< system.membus.snoop_fanout::1 4814081 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 4554580 100.00% 100.00% # Request fanout histogram
1520c1522
< system.membus.snoop_fanout::total 4814081 # Request fanout histogram
---
> system.membus.snoop_fanout::total 4554580 # Request fanout histogram
1573,1600c1575,1602
< system.toL2Bus.snoop_filter.tot_requests 11103531 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 5720804 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 1657088 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 128474 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 115294 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 13180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 3545235 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 2746880 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1000532 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 352734 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 317656 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 670390 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 2212632 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 2212632 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 3463102 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9045879 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7635651 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 16681530 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295373981 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 244078084 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 539452065 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 1992317 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 13215112 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.283607 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.452956 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 11149388 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 5745365 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 1662887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 135292 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 121804 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 13488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 3554010 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 2756862 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 2018423 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 360088 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 315545 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 675633 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 2226645 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 2226645 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 3471823 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9531217 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8234338 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 17765555 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294166716 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 247379555 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 541546271 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 2005695 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 13274431 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.283856 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.453116 # Request fanout histogram
1602,1604c1604,1606
< system.toL2Bus.snoop_fanout::0 9480390 71.74% 71.74% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 3721542 28.16% 99.90% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 13180 0.10% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 9519891 71.72% 71.72% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3741052 28.18% 99.90% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 13488 0.10% 100.00% # Request fanout histogram
1608c1610
< system.toL2Bus.snoop_fanout::total 13215112 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::total 13274431 # Request fanout histogram