Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt

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stats.txt (11606:6b749761c398)	stats.txt (11687:b3d5f0e9e258)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.296282 # Number of seconds simulated 4sim_ticks 47296281748500 # Number of ticks simulated 5final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.296282 # Number of seconds simulated 4sim_ticks 47296281748500 # Number of ticks simulated 5final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 890958 # Simulator instruction rate (inst/s) 8host_op_rate 1048084 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43128593002 # Simulator tick rate (ticks/s) 10host_mem_usage 697472 # Number of bytes of host memory used 11host_seconds 1096.63 # Real time elapsed on the host	7host_inst_rate 1698090 # Simulator instruction rate (inst/s) 8host_op_rate 1997558 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 82199406118 # Simulator tick rate (ticks/s) 10host_mem_usage 696116 # Number of bytes of host memory used 11host_seconds 575.38 # Real time elapsed on the host
12sim_insts 977055082 # Number of instructions simulated 13sim_ops 1149364510 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 154816 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4238644 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 35981768 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 224128 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 222976 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3009416 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 39414640 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 402560 # Number of bytes read from this memory 26system.physmem.bytes_read::total 83777076 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 4238644 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 3009416 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 7248060 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 102370496 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 33system.physmem.bytes_written::total 102391080 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 2419 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2002 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 106636 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 562228 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.dtb.walker 3502 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.itb.walker 3484 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 47129 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 615870 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 6290 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 1349560 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 1599539 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 1602113 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 3273 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 2709 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 89619 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 760774 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 4739 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.itb.walker 4714 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.inst 63629 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.data 833356 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 8511 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 1771325 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 89619 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 63629 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 153248 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 2164451 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 2164886 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 2164451 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 3273 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 2709 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 89619 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 761209 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 4739 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.itb.walker 4714 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 63629 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.data 833356 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 8511 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 3936211 # Total bandwidth to/from this memory (bytes/s) 76system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 77system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 80system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 81system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 82system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 83system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 84system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 85system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 86system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 87system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 88system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 89system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 90system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 91system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 92system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 93system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 94system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 95system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 96system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 97system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 98system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 99system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 100system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 101system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 102system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 103system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 104system.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 105system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 106system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 107system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 108system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 109system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 110system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 111system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 112system.cpu_clk_domain.clock 500 # Clock period in ticks 113system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 114system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 116system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 117system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 118system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 119system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 120system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 121system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 122system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 123system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 124system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 125system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 126system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 127system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 128system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 129system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 130system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 131system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 132system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 133system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 134system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 135system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 136system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 137system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 138system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 140system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 141system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 142system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 143system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 144system.cpu0.dtb.walker.walks 125159 # Table walker walks requested 145system.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors 146system.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency 147system.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148system.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency 149system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 150system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 151system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 152system.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated 153system.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated 154system.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated 155system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst 156system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 157system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst 158system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst 159system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 160system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst 161system.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst 162system.cpu0.dtb.inst_hits 0 # ITB inst hits 163system.cpu0.dtb.inst_misses 0 # ITB inst misses 164system.cpu0.dtb.read_hits 92471463 # DTB read hits 165system.cpu0.dtb.read_misses 88826 # DTB read misses 166system.cpu0.dtb.write_hits 85455153 # DTB write hits 167system.cpu0.dtb.write_misses 36333 # DTB write misses 168system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 169system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 170system.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 171system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 172system.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB 173system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch 175system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions 177system.cpu0.dtb.read_accesses 92560289 # DTB read accesses 178system.cpu0.dtb.write_accesses 85491486 # DTB write accesses 179system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 180system.cpu0.dtb.hits 177926616 # DTB hits 181system.cpu0.dtb.misses 125159 # DTB misses 182system.cpu0.dtb.accesses 178051775 # DTB accesses 183system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 184system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 185system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 186system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 187system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 188system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 189system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 190system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 191system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 192system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 193system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 194system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 195system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 196system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 197system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 198system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 199system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 200system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 201system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 202system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 203system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 204system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 205system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 208system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 209system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 210system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 211system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 212system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 213system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 214system.cpu0.itb.walker.walks 61082 # Table walker walks requested 215system.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors 216system.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency 217system.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency 218system.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency 219system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 220system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 221system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 222system.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated 223system.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated 224system.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated 225system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 226system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst 227system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst 228system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 229system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst 230system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst 231system.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst 232system.cpu0.itb.inst_hits 496679820 # ITB inst hits 233system.cpu0.itb.inst_misses 61082 # ITB inst misses 234system.cpu0.itb.read_hits 0 # DTB read hits 235system.cpu0.itb.read_misses 0 # DTB read misses 236system.cpu0.itb.write_hits 0 # DTB write hits 237system.cpu0.itb.write_misses 0 # DTB write misses 238system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 239system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 240system.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 241system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 242system.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB 243system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 244system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 245system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 246system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 247system.cpu0.itb.read_accesses 0 # DTB read accesses 248system.cpu0.itb.write_accesses 0 # DTB write accesses 249system.cpu0.itb.inst_accesses 496740902 # ITB inst accesses 250system.cpu0.itb.hits 496679820 # DTB hits 251system.cpu0.itb.misses 61082 # DTB misses 252system.cpu0.itb.accesses 496740902 # DTB accesses 253system.cpu0.numPwrStateTransitions 26445 # Number of power state transitions 254system.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state 255system.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state 256system.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state 257system.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state 258system.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state 259system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state 260system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state 261system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 262system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 263system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 264system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state 265system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 266system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 267system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 268system.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state 269system.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state 270system.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states 271system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states 272system.cpu0.numCycles 94592576721 # number of cpu cycles simulated 273system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 274system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 275system.cpu0.kern.inst.arm 0 # number of arm instructions executed 276system.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed 277system.cpu0.committedInsts 496443686 # Number of instructions committed 278system.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed 279system.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses 280system.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses 281system.cpu0.num_func_calls 28899937 # number of times a function call or return occured 282system.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls 283system.cpu0.num_int_insts 535025290 # number of integer instructions 284system.cpu0.num_fp_insts 524584 # number of float instructions 285system.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read 286system.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written 287system.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read 288system.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written 289system.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read 290system.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written 291system.cpu0.num_mem_refs 178027643 # number of memory refs 292system.cpu0.num_load_insts 92545018 # Number of load instructions 293system.cpu0.num_store_insts 85482625 # Number of store instructions 294system.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles 295system.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles 296system.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles 297system.cpu0.idle_fraction 0.993825 # Percentage of idle cycles 298system.cpu0.Branches 111093071 # Number of branches fetched 299system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 300system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction 301system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction 302system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction	12sim_insts 977055082 # Number of instructions simulated 13sim_ops 1149364510 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 154816 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4238644 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 35981768 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 224128 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 222976 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3009416 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 39414640 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 402560 # Number of bytes read from this memory 26system.physmem.bytes_read::total 83777076 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 4238644 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 3009416 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 7248060 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 102370496 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 33system.physmem.bytes_written::total 102391080 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 2419 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2002 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 106636 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 562228 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.dtb.walker 3502 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.itb.walker 3484 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 47129 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 615870 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 6290 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 1349560 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 1599539 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 1602113 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 3273 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 2709 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 89619 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 760774 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 4739 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.itb.walker 4714 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.inst 63629 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.data 833356 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 8511 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 1771325 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 89619 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 63629 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 153248 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 2164451 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 2164886 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 2164451 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 3273 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 2709 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 89619 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 761209 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 4739 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.itb.walker 4714 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 63629 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.data 833356 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 8511 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 3936211 # Total bandwidth to/from this memory (bytes/s) 76system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 77system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 78system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 79system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 80system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 81system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 82system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 83system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 84system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 85system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 86system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 87system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 88system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 89system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 90system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 91system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 92system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 93system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 94system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 95system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 96system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 97system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 98system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 99system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 100system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 101system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 102system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 103system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 104system.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 105system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 106system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 107system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 108system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 109system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 110system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 111system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 112system.cpu_clk_domain.clock 500 # Clock period in ticks 113system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 114system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 116system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 117system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 118system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 119system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 120system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 121system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 122system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 123system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 124system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 125system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 126system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 127system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 128system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 129system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 130system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 131system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 132system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 133system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 134system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 135system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 136system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 137system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 138system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 140system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 141system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 142system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 143system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 144system.cpu0.dtb.walker.walks 125159 # Table walker walks requested 145system.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors 146system.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency 147system.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148system.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency 149system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 150system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 151system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 152system.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated 153system.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated 154system.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated 155system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst 156system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 157system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst 158system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst 159system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 160system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst 161system.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst 162system.cpu0.dtb.inst_hits 0 # ITB inst hits 163system.cpu0.dtb.inst_misses 0 # ITB inst misses 164system.cpu0.dtb.read_hits 92471463 # DTB read hits 165system.cpu0.dtb.read_misses 88826 # DTB read misses 166system.cpu0.dtb.write_hits 85455153 # DTB write hits 167system.cpu0.dtb.write_misses 36333 # DTB write misses 168system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 169system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 170system.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 171system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 172system.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB 173system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch 175system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions 177system.cpu0.dtb.read_accesses 92560289 # DTB read accesses 178system.cpu0.dtb.write_accesses 85491486 # DTB write accesses 179system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 180system.cpu0.dtb.hits 177926616 # DTB hits 181system.cpu0.dtb.misses 125159 # DTB misses 182system.cpu0.dtb.accesses 178051775 # DTB accesses 183system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 184system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 185system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 186system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 187system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 188system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 189system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 190system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 191system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 192system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 193system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 194system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 195system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 196system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 197system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 198system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 199system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 200system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 201system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 202system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 203system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 204system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 205system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 206system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 207system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 208system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 209system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 210system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 211system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 212system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 213system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 214system.cpu0.itb.walker.walks 61082 # Table walker walks requested 215system.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors 216system.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency 217system.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency 218system.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency 219system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 220system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 221system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 222system.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated 223system.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated 224system.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated 225system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 226system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst 227system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst 228system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 229system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst 230system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst 231system.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst 232system.cpu0.itb.inst_hits 496679820 # ITB inst hits 233system.cpu0.itb.inst_misses 61082 # ITB inst misses 234system.cpu0.itb.read_hits 0 # DTB read hits 235system.cpu0.itb.read_misses 0 # DTB read misses 236system.cpu0.itb.write_hits 0 # DTB write hits 237system.cpu0.itb.write_misses 0 # DTB write misses 238system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 239system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 240system.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 241system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 242system.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB 243system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 244system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 245system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 246system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 247system.cpu0.itb.read_accesses 0 # DTB read accesses 248system.cpu0.itb.write_accesses 0 # DTB write accesses 249system.cpu0.itb.inst_accesses 496740902 # ITB inst accesses 250system.cpu0.itb.hits 496679820 # DTB hits 251system.cpu0.itb.misses 61082 # DTB misses 252system.cpu0.itb.accesses 496740902 # DTB accesses 253system.cpu0.numPwrStateTransitions 26445 # Number of power state transitions 254system.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state 255system.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state 256system.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state 257system.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state 258system.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state 259system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state 260system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state 261system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 262system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 263system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 264system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state 265system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 266system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 267system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 268system.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state 269system.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state 270system.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states 271system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states 272system.cpu0.numCycles 94592576721 # number of cpu cycles simulated 273system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 274system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 275system.cpu0.kern.inst.arm 0 # number of arm instructions executed 276system.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed 277system.cpu0.committedInsts 496443686 # Number of instructions committed 278system.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed 279system.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses 280system.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses 281system.cpu0.num_func_calls 28899937 # number of times a function call or return occured 282system.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls 283system.cpu0.num_int_insts 535025290 # number of integer instructions 284system.cpu0.num_fp_insts 524584 # number of float instructions 285system.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read 286system.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written 287system.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read 288system.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written 289system.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read 290system.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written 291system.cpu0.num_mem_refs 178027643 # number of memory refs 292system.cpu0.num_load_insts 92545018 # Number of load instructions 293system.cpu0.num_store_insts 85482625 # Number of store instructions 294system.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles 295system.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles 296system.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles 297system.cpu0.idle_fraction 0.993825 # Percentage of idle cycles 298system.cpu0.Branches 111093071 # Number of branches fetched 299system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 300system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction 301system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction 302system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction
303system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction 304system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction 305system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction	303system.cpu0.op_class::FloatAdd 8 0.00% 69.51% # Class of executed instruction 304system.cpu0.op_class::FloatCmp 13 0.00% 69.51% # Class of executed instruction 305system.cpu0.op_class::FloatCvt 21 0.00% 69.51% # Class of executed instruction
306system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction	306system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
	307system.cpu0.op_class::FloatMultAcc 0 0.00% 69.51% # Class of executed instruction
307system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction	308system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
308system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 309system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 310system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 311system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 312system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 313system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 314system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 315system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 316system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 317system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 318system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 319system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 320system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction 321system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 322system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction 323system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction 324system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 325system.cpu0.op_class::SimdFloatMisc 72938 0.01% 69.52% # Class of executed instruction	309system.cpu0.op_class::FloatMisc 72938 0.01% 69.52% # Class of executed instruction 310system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 311system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 312system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 313system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 314system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 315system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 316system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 317system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 318system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 319system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 320system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 321system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 322system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 323system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 324system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 325system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 326system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction 327system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.52% # Class of executed instruction
326system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 327system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 328system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction	328system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 329system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 330system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
329system.cpu0.op_class::MemRead 92545018 15.84% 85.36% # Class of executed instruction 330system.cpu0.op_class::MemWrite 85482625 14.64% 100.00% # Class of executed instruction	331system.cpu0.op_class::MemRead 92483705 15.83% 85.35% # Class of executed instruction 332system.cpu0.op_class::MemWrite 85092334 14.57% 99.92% # Class of executed instruction 333system.cpu0.op_class::FloatMemRead 61313 0.01% 99.93% # Class of executed instruction 334system.cpu0.op_class::FloatMemWrite 390291 0.07% 100.00% # Class of executed instruction
331system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 332system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 333system.cpu0.op_class::total 584096590 # Class of executed instruction 334system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 335system.cpu0.dcache.tags.replacements 6248914 # number of replacements 336system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use 337system.cpu0.dcache.tags.total_refs 171607957 # Total number of references to valid blocks. 338system.cpu0.dcache.tags.sampled_refs 6249426 # Sample count of references to valid blocks. 339system.cpu0.dcache.tags.avg_refs 27.459795 # Average number of references to valid blocks. 340system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 341system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor 342system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy 343system.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy 344system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 345system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 346system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 347system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 348system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 349system.cpu0.dcache.tags.tag_accesses 362271539 # Number of tag accesses 350system.cpu0.dcache.tags.data_accesses 362271539 # Number of data accesses 351system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 352system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits 353system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits 354system.cpu0.dcache.WriteReq_hits::cpu0.data 80674063 # number of WriteReq hits 355system.cpu0.dcache.WriteReq_hits::total 80674063 # number of WriteReq hits 356system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits 357system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits 358system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261006 # number of WriteLineReq hits 359system.cpu0.dcache.WriteLineReq_hits::total 261006 # number of WriteLineReq hits 360system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087975 # number of LoadLockedReq hits 361system.cpu0.dcache.LoadLockedReq_hits::total 2087975 # number of LoadLockedReq hits 362system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051823 # number of StoreCondReq hits 363system.cpu0.dcache.StoreCondReq_hits::total 2051823 # number of StoreCondReq hits 364system.cpu0.dcache.demand_hits::cpu0.data 166959241 # number of demand (read+write) hits 365system.cpu0.dcache.demand_hits::total 166959241 # number of demand (read+write) hits 366system.cpu0.dcache.overall_hits::cpu0.data 167175510 # number of overall hits 367system.cpu0.dcache.overall_hits::total 167175510 # number of overall hits 368system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses 369system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses 370system.cpu0.dcache.WriteReq_misses::cpu0.data 1477781 # number of WriteReq misses 371system.cpu0.dcache.WriteReq_misses::total 1477781 # number of WriteReq misses 372system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses 373system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses 374system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824193 # number of WriteLineReq misses 375system.cpu0.dcache.WriteLineReq_misses::total 824193 # number of WriteLineReq misses 376system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119751 # number of LoadLockedReq misses 377system.cpu0.dcache.LoadLockedReq_misses::total 119751 # number of LoadLockedReq misses 378system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154814 # number of StoreCondReq misses 379system.cpu0.dcache.StoreCondReq_misses::total 154814 # number of StoreCondReq misses 380system.cpu0.dcache.demand_misses::cpu0.data 5600396 # number of demand (read+write) misses 381system.cpu0.dcache.demand_misses::total 5600396 # number of demand (read+write) misses 382system.cpu0.dcache.overall_misses::cpu0.data 6369959 # number of overall misses 383system.cpu0.dcache.overall_misses::total 6369959 # number of overall misses 384system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) 385system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) 386system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) 387system.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses) 388system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses) 389system.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses) 390system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses) 391system.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses) 392system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses) 393system.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses) 394system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses) 395system.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses) 396system.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses 397system.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses 398system.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses 399system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses 400system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses 401system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses 402system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017988 # miss rate for WriteReq accesses 403system.cpu0.dcache.WriteReq_miss_rate::total 0.017988 # miss rate for WriteReq accesses 404system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses 405system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses 406system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759486 # miss rate for WriteLineReq accesses 407system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759486 # miss rate for WriteLineReq accesses 408system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054242 # miss rate for LoadLockedReq accesses 409system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054242 # miss rate for LoadLockedReq accesses 410system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070158 # miss rate for StoreCondReq accesses 411system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070158 # miss rate for StoreCondReq accesses 412system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032455 # miss rate for demand accesses 413system.cpu0.dcache.demand_miss_rate::total 0.032455 # miss rate for demand accesses 414system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036705 # miss rate for overall accesses 415system.cpu0.dcache.overall_miss_rate::total 0.036705 # miss rate for overall accesses 416system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 417system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 418system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 419system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 420system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 421system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 422system.cpu0.dcache.writebacks::writebacks 6248914 # number of writebacks 423system.cpu0.dcache.writebacks::total 6248914 # number of writebacks 424system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 425system.cpu0.icache.tags.replacements 5509624 # number of replacements 426system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use 427system.cpu0.icache.tags.total_refs 491225330 # Total number of references to valid blocks. 428system.cpu0.icache.tags.sampled_refs 5510136 # Sample count of references to valid blocks. 429system.cpu0.icache.tags.avg_refs 89.149402 # Average number of references to valid blocks. 430system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. 431system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor 432system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 433system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 434system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 435system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id 436system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 437system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 438system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 439system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 440system.cpu0.icache.tags.tag_accesses 998981083 # Number of tag accesses 441system.cpu0.icache.tags.data_accesses 998981083 # Number of data accesses 442system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 443system.cpu0.icache.ReadReq_hits::cpu0.inst 491225330 # number of ReadReq hits 444system.cpu0.icache.ReadReq_hits::total 491225330 # number of ReadReq hits 445system.cpu0.icache.demand_hits::cpu0.inst 491225330 # number of demand (read+write) hits 446system.cpu0.icache.demand_hits::total 491225330 # number of demand (read+write) hits 447system.cpu0.icache.overall_hits::cpu0.inst 491225330 # number of overall hits 448system.cpu0.icache.overall_hits::total 491225330 # number of overall hits 449system.cpu0.icache.ReadReq_misses::cpu0.inst 5510141 # number of ReadReq misses 450system.cpu0.icache.ReadReq_misses::total 5510141 # number of ReadReq misses 451system.cpu0.icache.demand_misses::cpu0.inst 5510141 # number of demand (read+write) misses 452system.cpu0.icache.demand_misses::total 5510141 # number of demand (read+write) misses 453system.cpu0.icache.overall_misses::cpu0.inst 5510141 # number of overall misses 454system.cpu0.icache.overall_misses::total 5510141 # number of overall misses 455system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) 456system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) 457system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses 458system.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses 459system.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses 460system.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses 461system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses 462system.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses 463system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses 464system.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses 465system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses 466system.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses 467system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 471system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 473system.cpu0.icache.writebacks::writebacks 5509624 # number of writebacks 474system.cpu0.icache.writebacks::total 5509624 # number of writebacks 475system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 476system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 477system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 478system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 479system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 480system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 481system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 482system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 483system.cpu0.l2cache.tags.replacements 2567589 # number of replacements 484system.cpu0.l2cache.tags.tagsinuse 15706.944975 # Cycle average of tags in use 485system.cpu0.l2cache.tags.total_refs 9429067 # Total number of references to valid blocks. 486system.cpu0.l2cache.tags.sampled_refs 2583246 # Sample count of references to valid blocks. 487system.cpu0.l2cache.tags.avg_refs 3.650085 # Average number of references to valid blocks. 488system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 489system.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594 # Average occupied blocks per requestor 490system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 27.364617 # Average occupied blocks per requestor 491system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.639763 # Average occupied blocks per requestor 492system.cpu0.l2cache.tags.occ_percent::writebacks 0.955624 # Average percentage of cache occupancy 493system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001670 # Average percentage of cache occupancy 494system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001382 # Average percentage of cache occupancy 495system.cpu0.l2cache.tags.occ_percent::total 0.958676 # Average percentage of cache occupancy 496system.cpu0.l2cache.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id 497system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15600 # Occupied blocks per task id 498system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 499system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 41 # Occupied blocks per task id 500system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 501system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 502system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 421 # Occupied blocks per task id 503system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2091 # Occupied blocks per task id 504system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5339 # Occupied blocks per task id 505system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5411 # Occupied blocks per task id 506system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2338 # Occupied blocks per task id 507system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id 508system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.952148 # Percentage of cache occupancy per task id 509system.cpu0.l2cache.tags.tag_accesses 401859473 # Number of tag accesses 510system.cpu0.l2cache.tags.data_accesses 401859473 # Number of data accesses 511system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 512system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 287369 # number of ReadReq hits 513system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155522 # number of ReadReq hits 514system.cpu0.l2cache.ReadReq_hits::total 442891 # number of ReadReq hits 515system.cpu0.l2cache.WritebackDirty_hits::writebacks 4441046 # number of WritebackDirty hits 516system.cpu0.l2cache.WritebackDirty_hits::total 4441046 # number of WritebackDirty hits 517system.cpu0.l2cache.WritebackClean_hits::writebacks 7316094 # number of WritebackClean hits 518system.cpu0.l2cache.WritebackClean_hits::total 7316094 # number of WritebackClean hits 519system.cpu0.l2cache.ReadExReq_hits::cpu0.data 640560 # number of ReadExReq hits 520system.cpu0.l2cache.ReadExReq_hits::total 640560 # number of ReadExReq hits 521system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5011469 # number of ReadCleanReq hits 522system.cpu0.l2cache.ReadCleanReq_hits::total 5011469 # number of ReadCleanReq hits 523system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2961462 # number of ReadSharedReq hits 524system.cpu0.l2cache.ReadSharedReq_hits::total 2961462 # number of ReadSharedReq hits 525system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222733 # number of InvalidateReq hits 526system.cpu0.l2cache.InvalidateReq_hits::total 222733 # number of InvalidateReq hits 527system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 287369 # number of demand (read+write) hits 528system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155522 # number of demand (read+write) hits 529system.cpu0.l2cache.demand_hits::cpu0.inst 5011469 # number of demand (read+write) hits 530system.cpu0.l2cache.demand_hits::cpu0.data 3602022 # number of demand (read+write) hits 531system.cpu0.l2cache.demand_hits::total 9056382 # number of demand (read+write) hits 532system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 287369 # number of overall hits 533system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155522 # number of overall hits 534system.cpu0.l2cache.overall_hits::cpu0.inst 5011469 # number of overall hits 535system.cpu0.l2cache.overall_hits::cpu0.data 3602022 # number of overall hits 536system.cpu0.l2cache.overall_hits::total 9056382 # number of overall hits 537system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20057 # number of ReadReq misses 538system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9858 # number of ReadReq misses 539system.cpu0.l2cache.ReadReq_misses::total 29915 # number of ReadReq misses 540system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137835 # number of UpgradeReq misses 541system.cpu0.l2cache.UpgradeReq_misses::total 137835 # number of UpgradeReq misses 542system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154814 # number of SCUpgradeReq misses 543system.cpu0.l2cache.SCUpgradeReq_misses::total 154814 # number of SCUpgradeReq misses 544system.cpu0.l2cache.ReadExReq_misses::cpu0.data 699738 # number of ReadExReq misses 545system.cpu0.l2cache.ReadExReq_misses::total 699738 # number of ReadExReq misses 546system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 498672 # number of ReadCleanReq misses 547system.cpu0.l2cache.ReadCleanReq_misses::total 498672 # number of ReadCleanReq misses 548system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1226274 # number of ReadSharedReq misses 549system.cpu0.l2cache.ReadSharedReq_misses::total 1226274 # number of ReadSharedReq misses 550system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601108 # number of InvalidateReq misses 551system.cpu0.l2cache.InvalidateReq_misses::total 601108 # number of InvalidateReq misses 552system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20057 # number of demand (read+write) misses 553system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9858 # number of demand (read+write) misses 554system.cpu0.l2cache.demand_misses::cpu0.inst 498672 # number of demand (read+write) misses 555system.cpu0.l2cache.demand_misses::cpu0.data 1926012 # number of demand (read+write) misses 556system.cpu0.l2cache.demand_misses::total 2454599 # number of demand (read+write) misses 557system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20057 # number of overall misses 558system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9858 # number of overall misses 559system.cpu0.l2cache.overall_misses::cpu0.inst 498672 # number of overall misses 560system.cpu0.l2cache.overall_misses::cpu0.data 1926012 # number of overall misses 561system.cpu0.l2cache.overall_misses::total 2454599 # number of overall misses 562system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 307426 # number of ReadReq accesses(hits+misses) 563system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165380 # number of ReadReq accesses(hits+misses) 564system.cpu0.l2cache.ReadReq_accesses::total 472806 # number of ReadReq accesses(hits+misses) 565system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4441046 # number of WritebackDirty accesses(hits+misses) 566system.cpu0.l2cache.WritebackDirty_accesses::total 4441046 # number of WritebackDirty accesses(hits+misses) 567system.cpu0.l2cache.WritebackClean_accesses::writebacks 7316094 # number of WritebackClean accesses(hits+misses) 568system.cpu0.l2cache.WritebackClean_accesses::total 7316094 # number of WritebackClean accesses(hits+misses) 569system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137835 # number of UpgradeReq accesses(hits+misses) 570system.cpu0.l2cache.UpgradeReq_accesses::total 137835 # number of UpgradeReq accesses(hits+misses) 571system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154814 # number of SCUpgradeReq accesses(hits+misses) 572system.cpu0.l2cache.SCUpgradeReq_accesses::total 154814 # number of SCUpgradeReq accesses(hits+misses) 573system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) 574system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) 575system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510141 # number of ReadCleanReq accesses(hits+misses) 576system.cpu0.l2cache.ReadCleanReq_accesses::total 5510141 # number of ReadCleanReq accesses(hits+misses) 577system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187736 # number of ReadSharedReq accesses(hits+misses) 578system.cpu0.l2cache.ReadSharedReq_accesses::total 4187736 # number of ReadSharedReq accesses(hits+misses) 579system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) 580system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) 581system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 307426 # number of demand (read+write) accesses 582system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165380 # number of demand (read+write) accesses 583system.cpu0.l2cache.demand_accesses::cpu0.inst 5510141 # number of demand (read+write) accesses 584system.cpu0.l2cache.demand_accesses::cpu0.data 5528034 # number of demand (read+write) accesses 585system.cpu0.l2cache.demand_accesses::total 11510981 # number of demand (read+write) accesses 586system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 307426 # number of overall (read+write) accesses 587system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165380 # number of overall (read+write) accesses 588system.cpu0.l2cache.overall_accesses::cpu0.inst 5510141 # number of overall (read+write) accesses 589system.cpu0.l2cache.overall_accesses::cpu0.data 5528034 # number of overall (read+write) accesses 590system.cpu0.l2cache.overall_accesses::total 11510981 # number of overall (read+write) accesses 591system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for ReadReq accesses 592system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059608 # miss rate for ReadReq accesses 593system.cpu0.l2cache.ReadReq_miss_rate::total 0.063271 # miss rate for ReadReq accesses 594system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 595system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 596system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 597system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 598system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.522076 # miss rate for ReadExReq accesses 599system.cpu0.l2cache.ReadExReq_miss_rate::total 0.522076 # miss rate for ReadExReq accesses 600system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090501 # miss rate for ReadCleanReq accesses 601system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090501 # miss rate for ReadCleanReq accesses 602system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292825 # miss rate for ReadSharedReq accesses 603system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292825 # miss rate for ReadSharedReq accesses 604system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729641 # miss rate for InvalidateReq accesses 605system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729641 # miss rate for InvalidateReq accesses 606system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for demand accesses 607system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059608 # miss rate for demand accesses 608system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090501 # miss rate for demand accesses 609system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.348408 # miss rate for demand accesses 610system.cpu0.l2cache.demand_miss_rate::total 0.213240 # miss rate for demand accesses 611system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for overall accesses 612system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059608 # miss rate for overall accesses 613system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090501 # miss rate for overall accesses 614system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.348408 # miss rate for overall accesses 615system.cpu0.l2cache.overall_miss_rate::total 0.213240 # miss rate for overall accesses 616system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 617system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 618system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 619system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 620system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 621system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 622system.cpu0.l2cache.writebacks::writebacks 1552940 # number of writebacks 623system.cpu0.l2cache.writebacks::total 1552940 # number of writebacks 624system.cpu0.toL2Bus.snoop_filter.tot_requests 24175638 # Total number of requests made to the snoop filter. 625system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12313629 # Number of requests hitting in the snoop filter with a single holder of the requested data. 626system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 627system.cpu0.toL2Bus.snoop_filter.tot_snoops 303605 # Total number of snoops made to the snoop filter. 628system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 303605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 629system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 630system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 631system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution 632system.cpu0.toL2Bus.trans_dist::ReadResp 10320494 # Transaction distribution 633system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution 634system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution 635system.cpu0.toL2Bus.trans_dist::WritebackDirty 4441046 # Transaction distribution 636system.cpu0.toL2Bus.trans_dist::WritebackClean 7317492 # Transaction distribution 637system.cpu0.toL2Bus.trans_dist::UpgradeReq 137835 # Transaction distribution 638system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154814 # Transaction distribution 639system.cpu0.toL2Bus.trans_dist::UpgradeResp 292649 # Transaction distribution 640system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution 641system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution 642system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510141 # Transaction distribution 643system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187736 # Transaction distribution 644system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution 645system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution 646system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616156 # Packet count per connected master and slave (bytes) 647system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19670562 # Packet count per connected master and slave (bytes) 648system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) 649system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) 650system.cpu0.toL2Bus.pkt_count::total 37379570 # Packet count per connected master and slave (bytes) 651system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705437460 # Cumulative packet size per connected master and slave (bytes) 652system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753923068 # Cumulative packet size per connected master and slave (bytes) 653system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) 654system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) 655system.cpu0.toL2Bus.pkt_size::total 1463731936 # Cumulative packet size per connected master and slave (bytes) 656system.cpu0.toL2Bus.snoops 4670427 # Total snoops (count) 657system.cpu0.toL2Bus.snoopTraffic 101174852 # Total snoop traffic (bytes) 658system.cpu0.toL2Bus.snoop_fanout::samples 29058250 # Request fanout histogram 659system.cpu0.toL2Bus.snoop_fanout::mean 0.019576 # Request fanout histogram 660system.cpu0.toL2Bus.snoop_fanout::stdev 0.138538 # Request fanout histogram 661system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 662system.cpu0.toL2Bus.snoop_fanout::0 28489407 98.04% 98.04% # Request fanout histogram 663system.cpu0.toL2Bus.snoop_fanout::1 568843 1.96% 100.00% # Request fanout histogram 664system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 665system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 666system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 667system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 668system.cpu0.toL2Bus.snoop_fanout::total 29058250 # Request fanout histogram 669system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 670system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 674system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 675system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 676system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 677system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 678system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 679system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 680system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 681system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 682system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 683system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 684system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 685system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 686system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 687system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 688system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 689system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 690system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 691system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 692system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 693system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 694system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 695system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 696system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 697system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 698system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 699system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 700system.cpu1.dtb.walker.walks 144363 # Table walker walks requested 701system.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors 702system.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency 703system.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency 704system.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency 705system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution 706system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution 707system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution 708system.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated 709system.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated 710system.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated 711system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst 712system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 713system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst 714system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst 715system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 716system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst 717system.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst 718system.cpu1.dtb.inst_hits 0 # ITB inst hits 719system.cpu1.dtb.inst_misses 0 # ITB inst misses 720system.cpu1.dtb.read_hits 90656208 # DTB read hits 721system.cpu1.dtb.read_misses 111973 # DTB read misses 722system.cpu1.dtb.write_hits 81688076 # DTB write hits 723system.cpu1.dtb.write_misses 32390 # DTB write misses 724system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 725system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 726system.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 727system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 728system.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB 729system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 730system.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch 731system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 732system.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions 733system.cpu1.dtb.read_accesses 90768181 # DTB read accesses 734system.cpu1.dtb.write_accesses 81720466 # DTB write accesses 735system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 736system.cpu1.dtb.hits 172344284 # DTB hits 737system.cpu1.dtb.misses 144363 # DTB misses 738system.cpu1.dtb.accesses 172488647 # DTB accesses 739system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 740system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 741system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 742system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 743system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 744system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 748system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 749system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 750system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 751system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 752system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 753system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 754system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 755system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 756system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 757system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 758system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 759system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 760system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 761system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 762system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 763system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 764system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 765system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 766system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 767system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 768system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 769system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 770system.cpu1.itb.walker.walks 61351 # Table walker walks requested 771system.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors 772system.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency 773system.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency 774system.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency 775system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution 776system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution 777system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution 778system.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated 779system.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated 780system.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated 781system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 782system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst 783system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst 784system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 785system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst 786system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst 787system.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst 788system.cpu1.itb.inst_hits 480862179 # ITB inst hits 789system.cpu1.itb.inst_misses 61351 # ITB inst misses 790system.cpu1.itb.read_hits 0 # DTB read hits 791system.cpu1.itb.read_misses 0 # DTB read misses 792system.cpu1.itb.write_hits 0 # DTB write hits 793system.cpu1.itb.write_misses 0 # DTB write misses 794system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 795system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 796system.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 797system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 798system.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB 799system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 800system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 801system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 802system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 803system.cpu1.itb.read_accesses 0 # DTB read accesses 804system.cpu1.itb.write_accesses 0 # DTB write accesses 805system.cpu1.itb.inst_accesses 480923530 # ITB inst accesses 806system.cpu1.itb.hits 480862179 # DTB hits 807system.cpu1.itb.misses 61351 # DTB misses 808system.cpu1.itb.accesses 480923530 # DTB accesses 809system.cpu1.numPwrStateTransitions 12248 # Number of power state transitions 810system.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state 811system.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state 812system.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state 813system.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state 814system.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state 815system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state 816system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state 817system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 818system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state 819system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 820system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 821system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state 822system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 823system.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state 824system.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state 825system.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states 826system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states 827system.cpu1.numCycles 94592569622 # number of cpu cycles simulated 828system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 829system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 830system.cpu1.kern.inst.arm 0 # number of arm instructions executed 831system.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed 832system.cpu1.committedInsts 480611396 # Number of instructions committed 833system.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed 834system.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses 835system.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses 836system.cpu1.num_func_calls 28363152 # number of times a function call or return occured 837system.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls 838system.cpu1.num_int_insts 519092247 # number of integer instructions 839system.cpu1.num_fp_insts 374666 # number of float instructions 840system.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read 841system.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written 842system.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read 843system.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written 844system.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read 845system.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written 846system.cpu1.num_mem_refs 172465256 # number of memory refs 847system.cpu1.num_load_insts 90755131 # Number of load instructions 848system.cpu1.num_store_insts 81710125 # Number of store instructions 849system.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles 850system.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles 851system.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles 852system.cpu1.idle_fraction 0.994017 # Percentage of idle cycles 853system.cpu1.Branches 107067845 # Number of branches fetched 854system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 855system.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction 856system.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction 857system.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction 858system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 859system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 860system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 861system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction	335system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 336system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 337system.cpu0.op_class::total 584096590 # Class of executed instruction 338system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 339system.cpu0.dcache.tags.replacements 6248914 # number of replacements 340system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use 341system.cpu0.dcache.tags.total_refs 171607957 # Total number of references to valid blocks. 342system.cpu0.dcache.tags.sampled_refs 6249426 # Sample count of references to valid blocks. 343system.cpu0.dcache.tags.avg_refs 27.459795 # Average number of references to valid blocks. 344system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 345system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor 346system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy 347system.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy 348system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 349system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 350system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 351system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 352system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 353system.cpu0.dcache.tags.tag_accesses 362271539 # Number of tag accesses 354system.cpu0.dcache.tags.data_accesses 362271539 # Number of data accesses 355system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 356system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits 357system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits 358system.cpu0.dcache.WriteReq_hits::cpu0.data 80674063 # number of WriteReq hits 359system.cpu0.dcache.WriteReq_hits::total 80674063 # number of WriteReq hits 360system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits 361system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits 362system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261006 # number of WriteLineReq hits 363system.cpu0.dcache.WriteLineReq_hits::total 261006 # number of WriteLineReq hits 364system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087975 # number of LoadLockedReq hits 365system.cpu0.dcache.LoadLockedReq_hits::total 2087975 # number of LoadLockedReq hits 366system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051823 # number of StoreCondReq hits 367system.cpu0.dcache.StoreCondReq_hits::total 2051823 # number of StoreCondReq hits 368system.cpu0.dcache.demand_hits::cpu0.data 166959241 # number of demand (read+write) hits 369system.cpu0.dcache.demand_hits::total 166959241 # number of demand (read+write) hits 370system.cpu0.dcache.overall_hits::cpu0.data 167175510 # number of overall hits 371system.cpu0.dcache.overall_hits::total 167175510 # number of overall hits 372system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses 373system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses 374system.cpu0.dcache.WriteReq_misses::cpu0.data 1477781 # number of WriteReq misses 375system.cpu0.dcache.WriteReq_misses::total 1477781 # number of WriteReq misses 376system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses 377system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses 378system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824193 # number of WriteLineReq misses 379system.cpu0.dcache.WriteLineReq_misses::total 824193 # number of WriteLineReq misses 380system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119751 # number of LoadLockedReq misses 381system.cpu0.dcache.LoadLockedReq_misses::total 119751 # number of LoadLockedReq misses 382system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154814 # number of StoreCondReq misses 383system.cpu0.dcache.StoreCondReq_misses::total 154814 # number of StoreCondReq misses 384system.cpu0.dcache.demand_misses::cpu0.data 5600396 # number of demand (read+write) misses 385system.cpu0.dcache.demand_misses::total 5600396 # number of demand (read+write) misses 386system.cpu0.dcache.overall_misses::cpu0.data 6369959 # number of overall misses 387system.cpu0.dcache.overall_misses::total 6369959 # number of overall misses 388system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) 389system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) 390system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) 391system.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses) 392system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses) 393system.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses) 394system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses) 395system.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses) 396system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses) 397system.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses) 398system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses) 399system.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses) 400system.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses 401system.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses 402system.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses 403system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses 404system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses 405system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses 406system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017988 # miss rate for WriteReq accesses 407system.cpu0.dcache.WriteReq_miss_rate::total 0.017988 # miss rate for WriteReq accesses 408system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses 409system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses 410system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759486 # miss rate for WriteLineReq accesses 411system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759486 # miss rate for WriteLineReq accesses 412system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054242 # miss rate for LoadLockedReq accesses 413system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054242 # miss rate for LoadLockedReq accesses 414system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070158 # miss rate for StoreCondReq accesses 415system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070158 # miss rate for StoreCondReq accesses 416system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032455 # miss rate for demand accesses 417system.cpu0.dcache.demand_miss_rate::total 0.032455 # miss rate for demand accesses 418system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036705 # miss rate for overall accesses 419system.cpu0.dcache.overall_miss_rate::total 0.036705 # miss rate for overall accesses 420system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu0.dcache.writebacks::writebacks 6248914 # number of writebacks 427system.cpu0.dcache.writebacks::total 6248914 # number of writebacks 428system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 429system.cpu0.icache.tags.replacements 5509624 # number of replacements 430system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use 431system.cpu0.icache.tags.total_refs 491225330 # Total number of references to valid blocks. 432system.cpu0.icache.tags.sampled_refs 5510136 # Sample count of references to valid blocks. 433system.cpu0.icache.tags.avg_refs 89.149402 # Average number of references to valid blocks. 434system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. 435system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor 436system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 437system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 438system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 439system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id 440system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 441system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id 442system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 443system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 444system.cpu0.icache.tags.tag_accesses 998981083 # Number of tag accesses 445system.cpu0.icache.tags.data_accesses 998981083 # Number of data accesses 446system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 447system.cpu0.icache.ReadReq_hits::cpu0.inst 491225330 # number of ReadReq hits 448system.cpu0.icache.ReadReq_hits::total 491225330 # number of ReadReq hits 449system.cpu0.icache.demand_hits::cpu0.inst 491225330 # number of demand (read+write) hits 450system.cpu0.icache.demand_hits::total 491225330 # number of demand (read+write) hits 451system.cpu0.icache.overall_hits::cpu0.inst 491225330 # number of overall hits 452system.cpu0.icache.overall_hits::total 491225330 # number of overall hits 453system.cpu0.icache.ReadReq_misses::cpu0.inst 5510141 # number of ReadReq misses 454system.cpu0.icache.ReadReq_misses::total 5510141 # number of ReadReq misses 455system.cpu0.icache.demand_misses::cpu0.inst 5510141 # number of demand (read+write) misses 456system.cpu0.icache.demand_misses::total 5510141 # number of demand (read+write) misses 457system.cpu0.icache.overall_misses::cpu0.inst 5510141 # number of overall misses 458system.cpu0.icache.overall_misses::total 5510141 # number of overall misses 459system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) 460system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) 461system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses 462system.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses 463system.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses 464system.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses 465system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses 466system.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses 467system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses 468system.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses 469system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses 470system.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses 471system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 472system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 473system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 474system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 475system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 476system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 477system.cpu0.icache.writebacks::writebacks 5509624 # number of writebacks 478system.cpu0.icache.writebacks::total 5509624 # number of writebacks 479system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 480system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 481system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 482system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 483system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 484system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 485system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 486system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 487system.cpu0.l2cache.tags.replacements 2567589 # number of replacements 488system.cpu0.l2cache.tags.tagsinuse 15706.944975 # Cycle average of tags in use 489system.cpu0.l2cache.tags.total_refs 9429067 # Total number of references to valid blocks. 490system.cpu0.l2cache.tags.sampled_refs 2583246 # Sample count of references to valid blocks. 491system.cpu0.l2cache.tags.avg_refs 3.650085 # Average number of references to valid blocks. 492system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 493system.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594 # Average occupied blocks per requestor 494system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 27.364617 # Average occupied blocks per requestor 495system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.639763 # Average occupied blocks per requestor 496system.cpu0.l2cache.tags.occ_percent::writebacks 0.955624 # Average percentage of cache occupancy 497system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001670 # Average percentage of cache occupancy 498system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001382 # Average percentage of cache occupancy 499system.cpu0.l2cache.tags.occ_percent::total 0.958676 # Average percentage of cache occupancy 500system.cpu0.l2cache.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id 501system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15600 # Occupied blocks per task id 502system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 503system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 41 # Occupied blocks per task id 504system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 505system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 506system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 421 # Occupied blocks per task id 507system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2091 # Occupied blocks per task id 508system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5339 # Occupied blocks per task id 509system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5411 # Occupied blocks per task id 510system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2338 # Occupied blocks per task id 511system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id 512system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.952148 # Percentage of cache occupancy per task id 513system.cpu0.l2cache.tags.tag_accesses 401859473 # Number of tag accesses 514system.cpu0.l2cache.tags.data_accesses 401859473 # Number of data accesses 515system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 516system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 287369 # number of ReadReq hits 517system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155522 # number of ReadReq hits 518system.cpu0.l2cache.ReadReq_hits::total 442891 # number of ReadReq hits 519system.cpu0.l2cache.WritebackDirty_hits::writebacks 4441046 # number of WritebackDirty hits 520system.cpu0.l2cache.WritebackDirty_hits::total 4441046 # number of WritebackDirty hits 521system.cpu0.l2cache.WritebackClean_hits::writebacks 7316094 # number of WritebackClean hits 522system.cpu0.l2cache.WritebackClean_hits::total 7316094 # number of WritebackClean hits 523system.cpu0.l2cache.ReadExReq_hits::cpu0.data 640560 # number of ReadExReq hits 524system.cpu0.l2cache.ReadExReq_hits::total 640560 # number of ReadExReq hits 525system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5011469 # number of ReadCleanReq hits 526system.cpu0.l2cache.ReadCleanReq_hits::total 5011469 # number of ReadCleanReq hits 527system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2961462 # number of ReadSharedReq hits 528system.cpu0.l2cache.ReadSharedReq_hits::total 2961462 # number of ReadSharedReq hits 529system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222733 # number of InvalidateReq hits 530system.cpu0.l2cache.InvalidateReq_hits::total 222733 # number of InvalidateReq hits 531system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 287369 # number of demand (read+write) hits 532system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155522 # number of demand (read+write) hits 533system.cpu0.l2cache.demand_hits::cpu0.inst 5011469 # number of demand (read+write) hits 534system.cpu0.l2cache.demand_hits::cpu0.data 3602022 # number of demand (read+write) hits 535system.cpu0.l2cache.demand_hits::total 9056382 # number of demand (read+write) hits 536system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 287369 # number of overall hits 537system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155522 # number of overall hits 538system.cpu0.l2cache.overall_hits::cpu0.inst 5011469 # number of overall hits 539system.cpu0.l2cache.overall_hits::cpu0.data 3602022 # number of overall hits 540system.cpu0.l2cache.overall_hits::total 9056382 # number of overall hits 541system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20057 # number of ReadReq misses 542system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9858 # number of ReadReq misses 543system.cpu0.l2cache.ReadReq_misses::total 29915 # number of ReadReq misses 544system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137835 # number of UpgradeReq misses 545system.cpu0.l2cache.UpgradeReq_misses::total 137835 # number of UpgradeReq misses 546system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154814 # number of SCUpgradeReq misses 547system.cpu0.l2cache.SCUpgradeReq_misses::total 154814 # number of SCUpgradeReq misses 548system.cpu0.l2cache.ReadExReq_misses::cpu0.data 699738 # number of ReadExReq misses 549system.cpu0.l2cache.ReadExReq_misses::total 699738 # number of ReadExReq misses 550system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 498672 # number of ReadCleanReq misses 551system.cpu0.l2cache.ReadCleanReq_misses::total 498672 # number of ReadCleanReq misses 552system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1226274 # number of ReadSharedReq misses 553system.cpu0.l2cache.ReadSharedReq_misses::total 1226274 # number of ReadSharedReq misses 554system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601108 # number of InvalidateReq misses 555system.cpu0.l2cache.InvalidateReq_misses::total 601108 # number of InvalidateReq misses 556system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20057 # number of demand (read+write) misses 557system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9858 # number of demand (read+write) misses 558system.cpu0.l2cache.demand_misses::cpu0.inst 498672 # number of demand (read+write) misses 559system.cpu0.l2cache.demand_misses::cpu0.data 1926012 # number of demand (read+write) misses 560system.cpu0.l2cache.demand_misses::total 2454599 # number of demand (read+write) misses 561system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20057 # number of overall misses 562system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9858 # number of overall misses 563system.cpu0.l2cache.overall_misses::cpu0.inst 498672 # number of overall misses 564system.cpu0.l2cache.overall_misses::cpu0.data 1926012 # number of overall misses 565system.cpu0.l2cache.overall_misses::total 2454599 # number of overall misses 566system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 307426 # number of ReadReq accesses(hits+misses) 567system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165380 # number of ReadReq accesses(hits+misses) 568system.cpu0.l2cache.ReadReq_accesses::total 472806 # number of ReadReq accesses(hits+misses) 569system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4441046 # number of WritebackDirty accesses(hits+misses) 570system.cpu0.l2cache.WritebackDirty_accesses::total 4441046 # number of WritebackDirty accesses(hits+misses) 571system.cpu0.l2cache.WritebackClean_accesses::writebacks 7316094 # number of WritebackClean accesses(hits+misses) 572system.cpu0.l2cache.WritebackClean_accesses::total 7316094 # number of WritebackClean accesses(hits+misses) 573system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137835 # number of UpgradeReq accesses(hits+misses) 574system.cpu0.l2cache.UpgradeReq_accesses::total 137835 # number of UpgradeReq accesses(hits+misses) 575system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154814 # number of SCUpgradeReq accesses(hits+misses) 576system.cpu0.l2cache.SCUpgradeReq_accesses::total 154814 # number of SCUpgradeReq accesses(hits+misses) 577system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) 578system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) 579system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510141 # number of ReadCleanReq accesses(hits+misses) 580system.cpu0.l2cache.ReadCleanReq_accesses::total 5510141 # number of ReadCleanReq accesses(hits+misses) 581system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187736 # number of ReadSharedReq accesses(hits+misses) 582system.cpu0.l2cache.ReadSharedReq_accesses::total 4187736 # number of ReadSharedReq accesses(hits+misses) 583system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) 584system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) 585system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 307426 # number of demand (read+write) accesses 586system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165380 # number of demand (read+write) accesses 587system.cpu0.l2cache.demand_accesses::cpu0.inst 5510141 # number of demand (read+write) accesses 588system.cpu0.l2cache.demand_accesses::cpu0.data 5528034 # number of demand (read+write) accesses 589system.cpu0.l2cache.demand_accesses::total 11510981 # number of demand (read+write) accesses 590system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 307426 # number of overall (read+write) accesses 591system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165380 # number of overall (read+write) accesses 592system.cpu0.l2cache.overall_accesses::cpu0.inst 5510141 # number of overall (read+write) accesses 593system.cpu0.l2cache.overall_accesses::cpu0.data 5528034 # number of overall (read+write) accesses 594system.cpu0.l2cache.overall_accesses::total 11510981 # number of overall (read+write) accesses 595system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for ReadReq accesses 596system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059608 # miss rate for ReadReq accesses 597system.cpu0.l2cache.ReadReq_miss_rate::total 0.063271 # miss rate for ReadReq accesses 598system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 599system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 600system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 601system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 602system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.522076 # miss rate for ReadExReq accesses 603system.cpu0.l2cache.ReadExReq_miss_rate::total 0.522076 # miss rate for ReadExReq accesses 604system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090501 # miss rate for ReadCleanReq accesses 605system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090501 # miss rate for ReadCleanReq accesses 606system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292825 # miss rate for ReadSharedReq accesses 607system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292825 # miss rate for ReadSharedReq accesses 608system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729641 # miss rate for InvalidateReq accesses 609system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729641 # miss rate for InvalidateReq accesses 610system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for demand accesses 611system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059608 # miss rate for demand accesses 612system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090501 # miss rate for demand accesses 613system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.348408 # miss rate for demand accesses 614system.cpu0.l2cache.demand_miss_rate::total 0.213240 # miss rate for demand accesses 615system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for overall accesses 616system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059608 # miss rate for overall accesses 617system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090501 # miss rate for overall accesses 618system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.348408 # miss rate for overall accesses 619system.cpu0.l2cache.overall_miss_rate::total 0.213240 # miss rate for overall accesses 620system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 621system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 622system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 623system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 624system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 625system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 626system.cpu0.l2cache.writebacks::writebacks 1552940 # number of writebacks 627system.cpu0.l2cache.writebacks::total 1552940 # number of writebacks 628system.cpu0.toL2Bus.snoop_filter.tot_requests 24175638 # Total number of requests made to the snoop filter. 629system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12313629 # Number of requests hitting in the snoop filter with a single holder of the requested data. 630system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 631system.cpu0.toL2Bus.snoop_filter.tot_snoops 303605 # Total number of snoops made to the snoop filter. 632system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 303605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 633system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 634system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 635system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution 636system.cpu0.toL2Bus.trans_dist::ReadResp 10320494 # Transaction distribution 637system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution 638system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution 639system.cpu0.toL2Bus.trans_dist::WritebackDirty 4441046 # Transaction distribution 640system.cpu0.toL2Bus.trans_dist::WritebackClean 7317492 # Transaction distribution 641system.cpu0.toL2Bus.trans_dist::UpgradeReq 137835 # Transaction distribution 642system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154814 # Transaction distribution 643system.cpu0.toL2Bus.trans_dist::UpgradeResp 292649 # Transaction distribution 644system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution 645system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution 646system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510141 # Transaction distribution 647system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187736 # Transaction distribution 648system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution 649system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution 650system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616156 # Packet count per connected master and slave (bytes) 651system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19670562 # Packet count per connected master and slave (bytes) 652system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) 653system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) 654system.cpu0.toL2Bus.pkt_count::total 37379570 # Packet count per connected master and slave (bytes) 655system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705437460 # Cumulative packet size per connected master and slave (bytes) 656system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753923068 # Cumulative packet size per connected master and slave (bytes) 657system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) 658system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) 659system.cpu0.toL2Bus.pkt_size::total 1463731936 # Cumulative packet size per connected master and slave (bytes) 660system.cpu0.toL2Bus.snoops 4670427 # Total snoops (count) 661system.cpu0.toL2Bus.snoopTraffic 101174852 # Total snoop traffic (bytes) 662system.cpu0.toL2Bus.snoop_fanout::samples 29058250 # Request fanout histogram 663system.cpu0.toL2Bus.snoop_fanout::mean 0.019576 # Request fanout histogram 664system.cpu0.toL2Bus.snoop_fanout::stdev 0.138538 # Request fanout histogram 665system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 666system.cpu0.toL2Bus.snoop_fanout::0 28489407 98.04% 98.04% # Request fanout histogram 667system.cpu0.toL2Bus.snoop_fanout::1 568843 1.96% 100.00% # Request fanout histogram 668system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 669system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 670system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 671system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 672system.cpu0.toL2Bus.snoop_fanout::total 29058250 # Request fanout histogram 673system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 674system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 675system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 676system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 677system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 678system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 679system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 680system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 681system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 682system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 683system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 684system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 685system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 686system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 687system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 688system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 689system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 690system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 691system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 692system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 693system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 694system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 695system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 696system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 697system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 698system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 699system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 700system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 701system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 702system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 703system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 704system.cpu1.dtb.walker.walks 144363 # Table walker walks requested 705system.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors 706system.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency 707system.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency 708system.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency 709system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution 710system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution 711system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution 712system.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated 713system.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated 714system.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated 715system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst 716system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 717system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst 718system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst 719system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 720system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst 721system.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst 722system.cpu1.dtb.inst_hits 0 # ITB inst hits 723system.cpu1.dtb.inst_misses 0 # ITB inst misses 724system.cpu1.dtb.read_hits 90656208 # DTB read hits 725system.cpu1.dtb.read_misses 111973 # DTB read misses 726system.cpu1.dtb.write_hits 81688076 # DTB write hits 727system.cpu1.dtb.write_misses 32390 # DTB write misses 728system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 729system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 730system.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 731system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 732system.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB 733system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 734system.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch 735system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 736system.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions 737system.cpu1.dtb.read_accesses 90768181 # DTB read accesses 738system.cpu1.dtb.write_accesses 81720466 # DTB write accesses 739system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 740system.cpu1.dtb.hits 172344284 # DTB hits 741system.cpu1.dtb.misses 144363 # DTB misses 742system.cpu1.dtb.accesses 172488647 # DTB accesses 743system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 744system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 751system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 752system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 753system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 754system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 755system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 756system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 757system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 758system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 759system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 760system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 761system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 762system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 763system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 764system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 765system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 766system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 767system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 768system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 769system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 770system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 771system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 772system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 773system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 774system.cpu1.itb.walker.walks 61351 # Table walker walks requested 775system.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors 776system.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency 777system.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency 778system.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency 779system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution 780system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution 781system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution 782system.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated 783system.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated 784system.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated 785system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 786system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst 787system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst 788system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 789system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst 790system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst 791system.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst 792system.cpu1.itb.inst_hits 480862179 # ITB inst hits 793system.cpu1.itb.inst_misses 61351 # ITB inst misses 794system.cpu1.itb.read_hits 0 # DTB read hits 795system.cpu1.itb.read_misses 0 # DTB read misses 796system.cpu1.itb.write_hits 0 # DTB write hits 797system.cpu1.itb.write_misses 0 # DTB write misses 798system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 799system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 800system.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID 801system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 802system.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB 803system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 804system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 805system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 806system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 807system.cpu1.itb.read_accesses 0 # DTB read accesses 808system.cpu1.itb.write_accesses 0 # DTB write accesses 809system.cpu1.itb.inst_accesses 480923530 # ITB inst accesses 810system.cpu1.itb.hits 480862179 # DTB hits 811system.cpu1.itb.misses 61351 # DTB misses 812system.cpu1.itb.accesses 480923530 # DTB accesses 813system.cpu1.numPwrStateTransitions 12248 # Number of power state transitions 814system.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state 815system.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state 816system.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state 817system.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state 818system.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state 819system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state 820system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state 821system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 822system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state 823system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 824system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state 825system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state 826system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 827system.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state 828system.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state 829system.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states 830system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states 831system.cpu1.numCycles 94592569622 # number of cpu cycles simulated 832system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 833system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 834system.cpu1.kern.inst.arm 0 # number of arm instructions executed 835system.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed 836system.cpu1.committedInsts 480611396 # Number of instructions committed 837system.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed 838system.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses 839system.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses 840system.cpu1.num_func_calls 28363152 # number of times a function call or return occured 841system.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls 842system.cpu1.num_int_insts 519092247 # number of integer instructions 843system.cpu1.num_fp_insts 374666 # number of float instructions 844system.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read 845system.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written 846system.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read 847system.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written 848system.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read 849system.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written 850system.cpu1.num_mem_refs 172465256 # number of memory refs 851system.cpu1.num_load_insts 90755131 # Number of load instructions 852system.cpu1.num_store_insts 81710125 # Number of store instructions 853system.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles 854system.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles 855system.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles 856system.cpu1.idle_fraction 0.994017 # Percentage of idle cycles 857system.cpu1.Branches 107067845 # Number of branches fetched 858system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 859system.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction 860system.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction 861system.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction 862system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction 863system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction 864system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction 865system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
	866system.cpu1.op_class::FloatMultAcc 0 0.00% 69.52% # Class of executed instruction
862system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction	867system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
	868system.cpu1.op_class::FloatMisc 36628 0.01% 69.52% # Class of executed instruction
863system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 864system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 865system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 866system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 867system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 868system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 869system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 870system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 871system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 872system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 873system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 874system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 875system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 876system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 877system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 878system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 879system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction	869system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction 870system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction 871system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction 872system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction 873system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction 874system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction 875system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction 876system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction 877system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction 878system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction 879system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction 880system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction 881system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction 882system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction 883system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction 884system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction 885system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
880system.cpu1.op_class::SimdFloatMisc 36628 0.01% 69.52% # Class of executed instruction	886system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.52% # Class of executed instruction
881system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 882system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 883system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction	887system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction 888system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction 889system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
884system.cpu1.op_class::MemRead 90755131 16.04% 85.56% # Class of executed instruction 885system.cpu1.op_class::MemWrite 81710125 14.44% 100.00% # Class of executed instruction	890system.cpu1.op_class::MemRead 90705162 16.03% 85.55% # Class of executed instruction 891system.cpu1.op_class::MemWrite 81422056 14.39% 99.94% # Class of executed instruction 892system.cpu1.op_class::FloatMemRead 49969 0.01% 99.95% # Class of executed instruction 893system.cpu1.op_class::FloatMemWrite 288069 0.05% 100.00% # Class of executed instruction
886system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 887system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 888system.cpu1.op_class::total 565908654 # Class of executed instruction 889system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 890system.cpu1.dcache.tags.replacements 5970884 # number of replacements 891system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use 892system.cpu1.dcache.tags.total_refs 166384448 # Total number of references to valid blocks. 893system.cpu1.dcache.tags.sampled_refs 5971395 # Sample count of references to valid blocks. 894system.cpu1.dcache.tags.avg_refs 27.863581 # Average number of references to valid blocks. 895system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. 896system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor 897system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy 898system.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy 899system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 900system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 901system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id 902system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 903system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 904system.cpu1.dcache.tags.tag_accesses 350957211 # Number of tag accesses 905system.cpu1.dcache.tags.data_accesses 350957211 # Number of data accesses 906system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 907system.cpu1.dcache.ReadReq_hits::cpu1.data 84198598 # number of ReadReq hits 908system.cpu1.dcache.ReadReq_hits::total 84198598 # number of ReadReq hits 909system.cpu1.dcache.WriteReq_hits::cpu1.data 77531561 # number of WriteReq hits 910system.cpu1.dcache.WriteReq_hits::total 77531561 # number of WriteReq hits 911system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits 912system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits 913system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64886 # number of WriteLineReq hits 914system.cpu1.dcache.WriteLineReq_hits::total 64886 # number of WriteLineReq hits 915system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055500 # number of LoadLockedReq hits 916system.cpu1.dcache.LoadLockedReq_hits::total 2055500 # number of LoadLockedReq hits 917system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044725 # number of StoreCondReq hits 918system.cpu1.dcache.StoreCondReq_hits::total 2044725 # number of StoreCondReq hits 919system.cpu1.dcache.demand_hits::cpu1.data 161795045 # number of demand (read+write) hits 920system.cpu1.dcache.demand_hits::total 161795045 # number of demand (read+write) hits 921system.cpu1.dcache.overall_hits::cpu1.data 161982308 # number of overall hits 922system.cpu1.dcache.overall_hits::total 161982308 # number of overall hits 923system.cpu1.dcache.ReadReq_misses::cpu1.data 3367290 # number of ReadReq misses 924system.cpu1.dcache.ReadReq_misses::total 3367290 # number of ReadReq misses 925system.cpu1.dcache.WriteReq_misses::cpu1.data 1466124 # number of WriteReq misses 926system.cpu1.dcache.WriteReq_misses::total 1466124 # number of WriteReq misses 927system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses 928system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses 929system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433871 # number of WriteLineReq misses 930system.cpu1.dcache.WriteLineReq_misses::total 433871 # number of WriteLineReq misses 931system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147105 # number of LoadLockedReq misses 932system.cpu1.dcache.LoadLockedReq_misses::total 147105 # number of LoadLockedReq misses 933system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156674 # number of StoreCondReq misses 934system.cpu1.dcache.StoreCondReq_misses::total 156674 # number of StoreCondReq misses 935system.cpu1.dcache.demand_misses::cpu1.data 5267285 # number of demand (read+write) misses 936system.cpu1.dcache.demand_misses::total 5267285 # number of demand (read+write) misses 937system.cpu1.dcache.overall_misses::cpu1.data 6060908 # number of overall misses 938system.cpu1.dcache.overall_misses::total 6060908 # number of overall misses 939system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) 940system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) 941system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) 942system.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses) 943system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses) 944system.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses) 945system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses) 946system.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses) 947system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses) 948system.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses) 949system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses) 950system.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses) 951system.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses 952system.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses 953system.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses 954system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses 955system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses 956system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses 957system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018559 # miss rate for WriteReq accesses 958system.cpu1.dcache.WriteReq_miss_rate::total 0.018559 # miss rate for WriteReq accesses 959system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses 960system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses 961system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869905 # miss rate for WriteLineReq accesses 962system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869905 # miss rate for WriteLineReq accesses 963system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066787 # miss rate for LoadLockedReq accesses 964system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066787 # miss rate for LoadLockedReq accesses 965system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071170 # miss rate for StoreCondReq accesses 966system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071170 # miss rate for StoreCondReq accesses 967system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031529 # miss rate for demand accesses 968system.cpu1.dcache.demand_miss_rate::total 0.031529 # miss rate for demand accesses 969system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036068 # miss rate for overall accesses 970system.cpu1.dcache.overall_miss_rate::total 0.036068 # miss rate for overall accesses 971system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 972system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 973system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 974system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 975system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 976system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 977system.cpu1.dcache.writebacks::writebacks 5970884 # number of writebacks 978system.cpu1.dcache.writebacks::total 5970884 # number of writebacks 979system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 980system.cpu1.icache.tags.replacements 4768482 # number of replacements 981system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use 982system.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks. 983system.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks. 984system.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks. 985system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. 986system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor 987system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy 988system.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy 989system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 990system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 991system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 992system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id 993system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 994system.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses 995system.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses 996system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 997system.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits 998system.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits 999system.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits 1000system.cpu1.icache.demand_hits::total 476148096 # number of demand (read+write) hits 1001system.cpu1.icache.overall_hits::cpu1.inst 476148096 # number of overall hits 1002system.cpu1.icache.overall_hits::total 476148096 # number of overall hits 1003system.cpu1.icache.ReadReq_misses::cpu1.inst 4768994 # number of ReadReq misses 1004system.cpu1.icache.ReadReq_misses::total 4768994 # number of ReadReq misses 1005system.cpu1.icache.demand_misses::cpu1.inst 4768994 # number of demand (read+write) misses 1006system.cpu1.icache.demand_misses::total 4768994 # number of demand (read+write) misses 1007system.cpu1.icache.overall_misses::cpu1.inst 4768994 # number of overall misses 1008system.cpu1.icache.overall_misses::total 4768994 # number of overall misses 1009system.cpu1.icache.ReadReq_accesses::cpu1.inst 480917090 # number of ReadReq accesses(hits+misses) 1010system.cpu1.icache.ReadReq_accesses::total 480917090 # number of ReadReq accesses(hits+misses) 1011system.cpu1.icache.demand_accesses::cpu1.inst 480917090 # number of demand (read+write) accesses 1012system.cpu1.icache.demand_accesses::total 480917090 # number of demand (read+write) accesses 1013system.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses 1014system.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses 1015system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses 1016system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses 1017system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses 1018system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses 1019system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses 1020system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses 1021system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1022system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1023system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1024system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1025system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1026system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1027system.cpu1.icache.writebacks::writebacks 4768482 # number of writebacks 1028system.cpu1.icache.writebacks::total 4768482 # number of writebacks 1029system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1030system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1031system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 1032system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1033system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1034system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1035system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 1036system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1037system.cpu1.l2cache.tags.replacements 2174770 # number of replacements 1038system.cpu1.l2cache.tags.tagsinuse 13105.960937 # Cycle average of tags in use 1039system.cpu1.l2cache.tags.total_refs 8815603 # Total number of references to valid blocks. 1040system.cpu1.l2cache.tags.sampled_refs 2190453 # Sample count of references to valid blocks. 1041system.cpu1.l2cache.tags.avg_refs 4.024557 # Average number of references to valid blocks. 1042system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1043system.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777 # Average occupied blocks per requestor 1044system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.863128 # Average occupied blocks per requestor 1045system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.242032 # Average occupied blocks per requestor 1046system.cpu1.l2cache.tags.occ_percent::writebacks 0.797660 # Average percentage of cache occupancy 1047system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001334 # Average percentage of cache occupancy 1048system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000930 # Average percentage of cache occupancy 1049system.cpu1.l2cache.tags.occ_percent::total 0.799924 # Average percentage of cache occupancy 1050system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id 1051system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15593 # Occupied blocks per task id 1052system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 57 # Occupied blocks per task id 1053system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 1054system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 1055system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id 1056system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2414 # Occupied blocks per task id 1057system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id 1058system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3564 # Occupied blocks per task id 1059system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1751 # Occupied blocks per task id 1060system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id 1061system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 1062system.cpu1.l2cache.tags.tag_accesses 369059783 # Number of tag accesses 1063system.cpu1.l2cache.tags.data_accesses 369059783 # Number of data accesses 1064system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1065system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 338101 # number of ReadReq hits 1066system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153667 # number of ReadReq hits 1067system.cpu1.l2cache.ReadReq_hits::total 491768 # number of ReadReq hits 1068system.cpu1.l2cache.WritebackDirty_hits::writebacks 4061526 # number of WritebackDirty hits 1069system.cpu1.l2cache.WritebackDirty_hits::total 4061526 # number of WritebackDirty hits 1070system.cpu1.l2cache.WritebackClean_hits::writebacks 6677473 # number of WritebackClean hits 1071system.cpu1.l2cache.WritebackClean_hits::total 6677473 # number of WritebackClean hits 1072system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614785 # number of ReadExReq hits 1073system.cpu1.l2cache.ReadExReq_hits::total 614785 # number of ReadExReq hits 1074system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4308825 # number of ReadCleanReq hits 1075system.cpu1.l2cache.ReadCleanReq_hits::total 4308825 # number of ReadCleanReq hits 1076system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3093892 # number of ReadSharedReq hits 1077system.cpu1.l2cache.ReadSharedReq_hits::total 3093892 # number of ReadSharedReq hits 1078system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164960 # number of InvalidateReq hits 1079system.cpu1.l2cache.InvalidateReq_hits::total 164960 # number of InvalidateReq hits 1080system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 338101 # number of demand (read+write) hits 1081system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153667 # number of demand (read+write) hits 1082system.cpu1.l2cache.demand_hits::cpu1.inst 4308825 # number of demand (read+write) hits 1083system.cpu1.l2cache.demand_hits::cpu1.data 3708677 # number of demand (read+write) hits 1084system.cpu1.l2cache.demand_hits::total 8509270 # number of demand (read+write) hits 1085system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 338101 # number of overall hits 1086system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153667 # number of overall hits 1087system.cpu1.l2cache.overall_hits::cpu1.inst 4308825 # number of overall hits 1088system.cpu1.l2cache.overall_hits::cpu1.data 3708677 # number of overall hits 1089system.cpu1.l2cache.overall_hits::total 8509270 # number of overall hits 1090system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22355 # number of ReadReq misses 1091system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10972 # number of ReadReq misses 1092system.cpu1.l2cache.ReadReq_misses::total 33327 # number of ReadReq misses 1093system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145242 # number of UpgradeReq misses 1094system.cpu1.l2cache.UpgradeReq_misses::total 145242 # number of UpgradeReq misses 1095system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156674 # number of SCUpgradeReq misses 1096system.cpu1.l2cache.SCUpgradeReq_misses::total 156674 # number of SCUpgradeReq misses 1097system.cpu1.l2cache.ReadExReq_misses::cpu1.data 706301 # number of ReadExReq misses 1098system.cpu1.l2cache.ReadExReq_misses::total 706301 # number of ReadExReq misses 1099system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 460169 # number of ReadCleanReq misses 1100system.cpu1.l2cache.ReadCleanReq_misses::total 460169 # number of ReadCleanReq misses 1101system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1214126 # number of ReadSharedReq misses 1102system.cpu1.l2cache.ReadSharedReq_misses::total 1214126 # number of ReadSharedReq misses 1103system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268707 # number of InvalidateReq misses 1104system.cpu1.l2cache.InvalidateReq_misses::total 268707 # number of InvalidateReq misses 1105system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22355 # number of demand (read+write) misses 1106system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10972 # number of demand (read+write) misses 1107system.cpu1.l2cache.demand_misses::cpu1.inst 460169 # number of demand (read+write) misses 1108system.cpu1.l2cache.demand_misses::cpu1.data 1920427 # number of demand (read+write) misses 1109system.cpu1.l2cache.demand_misses::total 2413923 # number of demand (read+write) misses 1110system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22355 # number of overall misses 1111system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10972 # number of overall misses 1112system.cpu1.l2cache.overall_misses::cpu1.inst 460169 # number of overall misses 1113system.cpu1.l2cache.overall_misses::cpu1.data 1920427 # number of overall misses 1114system.cpu1.l2cache.overall_misses::total 2413923 # number of overall misses 1115system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360456 # number of ReadReq accesses(hits+misses) 1116system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164639 # number of ReadReq accesses(hits+misses) 1117system.cpu1.l2cache.ReadReq_accesses::total 525095 # number of ReadReq accesses(hits+misses) 1118system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4061526 # number of WritebackDirty accesses(hits+misses) 1119system.cpu1.l2cache.WritebackDirty_accesses::total 4061526 # number of WritebackDirty accesses(hits+misses) 1120system.cpu1.l2cache.WritebackClean_accesses::writebacks 6677473 # number of WritebackClean accesses(hits+misses) 1121system.cpu1.l2cache.WritebackClean_accesses::total 6677473 # number of WritebackClean accesses(hits+misses) 1122system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145242 # number of UpgradeReq accesses(hits+misses) 1123system.cpu1.l2cache.UpgradeReq_accesses::total 145242 # number of UpgradeReq accesses(hits+misses) 1124system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156674 # number of SCUpgradeReq accesses(hits+misses) 1125system.cpu1.l2cache.SCUpgradeReq_accesses::total 156674 # number of SCUpgradeReq accesses(hits+misses) 1126system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) 1127system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) 1128system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) 1129system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) 1130system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308018 # number of ReadSharedReq accesses(hits+misses) 1131system.cpu1.l2cache.ReadSharedReq_accesses::total 4308018 # number of ReadSharedReq accesses(hits+misses) 1132system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) 1133system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) 1134system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360456 # number of demand (read+write) accesses 1135system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164639 # number of demand (read+write) accesses 1136system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses 1137system.cpu1.l2cache.demand_accesses::cpu1.data 5629104 # number of demand (read+write) accesses 1138system.cpu1.l2cache.demand_accesses::total 10923193 # number of demand (read+write) accesses 1139system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360456 # number of overall (read+write) accesses 1140system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164639 # number of overall (read+write) accesses 1141system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses 1142system.cpu1.l2cache.overall_accesses::cpu1.data 5629104 # number of overall (read+write) accesses 1143system.cpu1.l2cache.overall_accesses::total 10923193 # number of overall (read+write) accesses 1144system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for ReadReq accesses 1145system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.066643 # miss rate for ReadReq accesses 1146system.cpu1.l2cache.ReadReq_miss_rate::total 0.063469 # miss rate for ReadReq accesses 1147system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1148system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1149system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1150system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1151system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534637 # miss rate for ReadExReq accesses 1152system.cpu1.l2cache.ReadExReq_miss_rate::total 0.534637 # miss rate for ReadExReq accesses 1153system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096492 # miss rate for ReadCleanReq accesses 1154system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096492 # miss rate for ReadCleanReq accesses 1155system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281829 # miss rate for ReadSharedReq accesses 1156system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281829 # miss rate for ReadSharedReq accesses 1157system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.619616 # miss rate for InvalidateReq accesses 1158system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.619616 # miss rate for InvalidateReq accesses 1159system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for demand accesses 1160system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.066643 # miss rate for demand accesses 1161system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096492 # miss rate for demand accesses 1162system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341160 # miss rate for demand accesses 1163system.cpu1.l2cache.demand_miss_rate::total 0.220991 # miss rate for demand accesses 1164system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for overall accesses 1165system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.066643 # miss rate for overall accesses 1166system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096492 # miss rate for overall accesses 1167system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341160 # miss rate for overall accesses 1168system.cpu1.l2cache.overall_miss_rate::total 0.220991 # miss rate for overall accesses 1169system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1170system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1171system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1172system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1173system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1174system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1175system.cpu1.l2cache.writebacks::writebacks 1197912 # number of writebacks 1176system.cpu1.l2cache.writebacks::total 1197912 # number of writebacks 1177system.cpu1.toL2Bus.snoop_filter.tot_requests 22146544 # Total number of requests made to the snoop filter. 1178system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314780 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1179system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1180system.cpu1.toL2Bus.snoop_filter.tot_snoops 285761 # Total number of snoops made to the snoop filter. 1181system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 285759 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1182system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1183system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1184system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution 1185system.cpu1.toL2Bus.trans_dist::ReadResp 9684673 # Transaction distribution 1186system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution 1187system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution 1188system.cpu1.toL2Bus.trans_dist::WritebackDirty 4061526 # Transaction distribution 1189system.cpu1.toL2Bus.trans_dist::WritebackClean 6677840 # Transaction distribution 1190system.cpu1.toL2Bus.trans_dist::UpgradeReq 145242 # Transaction distribution 1191system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156674 # Transaction distribution 1192system.cpu1.toL2Bus.trans_dist::UpgradeResp 301916 # Transaction distribution 1193system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution 1194system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution 1195system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution 1196system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308018 # Transaction distribution 1197system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution 1198system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution 1199system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) 1200system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18723008 # Packet count per connected master and slave (bytes) 1201system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) 1202system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) 1203system.cpu1.toL2Bus.pkt_count::total 34233178 # Packet count per connected master and slave (bytes) 1204system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432559 # Cumulative packet size per connected master and slave (bytes) 1206system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) 1207system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) 1208system.cpu1.toL2Bus.pkt_size::total 1357645303 # Cumulative packet size per connected master and slave (bytes) 1209system.cpu1.toL2Bus.snoops 4277162 # Total snoops (count) 1210system.cpu1.toL2Bus.snoopTraffic 79243712 # Total snoop traffic (bytes) 1211system.cpu1.toL2Bus.snoop_fanout::samples 26604267 # Request fanout histogram 1212system.cpu1.toL2Bus.snoop_fanout::mean 0.021049 # Request fanout histogram 1213system.cpu1.toL2Bus.snoop_fanout::stdev 0.143548 # Request fanout histogram 1214system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1215system.cpu1.toL2Bus.snoop_fanout::0 26044274 97.90% 97.90% # Request fanout histogram 1216system.cpu1.toL2Bus.snoop_fanout::1 559991 2.10% 100.00% # Request fanout histogram 1217system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram 1218system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1219system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1220system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1221system.cpu1.toL2Bus.snoop_fanout::total 26604267 # Request fanout histogram 1222system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1223system.iobus.trans_dist::ReadReq 40301 # Transaction distribution 1224system.iobus.trans_dist::ReadResp 40301 # Transaction distribution 1225system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1226system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 1227system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 1228system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1229system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1230system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1231system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1232system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1240system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 1243system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1244system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1245system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) 1247system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1248system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1249system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1250system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1251system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1252system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1253system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1254system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1255system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) 1265system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1266system.iocache.tags.replacements 115590 # number of replacements 1267system.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use 1268system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1269system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 1270system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1271system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. 1272system.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor 1273system.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor 1274system.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy 1275system.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy 1276system.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy 1277system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1278system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1279system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1280system.iocache.tags.tag_accesses 1040838 # Number of tag accesses 1281system.iocache.tags.data_accesses 1040838 # Number of data accesses 1282system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1283system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1284system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 1285system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 1286system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1287system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1288system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1289system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1290system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1291system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses 1292system.iocache.demand_misses::total 115649 # number of demand (read+write) misses 1293system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1294system.iocache.overall_misses::realview.ide 115609 # number of overall misses 1295system.iocache.overall_misses::total 115649 # number of overall misses 1296system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1297system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 1298system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 1299system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1300system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1301system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1302system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1303system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1304system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses 1305system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses 1306system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1307system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses 1308system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses 1309system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1310system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1311system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1312system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1313system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1314system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1315system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1316system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1317system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1318system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1319system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1320system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1321system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1322system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1323system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1324system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1325system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1326system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1327system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1328system.iocache.writebacks::writebacks 106694 # number of writebacks 1329system.iocache.writebacks::total 106694 # number of writebacks 1330system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1331system.l2c.tags.replacements 1924793 # number of replacements 1332system.l2c.tags.tagsinuse 65250.197909 # Cycle average of tags in use 1333system.l2c.tags.total_refs 5713780 # Total number of references to valid blocks. 1334system.l2c.tags.sampled_refs 1986359 # Sample count of references to valid blocks. 1335system.l2c.tags.avg_refs 2.876509 # Average number of references to valid blocks. 1336system.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. 1337system.l2c.tags.occ_blocks::writebacks 10662.392220 # Average occupied blocks per requestor 1338system.l2c.tags.occ_blocks::cpu0.dtb.walker 41.728586 # Average occupied blocks per requestor 1339system.l2c.tags.occ_blocks::cpu0.itb.walker 44.787257 # Average occupied blocks per requestor 1340system.l2c.tags.occ_blocks::cpu0.inst 3175.849688 # Average occupied blocks per requestor 1341system.l2c.tags.occ_blocks::cpu0.data 15990.343630 # Average occupied blocks per requestor 1342system.l2c.tags.occ_blocks::cpu1.dtb.walker 362.595804 # Average occupied blocks per requestor 1343system.l2c.tags.occ_blocks::cpu1.itb.walker 421.087250 # Average occupied blocks per requestor 1344system.l2c.tags.occ_blocks::cpu1.inst 2804.760651 # Average occupied blocks per requestor 1345system.l2c.tags.occ_blocks::cpu1.data 31746.652822 # Average occupied blocks per requestor 1346system.l2c.tags.occ_percent::writebacks 0.162695 # Average percentage of cache occupancy 1347system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000637 # Average percentage of cache occupancy 1348system.l2c.tags.occ_percent::cpu0.itb.walker 0.000683 # Average percentage of cache occupancy 1349system.l2c.tags.occ_percent::cpu0.inst 0.048460 # Average percentage of cache occupancy 1350system.l2c.tags.occ_percent::cpu0.data 0.243993 # Average percentage of cache occupancy 1351system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005533 # Average percentage of cache occupancy 1352system.l2c.tags.occ_percent::cpu1.itb.walker 0.006425 # Average percentage of cache occupancy 1353system.l2c.tags.occ_percent::cpu1.inst 0.042797 # Average percentage of cache occupancy 1354system.l2c.tags.occ_percent::cpu1.data 0.484415 # Average percentage of cache occupancy 1355system.l2c.tags.occ_percent::total 0.995639 # Average percentage of cache occupancy 1356system.l2c.tags.occ_task_id_blocks::1023 224 # Occupied blocks per task id 1357system.l2c.tags.occ_task_id_blocks::1024 61342 # Occupied blocks per task id 1358system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1359system.l2c.tags.age_task_id_blocks_1023::4 223 # Occupied blocks per task id 1360system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 1361system.l2c.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id 1362system.l2c.tags.age_task_id_blocks_1024::2 3566 # Occupied blocks per task id 1363system.l2c.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id 1364system.l2c.tags.age_task_id_blocks_1024::4 52911 # Occupied blocks per task id 1365system.l2c.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 1366system.l2c.tags.occ_task_id_percent::1024 0.936005 # Percentage of cache occupancy per task id 1367system.l2c.tags.tag_accesses 71904156 # Number of tag accesses 1368system.l2c.tags.data_accesses 71904156 # Number of data accesses 1369system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1370system.l2c.WritebackDirty_hits::writebacks 2750852 # number of WritebackDirty hits 1371system.l2c.WritebackDirty_hits::total 2750852 # number of WritebackDirty hits 1372system.l2c.UpgradeReq_hits::cpu0.data 60132 # number of UpgradeReq hits 1373system.l2c.UpgradeReq_hits::cpu1.data 51539 # number of UpgradeReq hits 1374system.l2c.UpgradeReq_hits::total 111671 # number of UpgradeReq hits 1375system.l2c.SCUpgradeReq_hits::cpu0.data 8500 # number of SCUpgradeReq hits 1376system.l2c.SCUpgradeReq_hits::cpu1.data 7695 # number of SCUpgradeReq hits 1377system.l2c.SCUpgradeReq_hits::total 16195 # number of SCUpgradeReq hits 1378system.l2c.ReadExReq_hits::cpu0.data 199510 # number of ReadExReq hits 1379system.l2c.ReadExReq_hits::cpu1.data 176557 # number of ReadExReq hits 1380system.l2c.ReadExReq_hits::total 376067 # number of ReadExReq hits 1381system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12368 # number of ReadSharedReq hits 1382system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5246 # number of ReadSharedReq hits 1383system.l2c.ReadSharedReq_hits::cpu0.inst 435137 # number of ReadSharedReq hits 1384system.l2c.ReadSharedReq_hits::cpu0.data 707607 # number of ReadSharedReq hits 1385system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12105 # number of ReadSharedReq hits 1386system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4097 # number of ReadSharedReq hits 1387system.l2c.ReadSharedReq_hits::cpu1.inst 413141 # number of ReadSharedReq hits 1388system.l2c.ReadSharedReq_hits::cpu1.data 664483 # number of ReadSharedReq hits 1389system.l2c.ReadSharedReq_hits::total 2254184 # number of ReadSharedReq hits 1390system.l2c.InvalidateReq_hits::cpu0.data 130356 # number of InvalidateReq hits 1391system.l2c.InvalidateReq_hits::cpu1.data 113567 # number of InvalidateReq hits 1392system.l2c.InvalidateReq_hits::total 243923 # number of InvalidateReq hits 1393system.l2c.demand_hits::cpu0.dtb.walker 12368 # number of demand (read+write) hits 1394system.l2c.demand_hits::cpu0.itb.walker 5246 # number of demand (read+write) hits 1395system.l2c.demand_hits::cpu0.inst 435137 # number of demand (read+write) hits 1396system.l2c.demand_hits::cpu0.data 907117 # number of demand (read+write) hits 1397system.l2c.demand_hits::cpu1.dtb.walker 12105 # number of demand (read+write) hits 1398system.l2c.demand_hits::cpu1.itb.walker 4097 # number of demand (read+write) hits 1399system.l2c.demand_hits::cpu1.inst 413141 # number of demand (read+write) hits 1400system.l2c.demand_hits::cpu1.data 841040 # number of demand (read+write) hits 1401system.l2c.demand_hits::total 2630251 # number of demand (read+write) hits 1402system.l2c.overall_hits::cpu0.dtb.walker 12368 # number of overall hits 1403system.l2c.overall_hits::cpu0.itb.walker 5246 # number of overall hits 1404system.l2c.overall_hits::cpu0.inst 435137 # number of overall hits 1405system.l2c.overall_hits::cpu0.data 907117 # number of overall hits 1406system.l2c.overall_hits::cpu1.dtb.walker 12105 # number of overall hits 1407system.l2c.overall_hits::cpu1.itb.walker 4097 # number of overall hits 1408system.l2c.overall_hits::cpu1.inst 413141 # number of overall hits 1409system.l2c.overall_hits::cpu1.data 841040 # number of overall hits 1410system.l2c.overall_hits::total 2630251 # number of overall hits 1411system.l2c.UpgradeReq_misses::cpu0.data 21889 # number of UpgradeReq misses 1412system.l2c.UpgradeReq_misses::cpu1.data 25427 # number of UpgradeReq misses 1413system.l2c.UpgradeReq_misses::total 47316 # number of UpgradeReq misses 1414system.l2c.SCUpgradeReq_misses::cpu0.data 415 # number of SCUpgradeReq misses 1415system.l2c.SCUpgradeReq_misses::cpu1.data 794 # number of SCUpgradeReq misses 1416system.l2c.SCUpgradeReq_misses::total 1209 # number of SCUpgradeReq misses 1417system.l2c.ReadExReq_misses::cpu0.data 372583 # number of ReadExReq misses 1418system.l2c.ReadExReq_misses::cpu1.data 420111 # number of ReadExReq misses 1419system.l2c.ReadExReq_misses::total 792694 # number of ReadExReq misses 1420system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2419 # number of ReadSharedReq misses 1421system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2002 # number of ReadSharedReq misses 1422system.l2c.ReadSharedReq_misses::cpu0.inst 63535 # number of ReadSharedReq misses 1423system.l2c.ReadSharedReq_misses::cpu0.data 191729 # number of ReadSharedReq misses 1424system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3502 # number of ReadSharedReq misses 1425system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3484 # number of ReadSharedReq misses 1426system.l2c.ReadSharedReq_misses::cpu1.inst 47028 # number of ReadSharedReq misses 1427system.l2c.ReadSharedReq_misses::cpu1.data 197713 # number of ReadSharedReq misses 1428system.l2c.ReadSharedReq_misses::total 511412 # number of ReadSharedReq misses 1429system.l2c.InvalidateReq_misses::cpu0.data 462716 # number of InvalidateReq misses 1430system.l2c.InvalidateReq_misses::cpu1.data 149158 # number of InvalidateReq misses 1431system.l2c.InvalidateReq_misses::total 611874 # number of InvalidateReq misses 1432system.l2c.demand_misses::cpu0.dtb.walker 2419 # number of demand (read+write) misses 1433system.l2c.demand_misses::cpu0.itb.walker 2002 # number of demand (read+write) misses 1434system.l2c.demand_misses::cpu0.inst 63535 # number of demand (read+write) misses 1435system.l2c.demand_misses::cpu0.data 564312 # number of demand (read+write) misses 1436system.l2c.demand_misses::cpu1.dtb.walker 3502 # number of demand (read+write) misses 1437system.l2c.demand_misses::cpu1.itb.walker 3484 # number of demand (read+write) misses 1438system.l2c.demand_misses::cpu1.inst 47028 # number of demand (read+write) misses 1439system.l2c.demand_misses::cpu1.data 617824 # number of demand (read+write) misses 1440system.l2c.demand_misses::total 1304106 # number of demand (read+write) misses 1441system.l2c.overall_misses::cpu0.dtb.walker 2419 # number of overall misses 1442system.l2c.overall_misses::cpu0.itb.walker 2002 # number of overall misses 1443system.l2c.overall_misses::cpu0.inst 63535 # number of overall misses 1444system.l2c.overall_misses::cpu0.data 564312 # number of overall misses 1445system.l2c.overall_misses::cpu1.dtb.walker 3502 # number of overall misses 1446system.l2c.overall_misses::cpu1.itb.walker 3484 # number of overall misses 1447system.l2c.overall_misses::cpu1.inst 47028 # number of overall misses 1448system.l2c.overall_misses::cpu1.data 617824 # number of overall misses 1449system.l2c.overall_misses::total 1304106 # number of overall misses 1450system.l2c.WritebackDirty_accesses::writebacks 2750852 # number of WritebackDirty accesses(hits+misses) 1451system.l2c.WritebackDirty_accesses::total 2750852 # number of WritebackDirty accesses(hits+misses) 1452system.l2c.UpgradeReq_accesses::cpu0.data 82021 # number of UpgradeReq accesses(hits+misses) 1453system.l2c.UpgradeReq_accesses::cpu1.data 76966 # number of UpgradeReq accesses(hits+misses) 1454system.l2c.UpgradeReq_accesses::total 158987 # number of UpgradeReq accesses(hits+misses) 1455system.l2c.SCUpgradeReq_accesses::cpu0.data 8915 # number of SCUpgradeReq accesses(hits+misses) 1456system.l2c.SCUpgradeReq_accesses::cpu1.data 8489 # number of SCUpgradeReq accesses(hits+misses) 1457system.l2c.SCUpgradeReq_accesses::total 17404 # number of SCUpgradeReq accesses(hits+misses) 1458system.l2c.ReadExReq_accesses::cpu0.data 572093 # number of ReadExReq accesses(hits+misses) 1459system.l2c.ReadExReq_accesses::cpu1.data 596668 # number of ReadExReq accesses(hits+misses) 1460system.l2c.ReadExReq_accesses::total 1168761 # number of ReadExReq accesses(hits+misses) 1461system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 14787 # number of ReadSharedReq accesses(hits+misses) 1462system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7248 # number of ReadSharedReq accesses(hits+misses) 1463system.l2c.ReadSharedReq_accesses::cpu0.inst 498672 # number of ReadSharedReq accesses(hits+misses) 1464system.l2c.ReadSharedReq_accesses::cpu0.data 899336 # number of ReadSharedReq accesses(hits+misses) 1465system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15607 # number of ReadSharedReq accesses(hits+misses) 1466system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7581 # number of ReadSharedReq accesses(hits+misses) 1467system.l2c.ReadSharedReq_accesses::cpu1.inst 460169 # number of ReadSharedReq accesses(hits+misses) 1468system.l2c.ReadSharedReq_accesses::cpu1.data 862196 # number of ReadSharedReq accesses(hits+misses) 1469system.l2c.ReadSharedReq_accesses::total 2765596 # number of ReadSharedReq accesses(hits+misses) 1470system.l2c.InvalidateReq_accesses::cpu0.data 593072 # number of InvalidateReq accesses(hits+misses) 1471system.l2c.InvalidateReq_accesses::cpu1.data 262725 # number of InvalidateReq accesses(hits+misses) 1472system.l2c.InvalidateReq_accesses::total 855797 # number of InvalidateReq accesses(hits+misses) 1473system.l2c.demand_accesses::cpu0.dtb.walker 14787 # number of demand (read+write) accesses 1474system.l2c.demand_accesses::cpu0.itb.walker 7248 # number of demand (read+write) accesses 1475system.l2c.demand_accesses::cpu0.inst 498672 # number of demand (read+write) accesses 1476system.l2c.demand_accesses::cpu0.data 1471429 # number of demand (read+write) accesses 1477system.l2c.demand_accesses::cpu1.dtb.walker 15607 # number of demand (read+write) accesses 1478system.l2c.demand_accesses::cpu1.itb.walker 7581 # number of demand (read+write) accesses 1479system.l2c.demand_accesses::cpu1.inst 460169 # number of demand (read+write) accesses 1480system.l2c.demand_accesses::cpu1.data 1458864 # number of demand (read+write) accesses 1481system.l2c.demand_accesses::total 3934357 # number of demand (read+write) accesses 1482system.l2c.overall_accesses::cpu0.dtb.walker 14787 # number of overall (read+write) accesses 1483system.l2c.overall_accesses::cpu0.itb.walker 7248 # number of overall (read+write) accesses 1484system.l2c.overall_accesses::cpu0.inst 498672 # number of overall (read+write) accesses 1485system.l2c.overall_accesses::cpu0.data 1471429 # number of overall (read+write) accesses 1486system.l2c.overall_accesses::cpu1.dtb.walker 15607 # number of overall (read+write) accesses 1487system.l2c.overall_accesses::cpu1.itb.walker 7581 # number of overall (read+write) accesses 1488system.l2c.overall_accesses::cpu1.inst 460169 # number of overall (read+write) accesses 1489system.l2c.overall_accesses::cpu1.data 1458864 # number of overall (read+write) accesses 1490system.l2c.overall_accesses::total 3934357 # number of overall (read+write) accesses 1491system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266871 # miss rate for UpgradeReq accesses 1492system.l2c.UpgradeReq_miss_rate::cpu1.data 0.330367 # miss rate for UpgradeReq accesses 1493system.l2c.UpgradeReq_miss_rate::total 0.297609 # miss rate for UpgradeReq accesses 1494system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.046551 # miss rate for SCUpgradeReq accesses 1495system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.093533 # miss rate for SCUpgradeReq accesses 1496system.l2c.SCUpgradeReq_miss_rate::total 0.069467 # miss rate for SCUpgradeReq accesses 1497system.l2c.ReadExReq_miss_rate::cpu0.data 0.651263 # miss rate for ReadExReq accesses 1498system.l2c.ReadExReq_miss_rate::cpu1.data 0.704095 # miss rate for ReadExReq accesses 1499system.l2c.ReadExReq_miss_rate::total 0.678234 # miss rate for ReadExReq accesses 1500system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for ReadSharedReq accesses 1501system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276214 # miss rate for ReadSharedReq accesses 1502system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.127408 # miss rate for ReadSharedReq accesses 1503system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213190 # miss rate for ReadSharedReq accesses 1504system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for ReadSharedReq accesses 1505system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.459570 # miss rate for ReadSharedReq accesses 1506system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.102197 # miss rate for ReadSharedReq accesses 1507system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.229313 # miss rate for ReadSharedReq accesses 1508system.l2c.ReadSharedReq_miss_rate::total 0.184919 # miss rate for ReadSharedReq accesses 1509system.l2c.InvalidateReq_miss_rate::cpu0.data 0.780202 # miss rate for InvalidateReq accesses 1510system.l2c.InvalidateReq_miss_rate::cpu1.data 0.567734 # miss rate for InvalidateReq accesses 1511system.l2c.InvalidateReq_miss_rate::total 0.714976 # miss rate for InvalidateReq accesses 1512system.l2c.demand_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for demand accesses 1513system.l2c.demand_miss_rate::cpu0.itb.walker 0.276214 # miss rate for demand accesses 1514system.l2c.demand_miss_rate::cpu0.inst 0.127408 # miss rate for demand accesses 1515system.l2c.demand_miss_rate::cpu0.data 0.383513 # miss rate for demand accesses 1516system.l2c.demand_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for demand accesses 1517system.l2c.demand_miss_rate::cpu1.itb.walker 0.459570 # miss rate for demand accesses 1518system.l2c.demand_miss_rate::cpu1.inst 0.102197 # miss rate for demand accesses 1519system.l2c.demand_miss_rate::cpu1.data 0.423497 # miss rate for demand accesses 1520system.l2c.demand_miss_rate::total 0.331466 # miss rate for demand accesses 1521system.l2c.overall_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for overall accesses 1522system.l2c.overall_miss_rate::cpu0.itb.walker 0.276214 # miss rate for overall accesses 1523system.l2c.overall_miss_rate::cpu0.inst 0.127408 # miss rate for overall accesses 1524system.l2c.overall_miss_rate::cpu0.data 0.383513 # miss rate for overall accesses 1525system.l2c.overall_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for overall accesses 1526system.l2c.overall_miss_rate::cpu1.itb.walker 0.459570 # miss rate for overall accesses 1527system.l2c.overall_miss_rate::cpu1.inst 0.102197 # miss rate for overall accesses 1528system.l2c.overall_miss_rate::cpu1.data 0.423497 # miss rate for overall accesses 1529system.l2c.overall_miss_rate::total 0.331466 # miss rate for overall accesses 1530system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1531system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1532system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1533system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1534system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1535system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1536system.l2c.writebacks::writebacks 1492845 # number of writebacks 1537system.l2c.writebacks::total 1492845 # number of writebacks 1538system.membus.snoop_filter.tot_requests 4436915 # Total number of requests made to the snoop filter. 1539system.membus.snoop_filter.hit_single_requests 2508187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1540system.membus.snoop_filter.hit_multi_requests 3478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1541system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1542system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1543system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1544system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1545system.membus.trans_dist::ReadReq 82130 # Transaction distribution 1546system.membus.trans_dist::ReadResp 602460 # Transaction distribution 1547system.membus.trans_dist::WriteReq 38798 # Transaction distribution 1548system.membus.trans_dist::WriteResp 38798 # Transaction distribution 1549system.membus.trans_dist::WritebackDirty 1599539 # Transaction distribution 1550system.membus.trans_dist::CleanEvict 267122 # Transaction distribution 1551system.membus.trans_dist::UpgradeReq 245150 # Transaction distribution 1552system.membus.trans_dist::SCUpgradeReq 295293 # Transaction distribution 1553system.membus.trans_dist::UpgradeResp 53835 # Transaction distribution 1554system.membus.trans_dist::ReadExReq 792754 # Transaction distribution 1555system.membus.trans_dist::ReadExResp 789263 # Transaction distribution 1556system.membus.trans_dist::ReadSharedReq 520330 # Transaction distribution 1557system.membus.trans_dist::InvalidateReq 716726 # Transaction distribution 1558system.membus.trans_dist::InvalidateResp 716726 # Transaction distribution 1559system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) 1560system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 1561system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) 1562system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6261826 # Packet count per connected master and slave (bytes) 1563system.membus.pkt_count_system.l2c.mem_side::total 6412036 # Packet count per connected master and slave (bytes) 1564system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) 1565system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) 1566system.membus.pkt_count::total 6758924 # Packet count per connected master and slave (bytes) 1567system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) 1568system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178979036 # Cumulative packet size per connected master and slave (bytes) 1571system.membus.pkt_size_system.l2c.mem_side::total 179190007 # Cumulative packet size per connected master and slave (bytes) 1572system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) 1573system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) 1574system.membus.pkt_size::total 186589175 # Cumulative packet size per connected master and slave (bytes) 1575system.membus.snoops 0 # Total snoops (count) 1576system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1577system.membus.snoop_fanout::samples 4557842 # Request fanout histogram 1578system.membus.snoop_fanout::mean 0.007340 # Request fanout histogram 1579system.membus.snoop_fanout::stdev 0.085359 # Request fanout histogram 1580system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1581system.membus.snoop_fanout::0 4524387 99.27% 99.27% # Request fanout histogram 1582system.membus.snoop_fanout::1 33455 0.73% 100.00% # Request fanout histogram 1583system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1584system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1585system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1586system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1587system.membus.snoop_fanout::total 4557842 # Request fanout histogram 1588system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1589system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1590system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1591system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1592system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1593system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1594system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1595system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1596system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1597system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1598system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1599system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1600system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1601system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1602system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1603system.realview.ethernet.txBytes 966 # Bytes Transmitted 1604system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1605system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1606system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1607system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1608system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1609system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1610system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1611system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1612system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 1613system.realview.ethernet.totPackets 3 # Total Packets 1614system.realview.ethernet.totBytes 966 # Total Bytes 1615system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1616system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 1617system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1618system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1619system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1620system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1621system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1622system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1623system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1624system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1625system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1626system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1627system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1628system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1629system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1630system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1631system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1632system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1633system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1634system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1635system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1636system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1637system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1638system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1639system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1640system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1641system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1642system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1643system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1644system.realview.ethernet.droppedPackets 0 # number of packets dropped 1645system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1646system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1647system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1648system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1649system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1650system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1651system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1652system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1653system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1654system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1655system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1656system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1657system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1658system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1659system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1660system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1661system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1662system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1663system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1664system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1665system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1666system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1667system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1668system.toL2Bus.snoop_filter.tot_requests 11075061 # Total number of requests made to the snoop filter. 1669system.toL2Bus.snoop_filter.hit_single_requests 5706480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1670system.toL2Bus.snoop_filter.hit_multi_requests 1648775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1671system.toL2Bus.snoop_filter.tot_snoops 269190 # Total number of snoops made to the snoop filter. 1672system.toL2Bus.snoop_filter.hit_single_snoops 248390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1673system.toL2Bus.snoop_filter.hit_multi_snoops 20800 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1674system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1675system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution 1676system.toL2Bus.trans_dist::ReadResp 3544615 # Transaction distribution 1677system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution 1678system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution 1679system.toL2Bus.trans_dist::WritebackDirty 2750852 # Transaction distribution 1680system.toL2Bus.trans_dist::CleanEvict 1991304 # Transaction distribution 1681system.toL2Bus.trans_dist::UpgradeReq 351511 # Transaction distribution 1682system.toL2Bus.trans_dist::SCUpgradeReq 311488 # Transaction distribution 1683system.toL2Bus.trans_dist::UpgradeResp 662999 # Transaction distribution 1684system.toL2Bus.trans_dist::ReadExReq 1351623 # Transaction distribution 1685system.toL2Bus.trans_dist::ReadExResp 1351623 # Transaction distribution 1686system.toL2Bus.trans_dist::ReadSharedReq 3462483 # Transaction distribution 1687system.toL2Bus.trans_dist::InvalidateReq 855797 # Transaction distribution 1688system.toL2Bus.trans_dist::InvalidateResp 855797 # Transaction distribution 1689system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9483041 # Packet count per connected master and slave (bytes) 1690system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8166779 # Packet count per connected master and slave (bytes) 1691system.toL2Bus.pkt_count::total 17649820 # Packet count per connected master and slave (bytes) 1692system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254997904 # Cumulative packet size per connected master and slave (bytes) 1693system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229564151 # Cumulative packet size per connected master and slave (bytes) 1694system.toL2Bus.pkt_size::total 484562055 # Cumulative packet size per connected master and slave (bytes) 1695system.toL2Bus.snoops 1959256 # Total snoops (count) 1696system.toL2Bus.snoopTraffic 95582592 # Total snoop traffic (bytes) 1697system.toL2Bus.snoop_fanout::samples 13153559 # Request fanout histogram 1698system.toL2Bus.snoop_fanout::mean 0.293824 # Request fanout histogram 1699system.toL2Bus.snoop_fanout::stdev 0.458971 # Request fanout histogram 1700system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1701system.toL2Bus.snoop_fanout::0 9309527 70.78% 70.78% # Request fanout histogram 1702system.toL2Bus.snoop_fanout::1 3823232 29.07% 99.84% # Request fanout histogram 1703system.toL2Bus.snoop_fanout::2 20800 0.16% 100.00% # Request fanout histogram 1704system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1705system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1706system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1707system.toL2Bus.snoop_fanout::total 13153559 # Request fanout histogram 1708 1709---------- End Simulation Statistics ----------	894system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 895system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 896system.cpu1.op_class::total 565908654 # Class of executed instruction 897system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 898system.cpu1.dcache.tags.replacements 5970884 # number of replacements 899system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use 900system.cpu1.dcache.tags.total_refs 166384448 # Total number of references to valid blocks. 901system.cpu1.dcache.tags.sampled_refs 5971395 # Sample count of references to valid blocks. 902system.cpu1.dcache.tags.avg_refs 27.863581 # Average number of references to valid blocks. 903system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. 904system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor 905system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy 906system.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy 907system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 908system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 909system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id 910system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 911system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 912system.cpu1.dcache.tags.tag_accesses 350957211 # Number of tag accesses 913system.cpu1.dcache.tags.data_accesses 350957211 # Number of data accesses 914system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 915system.cpu1.dcache.ReadReq_hits::cpu1.data 84198598 # number of ReadReq hits 916system.cpu1.dcache.ReadReq_hits::total 84198598 # number of ReadReq hits 917system.cpu1.dcache.WriteReq_hits::cpu1.data 77531561 # number of WriteReq hits 918system.cpu1.dcache.WriteReq_hits::total 77531561 # number of WriteReq hits 919system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits 920system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits 921system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64886 # number of WriteLineReq hits 922system.cpu1.dcache.WriteLineReq_hits::total 64886 # number of WriteLineReq hits 923system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055500 # number of LoadLockedReq hits 924system.cpu1.dcache.LoadLockedReq_hits::total 2055500 # number of LoadLockedReq hits 925system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044725 # number of StoreCondReq hits 926system.cpu1.dcache.StoreCondReq_hits::total 2044725 # number of StoreCondReq hits 927system.cpu1.dcache.demand_hits::cpu1.data 161795045 # number of demand (read+write) hits 928system.cpu1.dcache.demand_hits::total 161795045 # number of demand (read+write) hits 929system.cpu1.dcache.overall_hits::cpu1.data 161982308 # number of overall hits 930system.cpu1.dcache.overall_hits::total 161982308 # number of overall hits 931system.cpu1.dcache.ReadReq_misses::cpu1.data 3367290 # number of ReadReq misses 932system.cpu1.dcache.ReadReq_misses::total 3367290 # number of ReadReq misses 933system.cpu1.dcache.WriteReq_misses::cpu1.data 1466124 # number of WriteReq misses 934system.cpu1.dcache.WriteReq_misses::total 1466124 # number of WriteReq misses 935system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses 936system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses 937system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433871 # number of WriteLineReq misses 938system.cpu1.dcache.WriteLineReq_misses::total 433871 # number of WriteLineReq misses 939system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147105 # number of LoadLockedReq misses 940system.cpu1.dcache.LoadLockedReq_misses::total 147105 # number of LoadLockedReq misses 941system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156674 # number of StoreCondReq misses 942system.cpu1.dcache.StoreCondReq_misses::total 156674 # number of StoreCondReq misses 943system.cpu1.dcache.demand_misses::cpu1.data 5267285 # number of demand (read+write) misses 944system.cpu1.dcache.demand_misses::total 5267285 # number of demand (read+write) misses 945system.cpu1.dcache.overall_misses::cpu1.data 6060908 # number of overall misses 946system.cpu1.dcache.overall_misses::total 6060908 # number of overall misses 947system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) 948system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) 949system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) 950system.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses) 951system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses) 952system.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses) 953system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses) 954system.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses) 955system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses) 956system.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses) 957system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses) 958system.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses) 959system.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses 960system.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses 961system.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses 962system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses 963system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses 964system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses 965system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018559 # miss rate for WriteReq accesses 966system.cpu1.dcache.WriteReq_miss_rate::total 0.018559 # miss rate for WriteReq accesses 967system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses 968system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses 969system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869905 # miss rate for WriteLineReq accesses 970system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869905 # miss rate for WriteLineReq accesses 971system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066787 # miss rate for LoadLockedReq accesses 972system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066787 # miss rate for LoadLockedReq accesses 973system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071170 # miss rate for StoreCondReq accesses 974system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071170 # miss rate for StoreCondReq accesses 975system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031529 # miss rate for demand accesses 976system.cpu1.dcache.demand_miss_rate::total 0.031529 # miss rate for demand accesses 977system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036068 # miss rate for overall accesses 978system.cpu1.dcache.overall_miss_rate::total 0.036068 # miss rate for overall accesses 979system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 980system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 981system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 982system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 983system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 984system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 985system.cpu1.dcache.writebacks::writebacks 5970884 # number of writebacks 986system.cpu1.dcache.writebacks::total 5970884 # number of writebacks 987system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 988system.cpu1.icache.tags.replacements 4768482 # number of replacements 989system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use 990system.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks. 991system.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks. 992system.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks. 993system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. 994system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor 995system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy 996system.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy 997system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 998system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 999system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 1000system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id 1001system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1002system.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses 1003system.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses 1004system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1005system.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits 1006system.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits 1007system.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits 1008system.cpu1.icache.demand_hits::total 476148096 # number of demand (read+write) hits 1009system.cpu1.icache.overall_hits::cpu1.inst 476148096 # number of overall hits 1010system.cpu1.icache.overall_hits::total 476148096 # number of overall hits 1011system.cpu1.icache.ReadReq_misses::cpu1.inst 4768994 # number of ReadReq misses 1012system.cpu1.icache.ReadReq_misses::total 4768994 # number of ReadReq misses 1013system.cpu1.icache.demand_misses::cpu1.inst 4768994 # number of demand (read+write) misses 1014system.cpu1.icache.demand_misses::total 4768994 # number of demand (read+write) misses 1015system.cpu1.icache.overall_misses::cpu1.inst 4768994 # number of overall misses 1016system.cpu1.icache.overall_misses::total 4768994 # number of overall misses 1017system.cpu1.icache.ReadReq_accesses::cpu1.inst 480917090 # number of ReadReq accesses(hits+misses) 1018system.cpu1.icache.ReadReq_accesses::total 480917090 # number of ReadReq accesses(hits+misses) 1019system.cpu1.icache.demand_accesses::cpu1.inst 480917090 # number of demand (read+write) accesses 1020system.cpu1.icache.demand_accesses::total 480917090 # number of demand (read+write) accesses 1021system.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses 1022system.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses 1023system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses 1024system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses 1025system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses 1026system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses 1027system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses 1028system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses 1029system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1030system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1031system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1032system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1033system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1034system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1035system.cpu1.icache.writebacks::writebacks 4768482 # number of writebacks 1036system.cpu1.icache.writebacks::total 4768482 # number of writebacks 1037system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1038system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1039system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 1040system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1041system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1042system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1043system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 1044system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1045system.cpu1.l2cache.tags.replacements 2174770 # number of replacements 1046system.cpu1.l2cache.tags.tagsinuse 13105.960937 # Cycle average of tags in use 1047system.cpu1.l2cache.tags.total_refs 8815603 # Total number of references to valid blocks. 1048system.cpu1.l2cache.tags.sampled_refs 2190453 # Sample count of references to valid blocks. 1049system.cpu1.l2cache.tags.avg_refs 4.024557 # Average number of references to valid blocks. 1050system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1051system.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777 # Average occupied blocks per requestor 1052system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.863128 # Average occupied blocks per requestor 1053system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.242032 # Average occupied blocks per requestor 1054system.cpu1.l2cache.tags.occ_percent::writebacks 0.797660 # Average percentage of cache occupancy 1055system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001334 # Average percentage of cache occupancy 1056system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000930 # Average percentage of cache occupancy 1057system.cpu1.l2cache.tags.occ_percent::total 0.799924 # Average percentage of cache occupancy 1058system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id 1059system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15593 # Occupied blocks per task id 1060system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 57 # Occupied blocks per task id 1061system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 1062system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 1063system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id 1064system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2414 # Occupied blocks per task id 1065system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id 1066system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3564 # Occupied blocks per task id 1067system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1751 # Occupied blocks per task id 1068system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id 1069system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 1070system.cpu1.l2cache.tags.tag_accesses 369059783 # Number of tag accesses 1071system.cpu1.l2cache.tags.data_accesses 369059783 # Number of data accesses 1072system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1073system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 338101 # number of ReadReq hits 1074system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153667 # number of ReadReq hits 1075system.cpu1.l2cache.ReadReq_hits::total 491768 # number of ReadReq hits 1076system.cpu1.l2cache.WritebackDirty_hits::writebacks 4061526 # number of WritebackDirty hits 1077system.cpu1.l2cache.WritebackDirty_hits::total 4061526 # number of WritebackDirty hits 1078system.cpu1.l2cache.WritebackClean_hits::writebacks 6677473 # number of WritebackClean hits 1079system.cpu1.l2cache.WritebackClean_hits::total 6677473 # number of WritebackClean hits 1080system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614785 # number of ReadExReq hits 1081system.cpu1.l2cache.ReadExReq_hits::total 614785 # number of ReadExReq hits 1082system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4308825 # number of ReadCleanReq hits 1083system.cpu1.l2cache.ReadCleanReq_hits::total 4308825 # number of ReadCleanReq hits 1084system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3093892 # number of ReadSharedReq hits 1085system.cpu1.l2cache.ReadSharedReq_hits::total 3093892 # number of ReadSharedReq hits 1086system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164960 # number of InvalidateReq hits 1087system.cpu1.l2cache.InvalidateReq_hits::total 164960 # number of InvalidateReq hits 1088system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 338101 # number of demand (read+write) hits 1089system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153667 # number of demand (read+write) hits 1090system.cpu1.l2cache.demand_hits::cpu1.inst 4308825 # number of demand (read+write) hits 1091system.cpu1.l2cache.demand_hits::cpu1.data 3708677 # number of demand (read+write) hits 1092system.cpu1.l2cache.demand_hits::total 8509270 # number of demand (read+write) hits 1093system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 338101 # number of overall hits 1094system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153667 # number of overall hits 1095system.cpu1.l2cache.overall_hits::cpu1.inst 4308825 # number of overall hits 1096system.cpu1.l2cache.overall_hits::cpu1.data 3708677 # number of overall hits 1097system.cpu1.l2cache.overall_hits::total 8509270 # number of overall hits 1098system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22355 # number of ReadReq misses 1099system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10972 # number of ReadReq misses 1100system.cpu1.l2cache.ReadReq_misses::total 33327 # number of ReadReq misses 1101system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145242 # number of UpgradeReq misses 1102system.cpu1.l2cache.UpgradeReq_misses::total 145242 # number of UpgradeReq misses 1103system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156674 # number of SCUpgradeReq misses 1104system.cpu1.l2cache.SCUpgradeReq_misses::total 156674 # number of SCUpgradeReq misses 1105system.cpu1.l2cache.ReadExReq_misses::cpu1.data 706301 # number of ReadExReq misses 1106system.cpu1.l2cache.ReadExReq_misses::total 706301 # number of ReadExReq misses 1107system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 460169 # number of ReadCleanReq misses 1108system.cpu1.l2cache.ReadCleanReq_misses::total 460169 # number of ReadCleanReq misses 1109system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1214126 # number of ReadSharedReq misses 1110system.cpu1.l2cache.ReadSharedReq_misses::total 1214126 # number of ReadSharedReq misses 1111system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268707 # number of InvalidateReq misses 1112system.cpu1.l2cache.InvalidateReq_misses::total 268707 # number of InvalidateReq misses 1113system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22355 # number of demand (read+write) misses 1114system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10972 # number of demand (read+write) misses 1115system.cpu1.l2cache.demand_misses::cpu1.inst 460169 # number of demand (read+write) misses 1116system.cpu1.l2cache.demand_misses::cpu1.data 1920427 # number of demand (read+write) misses 1117system.cpu1.l2cache.demand_misses::total 2413923 # number of demand (read+write) misses 1118system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22355 # number of overall misses 1119system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10972 # number of overall misses 1120system.cpu1.l2cache.overall_misses::cpu1.inst 460169 # number of overall misses 1121system.cpu1.l2cache.overall_misses::cpu1.data 1920427 # number of overall misses 1122system.cpu1.l2cache.overall_misses::total 2413923 # number of overall misses 1123system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360456 # number of ReadReq accesses(hits+misses) 1124system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164639 # number of ReadReq accesses(hits+misses) 1125system.cpu1.l2cache.ReadReq_accesses::total 525095 # number of ReadReq accesses(hits+misses) 1126system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4061526 # number of WritebackDirty accesses(hits+misses) 1127system.cpu1.l2cache.WritebackDirty_accesses::total 4061526 # number of WritebackDirty accesses(hits+misses) 1128system.cpu1.l2cache.WritebackClean_accesses::writebacks 6677473 # number of WritebackClean accesses(hits+misses) 1129system.cpu1.l2cache.WritebackClean_accesses::total 6677473 # number of WritebackClean accesses(hits+misses) 1130system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145242 # number of UpgradeReq accesses(hits+misses) 1131system.cpu1.l2cache.UpgradeReq_accesses::total 145242 # number of UpgradeReq accesses(hits+misses) 1132system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156674 # number of SCUpgradeReq accesses(hits+misses) 1133system.cpu1.l2cache.SCUpgradeReq_accesses::total 156674 # number of SCUpgradeReq accesses(hits+misses) 1134system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) 1135system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) 1136system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) 1137system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) 1138system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308018 # number of ReadSharedReq accesses(hits+misses) 1139system.cpu1.l2cache.ReadSharedReq_accesses::total 4308018 # number of ReadSharedReq accesses(hits+misses) 1140system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) 1141system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) 1142system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360456 # number of demand (read+write) accesses 1143system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164639 # number of demand (read+write) accesses 1144system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses 1145system.cpu1.l2cache.demand_accesses::cpu1.data 5629104 # number of demand (read+write) accesses 1146system.cpu1.l2cache.demand_accesses::total 10923193 # number of demand (read+write) accesses 1147system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360456 # number of overall (read+write) accesses 1148system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164639 # number of overall (read+write) accesses 1149system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses 1150system.cpu1.l2cache.overall_accesses::cpu1.data 5629104 # number of overall (read+write) accesses 1151system.cpu1.l2cache.overall_accesses::total 10923193 # number of overall (read+write) accesses 1152system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for ReadReq accesses 1153system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.066643 # miss rate for ReadReq accesses 1154system.cpu1.l2cache.ReadReq_miss_rate::total 0.063469 # miss rate for ReadReq accesses 1155system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1156system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1157system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1158system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1159system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534637 # miss rate for ReadExReq accesses 1160system.cpu1.l2cache.ReadExReq_miss_rate::total 0.534637 # miss rate for ReadExReq accesses 1161system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096492 # miss rate for ReadCleanReq accesses 1162system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096492 # miss rate for ReadCleanReq accesses 1163system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281829 # miss rate for ReadSharedReq accesses 1164system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281829 # miss rate for ReadSharedReq accesses 1165system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.619616 # miss rate for InvalidateReq accesses 1166system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.619616 # miss rate for InvalidateReq accesses 1167system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for demand accesses 1168system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.066643 # miss rate for demand accesses 1169system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096492 # miss rate for demand accesses 1170system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341160 # miss rate for demand accesses 1171system.cpu1.l2cache.demand_miss_rate::total 0.220991 # miss rate for demand accesses 1172system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for overall accesses 1173system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.066643 # miss rate for overall accesses 1174system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096492 # miss rate for overall accesses 1175system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341160 # miss rate for overall accesses 1176system.cpu1.l2cache.overall_miss_rate::total 0.220991 # miss rate for overall accesses 1177system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1178system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1179system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1180system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1181system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1182system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1183system.cpu1.l2cache.writebacks::writebacks 1197912 # number of writebacks 1184system.cpu1.l2cache.writebacks::total 1197912 # number of writebacks 1185system.cpu1.toL2Bus.snoop_filter.tot_requests 22146544 # Total number of requests made to the snoop filter. 1186system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314780 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1187system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1188system.cpu1.toL2Bus.snoop_filter.tot_snoops 285761 # Total number of snoops made to the snoop filter. 1189system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 285759 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1190system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1191system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1192system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution 1193system.cpu1.toL2Bus.trans_dist::ReadResp 9684673 # Transaction distribution 1194system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution 1195system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution 1196system.cpu1.toL2Bus.trans_dist::WritebackDirty 4061526 # Transaction distribution 1197system.cpu1.toL2Bus.trans_dist::WritebackClean 6677840 # Transaction distribution 1198system.cpu1.toL2Bus.trans_dist::UpgradeReq 145242 # Transaction distribution 1199system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156674 # Transaction distribution 1200system.cpu1.toL2Bus.trans_dist::UpgradeResp 301916 # Transaction distribution 1201system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution 1202system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution 1203system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution 1204system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308018 # Transaction distribution 1205system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution 1206system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution 1207system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) 1208system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18723008 # Packet count per connected master and slave (bytes) 1209system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) 1210system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) 1211system.cpu1.toL2Bus.pkt_count::total 34233178 # Packet count per connected master and slave (bytes) 1212system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) 1213system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432559 # Cumulative packet size per connected master and slave (bytes) 1214system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) 1215system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) 1216system.cpu1.toL2Bus.pkt_size::total 1357645303 # Cumulative packet size per connected master and slave (bytes) 1217system.cpu1.toL2Bus.snoops 4277162 # Total snoops (count) 1218system.cpu1.toL2Bus.snoopTraffic 79243712 # Total snoop traffic (bytes) 1219system.cpu1.toL2Bus.snoop_fanout::samples 26604267 # Request fanout histogram 1220system.cpu1.toL2Bus.snoop_fanout::mean 0.021049 # Request fanout histogram 1221system.cpu1.toL2Bus.snoop_fanout::stdev 0.143548 # Request fanout histogram 1222system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1223system.cpu1.toL2Bus.snoop_fanout::0 26044274 97.90% 97.90% # Request fanout histogram 1224system.cpu1.toL2Bus.snoop_fanout::1 559991 2.10% 100.00% # Request fanout histogram 1225system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram 1226system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1227system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1228system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1229system.cpu1.toL2Bus.snoop_fanout::total 26604267 # Request fanout histogram 1230system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1231system.iobus.trans_dist::ReadReq 40301 # Transaction distribution 1232system.iobus.trans_dist::ReadResp 40301 # Transaction distribution 1233system.iobus.trans_dist::WriteReq 136636 # Transaction distribution 1234system.iobus.trans_dist::WriteResp 136636 # Transaction distribution 1235system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1240system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1243system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1244system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1245system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 1247system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1253system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes) 1255system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) 1273system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1274system.iocache.tags.replacements 115590 # number of replacements 1275system.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use 1276system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1277system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. 1278system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1279system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. 1280system.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor 1281system.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor 1282system.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy 1283system.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy 1284system.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy 1285system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1286system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1287system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1288system.iocache.tags.tag_accesses 1040838 # Number of tag accesses 1289system.iocache.tags.data_accesses 1040838 # Number of data accesses 1290system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1291system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1292system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 1293system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 1294system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1295system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1296system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 1297system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 1298system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1299system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses 1300system.iocache.demand_misses::total 115649 # number of demand (read+write) misses 1301system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1302system.iocache.overall_misses::realview.ide 115609 # number of overall misses 1303system.iocache.overall_misses::total 115649 # number of overall misses 1304system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1305system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 1306system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 1307system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1308system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1309system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 1310system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 1311system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1312system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses 1313system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses 1314system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1315system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses 1316system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses 1317system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1318system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1319system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1320system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1321system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1322system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1323system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1324system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1325system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1326system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1327system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1328system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1329system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1330system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1331system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1332system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1333system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1334system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1335system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1336system.iocache.writebacks::writebacks 106694 # number of writebacks 1337system.iocache.writebacks::total 106694 # number of writebacks 1338system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1339system.l2c.tags.replacements 1924793 # number of replacements 1340system.l2c.tags.tagsinuse 65250.197909 # Cycle average of tags in use 1341system.l2c.tags.total_refs 5713780 # Total number of references to valid blocks. 1342system.l2c.tags.sampled_refs 1986359 # Sample count of references to valid blocks. 1343system.l2c.tags.avg_refs 2.876509 # Average number of references to valid blocks. 1344system.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. 1345system.l2c.tags.occ_blocks::writebacks 10662.392220 # Average occupied blocks per requestor 1346system.l2c.tags.occ_blocks::cpu0.dtb.walker 41.728586 # Average occupied blocks per requestor 1347system.l2c.tags.occ_blocks::cpu0.itb.walker 44.787257 # Average occupied blocks per requestor 1348system.l2c.tags.occ_blocks::cpu0.inst 3175.849688 # Average occupied blocks per requestor 1349system.l2c.tags.occ_blocks::cpu0.data 15990.343630 # Average occupied blocks per requestor 1350system.l2c.tags.occ_blocks::cpu1.dtb.walker 362.595804 # Average occupied blocks per requestor 1351system.l2c.tags.occ_blocks::cpu1.itb.walker 421.087250 # Average occupied blocks per requestor 1352system.l2c.tags.occ_blocks::cpu1.inst 2804.760651 # Average occupied blocks per requestor 1353system.l2c.tags.occ_blocks::cpu1.data 31746.652822 # Average occupied blocks per requestor 1354system.l2c.tags.occ_percent::writebacks 0.162695 # Average percentage of cache occupancy 1355system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000637 # Average percentage of cache occupancy 1356system.l2c.tags.occ_percent::cpu0.itb.walker 0.000683 # Average percentage of cache occupancy 1357system.l2c.tags.occ_percent::cpu0.inst 0.048460 # Average percentage of cache occupancy 1358system.l2c.tags.occ_percent::cpu0.data 0.243993 # Average percentage of cache occupancy 1359system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005533 # Average percentage of cache occupancy 1360system.l2c.tags.occ_percent::cpu1.itb.walker 0.006425 # Average percentage of cache occupancy 1361system.l2c.tags.occ_percent::cpu1.inst 0.042797 # Average percentage of cache occupancy 1362system.l2c.tags.occ_percent::cpu1.data 0.484415 # Average percentage of cache occupancy 1363system.l2c.tags.occ_percent::total 0.995639 # Average percentage of cache occupancy 1364system.l2c.tags.occ_task_id_blocks::1023 224 # Occupied blocks per task id 1365system.l2c.tags.occ_task_id_blocks::1024 61342 # Occupied blocks per task id 1366system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1367system.l2c.tags.age_task_id_blocks_1023::4 223 # Occupied blocks per task id 1368system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 1369system.l2c.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id 1370system.l2c.tags.age_task_id_blocks_1024::2 3566 # Occupied blocks per task id 1371system.l2c.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id 1372system.l2c.tags.age_task_id_blocks_1024::4 52911 # Occupied blocks per task id 1373system.l2c.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 1374system.l2c.tags.occ_task_id_percent::1024 0.936005 # Percentage of cache occupancy per task id 1375system.l2c.tags.tag_accesses 71904156 # Number of tag accesses 1376system.l2c.tags.data_accesses 71904156 # Number of data accesses 1377system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1378system.l2c.WritebackDirty_hits::writebacks 2750852 # number of WritebackDirty hits 1379system.l2c.WritebackDirty_hits::total 2750852 # number of WritebackDirty hits 1380system.l2c.UpgradeReq_hits::cpu0.data 60132 # number of UpgradeReq hits 1381system.l2c.UpgradeReq_hits::cpu1.data 51539 # number of UpgradeReq hits 1382system.l2c.UpgradeReq_hits::total 111671 # number of UpgradeReq hits 1383system.l2c.SCUpgradeReq_hits::cpu0.data 8500 # number of SCUpgradeReq hits 1384system.l2c.SCUpgradeReq_hits::cpu1.data 7695 # number of SCUpgradeReq hits 1385system.l2c.SCUpgradeReq_hits::total 16195 # number of SCUpgradeReq hits 1386system.l2c.ReadExReq_hits::cpu0.data 199510 # number of ReadExReq hits 1387system.l2c.ReadExReq_hits::cpu1.data 176557 # number of ReadExReq hits 1388system.l2c.ReadExReq_hits::total 376067 # number of ReadExReq hits 1389system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12368 # number of ReadSharedReq hits 1390system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5246 # number of ReadSharedReq hits 1391system.l2c.ReadSharedReq_hits::cpu0.inst 435137 # number of ReadSharedReq hits 1392system.l2c.ReadSharedReq_hits::cpu0.data 707607 # number of ReadSharedReq hits 1393system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12105 # number of ReadSharedReq hits 1394system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4097 # number of ReadSharedReq hits 1395system.l2c.ReadSharedReq_hits::cpu1.inst 413141 # number of ReadSharedReq hits 1396system.l2c.ReadSharedReq_hits::cpu1.data 664483 # number of ReadSharedReq hits 1397system.l2c.ReadSharedReq_hits::total 2254184 # number of ReadSharedReq hits 1398system.l2c.InvalidateReq_hits::cpu0.data 130356 # number of InvalidateReq hits 1399system.l2c.InvalidateReq_hits::cpu1.data 113567 # number of InvalidateReq hits 1400system.l2c.InvalidateReq_hits::total 243923 # number of InvalidateReq hits 1401system.l2c.demand_hits::cpu0.dtb.walker 12368 # number of demand (read+write) hits 1402system.l2c.demand_hits::cpu0.itb.walker 5246 # number of demand (read+write) hits 1403system.l2c.demand_hits::cpu0.inst 435137 # number of demand (read+write) hits 1404system.l2c.demand_hits::cpu0.data 907117 # number of demand (read+write) hits 1405system.l2c.demand_hits::cpu1.dtb.walker 12105 # number of demand (read+write) hits 1406system.l2c.demand_hits::cpu1.itb.walker 4097 # number of demand (read+write) hits 1407system.l2c.demand_hits::cpu1.inst 413141 # number of demand (read+write) hits 1408system.l2c.demand_hits::cpu1.data 841040 # number of demand (read+write) hits 1409system.l2c.demand_hits::total 2630251 # number of demand (read+write) hits 1410system.l2c.overall_hits::cpu0.dtb.walker 12368 # number of overall hits 1411system.l2c.overall_hits::cpu0.itb.walker 5246 # number of overall hits 1412system.l2c.overall_hits::cpu0.inst 435137 # number of overall hits 1413system.l2c.overall_hits::cpu0.data 907117 # number of overall hits 1414system.l2c.overall_hits::cpu1.dtb.walker 12105 # number of overall hits 1415system.l2c.overall_hits::cpu1.itb.walker 4097 # number of overall hits 1416system.l2c.overall_hits::cpu1.inst 413141 # number of overall hits 1417system.l2c.overall_hits::cpu1.data 841040 # number of overall hits 1418system.l2c.overall_hits::total 2630251 # number of overall hits 1419system.l2c.UpgradeReq_misses::cpu0.data 21889 # number of UpgradeReq misses 1420system.l2c.UpgradeReq_misses::cpu1.data 25427 # number of UpgradeReq misses 1421system.l2c.UpgradeReq_misses::total 47316 # number of UpgradeReq misses 1422system.l2c.SCUpgradeReq_misses::cpu0.data 415 # number of SCUpgradeReq misses 1423system.l2c.SCUpgradeReq_misses::cpu1.data 794 # number of SCUpgradeReq misses 1424system.l2c.SCUpgradeReq_misses::total 1209 # number of SCUpgradeReq misses 1425system.l2c.ReadExReq_misses::cpu0.data 372583 # number of ReadExReq misses 1426system.l2c.ReadExReq_misses::cpu1.data 420111 # number of ReadExReq misses 1427system.l2c.ReadExReq_misses::total 792694 # number of ReadExReq misses 1428system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2419 # number of ReadSharedReq misses 1429system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2002 # number of ReadSharedReq misses 1430system.l2c.ReadSharedReq_misses::cpu0.inst 63535 # number of ReadSharedReq misses 1431system.l2c.ReadSharedReq_misses::cpu0.data 191729 # number of ReadSharedReq misses 1432system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3502 # number of ReadSharedReq misses 1433system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3484 # number of ReadSharedReq misses 1434system.l2c.ReadSharedReq_misses::cpu1.inst 47028 # number of ReadSharedReq misses 1435system.l2c.ReadSharedReq_misses::cpu1.data 197713 # number of ReadSharedReq misses 1436system.l2c.ReadSharedReq_misses::total 511412 # number of ReadSharedReq misses 1437system.l2c.InvalidateReq_misses::cpu0.data 462716 # number of InvalidateReq misses 1438system.l2c.InvalidateReq_misses::cpu1.data 149158 # number of InvalidateReq misses 1439system.l2c.InvalidateReq_misses::total 611874 # number of InvalidateReq misses 1440system.l2c.demand_misses::cpu0.dtb.walker 2419 # number of demand (read+write) misses 1441system.l2c.demand_misses::cpu0.itb.walker 2002 # number of demand (read+write) misses 1442system.l2c.demand_misses::cpu0.inst 63535 # number of demand (read+write) misses 1443system.l2c.demand_misses::cpu0.data 564312 # number of demand (read+write) misses 1444system.l2c.demand_misses::cpu1.dtb.walker 3502 # number of demand (read+write) misses 1445system.l2c.demand_misses::cpu1.itb.walker 3484 # number of demand (read+write) misses 1446system.l2c.demand_misses::cpu1.inst 47028 # number of demand (read+write) misses 1447system.l2c.demand_misses::cpu1.data 617824 # number of demand (read+write) misses 1448system.l2c.demand_misses::total 1304106 # number of demand (read+write) misses 1449system.l2c.overall_misses::cpu0.dtb.walker 2419 # number of overall misses 1450system.l2c.overall_misses::cpu0.itb.walker 2002 # number of overall misses 1451system.l2c.overall_misses::cpu0.inst 63535 # number of overall misses 1452system.l2c.overall_misses::cpu0.data 564312 # number of overall misses 1453system.l2c.overall_misses::cpu1.dtb.walker 3502 # number of overall misses 1454system.l2c.overall_misses::cpu1.itb.walker 3484 # number of overall misses 1455system.l2c.overall_misses::cpu1.inst 47028 # number of overall misses 1456system.l2c.overall_misses::cpu1.data 617824 # number of overall misses 1457system.l2c.overall_misses::total 1304106 # number of overall misses 1458system.l2c.WritebackDirty_accesses::writebacks 2750852 # number of WritebackDirty accesses(hits+misses) 1459system.l2c.WritebackDirty_accesses::total 2750852 # number of WritebackDirty accesses(hits+misses) 1460system.l2c.UpgradeReq_accesses::cpu0.data 82021 # number of UpgradeReq accesses(hits+misses) 1461system.l2c.UpgradeReq_accesses::cpu1.data 76966 # number of UpgradeReq accesses(hits+misses) 1462system.l2c.UpgradeReq_accesses::total 158987 # number of UpgradeReq accesses(hits+misses) 1463system.l2c.SCUpgradeReq_accesses::cpu0.data 8915 # number of SCUpgradeReq accesses(hits+misses) 1464system.l2c.SCUpgradeReq_accesses::cpu1.data 8489 # number of SCUpgradeReq accesses(hits+misses) 1465system.l2c.SCUpgradeReq_accesses::total 17404 # number of SCUpgradeReq accesses(hits+misses) 1466system.l2c.ReadExReq_accesses::cpu0.data 572093 # number of ReadExReq accesses(hits+misses) 1467system.l2c.ReadExReq_accesses::cpu1.data 596668 # number of ReadExReq accesses(hits+misses) 1468system.l2c.ReadExReq_accesses::total 1168761 # number of ReadExReq accesses(hits+misses) 1469system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 14787 # number of ReadSharedReq accesses(hits+misses) 1470system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7248 # number of ReadSharedReq accesses(hits+misses) 1471system.l2c.ReadSharedReq_accesses::cpu0.inst 498672 # number of ReadSharedReq accesses(hits+misses) 1472system.l2c.ReadSharedReq_accesses::cpu0.data 899336 # number of ReadSharedReq accesses(hits+misses) 1473system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15607 # number of ReadSharedReq accesses(hits+misses) 1474system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7581 # number of ReadSharedReq accesses(hits+misses) 1475system.l2c.ReadSharedReq_accesses::cpu1.inst 460169 # number of ReadSharedReq accesses(hits+misses) 1476system.l2c.ReadSharedReq_accesses::cpu1.data 862196 # number of ReadSharedReq accesses(hits+misses) 1477system.l2c.ReadSharedReq_accesses::total 2765596 # number of ReadSharedReq accesses(hits+misses) 1478system.l2c.InvalidateReq_accesses::cpu0.data 593072 # number of InvalidateReq accesses(hits+misses) 1479system.l2c.InvalidateReq_accesses::cpu1.data 262725 # number of InvalidateReq accesses(hits+misses) 1480system.l2c.InvalidateReq_accesses::total 855797 # number of InvalidateReq accesses(hits+misses) 1481system.l2c.demand_accesses::cpu0.dtb.walker 14787 # number of demand (read+write) accesses 1482system.l2c.demand_accesses::cpu0.itb.walker 7248 # number of demand (read+write) accesses 1483system.l2c.demand_accesses::cpu0.inst 498672 # number of demand (read+write) accesses 1484system.l2c.demand_accesses::cpu0.data 1471429 # number of demand (read+write) accesses 1485system.l2c.demand_accesses::cpu1.dtb.walker 15607 # number of demand (read+write) accesses 1486system.l2c.demand_accesses::cpu1.itb.walker 7581 # number of demand (read+write) accesses 1487system.l2c.demand_accesses::cpu1.inst 460169 # number of demand (read+write) accesses 1488system.l2c.demand_accesses::cpu1.data 1458864 # number of demand (read+write) accesses 1489system.l2c.demand_accesses::total 3934357 # number of demand (read+write) accesses 1490system.l2c.overall_accesses::cpu0.dtb.walker 14787 # number of overall (read+write) accesses 1491system.l2c.overall_accesses::cpu0.itb.walker 7248 # number of overall (read+write) accesses 1492system.l2c.overall_accesses::cpu0.inst 498672 # number of overall (read+write) accesses 1493system.l2c.overall_accesses::cpu0.data 1471429 # number of overall (read+write) accesses 1494system.l2c.overall_accesses::cpu1.dtb.walker 15607 # number of overall (read+write) accesses 1495system.l2c.overall_accesses::cpu1.itb.walker 7581 # number of overall (read+write) accesses 1496system.l2c.overall_accesses::cpu1.inst 460169 # number of overall (read+write) accesses 1497system.l2c.overall_accesses::cpu1.data 1458864 # number of overall (read+write) accesses 1498system.l2c.overall_accesses::total 3934357 # number of overall (read+write) accesses 1499system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266871 # miss rate for UpgradeReq accesses 1500system.l2c.UpgradeReq_miss_rate::cpu1.data 0.330367 # miss rate for UpgradeReq accesses 1501system.l2c.UpgradeReq_miss_rate::total 0.297609 # miss rate for UpgradeReq accesses 1502system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.046551 # miss rate for SCUpgradeReq accesses 1503system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.093533 # miss rate for SCUpgradeReq accesses 1504system.l2c.SCUpgradeReq_miss_rate::total 0.069467 # miss rate for SCUpgradeReq accesses 1505system.l2c.ReadExReq_miss_rate::cpu0.data 0.651263 # miss rate for ReadExReq accesses 1506system.l2c.ReadExReq_miss_rate::cpu1.data 0.704095 # miss rate for ReadExReq accesses 1507system.l2c.ReadExReq_miss_rate::total 0.678234 # miss rate for ReadExReq accesses 1508system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for ReadSharedReq accesses 1509system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276214 # miss rate for ReadSharedReq accesses 1510system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.127408 # miss rate for ReadSharedReq accesses 1511system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213190 # miss rate for ReadSharedReq accesses 1512system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for ReadSharedReq accesses 1513system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.459570 # miss rate for ReadSharedReq accesses 1514system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.102197 # miss rate for ReadSharedReq accesses 1515system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.229313 # miss rate for ReadSharedReq accesses 1516system.l2c.ReadSharedReq_miss_rate::total 0.184919 # miss rate for ReadSharedReq accesses 1517system.l2c.InvalidateReq_miss_rate::cpu0.data 0.780202 # miss rate for InvalidateReq accesses 1518system.l2c.InvalidateReq_miss_rate::cpu1.data 0.567734 # miss rate for InvalidateReq accesses 1519system.l2c.InvalidateReq_miss_rate::total 0.714976 # miss rate for InvalidateReq accesses 1520system.l2c.demand_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for demand accesses 1521system.l2c.demand_miss_rate::cpu0.itb.walker 0.276214 # miss rate for demand accesses 1522system.l2c.demand_miss_rate::cpu0.inst 0.127408 # miss rate for demand accesses 1523system.l2c.demand_miss_rate::cpu0.data 0.383513 # miss rate for demand accesses 1524system.l2c.demand_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for demand accesses 1525system.l2c.demand_miss_rate::cpu1.itb.walker 0.459570 # miss rate for demand accesses 1526system.l2c.demand_miss_rate::cpu1.inst 0.102197 # miss rate for demand accesses 1527system.l2c.demand_miss_rate::cpu1.data 0.423497 # miss rate for demand accesses 1528system.l2c.demand_miss_rate::total 0.331466 # miss rate for demand accesses 1529system.l2c.overall_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for overall accesses 1530system.l2c.overall_miss_rate::cpu0.itb.walker 0.276214 # miss rate for overall accesses 1531system.l2c.overall_miss_rate::cpu0.inst 0.127408 # miss rate for overall accesses 1532system.l2c.overall_miss_rate::cpu0.data 0.383513 # miss rate for overall accesses 1533system.l2c.overall_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for overall accesses 1534system.l2c.overall_miss_rate::cpu1.itb.walker 0.459570 # miss rate for overall accesses 1535system.l2c.overall_miss_rate::cpu1.inst 0.102197 # miss rate for overall accesses 1536system.l2c.overall_miss_rate::cpu1.data 0.423497 # miss rate for overall accesses 1537system.l2c.overall_miss_rate::total 0.331466 # miss rate for overall accesses 1538system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1539system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1540system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1541system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1542system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1543system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1544system.l2c.writebacks::writebacks 1492845 # number of writebacks 1545system.l2c.writebacks::total 1492845 # number of writebacks 1546system.membus.snoop_filter.tot_requests 4436915 # Total number of requests made to the snoop filter. 1547system.membus.snoop_filter.hit_single_requests 2508187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1548system.membus.snoop_filter.hit_multi_requests 3478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1549system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1550system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1551system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1552system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1553system.membus.trans_dist::ReadReq 82130 # Transaction distribution 1554system.membus.trans_dist::ReadResp 602460 # Transaction distribution 1555system.membus.trans_dist::WriteReq 38798 # Transaction distribution 1556system.membus.trans_dist::WriteResp 38798 # Transaction distribution 1557system.membus.trans_dist::WritebackDirty 1599539 # Transaction distribution 1558system.membus.trans_dist::CleanEvict 267122 # Transaction distribution 1559system.membus.trans_dist::UpgradeReq 245150 # Transaction distribution 1560system.membus.trans_dist::SCUpgradeReq 295293 # Transaction distribution 1561system.membus.trans_dist::UpgradeResp 53835 # Transaction distribution 1562system.membus.trans_dist::ReadExReq 792754 # Transaction distribution 1563system.membus.trans_dist::ReadExResp 789263 # Transaction distribution 1564system.membus.trans_dist::ReadSharedReq 520330 # Transaction distribution 1565system.membus.trans_dist::InvalidateReq 716726 # Transaction distribution 1566system.membus.trans_dist::InvalidateResp 716726 # Transaction distribution 1567system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) 1568system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 1569system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) 1570system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6261826 # Packet count per connected master and slave (bytes) 1571system.membus.pkt_count_system.l2c.mem_side::total 6412036 # Packet count per connected master and slave (bytes) 1572system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) 1573system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) 1574system.membus.pkt_count::total 6758924 # Packet count per connected master and slave (bytes) 1575system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) 1576system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 1577system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) 1578system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178979036 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size_system.l2c.mem_side::total 179190007 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) 1581system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) 1582system.membus.pkt_size::total 186589175 # Cumulative packet size per connected master and slave (bytes) 1583system.membus.snoops 0 # Total snoops (count) 1584system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1585system.membus.snoop_fanout::samples 4557842 # Request fanout histogram 1586system.membus.snoop_fanout::mean 0.007340 # Request fanout histogram 1587system.membus.snoop_fanout::stdev 0.085359 # Request fanout histogram 1588system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1589system.membus.snoop_fanout::0 4524387 99.27% 99.27% # Request fanout histogram 1590system.membus.snoop_fanout::1 33455 0.73% 100.00% # Request fanout histogram 1591system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1592system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1593system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1594system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1595system.membus.snoop_fanout::total 4557842 # Request fanout histogram 1596system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1597system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1598system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1599system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1600system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1601system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1602system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1603system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1604system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1605system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1606system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1607system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1608system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1609system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1610system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1611system.realview.ethernet.txBytes 966 # Bytes Transmitted 1612system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1613system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1614system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1615system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1616system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1617system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1618system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1619system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1620system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 1621system.realview.ethernet.totPackets 3 # Total Packets 1622system.realview.ethernet.totBytes 966 # Total Bytes 1623system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1624system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 1625system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1626system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1627system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1628system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1629system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1630system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1631system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1632system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1633system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1634system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1635system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1636system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1637system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1638system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1639system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1640system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1641system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1642system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1643system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1644system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1645system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1646system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1647system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1648system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1649system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1650system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1651system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1652system.realview.ethernet.droppedPackets 0 # number of packets dropped 1653system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1654system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1655system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1656system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1657system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1658system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1659system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1660system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1661system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1662system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1663system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1664system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1665system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1666system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1667system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1668system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1669system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1670system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1671system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1672system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1673system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1674system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1675system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1676system.toL2Bus.snoop_filter.tot_requests 11075061 # Total number of requests made to the snoop filter. 1677system.toL2Bus.snoop_filter.hit_single_requests 5706480 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1678system.toL2Bus.snoop_filter.hit_multi_requests 1648775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1679system.toL2Bus.snoop_filter.tot_snoops 269190 # Total number of snoops made to the snoop filter. 1680system.toL2Bus.snoop_filter.hit_single_snoops 248390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1681system.toL2Bus.snoop_filter.hit_multi_snoops 20800 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1682system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states 1683system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution 1684system.toL2Bus.trans_dist::ReadResp 3544615 # Transaction distribution 1685system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution 1686system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution 1687system.toL2Bus.trans_dist::WritebackDirty 2750852 # Transaction distribution 1688system.toL2Bus.trans_dist::CleanEvict 1991304 # Transaction distribution 1689system.toL2Bus.trans_dist::UpgradeReq 351511 # Transaction distribution 1690system.toL2Bus.trans_dist::SCUpgradeReq 311488 # Transaction distribution 1691system.toL2Bus.trans_dist::UpgradeResp 662999 # Transaction distribution 1692system.toL2Bus.trans_dist::ReadExReq 1351623 # Transaction distribution 1693system.toL2Bus.trans_dist::ReadExResp 1351623 # Transaction distribution 1694system.toL2Bus.trans_dist::ReadSharedReq 3462483 # Transaction distribution 1695system.toL2Bus.trans_dist::InvalidateReq 855797 # Transaction distribution 1696system.toL2Bus.trans_dist::InvalidateResp 855797 # Transaction distribution 1697system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9483041 # Packet count per connected master and slave (bytes) 1698system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8166779 # Packet count per connected master and slave (bytes) 1699system.toL2Bus.pkt_count::total 17649820 # Packet count per connected master and slave (bytes) 1700system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254997904 # Cumulative packet size per connected master and slave (bytes) 1701system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229564151 # Cumulative packet size per connected master and slave (bytes) 1702system.toL2Bus.pkt_size::total 484562055 # Cumulative packet size per connected master and slave (bytes) 1703system.toL2Bus.snoops 1959256 # Total snoops (count) 1704system.toL2Bus.snoopTraffic 95582592 # Total snoop traffic (bytes) 1705system.toL2Bus.snoop_fanout::samples 13153559 # Request fanout histogram 1706system.toL2Bus.snoop_fanout::mean 0.293824 # Request fanout histogram 1707system.toL2Bus.snoop_fanout::stdev 0.458971 # Request fanout histogram 1708system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1709system.toL2Bus.snoop_fanout::0 9309527 70.78% 70.78% # Request fanout histogram 1710system.toL2Bus.snoop_fanout::1 3823232 29.07% 99.84% # Request fanout histogram 1711system.toL2Bus.snoop_fanout::2 20800 0.16% 100.00% # Request fanout histogram 1712system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1713system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1714system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1715system.toL2Bus.snoop_fanout::total 13153559 # Request fanout histogram 1716 1717---------- End Simulation Statistics ----------