12sim_insts 975457230 # Number of instructions simulated
13sim_ops 1147538415 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 152256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 127104 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 3638260 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 62923528 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.dtb.walker 221632 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.itb.walker 219968 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 2412168 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 46368688 # Number of bytes read from this memory
24system.physmem.bytes_read::realview.ide 419904 # Number of bytes read from this memory
25system.physmem.bytes_read::total 116483508 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 3638260 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 2412168 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 6050428 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 101038848 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
32system.physmem.bytes_written::total 101059432 # Number of bytes written to this memory
33system.physmem.num_reads::cpu0.dtb.walker 2379 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 1986 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 97255 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 983193 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.dtb.walker 3463 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.itb.walker 3437 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.inst 37797 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.data 724527 # Number of read requests responded to by this memory
41system.physmem.num_reads::realview.ide 6561 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 1860598 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 1578732 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 1581306 # Number of write requests responded to by this memory
47system.physmem.bw_read::cpu0.dtb.walker 3225 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.itb.walker 2692 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.inst 77054 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.data 1332651 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.dtb.walker 4694 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.itb.walker 4659 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.inst 51087 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.data 982038 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::realview.ide 8893 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 2466992 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 77054 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 51087 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 128141 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 2139891 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 2140327 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 2139891 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.dtb.walker 3225 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.itb.walker 2692 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.inst 77054 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.data 1333087 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.dtb.walker 4694 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.itb.walker 4659 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.inst 51087 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.data 982038 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::realview.ide 8893 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 4607319 # Total bandwidth to/from this memory (bytes/s)
75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
83system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
84system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
85system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
86system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
87system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
88system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
89system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
90system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
91system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
92system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
93system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
94system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
95system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
96system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
97system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
98system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
99system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
100system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
101system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
102system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
103system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
104system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
105system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
106system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
107system.cpu_clk_domain.clock 500 # Clock period in ticks
108system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
109system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
110system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
111system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
112system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
113system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
114system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
116system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
117system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
118system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
119system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
120system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
121system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
122system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
123system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
124system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
125system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
126system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
127system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
128system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
137system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
138system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
139system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
140system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
141system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
145system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
146system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
147system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
148system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
149system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
150system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
151system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
152system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
153system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
154system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
155system.cpu0.dtb.inst_hits 0 # ITB inst hits
156system.cpu0.dtb.inst_misses 0 # ITB inst misses
157system.cpu0.dtb.read_hits 92662773 # DTB read hits
158system.cpu0.dtb.read_misses 88786 # DTB read misses
159system.cpu0.dtb.write_hits 85694958 # DTB write hits
160system.cpu0.dtb.write_misses 36443 # DTB write misses
161system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
162system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
163system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
164system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
165system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
166system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
167system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
169system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
170system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
171system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
173system.cpu0.dtb.hits 178357731 # DTB hits
174system.cpu0.dtb.misses 125229 # DTB misses
175system.cpu0.dtb.accesses 178482960 # DTB accesses
176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
184system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
185system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
186system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
187system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
188system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
189system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
190system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
191system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
192system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
193system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
194system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
195system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
196system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
205system.cpu0.itb.walker.walks 61377 # Table walker walks requested
206system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
207system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
208system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
209system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
213system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
214system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
215system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
216system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
217system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
218system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
219system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
220system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
221system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
222system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
223system.cpu0.itb.inst_hits 497696393 # ITB inst hits
224system.cpu0.itb.inst_misses 61377 # ITB inst misses
225system.cpu0.itb.read_hits 0 # DTB read hits
226system.cpu0.itb.read_misses 0 # DTB read misses
227system.cpu0.itb.write_hits 0 # DTB write hits
228system.cpu0.itb.write_misses 0 # DTB write misses
229system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
230system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
231system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
232system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
233system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
234system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
235system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
238system.cpu0.itb.read_accesses 0 # DTB read accesses
239system.cpu0.itb.write_accesses 0 # DTB write accesses
240system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
241system.cpu0.itb.hits 497696393 # DTB hits
242system.cpu0.itb.misses 61377 # DTB misses
243system.cpu0.itb.accesses 497757770 # DTB accesses
244system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
247system.cpu0.committedInsts 497466384 # Number of instructions committed
248system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
249system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
250system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
251system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
252system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
253system.cpu0.num_int_insts 536103359 # number of integer instructions
254system.cpu0.num_fp_insts 526132 # number of float instructions
255system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
256system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
257system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
258system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
259system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
260system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
261system.cpu0.num_mem_refs 178459396 # number of memory refs
262system.cpu0.num_load_insts 92737001 # Number of load instructions
263system.cpu0.num_store_insts 85722395 # Number of store instructions
264system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
265system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
266system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
267system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
268system.cpu0.Branches 111287587 # Number of branches fetched
269system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
270system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
271system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
272system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
273system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
274system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
275system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
276system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
277system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
278system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
279system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
280system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
281system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
282system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
283system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
284system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
285system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
286system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
287system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
288system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
289system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
290system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
291system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
292system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
293system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
294system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
295system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
296system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
297system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
298system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
299system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
300system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
301system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
302system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
303system.cpu0.op_class::total 585300003 # Class of executed instruction
304system.cpu0.kern.inst.arm 0 # number of arm instructions executed
305system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
306system.cpu0.dcache.tags.replacements 6272773 # number of replacements
307system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
308system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks.
309system.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks.
310system.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks.
311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
314system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
320system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses
321system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses
322system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits
323system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits
324system.cpu0.dcache.WriteReq_hits::cpu0.data 80919787 # number of WriteReq hits
325system.cpu0.dcache.WriteReq_hits::total 80919787 # number of WriteReq hits
326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits
327system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits
328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262007 # number of WriteLineReq hits
329system.cpu0.dcache.WriteLineReq_hits::total 262007 # number of WriteLineReq hits
330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
331system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036572 # number of StoreCondReq hits
333system.cpu0.dcache.StoreCondReq_hits::total 2036572 # number of StoreCondReq hits
334system.cpu0.dcache.demand_hits::cpu0.data 167134698 # number of demand (read+write) hits
335system.cpu0.dcache.demand_hits::total 167134698 # number of demand (read+write) hits
336system.cpu0.dcache.overall_hits::cpu0.data 167350352 # number of overall hits
337system.cpu0.dcache.overall_hits::total 167350352 # number of overall hits
338system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses
339system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses
340system.cpu0.dcache.WriteReq_misses::cpu0.data 1475655 # number of WriteReq misses
341system.cpu0.dcache.WriteReq_misses::total 1475655 # number of WriteReq misses
342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses
343system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses
344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831713 # number of WriteLineReq misses
345system.cpu0.dcache.WriteLineReq_misses::total 831713 # number of WriteLineReq misses
346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
347system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158571 # number of StoreCondReq misses
349system.cpu0.dcache.StoreCondReq_misses::total 158571 # number of StoreCondReq misses
350system.cpu0.dcache.demand_misses::cpu0.data 4785037 # number of demand (read+write) misses
351system.cpu0.dcache.demand_misses::total 4785037 # number of demand (read+write) misses
352system.cpu0.dcache.overall_misses::cpu0.data 5557176 # number of overall misses
353system.cpu0.dcache.overall_misses::total 5557176 # number of overall misses
354system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses)
355system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses)
356system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses)
357system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses)
358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
359system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses)
361system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses)
362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
363system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
365system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
366system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses
367system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses
368system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses
369system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses
370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
371system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses
373system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses
374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses
375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses
376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760444 # miss rate for WriteLineReq accesses
377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760444 # miss rate for WriteLineReq accesses
378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses
381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses
382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses
383system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses
384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032140 # miss rate for overall accesses
385system.cpu0.dcache.overall_miss_rate::total 0.032140 # miss rate for overall accesses
386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
392system.cpu0.dcache.fast_writes 0 # number of fast writes performed
393system.cpu0.dcache.cache_copies 0 # number of cache copies performed
394system.cpu0.dcache.writebacks::writebacks 4472506 # number of writebacks
395system.cpu0.dcache.writebacks::total 4472506 # number of writebacks
396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
397system.cpu0.icache.tags.replacements 5539081 # number of replacements
398system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
399system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
400system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
401system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
405system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
406system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
407system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
408system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
409system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
410system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
411system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
412system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
413system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
414system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits
415system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits
416system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits
417system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits
418system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits
419system.cpu0.icache.overall_hits::total 492212891 # number of overall hits
420system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses
421system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses
422system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses
423system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses
424system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses
425system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
426system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses)
427system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
428system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
429system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
430system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
431system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
432system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
433system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
434system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
435system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
436system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
437system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
438system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
439system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
440system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
441system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
442system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
443system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
444system.cpu0.icache.fast_writes 0 # number of fast writes performed
445system.cpu0.icache.cache_copies 0 # number of cache copies performed
446system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
447system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
448system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
449system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
450system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
451system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
452system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
453system.cpu0.l2cache.tags.replacements 2713035 # number of replacements
454system.cpu0.l2cache.tags.tagsinuse 16212.776574 # Cycle average of tags in use
455system.cpu0.l2cache.tags.total_refs 18780735 # Total number of references to valid blocks.
456system.cpu0.l2cache.tags.sampled_refs 2729020 # Sample count of references to valid blocks.
457system.cpu0.l2cache.tags.avg_refs 6.881861 # Average number of references to valid blocks.
458system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
459system.cpu0.l2cache.tags.occ_blocks::writebacks 5698.548759 # Average occupied blocks per requestor
460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.293580 # Average occupied blocks per requestor
461system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 53.073220 # Average occupied blocks per requestor
462system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4549.413482 # Average occupied blocks per requestor
463system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5859.447533 # Average occupied blocks per requestor
464system.cpu0.l2cache.tags.occ_percent::writebacks 0.347812 # Average percentage of cache occupancy
465system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003192 # Average percentage of cache occupancy
466system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003239 # Average percentage of cache occupancy
467system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.277674 # Average percentage of cache occupancy
468system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357632 # Average percentage of cache occupancy
469system.cpu0.l2cache.tags.occ_percent::total 0.989549 # Average percentage of cache occupancy
470system.cpu0.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id
471system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id
472system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id
473system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
474system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
475system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
476system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1169 # Occupied blocks per task id
477system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4652 # Occupied blocks per task id
478system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5280 # Occupied blocks per task id
479system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4600 # Occupied blocks per task id
480system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id
481system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id
482system.cpu0.l2cache.tags.tag_accesses 396071662 # Number of tag accesses
483system.cpu0.l2cache.tags.data_accesses 396071662 # Number of data accesses
484system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267140 # number of ReadReq hits
485system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140047 # number of ReadReq hits
486system.cpu0.l2cache.ReadReq_hits::total 407187 # number of ReadReq hits
487system.cpu0.l2cache.Writeback_hits::writebacks 4472506 # number of Writeback hits
488system.cpu0.l2cache.Writeback_hits::total 4472506 # number of Writeback hits
489system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3480 # number of UpgradeReq hits
490system.cpu0.l2cache.UpgradeReq_hits::total 3480 # number of UpgradeReq hits
491system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634900 # number of ReadExReq hits
492system.cpu0.l2cache.ReadExReq_hits::total 634900 # number of ReadExReq hits
493system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4970860 # number of ReadCleanReq hits
494system.cpu0.l2cache.ReadCleanReq_hits::total 4970860 # number of ReadCleanReq hits
495system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2942102 # number of ReadSharedReq hits
496system.cpu0.l2cache.ReadSharedReq_hits::total 2942102 # number of ReadSharedReq hits
497system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223126 # number of InvalidateReq hits
498system.cpu0.l2cache.InvalidateReq_hits::total 223126 # number of InvalidateReq hits
499system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267140 # number of demand (read+write) hits
500system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140047 # number of demand (read+write) hits
501system.cpu0.l2cache.demand_hits::cpu0.inst 4970860 # number of demand (read+write) hits
502system.cpu0.l2cache.demand_hits::cpu0.data 3577002 # number of demand (read+write) hits
503system.cpu0.l2cache.demand_hits::total 8955049 # number of demand (read+write) hits
504system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267140 # number of overall hits
505system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140047 # number of overall hits
506system.cpu0.l2cache.overall_hits::cpu0.inst 4970860 # number of overall hits
507system.cpu0.l2cache.overall_hits::cpu0.data 3577002 # number of overall hits
508system.cpu0.l2cache.overall_hits::total 8955049 # number of overall hits
509system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11279 # number of ReadReq misses
510system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8435 # number of ReadReq misses
511system.cpu0.l2cache.ReadReq_misses::total 19714 # number of ReadReq misses
512system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128321 # number of UpgradeReq misses
513system.cpu0.l2cache.UpgradeReq_misses::total 128321 # number of UpgradeReq misses
514system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158571 # number of SCUpgradeReq misses
515system.cpu0.l2cache.SCUpgradeReq_misses::total 158571 # number of SCUpgradeReq misses
516system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709333 # number of ReadExReq misses
517system.cpu0.l2cache.ReadExReq_misses::total 709333 # number of ReadExReq misses
518system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568738 # number of ReadCleanReq misses
519system.cpu0.l2cache.ReadCleanReq_misses::total 568738 # number of ReadCleanReq misses
520system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1259235 # number of ReadSharedReq misses
521system.cpu0.l2cache.ReadSharedReq_misses::total 1259235 # number of ReadSharedReq misses
522system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608208 # number of InvalidateReq misses
523system.cpu0.l2cache.InvalidateReq_misses::total 608208 # number of InvalidateReq misses
524system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11279 # number of demand (read+write) misses
525system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8435 # number of demand (read+write) misses
526system.cpu0.l2cache.demand_misses::cpu0.inst 568738 # number of demand (read+write) misses
527system.cpu0.l2cache.demand_misses::cpu0.data 1968568 # number of demand (read+write) misses
528system.cpu0.l2cache.demand_misses::total 2557020 # number of demand (read+write) misses
529system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11279 # number of overall misses
530system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8435 # number of overall misses
531system.cpu0.l2cache.overall_misses::cpu0.inst 568738 # number of overall misses
532system.cpu0.l2cache.overall_misses::cpu0.data 1968568 # number of overall misses
533system.cpu0.l2cache.overall_misses::total 2557020 # number of overall misses
534system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278419 # number of ReadReq accesses(hits+misses)
535system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148482 # number of ReadReq accesses(hits+misses)
536system.cpu0.l2cache.ReadReq_accesses::total 426901 # number of ReadReq accesses(hits+misses)
537system.cpu0.l2cache.Writeback_accesses::writebacks 4472506 # number of Writeback accesses(hits+misses)
538system.cpu0.l2cache.Writeback_accesses::total 4472506 # number of Writeback accesses(hits+misses)
539system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131801 # number of UpgradeReq accesses(hits+misses)
540system.cpu0.l2cache.UpgradeReq_accesses::total 131801 # number of UpgradeReq accesses(hits+misses)
541system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158571 # number of SCUpgradeReq accesses(hits+misses)
542system.cpu0.l2cache.SCUpgradeReq_accesses::total 158571 # number of SCUpgradeReq accesses(hits+misses)
543system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344233 # number of ReadExReq accesses(hits+misses)
544system.cpu0.l2cache.ReadExReq_accesses::total 1344233 # number of ReadExReq accesses(hits+misses)
545system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses)
546system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses)
547system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses)
548system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses)
549system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831334 # number of InvalidateReq accesses(hits+misses)
550system.cpu0.l2cache.InvalidateReq_accesses::total 831334 # number of InvalidateReq accesses(hits+misses)
551system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278419 # number of demand (read+write) accesses
552system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148482 # number of demand (read+write) accesses
553system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
554system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses
555system.cpu0.l2cache.demand_accesses::total 11512069 # number of demand (read+write) accesses
556system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278419 # number of overall (read+write) accesses
557system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148482 # number of overall (read+write) accesses
558system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
559system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses
560system.cpu0.l2cache.overall_accesses::total 11512069 # number of overall (read+write) accesses
561system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for ReadReq accesses
562system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056808 # miss rate for ReadReq accesses
563system.cpu0.l2cache.ReadReq_miss_rate::total 0.046179 # miss rate for ReadReq accesses
564system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973597 # miss rate for UpgradeReq accesses
565system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973597 # miss rate for UpgradeReq accesses
566system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
567system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
568system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527686 # miss rate for ReadExReq accesses
569system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527686 # miss rate for ReadExReq accesses
570system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102668 # miss rate for ReadCleanReq accesses
571system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102668 # miss rate for ReadCleanReq accesses
572system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299722 # miss rate for ReadSharedReq accesses
573system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299722 # miss rate for ReadSharedReq accesses
574system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731605 # miss rate for InvalidateReq accesses
575system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731605 # miss rate for InvalidateReq accesses
576system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for demand accesses
577system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056808 # miss rate for demand accesses
578system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102668 # miss rate for demand accesses
579system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354980 # miss rate for demand accesses
580system.cpu0.l2cache.demand_miss_rate::total 0.222116 # miss rate for demand accesses
581system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for overall accesses
582system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056808 # miss rate for overall accesses
583system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102668 # miss rate for overall accesses
584system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354980 # miss rate for overall accesses
585system.cpu0.l2cache.overall_miss_rate::total 0.222116 # miss rate for overall accesses
586system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
587system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
588system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
589system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
590system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
591system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
592system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
593system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
594system.cpu0.l2cache.writebacks::writebacks 1573891 # number of writebacks
595system.cpu0.l2cache.writebacks::total 1573891 # number of writebacks
596system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
597system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution
598system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution
599system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution
600system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution
601system.cpu0.toL2Bus.trans_dist::Writeback 4472506 # Transaction distribution
602system.cpu0.toL2Bus.trans_dist::CleanEvict 7339348 # Transaction distribution
603system.cpu0.toL2Bus.trans_dist::UpgradeReq 131801 # Transaction distribution
604system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158571 # Transaction distribution
605system.cpu0.toL2Bus.trans_dist::UpgradeResp 290372 # Transaction distribution
606system.cpu0.toL2Bus.trans_dist::ReadExReq 1344233 # Transaction distribution
607system.cpu0.toL2Bus.trans_dist::ReadExResp 1344233 # Transaction distribution
608system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution
609system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution
610system.cpu0.toL2Bus.trans_dist::InvalidateReq 831334 # Transaction distribution
611system.cpu0.toL2Bus.trans_dist::InvalidateResp 831334 # Transaction distribution
612system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16704527 # Packet count per connected master and slave (bytes)
613system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19737201 # Packet count per connected master and slave (bytes)
614system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
615system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
616system.cpu0.toL2Bus.pkt_count::total 37536458 # Packet count per connected master and slave (bytes)
617system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
618system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641350217 # Cumulative packet size per connected master and slave (bytes)
619system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
620system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
621system.cpu0.toL2Bus.pkt_size::total 1000435909 # Cumulative packet size per connected master and slave (bytes)
622system.cpu0.toL2Bus.snoops 3360861 # Total snoops (count)
623system.cpu0.toL2Bus.snoop_fanout::samples 27849165 # Request fanout histogram
624system.cpu0.toL2Bus.snoop_fanout::mean 1.133662 # Request fanout histogram
625system.cpu0.toL2Bus.snoop_fanout::stdev 0.340289 # Request fanout histogram
626system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
627system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
628system.cpu0.toL2Bus.snoop_fanout::1 24126791 86.63% 86.63% # Request fanout histogram
629system.cpu0.toL2Bus.snoop_fanout::2 3722374 13.37% 100.00% # Request fanout histogram
630system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
631system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
632system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
633system.cpu0.toL2Bus.snoop_fanout::total 27849165 # Request fanout histogram
634system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
641system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
642system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
643system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
644system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
645system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
646system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
647system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
648system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
649system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
650system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
651system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
652system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
653system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
654system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
655system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
656system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
657system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
658system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
659system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
660system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
661system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
662system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
663system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
664system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
665system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
666system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
667system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
668system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
669system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
670system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
671system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
672system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
673system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
674system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
675system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
676system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
677system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
678system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
679system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
680system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
681system.cpu1.dtb.inst_hits 0 # ITB inst hits
682system.cpu1.dtb.inst_misses 0 # ITB inst misses
683system.cpu1.dtb.read_hits 90153061 # DTB read hits
684system.cpu1.dtb.read_misses 111753 # DTB read misses
685system.cpu1.dtb.write_hits 81132787 # DTB write hits
686system.cpu1.dtb.write_misses 32288 # DTB write misses
687system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
688system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
689system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
690system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
691system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
692system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
693system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
694system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
695system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
696system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
697system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
698system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
699system.cpu1.dtb.hits 171285848 # DTB hits
700system.cpu1.dtb.misses 144041 # DTB misses
701system.cpu1.dtb.accesses 171429889 # DTB accesses
702system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
710system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
711system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
712system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
713system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
714system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
715system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
716system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
717system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
718system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
719system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
720system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
721system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
722system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
723system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
724system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
725system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
726system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
727system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
728system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
729system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
730system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
731system.cpu1.itb.walker.walks 60885 # Table walker walks requested
732system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
733system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
734system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
735system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
736system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
737system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
738system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
739system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
740system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
741system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
742system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
743system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
744system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
745system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
746system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
747system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
748system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
749system.cpu1.itb.inst_hits 478248118 # ITB inst hits
750system.cpu1.itb.inst_misses 60885 # ITB inst misses
751system.cpu1.itb.read_hits 0 # DTB read hits
752system.cpu1.itb.read_misses 0 # DTB read misses
753system.cpu1.itb.write_hits 0 # DTB write hits
754system.cpu1.itb.write_misses 0 # DTB write misses
755system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
756system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
757system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
758system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
759system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
760system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
761system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
762system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
763system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
764system.cpu1.itb.read_accesses 0 # DTB read accesses
765system.cpu1.itb.write_accesses 0 # DTB write accesses
766system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
767system.cpu1.itb.hits 478248118 # DTB hits
768system.cpu1.itb.misses 60885 # DTB misses
769system.cpu1.itb.accesses 478309003 # DTB accesses
770system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
771system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
772system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
773system.cpu1.committedInsts 477990846 # Number of instructions committed
774system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
775system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
776system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
777system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
778system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
779system.cpu1.num_int_insts 516282159 # number of integer instructions
780system.cpu1.num_fp_insts 374678 # number of float instructions
781system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
782system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
783system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
784system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
785system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
786system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
787system.cpu1.num_mem_refs 171406825 # number of memory refs
788system.cpu1.num_load_insts 90251973 # Number of load instructions
789system.cpu1.num_store_insts 81154852 # Number of store instructions
790system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
791system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
792system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
793system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
794system.cpu1.Branches 106497601 # Number of branches fetched
795system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
796system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
797system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
798system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
799system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
800system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
801system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
802system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
803system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
804system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
805system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
806system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
807system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
808system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
809system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
810system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
811system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
812system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
813system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
814system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
815system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
816system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
817system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
818system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
819system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
820system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
821system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
822system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
823system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
824system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
825system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
826system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
827system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
828system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
829system.cpu1.op_class::total 562879339 # Class of executed instruction
830system.cpu1.kern.inst.arm 0 # number of arm instructions executed
831system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
832system.cpu1.dcache.tags.replacements 5945049 # number of replacements
833system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
834system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
835system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
836system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
837system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
838system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
839system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
840system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
841system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
842system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
843system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
844system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
845system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
846system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
847system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
848system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
849system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
850system.cpu1.dcache.WriteReq_hits::cpu1.data 76990238 # number of WriteReq hits
851system.cpu1.dcache.WriteReq_hits::total 76990238 # number of WriteReq hits
852system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
853system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
854system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits
855system.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits
856system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
857system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
858system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048840 # number of StoreCondReq hits
859system.cpu1.dcache.StoreCondReq_hits::total 2048840 # number of StoreCondReq hits
860system.cpu1.dcache.demand_hits::cpu1.data 160687802 # number of demand (read+write) hits
861system.cpu1.dcache.demand_hits::total 160687802 # number of demand (read+write) hits
862system.cpu1.dcache.overall_hits::cpu1.data 160875656 # number of overall hits
863system.cpu1.dcache.overall_hits::total 160875656 # number of overall hits
864system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
865system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
866system.cpu1.dcache.WriteReq_misses::cpu1.data 1453238 # number of WriteReq misses
867system.cpu1.dcache.WriteReq_misses::total 1453238 # number of WriteReq misses
868system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
869system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
870system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses
871system.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses
872system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
873system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
874system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158909 # number of StoreCondReq misses
875system.cpu1.dcache.StoreCondReq_misses::total 158909 # number of StoreCondReq misses
876system.cpu1.dcache.demand_misses::cpu1.data 4811460 # number of demand (read+write) misses
877system.cpu1.dcache.demand_misses::total 4811460 # number of demand (read+write) misses
878system.cpu1.dcache.overall_misses::cpu1.data 5603811 # number of overall misses
879system.cpu1.dcache.overall_misses::total 5603811 # number of overall misses
880system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
881system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
882system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
883system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
884system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
885system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
886system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses)
887system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses)
888system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
889system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
890system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
891system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
892system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
893system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
894system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
895system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
896system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
897system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
898system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018526 # miss rate for WriteReq accesses
899system.cpu1.dcache.WriteReq_miss_rate::total 0.018526 # miss rate for WriteReq accesses
900system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
901system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
902system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses
903system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses
904system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
905system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
906system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071978 # miss rate for StoreCondReq accesses
907system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071978 # miss rate for StoreCondReq accesses
908system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses
909system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses
910system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses
911system.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses
912system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
913system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
914system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
915system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
916system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
917system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
918system.cpu1.dcache.fast_writes 0 # number of fast writes performed
919system.cpu1.dcache.cache_copies 0 # number of cache copies performed
920system.cpu1.dcache.writebacks::writebacks 4032489 # number of writebacks
921system.cpu1.dcache.writebacks::total 4032489 # number of writebacks
922system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
923system.cpu1.icache.tags.replacements 4741297 # number of replacements
924system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
925system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
926system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
927system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
928system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
929system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
930system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
931system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
932system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
933system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
934system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
935system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
936system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
937system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
938system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
939system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
940system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
941system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
942system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
943system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
944system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
945system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
946system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
947system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
948system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
949system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
950system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
951system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
952system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
953system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
954system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
955system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
956system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
957system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
958system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
959system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
960system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
961system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
962system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
963system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
964system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
965system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
966system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
967system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
968system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
969system.cpu1.icache.fast_writes 0 # number of fast writes performed
970system.cpu1.icache.cache_copies 0 # number of cache copies performed
971system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
972system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
973system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
974system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
975system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
976system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
977system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
978system.cpu1.l2cache.tags.replacements 2278625 # number of replacements
979system.cpu1.l2cache.tags.tagsinuse 13455.366056 # Cycle average of tags in use
980system.cpu1.l2cache.tags.total_refs 17413486 # Total number of references to valid blocks.
981system.cpu1.l2cache.tags.sampled_refs 2294680 # Sample count of references to valid blocks.
982system.cpu1.l2cache.tags.avg_refs 7.588634 # Average number of references to valid blocks.
983system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit.
984system.cpu1.l2cache.tags.occ_blocks::writebacks 5192.867159 # Average occupied blocks per requestor
985system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.806245 # Average occupied blocks per requestor
986system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 99.441300 # Average occupied blocks per requestor
987system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2834.629918 # Average occupied blocks per requestor
988system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5261.621433 # Average occupied blocks per requestor
989system.cpu1.l2cache.tags.occ_percent::writebacks 0.316947 # Average percentage of cache occupancy
990system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004078 # Average percentage of cache occupancy
991system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006069 # Average percentage of cache occupancy
992system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173012 # Average percentage of cache occupancy
993system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.321144 # Average percentage of cache occupancy
994system.cpu1.l2cache.tags.occ_percent::total 0.821250 # Average percentage of cache occupancy
995system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id
996system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id
997system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
998system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
999system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
1000system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
1001system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id
1002system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
1003system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1614 # Occupied blocks per task id
1004system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5923 # Occupied blocks per task id
1005system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id
1006system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3815 # Occupied blocks per task id
1007system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id
1008system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id
1009system.cpu1.l2cache.tags.tag_accesses 360485676 # Number of tag accesses
1010system.cpu1.l2cache.tags.data_accesses 360485676 # Number of data accesses
1011system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324846 # number of ReadReq hits
1012system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140054 # number of ReadReq hits
1013system.cpu1.l2cache.ReadReq_hits::total 464900 # number of ReadReq hits
1014system.cpu1.l2cache.Writeback_hits::writebacks 4032489 # number of Writeback hits
1015system.cpu1.l2cache.Writeback_hits::total 4032489 # number of Writeback hits
1016system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3822 # number of UpgradeReq hits
1017system.cpu1.l2cache.UpgradeReq_hits::total 3822 # number of UpgradeReq hits
1018system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614016 # number of ReadExReq hits
1019system.cpu1.l2cache.ReadExReq_hits::total 614016 # number of ReadExReq hits
1020system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4217303 # number of ReadCleanReq hits
1021system.cpu1.l2cache.ReadCleanReq_hits::total 4217303 # number of ReadCleanReq hits
1022system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057649 # number of ReadSharedReq hits
1023system.cpu1.l2cache.ReadSharedReq_hits::total 3057649 # number of ReadSharedReq hits
1024system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161208 # number of InvalidateReq hits
1025system.cpu1.l2cache.InvalidateReq_hits::total 161208 # number of InvalidateReq hits
1026system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324846 # number of demand (read+write) hits
1027system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140054 # number of demand (read+write) hits
1028system.cpu1.l2cache.demand_hits::cpu1.inst 4217303 # number of demand (read+write) hits
1029system.cpu1.l2cache.demand_hits::cpu1.data 3671665 # number of demand (read+write) hits
1030system.cpu1.l2cache.demand_hits::total 8353868 # number of demand (read+write) hits
1031system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324846 # number of overall hits
1032system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140054 # number of overall hits
1033system.cpu1.l2cache.overall_hits::cpu1.inst 4217303 # number of overall hits
1034system.cpu1.l2cache.overall_hits::cpu1.data 3671665 # number of overall hits
1035system.cpu1.l2cache.overall_hits::total 8353868 # number of overall hits
1036system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12306 # number of ReadReq misses
1037system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9777 # number of ReadReq misses
1038system.cpu1.l2cache.ReadReq_misses::total 22083 # number of ReadReq misses
1039system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133739 # number of UpgradeReq misses
1040system.cpu1.l2cache.UpgradeReq_misses::total 133739 # number of UpgradeReq misses
1041system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158909 # number of SCUpgradeReq misses
1042system.cpu1.l2cache.SCUpgradeReq_misses::total 158909 # number of SCUpgradeReq misses
1043system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701874 # number of ReadExReq misses
1044system.cpu1.l2cache.ReadExReq_misses::total 701874 # number of ReadExReq misses
1045system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 524506 # number of ReadCleanReq misses
1046system.cpu1.l2cache.ReadCleanReq_misses::total 524506 # number of ReadCleanReq misses
1047system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239744 # number of ReadSharedReq misses
1048system.cpu1.l2cache.ReadSharedReq_misses::total 1239744 # number of ReadSharedReq misses
1049system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265638 # number of InvalidateReq misses
1050system.cpu1.l2cache.InvalidateReq_misses::total 265638 # number of InvalidateReq misses
1051system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12306 # number of demand (read+write) misses
1052system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9777 # number of demand (read+write) misses
1053system.cpu1.l2cache.demand_misses::cpu1.inst 524506 # number of demand (read+write) misses
1054system.cpu1.l2cache.demand_misses::cpu1.data 1941618 # number of demand (read+write) misses
1055system.cpu1.l2cache.demand_misses::total 2488207 # number of demand (read+write) misses
1056system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12306 # number of overall misses
1057system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9777 # number of overall misses
1058system.cpu1.l2cache.overall_misses::cpu1.inst 524506 # number of overall misses
1059system.cpu1.l2cache.overall_misses::cpu1.data 1941618 # number of overall misses
1060system.cpu1.l2cache.overall_misses::total 2488207 # number of overall misses
1061system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337152 # number of ReadReq accesses(hits+misses)
1062system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149831 # number of ReadReq accesses(hits+misses)
1063system.cpu1.l2cache.ReadReq_accesses::total 486983 # number of ReadReq accesses(hits+misses)
1064system.cpu1.l2cache.Writeback_accesses::writebacks 4032489 # number of Writeback accesses(hits+misses)
1065system.cpu1.l2cache.Writeback_accesses::total 4032489 # number of Writeback accesses(hits+misses)
1066system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137561 # number of UpgradeReq accesses(hits+misses)
1067system.cpu1.l2cache.UpgradeReq_accesses::total 137561 # number of UpgradeReq accesses(hits+misses)
1068system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158909 # number of SCUpgradeReq accesses(hits+misses)
1069system.cpu1.l2cache.SCUpgradeReq_accesses::total 158909 # number of SCUpgradeReq accesses(hits+misses)
1070system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
1071system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
1072system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses)
1073system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses)
1074system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses)
1075system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses)
1076system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses)
1077system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses)
1078system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337152 # number of demand (read+write) accesses
1079system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149831 # number of demand (read+write) accesses
1080system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
1081system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
1082system.cpu1.l2cache.demand_accesses::total 10842075 # number of demand (read+write) accesses
1083system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337152 # number of overall (read+write) accesses
1084system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149831 # number of overall (read+write) accesses
1085system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
1086system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
1087system.cpu1.l2cache.overall_accesses::total 10842075 # number of overall (read+write) accesses
1088system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for ReadReq accesses
1089system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065254 # miss rate for ReadReq accesses
1090system.cpu1.l2cache.ReadReq_miss_rate::total 0.045347 # miss rate for ReadReq accesses
1091system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972216 # miss rate for UpgradeReq accesses
1092system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972216 # miss rate for UpgradeReq accesses
1093system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1094system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1095system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533383 # miss rate for ReadExReq accesses
1096system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533383 # miss rate for ReadExReq accesses
1097system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110613 # miss rate for ReadCleanReq accesses
1098system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110613 # miss rate for ReadCleanReq accesses
1099system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288487 # miss rate for ReadSharedReq accesses
1100system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288487 # miss rate for ReadSharedReq accesses
1101system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622327 # miss rate for InvalidateReq accesses
1102system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622327 # miss rate for InvalidateReq accesses
1103system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for demand accesses
1104system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065254 # miss rate for demand accesses
1105system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110613 # miss rate for demand accesses
1106system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345897 # miss rate for demand accesses
1107system.cpu1.l2cache.demand_miss_rate::total 0.229495 # miss rate for demand accesses
1108system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for overall accesses
1109system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065254 # miss rate for overall accesses
1110system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110613 # miss rate for overall accesses
1111system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345897 # miss rate for overall accesses
1112system.cpu1.l2cache.overall_miss_rate::total 0.229495 # miss rate for overall accesses
1113system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1114system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1115system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1116system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1117system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1118system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1119system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1120system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1121system.cpu1.l2cache.writebacks::writebacks 1184748 # number of writebacks
1122system.cpu1.l2cache.writebacks::total 1184748 # number of writebacks
1123system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1124system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution
1125system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
1126system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
1127system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
1128system.cpu1.toL2Bus.trans_dist::Writeback 4032489 # Transaction distribution
1129system.cpu1.toL2Bus.trans_dist::CleanEvict 6653857 # Transaction distribution
1130system.cpu1.toL2Bus.trans_dist::UpgradeReq 137561 # Transaction distribution
1131system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158909 # Transaction distribution
1132system.cpu1.toL2Bus.trans_dist::UpgradeResp 296470 # Transaction distribution
1133system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
1134system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
1135system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution
1136system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution
1137system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution
1138system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution
1139system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225175 # Packet count per connected master and slave (bytes)
1140system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643731 # Packet count per connected master and slave (bytes)
1141system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
1142system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
1143system.cpu1.toL2Bus.pkt_count::total 34068350 # Packet count per connected master and slave (bytes)
1144system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
1145system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617367804 # Cumulative packet size per connected master and slave (bytes)
1146system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
1147system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
1148system.cpu1.toL2Bus.pkt_size::total 925641876 # Cumulative packet size per connected master and slave (bytes)
1149system.cpu1.toL2Bus.snoops 3842126 # Total snoops (count)
1150system.cpu1.toL2Bus.snoop_fanout::samples 26053175 # Request fanout histogram
1151system.cpu1.toL2Bus.snoop_fanout::mean 1.164109 # Request fanout histogram
1152system.cpu1.toL2Bus.snoop_fanout::stdev 0.370374 # Request fanout histogram
1153system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1154system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1155system.cpu1.toL2Bus.snoop_fanout::1 21777626 83.59% 83.59% # Request fanout histogram
1156system.cpu1.toL2Bus.snoop_fanout::2 4275549 16.41% 100.00% # Request fanout histogram
1157system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1158system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1159system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1160system.cpu1.toL2Bus.snoop_fanout::total 26053175 # Request fanout histogram
1161system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
1162system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
1163system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
1164system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
1165system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
1166system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1167system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1168system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1169system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1170system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1171system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1172system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1173system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1174system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1175system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
1176system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1177system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1178system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1179system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1180system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
1181system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
1182system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
1183system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1184system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1185system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
1186system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
1187system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1188system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1189system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1190system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1191system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1192system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1193system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1194system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1195system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1196system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
1197system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1198system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1199system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1200system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1201system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
1202system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
1203system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
1204system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1205system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1206system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
1207system.iocache.tags.replacements 115585 # number of replacements
1208system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
1209system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1210system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
1211system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1212system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
1213system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
1214system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
1215system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
1216system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
1217system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
1218system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1219system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1220system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1221system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
1222system.iocache.tags.data_accesses 1040793 # Number of data accesses
1223system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1224system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
1225system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
1226system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1227system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1228system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
1229system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
1230system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1231system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
1232system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
1233system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1234system.iocache.overall_misses::realview.ide 8876 # number of overall misses
1235system.iocache.overall_misses::total 8916 # number of overall misses
1236system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1237system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
1238system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
1239system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1240system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1241system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
1242system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
1243system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1244system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
1245system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
1246system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1247system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
1248system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
1249system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1250system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1251system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1252system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1253system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1254system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1255system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1256system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1257system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1258system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1259system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1260system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1261system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1262system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1263system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1264system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1265system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1266system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1267system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1268system.iocache.fast_writes 0 # number of fast writes performed
1269system.iocache.cache_copies 0 # number of cache copies performed
1270system.iocache.writebacks::writebacks 106694 # number of writebacks
1271system.iocache.writebacks::total 106694 # number of writebacks
1272system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1273system.l2c.tags.replacements 1751385 # number of replacements
1274system.l2c.tags.tagsinuse 62313.380560 # Cycle average of tags in use
1275system.l2c.tags.total_refs 6017106 # Total number of references to valid blocks.
1276system.l2c.tags.sampled_refs 1809468 # Sample count of references to valid blocks.
1277system.l2c.tags.avg_refs 3.325345 # Average number of references to valid blocks.
1278system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1279system.l2c.tags.occ_blocks::writebacks 34286.931814 # Average occupied blocks per requestor
1280system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.043983 # Average occupied blocks per requestor
1281system.l2c.tags.occ_blocks::cpu0.itb.walker 59.106418 # Average occupied blocks per requestor
1282system.l2c.tags.occ_blocks::cpu0.inst 3327.548165 # Average occupied blocks per requestor
1283system.l2c.tags.occ_blocks::cpu0.data 6997.138223 # Average occupied blocks per requestor
1284system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.986034 # Average occupied blocks per requestor
1285system.l2c.tags.occ_blocks::cpu1.itb.walker 428.835942 # Average occupied blocks per requestor
1286system.l2c.tags.occ_blocks::cpu1.inst 3021.438473 # Average occupied blocks per requestor
1287system.l2c.tags.occ_blocks::cpu1.data 13835.351509 # Average occupied blocks per requestor
1288system.l2c.tags.occ_percent::writebacks 0.523177 # Average percentage of cache occupancy
1289system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000718 # Average percentage of cache occupancy
1290system.l2c.tags.occ_percent::cpu0.itb.walker 0.000902 # Average percentage of cache occupancy
1291system.l2c.tags.occ_percent::cpu0.inst 0.050774 # Average percentage of cache occupancy
1292system.l2c.tags.occ_percent::cpu0.data 0.106768 # Average percentage of cache occupancy
1293system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004730 # Average percentage of cache occupancy
1294system.l2c.tags.occ_percent::cpu1.itb.walker 0.006544 # Average percentage of cache occupancy
1295system.l2c.tags.occ_percent::cpu1.inst 0.046103 # Average percentage of cache occupancy
1296system.l2c.tags.occ_percent::cpu1.data 0.211111 # Average percentage of cache occupancy
1297system.l2c.tags.occ_percent::total 0.950827 # Average percentage of cache occupancy
1298system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id
1299system.l2c.tags.occ_task_id_blocks::1024 57863 # Occupied blocks per task id
1300system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
1301system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id
1302system.l2c.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
1303system.l2c.tags.age_task_id_blocks_1024::1 545 # Occupied blocks per task id
1304system.l2c.tags.age_task_id_blocks_1024::2 3434 # Occupied blocks per task id
1305system.l2c.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id
1306system.l2c.tags.age_task_id_blocks_1024::4 48241 # Occupied blocks per task id
1307system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
1308system.l2c.tags.occ_task_id_percent::1024 0.882919 # Percentage of cache occupancy per task id
1309system.l2c.tags.tag_accesses 85814440 # Number of tag accesses
1310system.l2c.tags.data_accesses 85814440 # Number of data accesses
1311system.l2c.Writeback_hits::writebacks 2758639 # number of Writeback hits
1312system.l2c.Writeback_hits::total 2758639 # number of Writeback hits
1313system.l2c.UpgradeReq_hits::cpu0.data 13259 # number of UpgradeReq hits
1314system.l2c.UpgradeReq_hits::cpu1.data 10916 # number of UpgradeReq hits
1315system.l2c.UpgradeReq_hits::total 24175 # number of UpgradeReq hits
1316system.l2c.SCUpgradeReq_hits::cpu0.data 1481 # number of SCUpgradeReq hits
1317system.l2c.SCUpgradeReq_hits::cpu1.data 1240 # number of SCUpgradeReq hits
1318system.l2c.SCUpgradeReq_hits::total 2721 # number of SCUpgradeReq hits
1319system.l2c.ReadExReq_hits::cpu0.data 318588 # number of ReadExReq hits
1320system.l2c.ReadExReq_hits::cpu1.data 264415 # number of ReadExReq hits
1321system.l2c.ReadExReq_hits::total 583003 # number of ReadExReq hits
1322system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6289 # number of ReadSharedReq hits
1323system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4561 # number of ReadSharedReq hits
1324system.l2c.ReadSharedReq_hits::cpu0.inst 514584 # number of ReadSharedReq hits
1325system.l2c.ReadSharedReq_hits::cpu0.data 748348 # number of ReadSharedReq hits
1326system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5382 # number of ReadSharedReq hits
1327system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3638 # number of ReadSharedReq hits
1328system.l2c.ReadSharedReq_hits::cpu1.inst 486810 # number of ReadSharedReq hits
1329system.l2c.ReadSharedReq_hits::cpu1.data 695012 # number of ReadSharedReq hits
1330system.l2c.ReadSharedReq_hits::total 2464624 # number of ReadSharedReq hits
1331system.l2c.demand_hits::cpu0.dtb.walker 6289 # number of demand (read+write) hits
1332system.l2c.demand_hits::cpu0.itb.walker 4561 # number of demand (read+write) hits
1333system.l2c.demand_hits::cpu0.inst 514584 # number of demand (read+write) hits
1334system.l2c.demand_hits::cpu0.data 1066936 # number of demand (read+write) hits
1335system.l2c.demand_hits::cpu1.dtb.walker 5382 # number of demand (read+write) hits
1336system.l2c.demand_hits::cpu1.itb.walker 3638 # number of demand (read+write) hits
1337system.l2c.demand_hits::cpu1.inst 486810 # number of demand (read+write) hits
1338system.l2c.demand_hits::cpu1.data 959427 # number of demand (read+write) hits
1339system.l2c.demand_hits::total 3047627 # number of demand (read+write) hits
1340system.l2c.overall_hits::cpu0.dtb.walker 6289 # number of overall hits
1341system.l2c.overall_hits::cpu0.itb.walker 4561 # number of overall hits
1342system.l2c.overall_hits::cpu0.inst 514584 # number of overall hits
1343system.l2c.overall_hits::cpu0.data 1066936 # number of overall hits
1344system.l2c.overall_hits::cpu1.dtb.walker 5382 # number of overall hits
1345system.l2c.overall_hits::cpu1.itb.walker 3638 # number of overall hits
1346system.l2c.overall_hits::cpu1.inst 486810 # number of overall hits
1347system.l2c.overall_hits::cpu1.data 959427 # number of overall hits
1348system.l2c.overall_hits::total 3047627 # number of overall hits
1349system.l2c.UpgradeReq_misses::cpu0.data 58599 # number of UpgradeReq misses
1350system.l2c.UpgradeReq_misses::cpu1.data 54084 # number of UpgradeReq misses
1351system.l2c.UpgradeReq_misses::total 112683 # number of UpgradeReq misses
1352system.l2c.SCUpgradeReq_misses::cpu0.data 7811 # number of SCUpgradeReq misses
1353system.l2c.SCUpgradeReq_misses::cpu1.data 7438 # number of SCUpgradeReq misses
1354system.l2c.SCUpgradeReq_misses::total 15249 # number of SCUpgradeReq misses
1355system.l2c.ReadExReq_misses::cpu0.data 816245 # number of ReadExReq misses
1356system.l2c.ReadExReq_misses::cpu1.data 547345 # number of ReadExReq misses
1357system.l2c.ReadExReq_misses::total 1363590 # number of ReadExReq misses
1358system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2379 # number of ReadSharedReq misses
1359system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1986 # number of ReadSharedReq misses
1360system.l2c.ReadSharedReq_misses::cpu0.inst 54154 # number of ReadSharedReq misses
1361system.l2c.ReadSharedReq_misses::cpu0.data 180703 # number of ReadSharedReq misses
1362system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3463 # number of ReadSharedReq misses
1363system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3437 # number of ReadSharedReq misses
1364system.l2c.ReadSharedReq_misses::cpu1.inst 37696 # number of ReadSharedReq misses
1365system.l2c.ReadSharedReq_misses::cpu1.data 186059 # number of ReadSharedReq misses
1366system.l2c.ReadSharedReq_misses::total 469877 # number of ReadSharedReq misses
1367system.l2c.demand_misses::cpu0.dtb.walker 2379 # number of demand (read+write) misses
1368system.l2c.demand_misses::cpu0.itb.walker 1986 # number of demand (read+write) misses
1369system.l2c.demand_misses::cpu0.inst 54154 # number of demand (read+write) misses
1370system.l2c.demand_misses::cpu0.data 996948 # number of demand (read+write) misses
1371system.l2c.demand_misses::cpu1.dtb.walker 3463 # number of demand (read+write) misses
1372system.l2c.demand_misses::cpu1.itb.walker 3437 # number of demand (read+write) misses
1373system.l2c.demand_misses::cpu1.inst 37696 # number of demand (read+write) misses
1374system.l2c.demand_misses::cpu1.data 733404 # number of demand (read+write) misses
1375system.l2c.demand_misses::total 1833467 # number of demand (read+write) misses
1376system.l2c.overall_misses::cpu0.dtb.walker 2379 # number of overall misses
1377system.l2c.overall_misses::cpu0.itb.walker 1986 # number of overall misses
1378system.l2c.overall_misses::cpu0.inst 54154 # number of overall misses
1379system.l2c.overall_misses::cpu0.data 996948 # number of overall misses
1380system.l2c.overall_misses::cpu1.dtb.walker 3463 # number of overall misses
1381system.l2c.overall_misses::cpu1.itb.walker 3437 # number of overall misses
1382system.l2c.overall_misses::cpu1.inst 37696 # number of overall misses
1383system.l2c.overall_misses::cpu1.data 733404 # number of overall misses
1384system.l2c.overall_misses::total 1833467 # number of overall misses
1385system.l2c.Writeback_accesses::writebacks 2758639 # number of Writeback accesses(hits+misses)
1386system.l2c.Writeback_accesses::total 2758639 # number of Writeback accesses(hits+misses)
1387system.l2c.UpgradeReq_accesses::cpu0.data 71858 # number of UpgradeReq accesses(hits+misses)
1388system.l2c.UpgradeReq_accesses::cpu1.data 65000 # number of UpgradeReq accesses(hits+misses)
1389system.l2c.UpgradeReq_accesses::total 136858 # number of UpgradeReq accesses(hits+misses)
1390system.l2c.SCUpgradeReq_accesses::cpu0.data 9292 # number of SCUpgradeReq accesses(hits+misses)
1391system.l2c.SCUpgradeReq_accesses::cpu1.data 8678 # number of SCUpgradeReq accesses(hits+misses)
1392system.l2c.SCUpgradeReq_accesses::total 17970 # number of SCUpgradeReq accesses(hits+misses)
1393system.l2c.ReadExReq_accesses::cpu0.data 1134833 # number of ReadExReq accesses(hits+misses)
1394system.l2c.ReadExReq_accesses::cpu1.data 811760 # number of ReadExReq accesses(hits+misses)
1395system.l2c.ReadExReq_accesses::total 1946593 # number of ReadExReq accesses(hits+misses)
1396system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses)
1397system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6547 # number of ReadSharedReq accesses(hits+misses)
1398system.l2c.ReadSharedReq_accesses::cpu0.inst 568738 # number of ReadSharedReq accesses(hits+misses)
1399system.l2c.ReadSharedReq_accesses::cpu0.data 929051 # number of ReadSharedReq accesses(hits+misses)
1400system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8845 # number of ReadSharedReq accesses(hits+misses)
1401system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7075 # number of ReadSharedReq accesses(hits+misses)
1402system.l2c.ReadSharedReq_accesses::cpu1.inst 524506 # number of ReadSharedReq accesses(hits+misses)
1403system.l2c.ReadSharedReq_accesses::cpu1.data 881071 # number of ReadSharedReq accesses(hits+misses)
1404system.l2c.ReadSharedReq_accesses::total 2934501 # number of ReadSharedReq accesses(hits+misses)
1405system.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses
1406system.l2c.demand_accesses::cpu0.itb.walker 6547 # number of demand (read+write) accesses
1407system.l2c.demand_accesses::cpu0.inst 568738 # number of demand (read+write) accesses
1408system.l2c.demand_accesses::cpu0.data 2063884 # number of demand (read+write) accesses
1409system.l2c.demand_accesses::cpu1.dtb.walker 8845 # number of demand (read+write) accesses
1410system.l2c.demand_accesses::cpu1.itb.walker 7075 # number of demand (read+write) accesses
1411system.l2c.demand_accesses::cpu1.inst 524506 # number of demand (read+write) accesses
1412system.l2c.demand_accesses::cpu1.data 1692831 # number of demand (read+write) accesses
1413system.l2c.demand_accesses::total 4881094 # number of demand (read+write) accesses
1414system.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses
1415system.l2c.overall_accesses::cpu0.itb.walker 6547 # number of overall (read+write) accesses
1416system.l2c.overall_accesses::cpu0.inst 568738 # number of overall (read+write) accesses
1417system.l2c.overall_accesses::cpu0.data 2063884 # number of overall (read+write) accesses
1418system.l2c.overall_accesses::cpu1.dtb.walker 8845 # number of overall (read+write) accesses
1419system.l2c.overall_accesses::cpu1.itb.walker 7075 # number of overall (read+write) accesses
1420system.l2c.overall_accesses::cpu1.inst 524506 # number of overall (read+write) accesses
1421system.l2c.overall_accesses::cpu1.data 1692831 # number of overall (read+write) accesses
1422system.l2c.overall_accesses::total 4881094 # number of overall (read+write) accesses
1423system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815483 # miss rate for UpgradeReq accesses
1424system.l2c.UpgradeReq_miss_rate::cpu1.data 0.832062 # miss rate for UpgradeReq accesses
1425system.l2c.UpgradeReq_miss_rate::total 0.823357 # miss rate for UpgradeReq accesses
1426system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.840616 # miss rate for SCUpgradeReq accesses
1427system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.857110 # miss rate for SCUpgradeReq accesses
1428system.l2c.SCUpgradeReq_miss_rate::total 0.848581 # miss rate for SCUpgradeReq accesses
1429system.l2c.ReadExReq_miss_rate::cpu0.data 0.719264 # miss rate for ReadExReq accesses
1430system.l2c.ReadExReq_miss_rate::cpu1.data 0.674269 # miss rate for ReadExReq accesses
1431system.l2c.ReadExReq_miss_rate::total 0.700501 # miss rate for ReadExReq accesses
1432system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for ReadSharedReq accesses
1433system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303345 # miss rate for ReadSharedReq accesses
1434system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095218 # miss rate for ReadSharedReq accesses
1435system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194503 # miss rate for ReadSharedReq accesses
1436system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for ReadSharedReq accesses
1437system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485795 # miss rate for ReadSharedReq accesses
1438system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071870 # miss rate for ReadSharedReq accesses
1439system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211174 # miss rate for ReadSharedReq accesses
1440system.l2c.ReadSharedReq_miss_rate::total 0.160122 # miss rate for ReadSharedReq accesses
1441system.l2c.demand_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for demand accesses
1442system.l2c.demand_miss_rate::cpu0.itb.walker 0.303345 # miss rate for demand accesses
1443system.l2c.demand_miss_rate::cpu0.inst 0.095218 # miss rate for demand accesses
1444system.l2c.demand_miss_rate::cpu0.data 0.483045 # miss rate for demand accesses
1445system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for demand accesses
1446system.l2c.demand_miss_rate::cpu1.itb.walker 0.485795 # miss rate for demand accesses
1447system.l2c.demand_miss_rate::cpu1.inst 0.071870 # miss rate for demand accesses
1448system.l2c.demand_miss_rate::cpu1.data 0.433241 # miss rate for demand accesses
1449system.l2c.demand_miss_rate::total 0.375626 # miss rate for demand accesses
1450system.l2c.overall_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for overall accesses
1451system.l2c.overall_miss_rate::cpu0.itb.walker 0.303345 # miss rate for overall accesses
1452system.l2c.overall_miss_rate::cpu0.inst 0.095218 # miss rate for overall accesses
1453system.l2c.overall_miss_rate::cpu0.data 0.483045 # miss rate for overall accesses
1454system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for overall accesses
1455system.l2c.overall_miss_rate::cpu1.itb.walker 0.485795 # miss rate for overall accesses
1456system.l2c.overall_miss_rate::cpu1.inst 0.071870 # miss rate for overall accesses
1457system.l2c.overall_miss_rate::cpu1.data 0.433241 # miss rate for overall accesses
1458system.l2c.overall_miss_rate::total 0.375626 # miss rate for overall accesses
1459system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1460system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1461system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1462system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1463system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1464system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1465system.l2c.fast_writes 0 # number of fast writes performed
1466system.l2c.cache_copies 0 # number of cache copies performed
1467system.l2c.writebacks::writebacks 1472038 # number of writebacks
1468system.l2c.writebacks::total 1472038 # number of writebacks
1469system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1470system.membus.trans_dist::ReadReq 82131 # Transaction distribution
1471system.membus.trans_dist::ReadResp 560921 # Transaction distribution
1472system.membus.trans_dist::WriteReq 38802 # Transaction distribution
1473system.membus.trans_dist::WriteResp 38802 # Transaction distribution
1474system.membus.trans_dist::Writeback 1578732 # Transaction distribution
| 12sim_insts 975457230 # Number of instructions simulated
13sim_ops 1147538415 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 152256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 127104 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 3638260 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 62923528 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.dtb.walker 221632 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.itb.walker 219968 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 2412168 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 46368688 # Number of bytes read from this memory
24system.physmem.bytes_read::realview.ide 419904 # Number of bytes read from this memory
25system.physmem.bytes_read::total 116483508 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 3638260 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 2412168 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 6050428 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 101038848 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
32system.physmem.bytes_written::total 101059432 # Number of bytes written to this memory
33system.physmem.num_reads::cpu0.dtb.walker 2379 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 1986 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 97255 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 983193 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.dtb.walker 3463 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.itb.walker 3437 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.inst 37797 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.data 724527 # Number of read requests responded to by this memory
41system.physmem.num_reads::realview.ide 6561 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 1860598 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 1578732 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 1581306 # Number of write requests responded to by this memory
47system.physmem.bw_read::cpu0.dtb.walker 3225 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.itb.walker 2692 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.inst 77054 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.data 1332651 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.dtb.walker 4694 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.itb.walker 4659 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.inst 51087 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.data 982038 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::realview.ide 8893 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 2466992 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 77054 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 51087 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 128141 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 2139891 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 2140327 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 2139891 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.dtb.walker 3225 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.itb.walker 2692 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.inst 77054 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.data 1333087 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.dtb.walker 4694 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.itb.walker 4659 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.inst 51087 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.data 982038 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::realview.ide 8893 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 4607319 # Total bandwidth to/from this memory (bytes/s)
75system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
76system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
77system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
78system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
79system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
80system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
81system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
82system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
83system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
84system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
85system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
86system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
87system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
88system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
89system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
90system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
91system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
92system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
93system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
94system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
95system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
96system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
97system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
98system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
99system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
100system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
101system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
102system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
103system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
104system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
105system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
106system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
107system.cpu_clk_domain.clock 500 # Clock period in ticks
108system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
109system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
110system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
111system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
112system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
113system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
114system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
116system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
117system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
118system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
119system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
120system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
121system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
122system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
123system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
124system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
125system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
126system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
127system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
128system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
129system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
130system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
131system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
132system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
133system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
134system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
135system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
136system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
137system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
138system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
139system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
140system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
141system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
142system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
143system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
144system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
145system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
146system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
147system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
148system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
149system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
150system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
151system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
152system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
153system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
154system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
155system.cpu0.dtb.inst_hits 0 # ITB inst hits
156system.cpu0.dtb.inst_misses 0 # ITB inst misses
157system.cpu0.dtb.read_hits 92662773 # DTB read hits
158system.cpu0.dtb.read_misses 88786 # DTB read misses
159system.cpu0.dtb.write_hits 85694958 # DTB write hits
160system.cpu0.dtb.write_misses 36443 # DTB write misses
161system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
162system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
163system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
164system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
165system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
166system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
167system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
168system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
169system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
170system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
171system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
172system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
173system.cpu0.dtb.hits 178357731 # DTB hits
174system.cpu0.dtb.misses 125229 # DTB misses
175system.cpu0.dtb.accesses 178482960 # DTB accesses
176system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
180system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
181system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
182system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
183system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
184system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
185system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
186system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
187system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
188system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
189system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
190system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
191system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
192system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
193system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
194system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
195system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
196system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
197system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
198system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
199system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
200system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
201system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
202system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
203system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
204system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
205system.cpu0.itb.walker.walks 61377 # Table walker walks requested
206system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
207system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
208system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
209system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
210system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
211system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
212system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
213system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
214system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
215system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
216system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
217system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
218system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
219system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
220system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
221system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
222system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
223system.cpu0.itb.inst_hits 497696393 # ITB inst hits
224system.cpu0.itb.inst_misses 61377 # ITB inst misses
225system.cpu0.itb.read_hits 0 # DTB read hits
226system.cpu0.itb.read_misses 0 # DTB read misses
227system.cpu0.itb.write_hits 0 # DTB write hits
228system.cpu0.itb.write_misses 0 # DTB write misses
229system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
230system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
231system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
232system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
233system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
234system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
235system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
236system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
237system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
238system.cpu0.itb.read_accesses 0 # DTB read accesses
239system.cpu0.itb.write_accesses 0 # DTB write accesses
240system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
241system.cpu0.itb.hits 497696393 # DTB hits
242system.cpu0.itb.misses 61377 # DTB misses
243system.cpu0.itb.accesses 497757770 # DTB accesses
244system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
245system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
246system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
247system.cpu0.committedInsts 497466384 # Number of instructions committed
248system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
249system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
250system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
251system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
252system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
253system.cpu0.num_int_insts 536103359 # number of integer instructions
254system.cpu0.num_fp_insts 526132 # number of float instructions
255system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
256system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
257system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
258system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
259system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
260system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
261system.cpu0.num_mem_refs 178459396 # number of memory refs
262system.cpu0.num_load_insts 92737001 # Number of load instructions
263system.cpu0.num_store_insts 85722395 # Number of store instructions
264system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
265system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
266system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
267system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
268system.cpu0.Branches 111287587 # Number of branches fetched
269system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
270system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
271system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
272system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
273system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
274system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
275system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
276system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
277system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
278system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
279system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
280system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
281system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
282system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
283system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
284system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
285system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
286system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
287system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
288system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
289system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
290system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
291system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
292system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
293system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
294system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
295system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
296system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
297system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
298system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
299system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
300system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
301system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
302system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
303system.cpu0.op_class::total 585300003 # Class of executed instruction
304system.cpu0.kern.inst.arm 0 # number of arm instructions executed
305system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
306system.cpu0.dcache.tags.replacements 6272773 # number of replacements
307system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
308system.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks.
309system.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks.
310system.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks.
311system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
312system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
313system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
314system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
315system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
316system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
317system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
318system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
319system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
320system.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses
321system.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses
322system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits
323system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits
324system.cpu0.dcache.WriteReq_hits::cpu0.data 80919787 # number of WriteReq hits
325system.cpu0.dcache.WriteReq_hits::total 80919787 # number of WriteReq hits
326system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits
327system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits
328system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262007 # number of WriteLineReq hits
329system.cpu0.dcache.WriteLineReq_hits::total 262007 # number of WriteLineReq hits
330system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
331system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
332system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036572 # number of StoreCondReq hits
333system.cpu0.dcache.StoreCondReq_hits::total 2036572 # number of StoreCondReq hits
334system.cpu0.dcache.demand_hits::cpu0.data 167134698 # number of demand (read+write) hits
335system.cpu0.dcache.demand_hits::total 167134698 # number of demand (read+write) hits
336system.cpu0.dcache.overall_hits::cpu0.data 167350352 # number of overall hits
337system.cpu0.dcache.overall_hits::total 167350352 # number of overall hits
338system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses
339system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses
340system.cpu0.dcache.WriteReq_misses::cpu0.data 1475655 # number of WriteReq misses
341system.cpu0.dcache.WriteReq_misses::total 1475655 # number of WriteReq misses
342system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses
343system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses
344system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831713 # number of WriteLineReq misses
345system.cpu0.dcache.WriteLineReq_misses::total 831713 # number of WriteLineReq misses
346system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
347system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
348system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158571 # number of StoreCondReq misses
349system.cpu0.dcache.StoreCondReq_misses::total 158571 # number of StoreCondReq misses
350system.cpu0.dcache.demand_misses::cpu0.data 4785037 # number of demand (read+write) misses
351system.cpu0.dcache.demand_misses::total 4785037 # number of demand (read+write) misses
352system.cpu0.dcache.overall_misses::cpu0.data 5557176 # number of overall misses
353system.cpu0.dcache.overall_misses::total 5557176 # number of overall misses
354system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses)
355system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses)
356system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses)
357system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses)
358system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
359system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
360system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses)
361system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses)
362system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
363system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
364system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
365system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
366system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses
367system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses
368system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses
369system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses
370system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
371system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
372system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses
373system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses
374system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses
375system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses
376system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760444 # miss rate for WriteLineReq accesses
377system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760444 # miss rate for WriteLineReq accesses
378system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
379system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
380system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072237 # miss rate for StoreCondReq accesses
381system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072237 # miss rate for StoreCondReq accesses
382system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses
383system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses
384system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032140 # miss rate for overall accesses
385system.cpu0.dcache.overall_miss_rate::total 0.032140 # miss rate for overall accesses
386system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
387system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
388system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
389system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
390system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
391system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
392system.cpu0.dcache.fast_writes 0 # number of fast writes performed
393system.cpu0.dcache.cache_copies 0 # number of cache copies performed
394system.cpu0.dcache.writebacks::writebacks 4472506 # number of writebacks
395system.cpu0.dcache.writebacks::total 4472506 # number of writebacks
396system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
397system.cpu0.icache.tags.replacements 5539081 # number of replacements
398system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
399system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
400system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
401system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
402system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
403system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
404system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
405system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
406system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
407system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
408system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
409system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
410system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
411system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
412system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
413system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
414system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits
415system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits
416system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits
417system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits
418system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits
419system.cpu0.icache.overall_hits::total 492212891 # number of overall hits
420system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses
421system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses
422system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses
423system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses
424system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses
425system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
426system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses)
427system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
428system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
429system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
430system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
431system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
432system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
433system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
434system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
435system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
436system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
437system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
438system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
439system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
440system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
441system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
442system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
443system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
444system.cpu0.icache.fast_writes 0 # number of fast writes performed
445system.cpu0.icache.cache_copies 0 # number of cache copies performed
446system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
447system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
448system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
449system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
450system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
451system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
452system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
453system.cpu0.l2cache.tags.replacements 2713035 # number of replacements
454system.cpu0.l2cache.tags.tagsinuse 16212.776574 # Cycle average of tags in use
455system.cpu0.l2cache.tags.total_refs 18780735 # Total number of references to valid blocks.
456system.cpu0.l2cache.tags.sampled_refs 2729020 # Sample count of references to valid blocks.
457system.cpu0.l2cache.tags.avg_refs 6.881861 # Average number of references to valid blocks.
458system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
459system.cpu0.l2cache.tags.occ_blocks::writebacks 5698.548759 # Average occupied blocks per requestor
460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.293580 # Average occupied blocks per requestor
461system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 53.073220 # Average occupied blocks per requestor
462system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4549.413482 # Average occupied blocks per requestor
463system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5859.447533 # Average occupied blocks per requestor
464system.cpu0.l2cache.tags.occ_percent::writebacks 0.347812 # Average percentage of cache occupancy
465system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003192 # Average percentage of cache occupancy
466system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003239 # Average percentage of cache occupancy
467system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.277674 # Average percentage of cache occupancy
468system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357632 # Average percentage of cache occupancy
469system.cpu0.l2cache.tags.occ_percent::total 0.989549 # Average percentage of cache occupancy
470system.cpu0.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id
471system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id
472system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id
473system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
474system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
475system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
476system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1169 # Occupied blocks per task id
477system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4652 # Occupied blocks per task id
478system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5280 # Occupied blocks per task id
479system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4600 # Occupied blocks per task id
480system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id
481system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id
482system.cpu0.l2cache.tags.tag_accesses 396071662 # Number of tag accesses
483system.cpu0.l2cache.tags.data_accesses 396071662 # Number of data accesses
484system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 267140 # number of ReadReq hits
485system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140047 # number of ReadReq hits
486system.cpu0.l2cache.ReadReq_hits::total 407187 # number of ReadReq hits
487system.cpu0.l2cache.Writeback_hits::writebacks 4472506 # number of Writeback hits
488system.cpu0.l2cache.Writeback_hits::total 4472506 # number of Writeback hits
489system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3480 # number of UpgradeReq hits
490system.cpu0.l2cache.UpgradeReq_hits::total 3480 # number of UpgradeReq hits
491system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634900 # number of ReadExReq hits
492system.cpu0.l2cache.ReadExReq_hits::total 634900 # number of ReadExReq hits
493system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4970860 # number of ReadCleanReq hits
494system.cpu0.l2cache.ReadCleanReq_hits::total 4970860 # number of ReadCleanReq hits
495system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2942102 # number of ReadSharedReq hits
496system.cpu0.l2cache.ReadSharedReq_hits::total 2942102 # number of ReadSharedReq hits
497system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223126 # number of InvalidateReq hits
498system.cpu0.l2cache.InvalidateReq_hits::total 223126 # number of InvalidateReq hits
499system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 267140 # number of demand (read+write) hits
500system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140047 # number of demand (read+write) hits
501system.cpu0.l2cache.demand_hits::cpu0.inst 4970860 # number of demand (read+write) hits
502system.cpu0.l2cache.demand_hits::cpu0.data 3577002 # number of demand (read+write) hits
503system.cpu0.l2cache.demand_hits::total 8955049 # number of demand (read+write) hits
504system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 267140 # number of overall hits
505system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140047 # number of overall hits
506system.cpu0.l2cache.overall_hits::cpu0.inst 4970860 # number of overall hits
507system.cpu0.l2cache.overall_hits::cpu0.data 3577002 # number of overall hits
508system.cpu0.l2cache.overall_hits::total 8955049 # number of overall hits
509system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11279 # number of ReadReq misses
510system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8435 # number of ReadReq misses
511system.cpu0.l2cache.ReadReq_misses::total 19714 # number of ReadReq misses
512system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128321 # number of UpgradeReq misses
513system.cpu0.l2cache.UpgradeReq_misses::total 128321 # number of UpgradeReq misses
514system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158571 # number of SCUpgradeReq misses
515system.cpu0.l2cache.SCUpgradeReq_misses::total 158571 # number of SCUpgradeReq misses
516system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709333 # number of ReadExReq misses
517system.cpu0.l2cache.ReadExReq_misses::total 709333 # number of ReadExReq misses
518system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568738 # number of ReadCleanReq misses
519system.cpu0.l2cache.ReadCleanReq_misses::total 568738 # number of ReadCleanReq misses
520system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1259235 # number of ReadSharedReq misses
521system.cpu0.l2cache.ReadSharedReq_misses::total 1259235 # number of ReadSharedReq misses
522system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608208 # number of InvalidateReq misses
523system.cpu0.l2cache.InvalidateReq_misses::total 608208 # number of InvalidateReq misses
524system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11279 # number of demand (read+write) misses
525system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8435 # number of demand (read+write) misses
526system.cpu0.l2cache.demand_misses::cpu0.inst 568738 # number of demand (read+write) misses
527system.cpu0.l2cache.demand_misses::cpu0.data 1968568 # number of demand (read+write) misses
528system.cpu0.l2cache.demand_misses::total 2557020 # number of demand (read+write) misses
529system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11279 # number of overall misses
530system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8435 # number of overall misses
531system.cpu0.l2cache.overall_misses::cpu0.inst 568738 # number of overall misses
532system.cpu0.l2cache.overall_misses::cpu0.data 1968568 # number of overall misses
533system.cpu0.l2cache.overall_misses::total 2557020 # number of overall misses
534system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 278419 # number of ReadReq accesses(hits+misses)
535system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148482 # number of ReadReq accesses(hits+misses)
536system.cpu0.l2cache.ReadReq_accesses::total 426901 # number of ReadReq accesses(hits+misses)
537system.cpu0.l2cache.Writeback_accesses::writebacks 4472506 # number of Writeback accesses(hits+misses)
538system.cpu0.l2cache.Writeback_accesses::total 4472506 # number of Writeback accesses(hits+misses)
539system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131801 # number of UpgradeReq accesses(hits+misses)
540system.cpu0.l2cache.UpgradeReq_accesses::total 131801 # number of UpgradeReq accesses(hits+misses)
541system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158571 # number of SCUpgradeReq accesses(hits+misses)
542system.cpu0.l2cache.SCUpgradeReq_accesses::total 158571 # number of SCUpgradeReq accesses(hits+misses)
543system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344233 # number of ReadExReq accesses(hits+misses)
544system.cpu0.l2cache.ReadExReq_accesses::total 1344233 # number of ReadExReq accesses(hits+misses)
545system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses)
546system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses)
547system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses)
548system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses)
549system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831334 # number of InvalidateReq accesses(hits+misses)
550system.cpu0.l2cache.InvalidateReq_accesses::total 831334 # number of InvalidateReq accesses(hits+misses)
551system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 278419 # number of demand (read+write) accesses
552system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148482 # number of demand (read+write) accesses
553system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
554system.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses
555system.cpu0.l2cache.demand_accesses::total 11512069 # number of demand (read+write) accesses
556system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 278419 # number of overall (read+write) accesses
557system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148482 # number of overall (read+write) accesses
558system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
559system.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses
560system.cpu0.l2cache.overall_accesses::total 11512069 # number of overall (read+write) accesses
561system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for ReadReq accesses
562system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056808 # miss rate for ReadReq accesses
563system.cpu0.l2cache.ReadReq_miss_rate::total 0.046179 # miss rate for ReadReq accesses
564system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973597 # miss rate for UpgradeReq accesses
565system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973597 # miss rate for UpgradeReq accesses
566system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
567system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
568system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527686 # miss rate for ReadExReq accesses
569system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527686 # miss rate for ReadExReq accesses
570system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102668 # miss rate for ReadCleanReq accesses
571system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102668 # miss rate for ReadCleanReq accesses
572system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299722 # miss rate for ReadSharedReq accesses
573system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299722 # miss rate for ReadSharedReq accesses
574system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731605 # miss rate for InvalidateReq accesses
575system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731605 # miss rate for InvalidateReq accesses
576system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for demand accesses
577system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056808 # miss rate for demand accesses
578system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102668 # miss rate for demand accesses
579system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354980 # miss rate for demand accesses
580system.cpu0.l2cache.demand_miss_rate::total 0.222116 # miss rate for demand accesses
581system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040511 # miss rate for overall accesses
582system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056808 # miss rate for overall accesses
583system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102668 # miss rate for overall accesses
584system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354980 # miss rate for overall accesses
585system.cpu0.l2cache.overall_miss_rate::total 0.222116 # miss rate for overall accesses
586system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
587system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
588system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
589system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
590system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
591system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
592system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
593system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
594system.cpu0.l2cache.writebacks::writebacks 1573891 # number of writebacks
595system.cpu0.l2cache.writebacks::total 1573891 # number of writebacks
596system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
597system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution
598system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution
599system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution
600system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution
601system.cpu0.toL2Bus.trans_dist::Writeback 4472506 # Transaction distribution
602system.cpu0.toL2Bus.trans_dist::CleanEvict 7339348 # Transaction distribution
603system.cpu0.toL2Bus.trans_dist::UpgradeReq 131801 # Transaction distribution
604system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158571 # Transaction distribution
605system.cpu0.toL2Bus.trans_dist::UpgradeResp 290372 # Transaction distribution
606system.cpu0.toL2Bus.trans_dist::ReadExReq 1344233 # Transaction distribution
607system.cpu0.toL2Bus.trans_dist::ReadExResp 1344233 # Transaction distribution
608system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution
609system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution
610system.cpu0.toL2Bus.trans_dist::InvalidateReq 831334 # Transaction distribution
611system.cpu0.toL2Bus.trans_dist::InvalidateResp 831334 # Transaction distribution
612system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16704527 # Packet count per connected master and slave (bytes)
613system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19737201 # Packet count per connected master and slave (bytes)
614system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
615system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
616system.cpu0.toL2Bus.pkt_count::total 37536458 # Packet count per connected master and slave (bytes)
617system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
618system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641350217 # Cumulative packet size per connected master and slave (bytes)
619system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
620system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
621system.cpu0.toL2Bus.pkt_size::total 1000435909 # Cumulative packet size per connected master and slave (bytes)
622system.cpu0.toL2Bus.snoops 3360861 # Total snoops (count)
623system.cpu0.toL2Bus.snoop_fanout::samples 27849165 # Request fanout histogram
624system.cpu0.toL2Bus.snoop_fanout::mean 1.133662 # Request fanout histogram
625system.cpu0.toL2Bus.snoop_fanout::stdev 0.340289 # Request fanout histogram
626system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
627system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
628system.cpu0.toL2Bus.snoop_fanout::1 24126791 86.63% 86.63% # Request fanout histogram
629system.cpu0.toL2Bus.snoop_fanout::2 3722374 13.37% 100.00% # Request fanout histogram
630system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
631system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
632system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
633system.cpu0.toL2Bus.snoop_fanout::total 27849165 # Request fanout histogram
634system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
641system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
642system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
643system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
644system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
645system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
646system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
647system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
648system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
649system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
650system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
651system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
652system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
653system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
654system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
655system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
656system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
657system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
658system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
659system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
660system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
661system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
662system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
663system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
664system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
665system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
666system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
667system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
668system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
669system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
670system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
671system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
672system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
673system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
674system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
675system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
676system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
677system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
678system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
679system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
680system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
681system.cpu1.dtb.inst_hits 0 # ITB inst hits
682system.cpu1.dtb.inst_misses 0 # ITB inst misses
683system.cpu1.dtb.read_hits 90153061 # DTB read hits
684system.cpu1.dtb.read_misses 111753 # DTB read misses
685system.cpu1.dtb.write_hits 81132787 # DTB write hits
686system.cpu1.dtb.write_misses 32288 # DTB write misses
687system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
688system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
689system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
690system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
691system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
692system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
693system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
694system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
695system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
696system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
697system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
698system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
699system.cpu1.dtb.hits 171285848 # DTB hits
700system.cpu1.dtb.misses 144041 # DTB misses
701system.cpu1.dtb.accesses 171429889 # DTB accesses
702system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
710system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
711system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
712system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
713system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
714system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
715system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
716system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
717system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
718system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
719system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
720system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
721system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
722system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
723system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
724system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
725system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
726system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
727system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
728system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
729system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
730system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
731system.cpu1.itb.walker.walks 60885 # Table walker walks requested
732system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
733system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
734system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
735system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
736system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
737system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
738system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
739system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
740system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
741system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
742system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
743system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
744system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
745system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
746system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
747system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
748system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
749system.cpu1.itb.inst_hits 478248118 # ITB inst hits
750system.cpu1.itb.inst_misses 60885 # ITB inst misses
751system.cpu1.itb.read_hits 0 # DTB read hits
752system.cpu1.itb.read_misses 0 # DTB read misses
753system.cpu1.itb.write_hits 0 # DTB write hits
754system.cpu1.itb.write_misses 0 # DTB write misses
755system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
756system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
757system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
758system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
759system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
760system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
761system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
762system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
763system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
764system.cpu1.itb.read_accesses 0 # DTB read accesses
765system.cpu1.itb.write_accesses 0 # DTB write accesses
766system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
767system.cpu1.itb.hits 478248118 # DTB hits
768system.cpu1.itb.misses 60885 # DTB misses
769system.cpu1.itb.accesses 478309003 # DTB accesses
770system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
771system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
772system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
773system.cpu1.committedInsts 477990846 # Number of instructions committed
774system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
775system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
776system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
777system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
778system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
779system.cpu1.num_int_insts 516282159 # number of integer instructions
780system.cpu1.num_fp_insts 374678 # number of float instructions
781system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
782system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
783system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
784system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
785system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
786system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
787system.cpu1.num_mem_refs 171406825 # number of memory refs
788system.cpu1.num_load_insts 90251973 # Number of load instructions
789system.cpu1.num_store_insts 81154852 # Number of store instructions
790system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
791system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
792system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
793system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
794system.cpu1.Branches 106497601 # Number of branches fetched
795system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
796system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
797system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
798system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
799system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
800system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
801system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
802system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
803system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
804system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
805system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
806system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
807system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
808system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
809system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
810system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
811system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
812system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
813system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
814system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
815system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
816system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
817system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
818system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
819system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
820system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
821system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
822system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
823system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
824system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
825system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
826system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
827system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
828system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
829system.cpu1.op_class::total 562879339 # Class of executed instruction
830system.cpu1.kern.inst.arm 0 # number of arm instructions executed
831system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
832system.cpu1.dcache.tags.replacements 5945049 # number of replacements
833system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
834system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
835system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
836system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
837system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
838system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
839system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
840system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
841system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
842system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
843system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
844system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
845system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
846system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
847system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
848system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
849system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
850system.cpu1.dcache.WriteReq_hits::cpu1.data 76990238 # number of WriteReq hits
851system.cpu1.dcache.WriteReq_hits::total 76990238 # number of WriteReq hits
852system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
853system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
854system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits
855system.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits
856system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
857system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
858system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048840 # number of StoreCondReq hits
859system.cpu1.dcache.StoreCondReq_hits::total 2048840 # number of StoreCondReq hits
860system.cpu1.dcache.demand_hits::cpu1.data 160687802 # number of demand (read+write) hits
861system.cpu1.dcache.demand_hits::total 160687802 # number of demand (read+write) hits
862system.cpu1.dcache.overall_hits::cpu1.data 160875656 # number of overall hits
863system.cpu1.dcache.overall_hits::total 160875656 # number of overall hits
864system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
865system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
866system.cpu1.dcache.WriteReq_misses::cpu1.data 1453238 # number of WriteReq misses
867system.cpu1.dcache.WriteReq_misses::total 1453238 # number of WriteReq misses
868system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
869system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
870system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses
871system.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses
872system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
873system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
874system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158909 # number of StoreCondReq misses
875system.cpu1.dcache.StoreCondReq_misses::total 158909 # number of StoreCondReq misses
876system.cpu1.dcache.demand_misses::cpu1.data 4811460 # number of demand (read+write) misses
877system.cpu1.dcache.demand_misses::total 4811460 # number of demand (read+write) misses
878system.cpu1.dcache.overall_misses::cpu1.data 5603811 # number of overall misses
879system.cpu1.dcache.overall_misses::total 5603811 # number of overall misses
880system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
881system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
882system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
883system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
884system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
885system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
886system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses)
887system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses)
888system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
889system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
890system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
891system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
892system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
893system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
894system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
895system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
896system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
897system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
898system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018526 # miss rate for WriteReq accesses
899system.cpu1.dcache.WriteReq_miss_rate::total 0.018526 # miss rate for WriteReq accesses
900system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
901system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
902system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses
903system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses
904system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
905system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
906system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071978 # miss rate for StoreCondReq accesses
907system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071978 # miss rate for StoreCondReq accesses
908system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses
909system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses
910system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses
911system.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses
912system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
913system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
914system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
915system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
916system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
917system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
918system.cpu1.dcache.fast_writes 0 # number of fast writes performed
919system.cpu1.dcache.cache_copies 0 # number of cache copies performed
920system.cpu1.dcache.writebacks::writebacks 4032489 # number of writebacks
921system.cpu1.dcache.writebacks::total 4032489 # number of writebacks
922system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
923system.cpu1.icache.tags.replacements 4741297 # number of replacements
924system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
925system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
926system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
927system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
928system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
929system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
930system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
931system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
932system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
933system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
934system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
935system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
936system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
937system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
938system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
939system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
940system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
941system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
942system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
943system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
944system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
945system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
946system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
947system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
948system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
949system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
950system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
951system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
952system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
953system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
954system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
955system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
956system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
957system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
958system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
959system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
960system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
961system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
962system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
963system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
964system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
965system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
966system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
967system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
968system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
969system.cpu1.icache.fast_writes 0 # number of fast writes performed
970system.cpu1.icache.cache_copies 0 # number of cache copies performed
971system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
972system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
973system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
974system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
975system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
976system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
977system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
978system.cpu1.l2cache.tags.replacements 2278625 # number of replacements
979system.cpu1.l2cache.tags.tagsinuse 13455.366056 # Cycle average of tags in use
980system.cpu1.l2cache.tags.total_refs 17413486 # Total number of references to valid blocks.
981system.cpu1.l2cache.tags.sampled_refs 2294680 # Sample count of references to valid blocks.
982system.cpu1.l2cache.tags.avg_refs 7.588634 # Average number of references to valid blocks.
983system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit.
984system.cpu1.l2cache.tags.occ_blocks::writebacks 5192.867159 # Average occupied blocks per requestor
985system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.806245 # Average occupied blocks per requestor
986system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 99.441300 # Average occupied blocks per requestor
987system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2834.629918 # Average occupied blocks per requestor
988system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5261.621433 # Average occupied blocks per requestor
989system.cpu1.l2cache.tags.occ_percent::writebacks 0.316947 # Average percentage of cache occupancy
990system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004078 # Average percentage of cache occupancy
991system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.006069 # Average percentage of cache occupancy
992system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173012 # Average percentage of cache occupancy
993system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.321144 # Average percentage of cache occupancy
994system.cpu1.l2cache.tags.occ_percent::total 0.821250 # Average percentage of cache occupancy
995system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id
996system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id
997system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
998system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
999system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
1000system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
1001system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id
1002system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
1003system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1614 # Occupied blocks per task id
1004system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5923 # Occupied blocks per task id
1005system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id
1006system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3815 # Occupied blocks per task id
1007system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id
1008system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id
1009system.cpu1.l2cache.tags.tag_accesses 360485676 # Number of tag accesses
1010system.cpu1.l2cache.tags.data_accesses 360485676 # Number of data accesses
1011system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324846 # number of ReadReq hits
1012system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140054 # number of ReadReq hits
1013system.cpu1.l2cache.ReadReq_hits::total 464900 # number of ReadReq hits
1014system.cpu1.l2cache.Writeback_hits::writebacks 4032489 # number of Writeback hits
1015system.cpu1.l2cache.Writeback_hits::total 4032489 # number of Writeback hits
1016system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3822 # number of UpgradeReq hits
1017system.cpu1.l2cache.UpgradeReq_hits::total 3822 # number of UpgradeReq hits
1018system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614016 # number of ReadExReq hits
1019system.cpu1.l2cache.ReadExReq_hits::total 614016 # number of ReadExReq hits
1020system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4217303 # number of ReadCleanReq hits
1021system.cpu1.l2cache.ReadCleanReq_hits::total 4217303 # number of ReadCleanReq hits
1022system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057649 # number of ReadSharedReq hits
1023system.cpu1.l2cache.ReadSharedReq_hits::total 3057649 # number of ReadSharedReq hits
1024system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161208 # number of InvalidateReq hits
1025system.cpu1.l2cache.InvalidateReq_hits::total 161208 # number of InvalidateReq hits
1026system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324846 # number of demand (read+write) hits
1027system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140054 # number of demand (read+write) hits
1028system.cpu1.l2cache.demand_hits::cpu1.inst 4217303 # number of demand (read+write) hits
1029system.cpu1.l2cache.demand_hits::cpu1.data 3671665 # number of demand (read+write) hits
1030system.cpu1.l2cache.demand_hits::total 8353868 # number of demand (read+write) hits
1031system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324846 # number of overall hits
1032system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140054 # number of overall hits
1033system.cpu1.l2cache.overall_hits::cpu1.inst 4217303 # number of overall hits
1034system.cpu1.l2cache.overall_hits::cpu1.data 3671665 # number of overall hits
1035system.cpu1.l2cache.overall_hits::total 8353868 # number of overall hits
1036system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12306 # number of ReadReq misses
1037system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9777 # number of ReadReq misses
1038system.cpu1.l2cache.ReadReq_misses::total 22083 # number of ReadReq misses
1039system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133739 # number of UpgradeReq misses
1040system.cpu1.l2cache.UpgradeReq_misses::total 133739 # number of UpgradeReq misses
1041system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158909 # number of SCUpgradeReq misses
1042system.cpu1.l2cache.SCUpgradeReq_misses::total 158909 # number of SCUpgradeReq misses
1043system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701874 # number of ReadExReq misses
1044system.cpu1.l2cache.ReadExReq_misses::total 701874 # number of ReadExReq misses
1045system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 524506 # number of ReadCleanReq misses
1046system.cpu1.l2cache.ReadCleanReq_misses::total 524506 # number of ReadCleanReq misses
1047system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239744 # number of ReadSharedReq misses
1048system.cpu1.l2cache.ReadSharedReq_misses::total 1239744 # number of ReadSharedReq misses
1049system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265638 # number of InvalidateReq misses
1050system.cpu1.l2cache.InvalidateReq_misses::total 265638 # number of InvalidateReq misses
1051system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12306 # number of demand (read+write) misses
1052system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9777 # number of demand (read+write) misses
1053system.cpu1.l2cache.demand_misses::cpu1.inst 524506 # number of demand (read+write) misses
1054system.cpu1.l2cache.demand_misses::cpu1.data 1941618 # number of demand (read+write) misses
1055system.cpu1.l2cache.demand_misses::total 2488207 # number of demand (read+write) misses
1056system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12306 # number of overall misses
1057system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9777 # number of overall misses
1058system.cpu1.l2cache.overall_misses::cpu1.inst 524506 # number of overall misses
1059system.cpu1.l2cache.overall_misses::cpu1.data 1941618 # number of overall misses
1060system.cpu1.l2cache.overall_misses::total 2488207 # number of overall misses
1061system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337152 # number of ReadReq accesses(hits+misses)
1062system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149831 # number of ReadReq accesses(hits+misses)
1063system.cpu1.l2cache.ReadReq_accesses::total 486983 # number of ReadReq accesses(hits+misses)
1064system.cpu1.l2cache.Writeback_accesses::writebacks 4032489 # number of Writeback accesses(hits+misses)
1065system.cpu1.l2cache.Writeback_accesses::total 4032489 # number of Writeback accesses(hits+misses)
1066system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137561 # number of UpgradeReq accesses(hits+misses)
1067system.cpu1.l2cache.UpgradeReq_accesses::total 137561 # number of UpgradeReq accesses(hits+misses)
1068system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158909 # number of SCUpgradeReq accesses(hits+misses)
1069system.cpu1.l2cache.SCUpgradeReq_accesses::total 158909 # number of SCUpgradeReq accesses(hits+misses)
1070system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
1071system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
1072system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses)
1073system.cpu1.l2cache.ReadCleanReq_accesses::total 4741809 # number of ReadCleanReq accesses(hits+misses)
1074system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 # number of ReadSharedReq accesses(hits+misses)
1075system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses)
1076system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses)
1077system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses)
1078system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337152 # number of demand (read+write) accesses
1079system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149831 # number of demand (read+write) accesses
1080system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
1081system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
1082system.cpu1.l2cache.demand_accesses::total 10842075 # number of demand (read+write) accesses
1083system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337152 # number of overall (read+write) accesses
1084system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149831 # number of overall (read+write) accesses
1085system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
1086system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
1087system.cpu1.l2cache.overall_accesses::total 10842075 # number of overall (read+write) accesses
1088system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for ReadReq accesses
1089system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065254 # miss rate for ReadReq accesses
1090system.cpu1.l2cache.ReadReq_miss_rate::total 0.045347 # miss rate for ReadReq accesses
1091system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972216 # miss rate for UpgradeReq accesses
1092system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972216 # miss rate for UpgradeReq accesses
1093system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1094system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1095system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533383 # miss rate for ReadExReq accesses
1096system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533383 # miss rate for ReadExReq accesses
1097system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110613 # miss rate for ReadCleanReq accesses
1098system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110613 # miss rate for ReadCleanReq accesses
1099system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288487 # miss rate for ReadSharedReq accesses
1100system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288487 # miss rate for ReadSharedReq accesses
1101system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622327 # miss rate for InvalidateReq accesses
1102system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622327 # miss rate for InvalidateReq accesses
1103system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for demand accesses
1104system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065254 # miss rate for demand accesses
1105system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110613 # miss rate for demand accesses
1106system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345897 # miss rate for demand accesses
1107system.cpu1.l2cache.demand_miss_rate::total 0.229495 # miss rate for demand accesses
1108system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036500 # miss rate for overall accesses
1109system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065254 # miss rate for overall accesses
1110system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110613 # miss rate for overall accesses
1111system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345897 # miss rate for overall accesses
1112system.cpu1.l2cache.overall_miss_rate::total 0.229495 # miss rate for overall accesses
1113system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1114system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1115system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1116system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1117system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1118system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1119system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1120system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1121system.cpu1.l2cache.writebacks::writebacks 1184748 # number of writebacks
1122system.cpu1.l2cache.writebacks::total 1184748 # number of writebacks
1123system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1124system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution
1125system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
1126system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
1127system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
1128system.cpu1.toL2Bus.trans_dist::Writeback 4032489 # Transaction distribution
1129system.cpu1.toL2Bus.trans_dist::CleanEvict 6653857 # Transaction distribution
1130system.cpu1.toL2Bus.trans_dist::UpgradeReq 137561 # Transaction distribution
1131system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158909 # Transaction distribution
1132system.cpu1.toL2Bus.trans_dist::UpgradeResp 296470 # Transaction distribution
1133system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
1134system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
1135system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution
1136system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution
1137system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution
1138system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution
1139system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225175 # Packet count per connected master and slave (bytes)
1140system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643731 # Packet count per connected master and slave (bytes)
1141system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
1142system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
1143system.cpu1.toL2Bus.pkt_count::total 34068350 # Packet count per connected master and slave (bytes)
1144system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
1145system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617367804 # Cumulative packet size per connected master and slave (bytes)
1146system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
1147system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
1148system.cpu1.toL2Bus.pkt_size::total 925641876 # Cumulative packet size per connected master and slave (bytes)
1149system.cpu1.toL2Bus.snoops 3842126 # Total snoops (count)
1150system.cpu1.toL2Bus.snoop_fanout::samples 26053175 # Request fanout histogram
1151system.cpu1.toL2Bus.snoop_fanout::mean 1.164109 # Request fanout histogram
1152system.cpu1.toL2Bus.snoop_fanout::stdev 0.370374 # Request fanout histogram
1153system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1154system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1155system.cpu1.toL2Bus.snoop_fanout::1 21777626 83.59% 83.59% # Request fanout histogram
1156system.cpu1.toL2Bus.snoop_fanout::2 4275549 16.41% 100.00% # Request fanout histogram
1157system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1158system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1159system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1160system.cpu1.toL2Bus.snoop_fanout::total 26053175 # Request fanout histogram
1161system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
1162system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
1163system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
1164system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
1165system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
1166system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1167system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1168system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1169system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1170system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1171system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1172system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1173system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1174system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1175system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
1176system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1177system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1178system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1179system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1180system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
1181system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
1182system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
1183system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1184system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1185system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
1186system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
1187system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1188system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1189system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1190system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1191system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1192system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1193system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1194system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1195system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1196system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
1197system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1198system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1199system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1200system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1201system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
1202system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
1203system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
1204system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1205system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1206system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
1207system.iocache.tags.replacements 115585 # number of replacements
1208system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
1209system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1210system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
1211system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1212system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
1213system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
1214system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
1215system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
1216system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
1217system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
1218system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1219system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1220system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1221system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
1222system.iocache.tags.data_accesses 1040793 # Number of data accesses
1223system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1224system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
1225system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
1226system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1227system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1228system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
1229system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
1230system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1231system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
1232system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
1233system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1234system.iocache.overall_misses::realview.ide 8876 # number of overall misses
1235system.iocache.overall_misses::total 8916 # number of overall misses
1236system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1237system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
1238system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
1239system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1240system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1241system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
1242system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
1243system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1244system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
1245system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
1246system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1247system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
1248system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
1249system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1250system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1251system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1252system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1253system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1254system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1255system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1256system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1257system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1258system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1259system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1260system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1261system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1262system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1263system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1264system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1265system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1266system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1267system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1268system.iocache.fast_writes 0 # number of fast writes performed
1269system.iocache.cache_copies 0 # number of cache copies performed
1270system.iocache.writebacks::writebacks 106694 # number of writebacks
1271system.iocache.writebacks::total 106694 # number of writebacks
1272system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1273system.l2c.tags.replacements 1751385 # number of replacements
1274system.l2c.tags.tagsinuse 62313.380560 # Cycle average of tags in use
1275system.l2c.tags.total_refs 6017106 # Total number of references to valid blocks.
1276system.l2c.tags.sampled_refs 1809468 # Sample count of references to valid blocks.
1277system.l2c.tags.avg_refs 3.325345 # Average number of references to valid blocks.
1278system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1279system.l2c.tags.occ_blocks::writebacks 34286.931814 # Average occupied blocks per requestor
1280system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.043983 # Average occupied blocks per requestor
1281system.l2c.tags.occ_blocks::cpu0.itb.walker 59.106418 # Average occupied blocks per requestor
1282system.l2c.tags.occ_blocks::cpu0.inst 3327.548165 # Average occupied blocks per requestor
1283system.l2c.tags.occ_blocks::cpu0.data 6997.138223 # Average occupied blocks per requestor
1284system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.986034 # Average occupied blocks per requestor
1285system.l2c.tags.occ_blocks::cpu1.itb.walker 428.835942 # Average occupied blocks per requestor
1286system.l2c.tags.occ_blocks::cpu1.inst 3021.438473 # Average occupied blocks per requestor
1287system.l2c.tags.occ_blocks::cpu1.data 13835.351509 # Average occupied blocks per requestor
1288system.l2c.tags.occ_percent::writebacks 0.523177 # Average percentage of cache occupancy
1289system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000718 # Average percentage of cache occupancy
1290system.l2c.tags.occ_percent::cpu0.itb.walker 0.000902 # Average percentage of cache occupancy
1291system.l2c.tags.occ_percent::cpu0.inst 0.050774 # Average percentage of cache occupancy
1292system.l2c.tags.occ_percent::cpu0.data 0.106768 # Average percentage of cache occupancy
1293system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004730 # Average percentage of cache occupancy
1294system.l2c.tags.occ_percent::cpu1.itb.walker 0.006544 # Average percentage of cache occupancy
1295system.l2c.tags.occ_percent::cpu1.inst 0.046103 # Average percentage of cache occupancy
1296system.l2c.tags.occ_percent::cpu1.data 0.211111 # Average percentage of cache occupancy
1297system.l2c.tags.occ_percent::total 0.950827 # Average percentage of cache occupancy
1298system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id
1299system.l2c.tags.occ_task_id_blocks::1024 57863 # Occupied blocks per task id
1300system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
1301system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id
1302system.l2c.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
1303system.l2c.tags.age_task_id_blocks_1024::1 545 # Occupied blocks per task id
1304system.l2c.tags.age_task_id_blocks_1024::2 3434 # Occupied blocks per task id
1305system.l2c.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id
1306system.l2c.tags.age_task_id_blocks_1024::4 48241 # Occupied blocks per task id
1307system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
1308system.l2c.tags.occ_task_id_percent::1024 0.882919 # Percentage of cache occupancy per task id
1309system.l2c.tags.tag_accesses 85814440 # Number of tag accesses
1310system.l2c.tags.data_accesses 85814440 # Number of data accesses
1311system.l2c.Writeback_hits::writebacks 2758639 # number of Writeback hits
1312system.l2c.Writeback_hits::total 2758639 # number of Writeback hits
1313system.l2c.UpgradeReq_hits::cpu0.data 13259 # number of UpgradeReq hits
1314system.l2c.UpgradeReq_hits::cpu1.data 10916 # number of UpgradeReq hits
1315system.l2c.UpgradeReq_hits::total 24175 # number of UpgradeReq hits
1316system.l2c.SCUpgradeReq_hits::cpu0.data 1481 # number of SCUpgradeReq hits
1317system.l2c.SCUpgradeReq_hits::cpu1.data 1240 # number of SCUpgradeReq hits
1318system.l2c.SCUpgradeReq_hits::total 2721 # number of SCUpgradeReq hits
1319system.l2c.ReadExReq_hits::cpu0.data 318588 # number of ReadExReq hits
1320system.l2c.ReadExReq_hits::cpu1.data 264415 # number of ReadExReq hits
1321system.l2c.ReadExReq_hits::total 583003 # number of ReadExReq hits
1322system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6289 # number of ReadSharedReq hits
1323system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4561 # number of ReadSharedReq hits
1324system.l2c.ReadSharedReq_hits::cpu0.inst 514584 # number of ReadSharedReq hits
1325system.l2c.ReadSharedReq_hits::cpu0.data 748348 # number of ReadSharedReq hits
1326system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5382 # number of ReadSharedReq hits
1327system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3638 # number of ReadSharedReq hits
1328system.l2c.ReadSharedReq_hits::cpu1.inst 486810 # number of ReadSharedReq hits
1329system.l2c.ReadSharedReq_hits::cpu1.data 695012 # number of ReadSharedReq hits
1330system.l2c.ReadSharedReq_hits::total 2464624 # number of ReadSharedReq hits
1331system.l2c.demand_hits::cpu0.dtb.walker 6289 # number of demand (read+write) hits
1332system.l2c.demand_hits::cpu0.itb.walker 4561 # number of demand (read+write) hits
1333system.l2c.demand_hits::cpu0.inst 514584 # number of demand (read+write) hits
1334system.l2c.demand_hits::cpu0.data 1066936 # number of demand (read+write) hits
1335system.l2c.demand_hits::cpu1.dtb.walker 5382 # number of demand (read+write) hits
1336system.l2c.demand_hits::cpu1.itb.walker 3638 # number of demand (read+write) hits
1337system.l2c.demand_hits::cpu1.inst 486810 # number of demand (read+write) hits
1338system.l2c.demand_hits::cpu1.data 959427 # number of demand (read+write) hits
1339system.l2c.demand_hits::total 3047627 # number of demand (read+write) hits
1340system.l2c.overall_hits::cpu0.dtb.walker 6289 # number of overall hits
1341system.l2c.overall_hits::cpu0.itb.walker 4561 # number of overall hits
1342system.l2c.overall_hits::cpu0.inst 514584 # number of overall hits
1343system.l2c.overall_hits::cpu0.data 1066936 # number of overall hits
1344system.l2c.overall_hits::cpu1.dtb.walker 5382 # number of overall hits
1345system.l2c.overall_hits::cpu1.itb.walker 3638 # number of overall hits
1346system.l2c.overall_hits::cpu1.inst 486810 # number of overall hits
1347system.l2c.overall_hits::cpu1.data 959427 # number of overall hits
1348system.l2c.overall_hits::total 3047627 # number of overall hits
1349system.l2c.UpgradeReq_misses::cpu0.data 58599 # number of UpgradeReq misses
1350system.l2c.UpgradeReq_misses::cpu1.data 54084 # number of UpgradeReq misses
1351system.l2c.UpgradeReq_misses::total 112683 # number of UpgradeReq misses
1352system.l2c.SCUpgradeReq_misses::cpu0.data 7811 # number of SCUpgradeReq misses
1353system.l2c.SCUpgradeReq_misses::cpu1.data 7438 # number of SCUpgradeReq misses
1354system.l2c.SCUpgradeReq_misses::total 15249 # number of SCUpgradeReq misses
1355system.l2c.ReadExReq_misses::cpu0.data 816245 # number of ReadExReq misses
1356system.l2c.ReadExReq_misses::cpu1.data 547345 # number of ReadExReq misses
1357system.l2c.ReadExReq_misses::total 1363590 # number of ReadExReq misses
1358system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2379 # number of ReadSharedReq misses
1359system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1986 # number of ReadSharedReq misses
1360system.l2c.ReadSharedReq_misses::cpu0.inst 54154 # number of ReadSharedReq misses
1361system.l2c.ReadSharedReq_misses::cpu0.data 180703 # number of ReadSharedReq misses
1362system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3463 # number of ReadSharedReq misses
1363system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3437 # number of ReadSharedReq misses
1364system.l2c.ReadSharedReq_misses::cpu1.inst 37696 # number of ReadSharedReq misses
1365system.l2c.ReadSharedReq_misses::cpu1.data 186059 # number of ReadSharedReq misses
1366system.l2c.ReadSharedReq_misses::total 469877 # number of ReadSharedReq misses
1367system.l2c.demand_misses::cpu0.dtb.walker 2379 # number of demand (read+write) misses
1368system.l2c.demand_misses::cpu0.itb.walker 1986 # number of demand (read+write) misses
1369system.l2c.demand_misses::cpu0.inst 54154 # number of demand (read+write) misses
1370system.l2c.demand_misses::cpu0.data 996948 # number of demand (read+write) misses
1371system.l2c.demand_misses::cpu1.dtb.walker 3463 # number of demand (read+write) misses
1372system.l2c.demand_misses::cpu1.itb.walker 3437 # number of demand (read+write) misses
1373system.l2c.demand_misses::cpu1.inst 37696 # number of demand (read+write) misses
1374system.l2c.demand_misses::cpu1.data 733404 # number of demand (read+write) misses
1375system.l2c.demand_misses::total 1833467 # number of demand (read+write) misses
1376system.l2c.overall_misses::cpu0.dtb.walker 2379 # number of overall misses
1377system.l2c.overall_misses::cpu0.itb.walker 1986 # number of overall misses
1378system.l2c.overall_misses::cpu0.inst 54154 # number of overall misses
1379system.l2c.overall_misses::cpu0.data 996948 # number of overall misses
1380system.l2c.overall_misses::cpu1.dtb.walker 3463 # number of overall misses
1381system.l2c.overall_misses::cpu1.itb.walker 3437 # number of overall misses
1382system.l2c.overall_misses::cpu1.inst 37696 # number of overall misses
1383system.l2c.overall_misses::cpu1.data 733404 # number of overall misses
1384system.l2c.overall_misses::total 1833467 # number of overall misses
1385system.l2c.Writeback_accesses::writebacks 2758639 # number of Writeback accesses(hits+misses)
1386system.l2c.Writeback_accesses::total 2758639 # number of Writeback accesses(hits+misses)
1387system.l2c.UpgradeReq_accesses::cpu0.data 71858 # number of UpgradeReq accesses(hits+misses)
1388system.l2c.UpgradeReq_accesses::cpu1.data 65000 # number of UpgradeReq accesses(hits+misses)
1389system.l2c.UpgradeReq_accesses::total 136858 # number of UpgradeReq accesses(hits+misses)
1390system.l2c.SCUpgradeReq_accesses::cpu0.data 9292 # number of SCUpgradeReq accesses(hits+misses)
1391system.l2c.SCUpgradeReq_accesses::cpu1.data 8678 # number of SCUpgradeReq accesses(hits+misses)
1392system.l2c.SCUpgradeReq_accesses::total 17970 # number of SCUpgradeReq accesses(hits+misses)
1393system.l2c.ReadExReq_accesses::cpu0.data 1134833 # number of ReadExReq accesses(hits+misses)
1394system.l2c.ReadExReq_accesses::cpu1.data 811760 # number of ReadExReq accesses(hits+misses)
1395system.l2c.ReadExReq_accesses::total 1946593 # number of ReadExReq accesses(hits+misses)
1396system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses)
1397system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6547 # number of ReadSharedReq accesses(hits+misses)
1398system.l2c.ReadSharedReq_accesses::cpu0.inst 568738 # number of ReadSharedReq accesses(hits+misses)
1399system.l2c.ReadSharedReq_accesses::cpu0.data 929051 # number of ReadSharedReq accesses(hits+misses)
1400system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8845 # number of ReadSharedReq accesses(hits+misses)
1401system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7075 # number of ReadSharedReq accesses(hits+misses)
1402system.l2c.ReadSharedReq_accesses::cpu1.inst 524506 # number of ReadSharedReq accesses(hits+misses)
1403system.l2c.ReadSharedReq_accesses::cpu1.data 881071 # number of ReadSharedReq accesses(hits+misses)
1404system.l2c.ReadSharedReq_accesses::total 2934501 # number of ReadSharedReq accesses(hits+misses)
1405system.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses
1406system.l2c.demand_accesses::cpu0.itb.walker 6547 # number of demand (read+write) accesses
1407system.l2c.demand_accesses::cpu0.inst 568738 # number of demand (read+write) accesses
1408system.l2c.demand_accesses::cpu0.data 2063884 # number of demand (read+write) accesses
1409system.l2c.demand_accesses::cpu1.dtb.walker 8845 # number of demand (read+write) accesses
1410system.l2c.demand_accesses::cpu1.itb.walker 7075 # number of demand (read+write) accesses
1411system.l2c.demand_accesses::cpu1.inst 524506 # number of demand (read+write) accesses
1412system.l2c.demand_accesses::cpu1.data 1692831 # number of demand (read+write) accesses
1413system.l2c.demand_accesses::total 4881094 # number of demand (read+write) accesses
1414system.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses
1415system.l2c.overall_accesses::cpu0.itb.walker 6547 # number of overall (read+write) accesses
1416system.l2c.overall_accesses::cpu0.inst 568738 # number of overall (read+write) accesses
1417system.l2c.overall_accesses::cpu0.data 2063884 # number of overall (read+write) accesses
1418system.l2c.overall_accesses::cpu1.dtb.walker 8845 # number of overall (read+write) accesses
1419system.l2c.overall_accesses::cpu1.itb.walker 7075 # number of overall (read+write) accesses
1420system.l2c.overall_accesses::cpu1.inst 524506 # number of overall (read+write) accesses
1421system.l2c.overall_accesses::cpu1.data 1692831 # number of overall (read+write) accesses
1422system.l2c.overall_accesses::total 4881094 # number of overall (read+write) accesses
1423system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815483 # miss rate for UpgradeReq accesses
1424system.l2c.UpgradeReq_miss_rate::cpu1.data 0.832062 # miss rate for UpgradeReq accesses
1425system.l2c.UpgradeReq_miss_rate::total 0.823357 # miss rate for UpgradeReq accesses
1426system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.840616 # miss rate for SCUpgradeReq accesses
1427system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.857110 # miss rate for SCUpgradeReq accesses
1428system.l2c.SCUpgradeReq_miss_rate::total 0.848581 # miss rate for SCUpgradeReq accesses
1429system.l2c.ReadExReq_miss_rate::cpu0.data 0.719264 # miss rate for ReadExReq accesses
1430system.l2c.ReadExReq_miss_rate::cpu1.data 0.674269 # miss rate for ReadExReq accesses
1431system.l2c.ReadExReq_miss_rate::total 0.700501 # miss rate for ReadExReq accesses
1432system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for ReadSharedReq accesses
1433system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303345 # miss rate for ReadSharedReq accesses
1434system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095218 # miss rate for ReadSharedReq accesses
1435system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194503 # miss rate for ReadSharedReq accesses
1436system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for ReadSharedReq accesses
1437system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485795 # miss rate for ReadSharedReq accesses
1438system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.071870 # miss rate for ReadSharedReq accesses
1439system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211174 # miss rate for ReadSharedReq accesses
1440system.l2c.ReadSharedReq_miss_rate::total 0.160122 # miss rate for ReadSharedReq accesses
1441system.l2c.demand_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for demand accesses
1442system.l2c.demand_miss_rate::cpu0.itb.walker 0.303345 # miss rate for demand accesses
1443system.l2c.demand_miss_rate::cpu0.inst 0.095218 # miss rate for demand accesses
1444system.l2c.demand_miss_rate::cpu0.data 0.483045 # miss rate for demand accesses
1445system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for demand accesses
1446system.l2c.demand_miss_rate::cpu1.itb.walker 0.485795 # miss rate for demand accesses
1447system.l2c.demand_miss_rate::cpu1.inst 0.071870 # miss rate for demand accesses
1448system.l2c.demand_miss_rate::cpu1.data 0.433241 # miss rate for demand accesses
1449system.l2c.demand_miss_rate::total 0.375626 # miss rate for demand accesses
1450system.l2c.overall_miss_rate::cpu0.dtb.walker 0.274458 # miss rate for overall accesses
1451system.l2c.overall_miss_rate::cpu0.itb.walker 0.303345 # miss rate for overall accesses
1452system.l2c.overall_miss_rate::cpu0.inst 0.095218 # miss rate for overall accesses
1453system.l2c.overall_miss_rate::cpu0.data 0.483045 # miss rate for overall accesses
1454system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391521 # miss rate for overall accesses
1455system.l2c.overall_miss_rate::cpu1.itb.walker 0.485795 # miss rate for overall accesses
1456system.l2c.overall_miss_rate::cpu1.inst 0.071870 # miss rate for overall accesses
1457system.l2c.overall_miss_rate::cpu1.data 0.433241 # miss rate for overall accesses
1458system.l2c.overall_miss_rate::total 0.375626 # miss rate for overall accesses
1459system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1460system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1461system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1462system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1463system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1464system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1465system.l2c.fast_writes 0 # number of fast writes performed
1466system.l2c.cache_copies 0 # number of cache copies performed
1467system.l2c.writebacks::writebacks 1472038 # number of writebacks
1468system.l2c.writebacks::total 1472038 # number of writebacks
1469system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1470system.membus.trans_dist::ReadReq 82131 # Transaction distribution
1471system.membus.trans_dist::ReadResp 560921 # Transaction distribution
1472system.membus.trans_dist::WriteReq 38802 # Transaction distribution
1473system.membus.trans_dist::WriteResp 38802 # Transaction distribution
1474system.membus.trans_dist::Writeback 1578732 # Transaction distribution
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