1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.256223 # Number of seconds simulated
4sim_ticks 47256222864000 # Number of ticks simulated
5final_tick 47256222864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1686655 # Simulator instruction rate (inst/s)
8host_op_rate 2012712 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 87867845670 # Simulator tick rate (ticks/s)
10host_mem_usage 696856 # Number of bytes of host memory used
11host_seconds 537.81 # Real time elapsed on the host
12sim_insts 907100218 # Number of instructions simulated
13sim_ops 1082456754 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 160064 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 126784 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 3921972 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 37880648 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 245824 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 244416 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3131208 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 41316208 # Number of bytes read from this memory
25system.physmem.bytes_read::realview.ide 428544 # Number of bytes read from this memory
26system.physmem.bytes_read::total 87455668 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 3921972 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 3131208 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 7053180 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 106476736 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
33system.physmem.bytes_written::total 106497320 # Number of bytes written to this memory
34system.physmem.num_reads::cpu0.dtb.walker 2501 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 1981 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 65688 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 591898 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.dtb.walker 3841 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.itb.walker 3819 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.inst 49032 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.data 645582 # Number of read requests responded to by this memory
42system.physmem.num_reads::realview.ide 6696 # Number of read requests responded to by this memory
43system.physmem.num_reads::total 1371038 # Number of read requests responded to by this memory
44system.physmem.num_writes::writebacks 1663699 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
47system.physmem.num_writes::total 1666273 # Number of write requests responded to by this memory
48system.physmem.bw_read::cpu0.dtb.walker 3387 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.itb.walker 2683 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.inst 82994 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.data 801601 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.dtb.walker 5202 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.itb.walker 5172 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.inst 66260 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.data 874302 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::realview.ide 9069 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::total 1850670 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu0.inst 82994 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::cpu1.inst 66260 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::total 149254 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_write::writebacks 2253179 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::total 2253615 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_total::writebacks 2253179 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.dtb.walker 3387 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.itb.walker 2683 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.inst 82994 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.data 802037 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.dtb.walker 5202 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.itb.walker 5172 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.inst 66260 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.data 874302 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::realview.ide 9069 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::total 4104285 # Total bandwidth to/from this memory (bytes/s)
76system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
77system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
78system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
79system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
80system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
81system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
82system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
83system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
84system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory

--- 10 unchanged lines hidden (view full) ---

95system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
96system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
97system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
98system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
99system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
100system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
101system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
102system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
103system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
104system.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
105system.bridge.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
106system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
107system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
108system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
109system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
110system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
111system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
112system.cpu_clk_domain.clock 500 # Clock period in ticks
113system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
114system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
115system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
116system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
117system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
118system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
119system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
120system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
121system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

135system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
136system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
137system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
138system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
139system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
140system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
141system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
142system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
143system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
144system.cpu0.dtb.walker.walks 130714 # Table walker walks requested
145system.cpu0.dtb.walker.walksLong 130714 # Table walker walks initiated with long descriptors
146system.cpu0.dtb.walker.walkWaitTime::samples 130714 # Table walker wait (enqueue to first request) latency
147system.cpu0.dtb.walker.walkWaitTime::0 130714 100.00% 100.00% # Table walker wait (enqueue to first request) latency
148system.cpu0.dtb.walker.walkWaitTime::total 130714 # Table walker wait (enqueue to first request) latency
149system.cpu0.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution
150system.cpu0.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution
151system.cpu0.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution
152system.cpu0.dtb.walker.walkPageSizes::4K 100196 89.16% 89.16% # Table walker page sizes translated
153system.cpu0.dtb.walker.walkPageSizes::2M 12181 10.84% 100.00% # Table walker page sizes translated
154system.cpu0.dtb.walker.walkPageSizes::total 112377 # Table walker page sizes translated
155system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130714 # Table walker requests started/completed, data/inst
156system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
157system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130714 # Table walker requests started/completed, data/inst
158system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112377 # Table walker requests started/completed, data/inst
159system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
160system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112377 # Table walker requests started/completed, data/inst
161system.cpu0.dtb.walker.walkRequestOrigin::total 243091 # Table walker requests started/completed, data/inst
162system.cpu0.dtb.inst_hits 0 # ITB inst hits
163system.cpu0.dtb.inst_misses 0 # ITB inst misses
164system.cpu0.dtb.read_hits 93175374 # DTB read hits
165system.cpu0.dtb.read_misses 92435 # DTB read misses
166system.cpu0.dtb.write_hits 86370526 # DTB write hits
167system.cpu0.dtb.write_misses 38279 # DTB write misses
168system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
169system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
170system.cpu0.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
171system.cpu0.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
172system.cpu0.dtb.flush_entries 36393 # Number of entries that have been flushed from TLB
173system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
174system.cpu0.dtb.prefetch_faults 5252 # Number of TLB faults due to prefetch
175system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
176system.cpu0.dtb.perms_faults 10620 # Number of TLB faults due to permissions restrictions
177system.cpu0.dtb.read_accesses 93267809 # DTB read accesses
178system.cpu0.dtb.write_accesses 86408805 # DTB write accesses
179system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
180system.cpu0.dtb.hits 179545900 # DTB hits
181system.cpu0.dtb.misses 130714 # DTB misses
182system.cpu0.dtb.accesses 179676614 # DTB accesses
183system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
184system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
185system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
186system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
187system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
188system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
189system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
190system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
191system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

205system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
206system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
207system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
208system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
209system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
210system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
211system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
212system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
213system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
214system.cpu0.itb.walker.walks 60670 # Table walker walks requested
215system.cpu0.itb.walker.walksLong 60670 # Table walker walks initiated with long descriptors
216system.cpu0.itb.walker.walkWaitTime::samples 60670 # Table walker wait (enqueue to first request) latency
217system.cpu0.itb.walker.walkWaitTime::0 60670 100.00% 100.00% # Table walker wait (enqueue to first request) latency
218system.cpu0.itb.walker.walkWaitTime::total 60670 # Table walker wait (enqueue to first request) latency
219system.cpu0.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution
220system.cpu0.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution
221system.cpu0.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution
222system.cpu0.itb.walker.walkPageSizes::4K 54534 98.81% 98.81% # Table walker page sizes translated
223system.cpu0.itb.walker.walkPageSizes::2M 657 1.19% 100.00% # Table walker page sizes translated
224system.cpu0.itb.walker.walkPageSizes::total 55191 # Table walker page sizes translated
225system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
226system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60670 # Table walker requests started/completed, data/inst
227system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60670 # Table walker requests started/completed, data/inst
228system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
229system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55191 # Table walker requests started/completed, data/inst
230system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55191 # Table walker requests started/completed, data/inst
231system.cpu0.itb.walker.walkRequestOrigin::total 115861 # Table walker requests started/completed, data/inst
232system.cpu0.itb.inst_hits 460432126 # ITB inst hits
233system.cpu0.itb.inst_misses 60670 # ITB inst misses
234system.cpu0.itb.read_hits 0 # DTB read hits
235system.cpu0.itb.read_misses 0 # DTB read misses
236system.cpu0.itb.write_hits 0 # DTB write hits
237system.cpu0.itb.write_misses 0 # DTB write misses
238system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
239system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
240system.cpu0.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
241system.cpu0.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
242system.cpu0.itb.flush_entries 25186 # Number of entries that have been flushed from TLB
243system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
244system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
245system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
246system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
247system.cpu0.itb.read_accesses 0 # DTB read accesses
248system.cpu0.itb.write_accesses 0 # DTB write accesses
249system.cpu0.itb.inst_accesses 460492796 # ITB inst accesses
250system.cpu0.itb.hits 460432126 # DTB hits
251system.cpu0.itb.misses 60670 # DTB misses
252system.cpu0.itb.accesses 460492796 # DTB accesses
253system.cpu0.numPwrStateTransitions 26581 # Number of power state transitions
254system.cpu0.pwrStateClkGateDist::samples 13288 # Distribution of time spent in the clock gated state
255system.cpu0.pwrStateClkGateDist::mean 3535659625.946418 # Distribution of time spent in the clock gated state
256system.cpu0.pwrStateClkGateDist::stdev 88810636016.861053 # Distribution of time spent in the clock gated state
257system.cpu0.pwrStateClkGateDist::underflows 3229 24.30% 24.30% # Distribution of time spent in the clock gated state
258system.cpu0.pwrStateClkGateDist::1000-5e+10 10032 75.50% 99.80% # Distribution of time spent in the clock gated state
259system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state
260system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state
261system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
262system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
263system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
264system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
265system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state
266system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state
267system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
268system.cpu0.pwrStateClkGateDist::max_value 7390911651500 # Distribution of time spent in the clock gated state
269system.cpu0.pwrStateClkGateDist::total 13288 # Distribution of time spent in the clock gated state
270system.cpu0.pwrStateResidencyTicks::ON 274377754424 # Cumulative time (in ticks) in various power states
271system.cpu0.pwrStateResidencyTicks::CLK_GATED 46981845109576 # Cumulative time (in ticks) in various power states
272system.cpu0.numCycles 94512459022 # number of cpu cycles simulated
273system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
274system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
275system.cpu0.kern.inst.arm 0 # number of arm instructions executed
276system.cpu0.kern.inst.quiesce 13293 # number of quiesce instructions executed
277system.cpu0.committedInsts 460154624 # Number of instructions committed
278system.cpu0.committedOps 548413661 # Number of ops (including micro ops) committed
279system.cpu0.num_int_alu_accesses 509180687 # Number of integer alu accesses
280system.cpu0.num_fp_alu_accesses 522850 # Number of float alu accesses
281system.cpu0.num_func_calls 28957516 # number of times a function call or return occured
282system.cpu0.num_conditional_control_insts 67014933 # number of instructions that are conditional controls
283system.cpu0.num_int_insts 509180687 # number of integer instructions
284system.cpu0.num_fp_insts 522850 # number of float instructions
285system.cpu0.num_int_register_reads 679939222 # number of times the integer registers were read
286system.cpu0.num_int_register_writes 397756518 # number of times the integer registers were written
287system.cpu0.num_fp_register_reads 842282 # number of times the floating registers were read
288system.cpu0.num_fp_register_writes 446532 # number of times the floating registers were written
289system.cpu0.num_cc_register_reads 104721942 # number of times the CC registers were read
290system.cpu0.num_cc_register_writes 104390194 # number of times the CC registers were written
291system.cpu0.num_mem_refs 179652770 # number of memory refs
292system.cpu0.num_load_insts 93252874 # Number of load instructions
293system.cpu0.num_store_insts 86399896 # Number of store instructions
294system.cpu0.num_idle_cycles 93963703435.962769 # Number of idle cycles
295system.cpu0.num_busy_cycles 548755586.037238 # Number of busy cycles
296system.cpu0.not_idle_fraction 0.005806 # Percentage of non-idle cycles
297system.cpu0.idle_fraction 0.994194 # Percentage of idle cycles
298system.cpu0.Branches 101918794 # Number of branches fetched
299system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
300system.cpu0.op_class::IntAlu 367730477 67.01% 67.01% # Class of executed instruction
301system.cpu0.op_class::IntMult 1235344 0.23% 67.24% # Class of executed instruction
302system.cpu0.op_class::IntDiv 59786 0.01% 67.25% # Class of executed instruction
303system.cpu0.op_class::FloatAdd 8 0.00% 67.25% # Class of executed instruction
304system.cpu0.op_class::FloatCmp 13 0.00% 67.25% # Class of executed instruction
305system.cpu0.op_class::FloatCvt 21 0.00% 67.25% # Class of executed instruction
306system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction
307system.cpu0.op_class::FloatMultAcc 0 0.00% 67.25% # Class of executed instruction
308system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction
309system.cpu0.op_class::FloatMisc 72659 0.01% 67.26% # Class of executed instruction
310system.cpu0.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
311system.cpu0.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
312system.cpu0.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
313system.cpu0.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
314system.cpu0.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
315system.cpu0.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
316system.cpu0.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
317system.cpu0.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
318system.cpu0.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
319system.cpu0.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
320system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
321system.cpu0.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
322system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
323system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
324system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
325system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
326system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
327system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.26% # Class of executed instruction
328system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
329system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
330system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
331system.cpu0.op_class::MemRead 93191543 16.98% 84.24% # Class of executed instruction
332system.cpu0.op_class::MemWrite 86011078 15.67% 99.92% # Class of executed instruction
333system.cpu0.op_class::FloatMemRead 61331 0.01% 99.93% # Class of executed instruction
334system.cpu0.op_class::FloatMemWrite 388818 0.07% 100.00% # Class of executed instruction
335system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
336system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
337system.cpu0.op_class::total 548751079 # Class of executed instruction
338system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
339system.cpu0.dcache.tags.replacements 6361267 # number of replacements
340system.cpu0.dcache.tags.tagsinuse 499.577143 # Cycle average of tags in use
341system.cpu0.dcache.tags.total_refs 173125033 # Total number of references to valid blocks.
342system.cpu0.dcache.tags.sampled_refs 6361779 # Sample count of references to valid blocks.
343system.cpu0.dcache.tags.avg_refs 27.213305 # Average number of references to valid blocks.
344system.cpu0.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit.
345system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.577143 # Average occupied blocks per requestor
346system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975737 # Average percentage of cache occupancy
347system.cpu0.dcache.tags.occ_percent::total 0.975737 # Average percentage of cache occupancy
348system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
349system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
350system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
351system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
352system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
353system.cpu0.dcache.tags.tag_accesses 365631383 # Number of tag accesses
354system.cpu0.dcache.tags.data_accesses 365631383 # Number of data accesses
355system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
356system.cpu0.dcache.ReadReq_hits::cpu0.data 86603750 # number of ReadReq hits
357system.cpu0.dcache.ReadReq_hits::total 86603750 # number of ReadReq hits
358system.cpu0.dcache.WriteReq_hits::cpu0.data 81517458 # number of WriteReq hits
359system.cpu0.dcache.WriteReq_hits::total 81517458 # number of WriteReq hits
360system.cpu0.dcache.SoftPFReq_hits::cpu0.data 217950 # number of SoftPFReq hits
361system.cpu0.dcache.SoftPFReq_hits::total 217950 # number of SoftPFReq hits
362system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259225 # number of WriteLineReq hits
363system.cpu0.dcache.WriteLineReq_hits::total 259225 # number of WriteLineReq hits
364system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2136353 # number of LoadLockedReq hits
365system.cpu0.dcache.LoadLockedReq_hits::total 2136353 # number of LoadLockedReq hits
366system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2100440 # number of StoreCondReq hits
367system.cpu0.dcache.StoreCondReq_hits::total 2100440 # number of StoreCondReq hits
368system.cpu0.dcache.demand_hits::cpu0.data 168380433 # number of demand (read+write) hits
369system.cpu0.dcache.demand_hits::total 168380433 # number of demand (read+write) hits
370system.cpu0.dcache.overall_hits::cpu0.data 168598383 # number of overall hits
371system.cpu0.dcache.overall_hits::total 168598383 # number of overall hits
372system.cpu0.dcache.ReadReq_misses::cpu0.data 3343142 # number of ReadReq misses
373system.cpu0.dcache.ReadReq_misses::total 3343142 # number of ReadReq misses
374system.cpu0.dcache.WriteReq_misses::cpu0.data 1509525 # number of WriteReq misses
375system.cpu0.dcache.WriteReq_misses::total 1509525 # number of WriteReq misses
376system.cpu0.dcache.SoftPFReq_misses::cpu0.data 802963 # number of SoftPFReq misses
377system.cpu0.dcache.SoftPFReq_misses::total 802963 # number of SoftPFReq misses
378system.cpu0.dcache.WriteLineReq_misses::cpu0.data 820079 # number of WriteLineReq misses
379system.cpu0.dcache.WriteLineReq_misses::total 820079 # number of WriteLineReq misses
380system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119939 # number of LoadLockedReq misses
381system.cpu0.dcache.LoadLockedReq_misses::total 119939 # number of LoadLockedReq misses
382system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154648 # number of StoreCondReq misses
383system.cpu0.dcache.StoreCondReq_misses::total 154648 # number of StoreCondReq misses
384system.cpu0.dcache.demand_misses::cpu0.data 5672746 # number of demand (read+write) misses
385system.cpu0.dcache.demand_misses::total 5672746 # number of demand (read+write) misses
386system.cpu0.dcache.overall_misses::cpu0.data 6475709 # number of overall misses
387system.cpu0.dcache.overall_misses::total 6475709 # number of overall misses
388system.cpu0.dcache.ReadReq_accesses::cpu0.data 89946892 # number of ReadReq accesses(hits+misses)
389system.cpu0.dcache.ReadReq_accesses::total 89946892 # number of ReadReq accesses(hits+misses)
390system.cpu0.dcache.WriteReq_accesses::cpu0.data 83026983 # number of WriteReq accesses(hits+misses)
391system.cpu0.dcache.WriteReq_accesses::total 83026983 # number of WriteReq accesses(hits+misses)
392system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1020913 # number of SoftPFReq accesses(hits+misses)
393system.cpu0.dcache.SoftPFReq_accesses::total 1020913 # number of SoftPFReq accesses(hits+misses)
394system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1079304 # number of WriteLineReq accesses(hits+misses)
395system.cpu0.dcache.WriteLineReq_accesses::total 1079304 # number of WriteLineReq accesses(hits+misses)
396system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2256292 # number of LoadLockedReq accesses(hits+misses)
397system.cpu0.dcache.LoadLockedReq_accesses::total 2256292 # number of LoadLockedReq accesses(hits+misses)
398system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2255088 # number of StoreCondReq accesses(hits+misses)
399system.cpu0.dcache.StoreCondReq_accesses::total 2255088 # number of StoreCondReq accesses(hits+misses)
400system.cpu0.dcache.demand_accesses::cpu0.data 174053179 # number of demand (read+write) accesses
401system.cpu0.dcache.demand_accesses::total 174053179 # number of demand (read+write) accesses
402system.cpu0.dcache.overall_accesses::cpu0.data 175074092 # number of overall (read+write) accesses
403system.cpu0.dcache.overall_accesses::total 175074092 # number of overall (read+write) accesses
404system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037168 # miss rate for ReadReq accesses
405system.cpu0.dcache.ReadReq_miss_rate::total 0.037168 # miss rate for ReadReq accesses
406system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018181 # miss rate for WriteReq accesses
407system.cpu0.dcache.WriteReq_miss_rate::total 0.018181 # miss rate for WriteReq accesses
408system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786515 # miss rate for SoftPFReq accesses
409system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786515 # miss rate for SoftPFReq accesses
410system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759822 # miss rate for WriteLineReq accesses
411system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759822 # miss rate for WriteLineReq accesses
412system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053158 # miss rate for LoadLockedReq accesses
413system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053158 # miss rate for LoadLockedReq accesses
414system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068577 # miss rate for StoreCondReq accesses
415system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068577 # miss rate for StoreCondReq accesses
416system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032592 # miss rate for demand accesses
417system.cpu0.dcache.demand_miss_rate::total 0.032592 # miss rate for demand accesses
418system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036988 # miss rate for overall accesses
419system.cpu0.dcache.overall_miss_rate::total 0.036988 # miss rate for overall accesses
420system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
421system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
422system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
423system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
424system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
425system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
426system.cpu0.dcache.writebacks::writebacks 6361267 # number of writebacks
427system.cpu0.dcache.writebacks::total 6361267 # number of writebacks
428system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
429system.cpu0.icache.tags.replacements 5436488 # number of replacements
430system.cpu0.icache.tags.tagsinuse 511.989232 # Cycle average of tags in use
431system.cpu0.icache.tags.total_refs 455050312 # Total number of references to valid blocks.
432system.cpu0.icache.tags.sampled_refs 5437000 # Sample count of references to valid blocks.
433system.cpu0.icache.tags.avg_refs 83.695110 # Average number of references to valid blocks.
434system.cpu0.icache.tags.warmup_cycle 5738328000 # Cycle when the warmup percentage was hit.
435system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989232 # Average occupied blocks per requestor
436system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
437system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
438system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
439system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
440system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id
441system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
442system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
443system.cpu0.icache.tags.tag_accesses 926411639 # Number of tag accesses
444system.cpu0.icache.tags.data_accesses 926411639 # Number of data accesses
445system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
446system.cpu0.icache.ReadReq_hits::cpu0.inst 455050312 # number of ReadReq hits
447system.cpu0.icache.ReadReq_hits::total 455050312 # number of ReadReq hits
448system.cpu0.icache.demand_hits::cpu0.inst 455050312 # number of demand (read+write) hits
449system.cpu0.icache.demand_hits::total 455050312 # number of demand (read+write) hits
450system.cpu0.icache.overall_hits::cpu0.inst 455050312 # number of overall hits
451system.cpu0.icache.overall_hits::total 455050312 # number of overall hits
452system.cpu0.icache.ReadReq_misses::cpu0.inst 5437005 # number of ReadReq misses
453system.cpu0.icache.ReadReq_misses::total 5437005 # number of ReadReq misses
454system.cpu0.icache.demand_misses::cpu0.inst 5437005 # number of demand (read+write) misses
455system.cpu0.icache.demand_misses::total 5437005 # number of demand (read+write) misses
456system.cpu0.icache.overall_misses::cpu0.inst 5437005 # number of overall misses
457system.cpu0.icache.overall_misses::total 5437005 # number of overall misses
458system.cpu0.icache.ReadReq_accesses::cpu0.inst 460487317 # number of ReadReq accesses(hits+misses)
459system.cpu0.icache.ReadReq_accesses::total 460487317 # number of ReadReq accesses(hits+misses)
460system.cpu0.icache.demand_accesses::cpu0.inst 460487317 # number of demand (read+write) accesses
461system.cpu0.icache.demand_accesses::total 460487317 # number of demand (read+write) accesses
462system.cpu0.icache.overall_accesses::cpu0.inst 460487317 # number of overall (read+write) accesses
463system.cpu0.icache.overall_accesses::total 460487317 # number of overall (read+write) accesses
464system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011807 # miss rate for ReadReq accesses
465system.cpu0.icache.ReadReq_miss_rate::total 0.011807 # miss rate for ReadReq accesses
466system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011807 # miss rate for demand accesses
467system.cpu0.icache.demand_miss_rate::total 0.011807 # miss rate for demand accesses
468system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011807 # miss rate for overall accesses
469system.cpu0.icache.overall_miss_rate::total 0.011807 # miss rate for overall accesses
470system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
471system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
472system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
473system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
474system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
475system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
476system.cpu0.icache.writebacks::writebacks 5436488 # number of writebacks
477system.cpu0.icache.writebacks::total 5436488 # number of writebacks
478system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
479system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
480system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
481system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
482system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
483system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
484system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
485system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
486system.cpu0.l2cache.tags.replacements 2619867 # number of replacements
487system.cpu0.l2cache.tags.tagsinuse 15716.053325 # Cycle average of tags in use
488system.cpu0.l2cache.tags.total_refs 9431762 # Total number of references to valid blocks.
489system.cpu0.l2cache.tags.sampled_refs 2635628 # Sample count of references to valid blocks.
490system.cpu0.l2cache.tags.avg_refs 3.578563 # Average number of references to valid blocks.
491system.cpu0.l2cache.tags.warmup_cycle 269403000 # Cycle when the warmup percentage was hit.
492system.cpu0.l2cache.tags.occ_blocks::writebacks 15665.638757 # Average occupied blocks per requestor
493system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.618352 # Average occupied blocks per requestor
494system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.796216 # Average occupied blocks per requestor
495system.cpu0.l2cache.tags.occ_percent::writebacks 0.956155 # Average percentage of cache occupancy
496system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001869 # Average percentage of cache occupancy
497system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001208 # Average percentage of cache occupancy
498system.cpu0.l2cache.tags.occ_percent::total 0.959232 # Average percentage of cache occupancy
499system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
500system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15683 # Occupied blocks per task id
501system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
502system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id
503system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
504system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
505system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id
506system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2189 # Occupied blocks per task id
507system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5717 # Occupied blocks per task id
508system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5104 # Occupied blocks per task id
509system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id
510system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
511system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.957214 # Percentage of cache occupancy per task id
512system.cpu0.l2cache.tags.tag_accesses 403271236 # Number of tag accesses
513system.cpu0.l2cache.tags.data_accesses 403271236 # Number of data accesses
514system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
515system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 300949 # number of ReadReq hits
516system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154418 # number of ReadReq hits
517system.cpu0.l2cache.ReadReq_hits::total 455367 # number of ReadReq hits
518system.cpu0.l2cache.WritebackDirty_hits::writebacks 4541229 # number of WritebackDirty hits
519system.cpu0.l2cache.WritebackDirty_hits::total 4541229 # number of WritebackDirty hits
520system.cpu0.l2cache.WritebackClean_hits::writebacks 7255159 # number of WritebackClean hits
521system.cpu0.l2cache.WritebackClean_hits::total 7255159 # number of WritebackClean hits
522system.cpu0.l2cache.ReadExReq_hits::cpu0.data 644334 # number of ReadExReq hits
523system.cpu0.l2cache.ReadExReq_hits::total 644334 # number of ReadExReq hits
524system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4939776 # number of ReadCleanReq hits
525system.cpu0.l2cache.ReadCleanReq_hits::total 4939776 # number of ReadCleanReq hits
526system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3020372 # number of ReadSharedReq hits
527system.cpu0.l2cache.ReadSharedReq_hits::total 3020372 # number of ReadSharedReq hits
528system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222433 # number of InvalidateReq hits
529system.cpu0.l2cache.InvalidateReq_hits::total 222433 # number of InvalidateReq hits
530system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 300949 # number of demand (read+write) hits
531system.cpu0.l2cache.demand_hits::cpu0.itb.walker 154418 # number of demand (read+write) hits
532system.cpu0.l2cache.demand_hits::cpu0.inst 4939776 # number of demand (read+write) hits
533system.cpu0.l2cache.demand_hits::cpu0.data 3664706 # number of demand (read+write) hits
534system.cpu0.l2cache.demand_hits::total 9059849 # number of demand (read+write) hits
535system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 300949 # number of overall hits
536system.cpu0.l2cache.overall_hits::cpu0.itb.walker 154418 # number of overall hits
537system.cpu0.l2cache.overall_hits::cpu0.inst 4939776 # number of overall hits
538system.cpu0.l2cache.overall_hits::cpu0.data 3664706 # number of overall hits
539system.cpu0.l2cache.overall_hits::total 9059849 # number of overall hits
540system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21207 # number of ReadReq misses
541system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses
542system.cpu0.l2cache.ReadReq_misses::total 31327 # number of ReadReq misses
543system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134662 # number of UpgradeReq misses
544system.cpu0.l2cache.UpgradeReq_misses::total 134662 # number of UpgradeReq misses
545system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154648 # number of SCUpgradeReq misses
546system.cpu0.l2cache.SCUpgradeReq_misses::total 154648 # number of SCUpgradeReq misses
547system.cpu0.l2cache.ReadExReq_misses::cpu0.data 730529 # number of ReadExReq misses
548system.cpu0.l2cache.ReadExReq_misses::total 730529 # number of ReadExReq misses
549system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses
550system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses
551system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1245672 # number of ReadSharedReq misses
552system.cpu0.l2cache.ReadSharedReq_misses::total 1245672 # number of ReadSharedReq misses
553system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597646 # number of InvalidateReq misses
554system.cpu0.l2cache.InvalidateReq_misses::total 597646 # number of InvalidateReq misses
555system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21207 # number of demand (read+write) misses
556system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10120 # number of demand (read+write) misses
557system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses
558system.cpu0.l2cache.demand_misses::cpu0.data 1976201 # number of demand (read+write) misses
559system.cpu0.l2cache.demand_misses::total 2504757 # number of demand (read+write) misses
560system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21207 # number of overall misses
561system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10120 # number of overall misses
562system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses
563system.cpu0.l2cache.overall_misses::cpu0.data 1976201 # number of overall misses
564system.cpu0.l2cache.overall_misses::total 2504757 # number of overall misses
565system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 322156 # number of ReadReq accesses(hits+misses)
566system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164538 # number of ReadReq accesses(hits+misses)
567system.cpu0.l2cache.ReadReq_accesses::total 486694 # number of ReadReq accesses(hits+misses)
568system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4541229 # number of WritebackDirty accesses(hits+misses)
569system.cpu0.l2cache.WritebackDirty_accesses::total 4541229 # number of WritebackDirty accesses(hits+misses)
570system.cpu0.l2cache.WritebackClean_accesses::writebacks 7255159 # number of WritebackClean accesses(hits+misses)
571system.cpu0.l2cache.WritebackClean_accesses::total 7255159 # number of WritebackClean accesses(hits+misses)
572system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134662 # number of UpgradeReq accesses(hits+misses)
573system.cpu0.l2cache.UpgradeReq_accesses::total 134662 # number of UpgradeReq accesses(hits+misses)
574system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154648 # number of SCUpgradeReq accesses(hits+misses)
575system.cpu0.l2cache.SCUpgradeReq_accesses::total 154648 # number of SCUpgradeReq accesses(hits+misses)
576system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1374863 # number of ReadExReq accesses(hits+misses)
577system.cpu0.l2cache.ReadExReq_accesses::total 1374863 # number of ReadExReq accesses(hits+misses)
578system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5437005 # number of ReadCleanReq accesses(hits+misses)
579system.cpu0.l2cache.ReadCleanReq_accesses::total 5437005 # number of ReadCleanReq accesses(hits+misses)
580system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4266044 # number of ReadSharedReq accesses(hits+misses)
581system.cpu0.l2cache.ReadSharedReq_accesses::total 4266044 # number of ReadSharedReq accesses(hits+misses)
582system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 820079 # number of InvalidateReq accesses(hits+misses)
583system.cpu0.l2cache.InvalidateReq_accesses::total 820079 # number of InvalidateReq accesses(hits+misses)
584system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 322156 # number of demand (read+write) accesses
585system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164538 # number of demand (read+write) accesses
586system.cpu0.l2cache.demand_accesses::cpu0.inst 5437005 # number of demand (read+write) accesses
587system.cpu0.l2cache.demand_accesses::cpu0.data 5640907 # number of demand (read+write) accesses
588system.cpu0.l2cache.demand_accesses::total 11564606 # number of demand (read+write) accesses
589system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 322156 # number of overall (read+write) accesses
590system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164538 # number of overall (read+write) accesses
591system.cpu0.l2cache.overall_accesses::cpu0.inst 5437005 # number of overall (read+write) accesses
592system.cpu0.l2cache.overall_accesses::cpu0.data 5640907 # number of overall (read+write) accesses
593system.cpu0.l2cache.overall_accesses::total 11564606 # number of overall (read+write) accesses
594system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for ReadReq accesses
595system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061506 # miss rate for ReadReq accesses
596system.cpu0.l2cache.ReadReq_miss_rate::total 0.064367 # miss rate for ReadReq accesses
597system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
598system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
599system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
600system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
601system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.531347 # miss rate for ReadExReq accesses
602system.cpu0.l2cache.ReadExReq_miss_rate::total 0.531347 # miss rate for ReadExReq accesses
603system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091453 # miss rate for ReadCleanReq accesses
604system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091453 # miss rate for ReadCleanReq accesses
605system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.291997 # miss rate for ReadSharedReq accesses
606system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.291997 # miss rate for ReadSharedReq accesses
607system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728766 # miss rate for InvalidateReq accesses
608system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728766 # miss rate for InvalidateReq accesses
609system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for demand accesses
610system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061506 # miss rate for demand accesses
611system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091453 # miss rate for demand accesses
612system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350334 # miss rate for demand accesses
613system.cpu0.l2cache.demand_miss_rate::total 0.216588 # miss rate for demand accesses
614system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for overall accesses
615system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061506 # miss rate for overall accesses
616system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091453 # miss rate for overall accesses
617system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350334 # miss rate for overall accesses
618system.cpu0.l2cache.overall_miss_rate::total 0.216588 # miss rate for overall accesses
619system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
620system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
621system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
622system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
623system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
624system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
625system.cpu0.l2cache.writebacks::writebacks 1595934 # number of writebacks
626system.cpu0.l2cache.writebacks::total 1595934 # number of writebacks
627system.cpu0.toL2Bus.snoop_filter.tot_requests 24251358 # Total number of requests made to the snoop filter.
628system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12353916 # Number of requests hitting in the snoop filter with a single holder of the requested data.
629system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1372 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
630system.cpu0.toL2Bus.snoop_filter.tot_snoops 295344 # Total number of snoops made to the snoop filter.
631system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 295344 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
632system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
633system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
634system.cpu0.toL2Bus.trans_dist::ReadReq 597776 # Transaction distribution
635system.cpu0.toL2Bus.trans_dist::ReadResp 10300825 # Transaction distribution
636system.cpu0.toL2Bus.trans_dist::WriteReq 32321 # Transaction distribution
637system.cpu0.toL2Bus.trans_dist::WriteResp 32321 # Transaction distribution
638system.cpu0.toL2Bus.trans_dist::WritebackDirty 4541229 # Transaction distribution
639system.cpu0.toL2Bus.trans_dist::WritebackClean 7256526 # Transaction distribution
640system.cpu0.toL2Bus.trans_dist::UpgradeReq 134662 # Transaction distribution
641system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154648 # Transaction distribution
642system.cpu0.toL2Bus.trans_dist::UpgradeResp 289310 # Transaction distribution
643system.cpu0.toL2Bus.trans_dist::ReadExReq 1374863 # Transaction distribution
644system.cpu0.toL2Bus.trans_dist::ReadExResp 1374863 # Transaction distribution
645system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5437005 # Transaction distribution
646system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4266044 # Transaction distribution
647system.cpu0.toL2Bus.trans_dist::InvalidateReq 820079 # Transaction distribution
648system.cpu0.toL2Bus.trans_dist::InvalidateResp 820079 # Transaction distribution
649system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16319948 # Packet count per connected master and slave (bytes)
650system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19991301 # Packet count per connected master and slave (bytes)
651system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362448 # Packet count per connected master and slave (bytes)
652system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 758854 # Packet count per connected master and slave (bytes)
653system.cpu0.toL2Bus.pkt_count::total 37432551 # Packet count per connected master and slave (bytes)
654system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 695922452 # Cumulative packet size per connected master and slave (bytes)
655system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 768331945 # Cumulative packet size per connected master and slave (bytes)
656system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1449792 # Cumulative packet size per connected master and slave (bytes)
657system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3035416 # Cumulative packet size per connected master and slave (bytes)
658system.cpu0.toL2Bus.pkt_size::total 1468739605 # Cumulative packet size per connected master and slave (bytes)
659system.cpu0.toL2Bus.snoops 4809457 # Total snoops (count)
660system.cpu0.toL2Bus.snoopTraffic 106507396 # Total snoop traffic (bytes)
661system.cpu0.toL2Bus.snoop_fanout::samples 29250499 # Request fanout histogram
662system.cpu0.toL2Bus.snoop_fanout::mean 0.019295 # Request fanout histogram
663system.cpu0.toL2Bus.snoop_fanout::stdev 0.137560 # Request fanout histogram
664system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
665system.cpu0.toL2Bus.snoop_fanout::0 28686107 98.07% 98.07% # Request fanout histogram
666system.cpu0.toL2Bus.snoop_fanout::1 564392 1.93% 100.00% # Request fanout histogram
667system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
668system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
669system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
670system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
671system.cpu0.toL2Bus.snoop_fanout::total 29250499 # Request fanout histogram
672system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
673system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
674system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
675system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
676system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
677system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
678system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
679system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
680system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

694system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
695system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
696system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
697system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
698system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
699system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
700system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
701system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
702system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
703system.cpu1.dtb.walker.walks 149830 # Table walker walks requested
704system.cpu1.dtb.walker.walksLong 149830 # Table walker walks initiated with long descriptors
705system.cpu1.dtb.walker.walkWaitTime::samples 149830 # Table walker wait (enqueue to first request) latency
706system.cpu1.dtb.walker.walkWaitTime::0 149830 100.00% 100.00% # Table walker wait (enqueue to first request) latency
707system.cpu1.dtb.walker.walkWaitTime::total 149830 # Table walker wait (enqueue to first request) latency
708system.cpu1.dtb.walker.walksPending::samples -295973872 # Table walker pending requests distribution
709system.cpu1.dtb.walker.walksPending::0 -295973872 100.00% 100.00% # Table walker pending requests distribution
710system.cpu1.dtb.walker.walksPending::total -295973872 # Table walker pending requests distribution
711system.cpu1.dtb.walker.walkPageSizes::4K 115525 88.27% 88.27% # Table walker page sizes translated
712system.cpu1.dtb.walker.walkPageSizes::2M 15355 11.73% 100.00% # Table walker page sizes translated
713system.cpu1.dtb.walker.walkPageSizes::total 130880 # Table walker page sizes translated
714system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 149830 # Table walker requests started/completed, data/inst
715system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
716system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 149830 # Table walker requests started/completed, data/inst
717system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 130880 # Table walker requests started/completed, data/inst
718system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
719system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 130880 # Table walker requests started/completed, data/inst
720system.cpu1.dtb.walker.walkRequestOrigin::total 280710 # Table walker requests started/completed, data/inst
721system.cpu1.dtb.inst_hits 0 # ITB inst hits
722system.cpu1.dtb.inst_misses 0 # ITB inst misses
723system.cpu1.dtb.read_hits 93113840 # DTB read hits
724system.cpu1.dtb.read_misses 115970 # DTB read misses
725system.cpu1.dtb.write_hits 83725509 # DTB write hits
726system.cpu1.dtb.write_misses 33860 # DTB write misses
727system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
728system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
729system.cpu1.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
730system.cpu1.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
731system.cpu1.dtb.flush_entries 45912 # Number of entries that have been flushed from TLB
732system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
733system.cpu1.dtb.prefetch_faults 4582 # Number of TLB faults due to prefetch
734system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
735system.cpu1.dtb.perms_faults 11647 # Number of TLB faults due to permissions restrictions
736system.cpu1.dtb.read_accesses 93229810 # DTB read accesses
737system.cpu1.dtb.write_accesses 83759369 # DTB write accesses
738system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
739system.cpu1.dtb.hits 176839349 # DTB hits
740system.cpu1.dtb.misses 149830 # DTB misses
741system.cpu1.dtb.accesses 176989179 # DTB accesses
742system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
743system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
744system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
746system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
747system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
748system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
749system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
750system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

764system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
765system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
766system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
767system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
768system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
769system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
770system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
771system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
772system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
773system.cpu1.itb.walker.walks 62588 # Table walker walks requested
774system.cpu1.itb.walker.walksLong 62588 # Table walker walks initiated with long descriptors
775system.cpu1.itb.walker.walkWaitTime::samples 62588 # Table walker wait (enqueue to first request) latency
776system.cpu1.itb.walker.walkWaitTime::0 62588 100.00% 100.00% # Table walker wait (enqueue to first request) latency
777system.cpu1.itb.walker.walkWaitTime::total 62588 # Table walker wait (enqueue to first request) latency
778system.cpu1.itb.walker.walksPending::samples -295974872 # Table walker pending requests distribution
779system.cpu1.itb.walker.walksPending::0 -295974872 100.00% 100.00% # Table walker pending requests distribution
780system.cpu1.itb.walker.walksPending::total -295974872 # Table walker pending requests distribution
781system.cpu1.itb.walker.walkPageSizes::4K 55491 99.07% 99.07% # Table walker page sizes translated
782system.cpu1.itb.walker.walkPageSizes::2M 523 0.93% 100.00% # Table walker page sizes translated
783system.cpu1.itb.walker.walkPageSizes::total 56014 # Table walker page sizes translated
784system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
785system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62588 # Table walker requests started/completed, data/inst
786system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62588 # Table walker requests started/completed, data/inst
787system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
788system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56014 # Table walker requests started/completed, data/inst
789system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56014 # Table walker requests started/completed, data/inst
790system.cpu1.itb.walker.walkRequestOrigin::total 118602 # Table walker requests started/completed, data/inst
791system.cpu1.itb.inst_hits 447202663 # ITB inst hits
792system.cpu1.itb.inst_misses 62588 # ITB inst misses
793system.cpu1.itb.read_hits 0 # DTB read hits
794system.cpu1.itb.read_misses 0 # DTB read misses
795system.cpu1.itb.write_hits 0 # DTB write hits
796system.cpu1.itb.write_misses 0 # DTB write misses
797system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
798system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
799system.cpu1.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID
800system.cpu1.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID
801system.cpu1.itb.flush_entries 32344 # Number of entries that have been flushed from TLB
802system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
803system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
804system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
805system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
806system.cpu1.itb.read_accesses 0 # DTB read accesses
807system.cpu1.itb.write_accesses 0 # DTB write accesses
808system.cpu1.itb.inst_accesses 447265251 # ITB inst accesses
809system.cpu1.itb.hits 447202663 # DTB hits
810system.cpu1.itb.misses 62588 # DTB misses
811system.cpu1.itb.accesses 447265251 # DTB accesses
812system.cpu1.numPwrStateTransitions 12622 # Number of power state transitions
813system.cpu1.pwrStateClkGateDist::samples 6311 # Distribution of time spent in the clock gated state
814system.cpu1.pwrStateClkGateDist::mean 7445577920.705118 # Distribution of time spent in the clock gated state
815system.cpu1.pwrStateClkGateDist::stdev 138960729730.016388 # Distribution of time spent in the clock gated state
816system.cpu1.pwrStateClkGateDist::underflows 4567 72.37% 72.37% # Distribution of time spent in the clock gated state
817system.cpu1.pwrStateClkGateDist::1000-5e+10 1718 27.22% 99.59% # Distribution of time spent in the clock gated state
818system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.67% # Distribution of time spent in the clock gated state
819system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.05% 99.71% # Distribution of time spent in the clock gated state
820system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.75% # Distribution of time spent in the clock gated state
821system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.03% 99.78% # Distribution of time spent in the clock gated state
822system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state
823system.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state
824system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
825system.cpu1.pwrStateClkGateDist::max_value 6953792880276 # Distribution of time spent in the clock gated state
826system.cpu1.pwrStateClkGateDist::total 6311 # Distribution of time spent in the clock gated state
827system.cpu1.pwrStateResidencyTicks::ON 267180606430 # Cumulative time (in ticks) in various power states
828system.cpu1.pwrStateResidencyTicks::CLK_GATED 46989042257570 # Cumulative time (in ticks) in various power states
829system.cpu1.numCycles 94512452040 # number of cpu cycles simulated
830system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
831system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
832system.cpu1.kern.inst.arm 0 # number of arm instructions executed
833system.cpu1.kern.inst.quiesce 6311 # number of quiesce instructions executed
834system.cpu1.committedInsts 446945594 # Number of instructions committed
835system.cpu1.committedOps 534043093 # Number of ops (including micro ops) committed
836system.cpu1.num_int_alu_accesses 497796457 # Number of integer alu accesses
837system.cpu1.num_fp_alu_accesses 375258 # Number of float alu accesses
838system.cpu1.num_func_calls 29044812 # number of times a function call or return occured
839system.cpu1.num_conditional_control_insts 64056743 # number of instructions that are conditional controls
840system.cpu1.num_int_insts 497796457 # number of integer instructions
841system.cpu1.num_fp_insts 375258 # number of float instructions
842system.cpu1.num_int_register_reads 659899184 # number of times the integer registers were read
843system.cpu1.num_int_register_writes 389220604 # number of times the integer registers were written
844system.cpu1.num_fp_register_reads 611056 # number of times the floating registers were read
845system.cpu1.num_fp_register_writes 302696 # number of times the floating registers were written
846system.cpu1.num_cc_register_reads 95980638 # number of times the CC registers were read
847system.cpu1.num_cc_register_writes 95700174 # number of times the CC registers were written
848system.cpu1.num_mem_refs 176965712 # number of memory refs
849system.cpu1.num_load_insts 93216701 # Number of load instructions
850system.cpu1.num_store_insts 83749011 # Number of store instructions
851system.cpu1.num_idle_cycles 93978090791.450775 # Number of idle cycles
852system.cpu1.num_busy_cycles 534361248.549225 # Number of busy cycles
853system.cpu1.not_idle_fraction 0.005654 # Percentage of non-idle cycles
854system.cpu1.idle_fraction 0.994346 # Percentage of idle cycles
855system.cpu1.Branches 98364194 # Number of branches fetched
856system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
857system.cpu1.op_class::IntAlu 356129610 66.65% 66.65% # Class of executed instruction
858system.cpu1.op_class::IntMult 1162336 0.22% 66.86% # Class of executed instruction
859system.cpu1.op_class::IntDiv 62196 0.01% 66.88% # Class of executed instruction
860system.cpu1.op_class::FloatAdd 0 0.00% 66.88% # Class of executed instruction
861system.cpu1.op_class::FloatCmp 0 0.00% 66.88% # Class of executed instruction
862system.cpu1.op_class::FloatCvt 0 0.00% 66.88% # Class of executed instruction
863system.cpu1.op_class::FloatMult 0 0.00% 66.88% # Class of executed instruction
864system.cpu1.op_class::FloatMultAcc 0 0.00% 66.88% # Class of executed instruction
865system.cpu1.op_class::FloatDiv 0 0.00% 66.88% # Class of executed instruction
866system.cpu1.op_class::FloatMisc 36452 0.01% 66.88% # Class of executed instruction
867system.cpu1.op_class::FloatSqrt 0 0.00% 66.88% # Class of executed instruction
868system.cpu1.op_class::SimdAdd 0 0.00% 66.88% # Class of executed instruction
869system.cpu1.op_class::SimdAddAcc 0 0.00% 66.88% # Class of executed instruction
870system.cpu1.op_class::SimdAlu 0 0.00% 66.88% # Class of executed instruction
871system.cpu1.op_class::SimdCmp 0 0.00% 66.88% # Class of executed instruction
872system.cpu1.op_class::SimdCvt 0 0.00% 66.88% # Class of executed instruction
873system.cpu1.op_class::SimdMisc 0 0.00% 66.88% # Class of executed instruction
874system.cpu1.op_class::SimdMult 0 0.00% 66.88% # Class of executed instruction
875system.cpu1.op_class::SimdMultAcc 0 0.00% 66.88% # Class of executed instruction
876system.cpu1.op_class::SimdShift 0 0.00% 66.88% # Class of executed instruction
877system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.88% # Class of executed instruction
878system.cpu1.op_class::SimdSqrt 0 0.00% 66.88% # Class of executed instruction
879system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.88% # Class of executed instruction
880system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.88% # Class of executed instruction
881system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.88% # Class of executed instruction
882system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.88% # Class of executed instruction
883system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.88% # Class of executed instruction
884system.cpu1.op_class::SimdFloatMisc 0 0.00% 66.88% # Class of executed instruction
885system.cpu1.op_class::SimdFloatMult 0 0.00% 66.88% # Class of executed instruction
886system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.88% # Class of executed instruction
887system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.88% # Class of executed instruction
888system.cpu1.op_class::MemRead 93166406 17.44% 84.32% # Class of executed instruction
889system.cpu1.op_class::MemWrite 83460500 15.62% 99.94% # Class of executed instruction
890system.cpu1.op_class::FloatMemRead 50295 0.01% 99.95% # Class of executed instruction
891system.cpu1.op_class::FloatMemWrite 288511 0.05% 100.00% # Class of executed instruction
892system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
893system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
894system.cpu1.op_class::total 534356306 # Class of executed instruction
895system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
896system.cpu1.dcache.tags.replacements 6135169 # number of replacements
897system.cpu1.dcache.tags.tagsinuse 439.724728 # Cycle average of tags in use
898system.cpu1.dcache.tags.total_refs 170720636 # Total number of references to valid blocks.
899system.cpu1.dcache.tags.sampled_refs 6135681 # Sample count of references to valid blocks.
900system.cpu1.dcache.tags.avg_refs 27.824236 # Average number of references to valid blocks.
901system.cpu1.dcache.tags.warmup_cycle 8470256211500 # Cycle when the warmup percentage was hit.
902system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.724728 # Average occupied blocks per requestor
903system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858837 # Average percentage of cache occupancy
904system.cpu1.dcache.tags.occ_percent::total 0.858837 # Average percentage of cache occupancy
905system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
906system.cpu1.dcache.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id
907system.cpu1.dcache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id
908system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
909system.cpu1.dcache.tags.tag_accesses 360116437 # Number of tag accesses
910system.cpu1.dcache.tags.data_accesses 360116437 # Number of data accesses
911system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
912system.cpu1.dcache.ReadReq_hits::cpu1.data 86463703 # number of ReadReq hits
913system.cpu1.dcache.ReadReq_hits::total 86463703 # number of ReadReq hits
914system.cpu1.dcache.WriteReq_hits::cpu1.data 79472088 # number of WriteReq hits
915system.cpu1.dcache.WriteReq_hits::total 79472088 # number of WriteReq hits
916system.cpu1.dcache.SoftPFReq_hits::cpu1.data 192310 # number of SoftPFReq hits
917system.cpu1.dcache.SoftPFReq_hits::total 192310 # number of SoftPFReq hits
918system.cpu1.dcache.WriteLineReq_hits::cpu1.data 67346 # number of WriteLineReq hits
919system.cpu1.dcache.WriteLineReq_hits::total 67346 # number of WriteLineReq hits
920system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2116228 # number of LoadLockedReq hits
921system.cpu1.dcache.LoadLockedReq_hits::total 2116228 # number of LoadLockedReq hits
922system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2109994 # number of StoreCondReq hits
923system.cpu1.dcache.StoreCondReq_hits::total 2109994 # number of StoreCondReq hits
924system.cpu1.dcache.demand_hits::cpu1.data 166003137 # number of demand (read+write) hits
925system.cpu1.dcache.demand_hits::total 166003137 # number of demand (read+write) hits
926system.cpu1.dcache.overall_hits::cpu1.data 166195447 # number of overall hits
927system.cpu1.dcache.overall_hits::total 166195447 # number of overall hits
928system.cpu1.dcache.ReadReq_misses::cpu1.data 3476659 # number of ReadReq misses
929system.cpu1.dcache.ReadReq_misses::total 3476659 # number of ReadReq misses
930system.cpu1.dcache.WriteReq_misses::cpu1.data 1488439 # number of WriteReq misses
931system.cpu1.dcache.WriteReq_misses::total 1488439 # number of WriteReq misses
932system.cpu1.dcache.SoftPFReq_misses::cpu1.data 809340 # number of SoftPFReq misses
933system.cpu1.dcache.SoftPFReq_misses::total 809340 # number of SoftPFReq misses
934system.cpu1.dcache.WriteLineReq_misses::cpu1.data 440862 # number of WriteLineReq misses
935system.cpu1.dcache.WriteLineReq_misses::total 440862 # number of WriteLineReq misses
936system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151875 # number of LoadLockedReq misses
937system.cpu1.dcache.LoadLockedReq_misses::total 151875 # number of LoadLockedReq misses
938system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156847 # number of StoreCondReq misses
939system.cpu1.dcache.StoreCondReq_misses::total 156847 # number of StoreCondReq misses
940system.cpu1.dcache.demand_misses::cpu1.data 5405960 # number of demand (read+write) misses
941system.cpu1.dcache.demand_misses::total 5405960 # number of demand (read+write) misses
942system.cpu1.dcache.overall_misses::cpu1.data 6215300 # number of overall misses
943system.cpu1.dcache.overall_misses::total 6215300 # number of overall misses
944system.cpu1.dcache.ReadReq_accesses::cpu1.data 89940362 # number of ReadReq accesses(hits+misses)
945system.cpu1.dcache.ReadReq_accesses::total 89940362 # number of ReadReq accesses(hits+misses)
946system.cpu1.dcache.WriteReq_accesses::cpu1.data 80960527 # number of WriteReq accesses(hits+misses)
947system.cpu1.dcache.WriteReq_accesses::total 80960527 # number of WriteReq accesses(hits+misses)
948system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 1001650 # number of SoftPFReq accesses(hits+misses)
949system.cpu1.dcache.SoftPFReq_accesses::total 1001650 # number of SoftPFReq accesses(hits+misses)
950system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 508208 # number of WriteLineReq accesses(hits+misses)
951system.cpu1.dcache.WriteLineReq_accesses::total 508208 # number of WriteLineReq accesses(hits+misses)
952system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2268103 # number of LoadLockedReq accesses(hits+misses)
953system.cpu1.dcache.LoadLockedReq_accesses::total 2268103 # number of LoadLockedReq accesses(hits+misses)
954system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2266841 # number of StoreCondReq accesses(hits+misses)
955system.cpu1.dcache.StoreCondReq_accesses::total 2266841 # number of StoreCondReq accesses(hits+misses)
956system.cpu1.dcache.demand_accesses::cpu1.data 171409097 # number of demand (read+write) accesses
957system.cpu1.dcache.demand_accesses::total 171409097 # number of demand (read+write) accesses
958system.cpu1.dcache.overall_accesses::cpu1.data 172410747 # number of overall (read+write) accesses
959system.cpu1.dcache.overall_accesses::total 172410747 # number of overall (read+write) accesses
960system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038655 # miss rate for ReadReq accesses
961system.cpu1.dcache.ReadReq_miss_rate::total 0.038655 # miss rate for ReadReq accesses
962system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018385 # miss rate for WriteReq accesses
963system.cpu1.dcache.WriteReq_miss_rate::total 0.018385 # miss rate for WriteReq accesses
964system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808007 # miss rate for SoftPFReq accesses
965system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808007 # miss rate for SoftPFReq accesses
966system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.867483 # miss rate for WriteLineReq accesses
967system.cpu1.dcache.WriteLineReq_miss_rate::total 0.867483 # miss rate for WriteLineReq accesses
968system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066961 # miss rate for LoadLockedReq accesses
969system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066961 # miss rate for LoadLockedReq accesses
970system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069192 # miss rate for StoreCondReq accesses
971system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069192 # miss rate for StoreCondReq accesses
972system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031538 # miss rate for demand accesses
973system.cpu1.dcache.demand_miss_rate::total 0.031538 # miss rate for demand accesses
974system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036049 # miss rate for overall accesses
975system.cpu1.dcache.overall_miss_rate::total 0.036049 # miss rate for overall accesses
976system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
977system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
978system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
979system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
980system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
981system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
982system.cpu1.dcache.writebacks::writebacks 6135169 # number of writebacks
983system.cpu1.dcache.writebacks::total 6135169 # number of writebacks
984system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
985system.cpu1.icache.tags.replacements 4821762 # number of replacements
986system.cpu1.icache.tags.tagsinuse 496.439302 # Cycle average of tags in use
987system.cpu1.icache.tags.total_refs 442436403 # Total number of references to valid blocks.
988system.cpu1.icache.tags.sampled_refs 4822274 # Sample count of references to valid blocks.
989system.cpu1.icache.tags.avg_refs 91.748499 # Average number of references to valid blocks.
990system.cpu1.icache.tags.warmup_cycle 8470184249000 # Cycle when the warmup percentage was hit.
991system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439302 # Average occupied blocks per requestor
992system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy
993system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy
994system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
995system.cpu1.icache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
996system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
997system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
998system.cpu1.icache.tags.tag_accesses 899339628 # Number of tag accesses
999system.cpu1.icache.tags.data_accesses 899339628 # Number of data accesses
1000system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1001system.cpu1.icache.ReadReq_hits::cpu1.inst 442436403 # number of ReadReq hits
1002system.cpu1.icache.ReadReq_hits::total 442436403 # number of ReadReq hits
1003system.cpu1.icache.demand_hits::cpu1.inst 442436403 # number of demand (read+write) hits
1004system.cpu1.icache.demand_hits::total 442436403 # number of demand (read+write) hits
1005system.cpu1.icache.overall_hits::cpu1.inst 442436403 # number of overall hits
1006system.cpu1.icache.overall_hits::total 442436403 # number of overall hits
1007system.cpu1.icache.ReadReq_misses::cpu1.inst 4822274 # number of ReadReq misses
1008system.cpu1.icache.ReadReq_misses::total 4822274 # number of ReadReq misses
1009system.cpu1.icache.demand_misses::cpu1.inst 4822274 # number of demand (read+write) misses
1010system.cpu1.icache.demand_misses::total 4822274 # number of demand (read+write) misses
1011system.cpu1.icache.overall_misses::cpu1.inst 4822274 # number of overall misses
1012system.cpu1.icache.overall_misses::total 4822274 # number of overall misses
1013system.cpu1.icache.ReadReq_accesses::cpu1.inst 447258677 # number of ReadReq accesses(hits+misses)
1014system.cpu1.icache.ReadReq_accesses::total 447258677 # number of ReadReq accesses(hits+misses)
1015system.cpu1.icache.demand_accesses::cpu1.inst 447258677 # number of demand (read+write) accesses
1016system.cpu1.icache.demand_accesses::total 447258677 # number of demand (read+write) accesses
1017system.cpu1.icache.overall_accesses::cpu1.inst 447258677 # number of overall (read+write) accesses
1018system.cpu1.icache.overall_accesses::total 447258677 # number of overall (read+write) accesses
1019system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010782 # miss rate for ReadReq accesses
1020system.cpu1.icache.ReadReq_miss_rate::total 0.010782 # miss rate for ReadReq accesses
1021system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010782 # miss rate for demand accesses
1022system.cpu1.icache.demand_miss_rate::total 0.010782 # miss rate for demand accesses
1023system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010782 # miss rate for overall accesses
1024system.cpu1.icache.overall_miss_rate::total 0.010782 # miss rate for overall accesses
1025system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1026system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1027system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1028system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1029system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1030system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1031system.cpu1.icache.writebacks::writebacks 4821762 # number of writebacks
1032system.cpu1.icache.writebacks::total 4821762 # number of writebacks
1033system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1034system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
1035system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
1036system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
1037system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1038system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1039system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
1040system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1041system.cpu1.l2cache.tags.replacements 2257136 # number of replacements
1042system.cpu1.l2cache.tags.tagsinuse 13044.860493 # Cycle average of tags in use
1043system.cpu1.l2cache.tags.total_refs 8980176 # Total number of references to valid blocks.
1044system.cpu1.l2cache.tags.sampled_refs 2273016 # Sample count of references to valid blocks.
1045system.cpu1.l2cache.tags.avg_refs 3.950776 # Average number of references to valid blocks.
1046system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1047system.cpu1.l2cache.tags.occ_blocks::writebacks 13005.388479 # Average occupied blocks per requestor
1048system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.571640 # Average occupied blocks per requestor
1049system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.900374 # Average occupied blocks per requestor
1050system.cpu1.l2cache.tags.occ_percent::writebacks 0.793786 # Average percentage of cache occupancy
1051system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001378 # Average percentage of cache occupancy
1052system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001032 # Average percentage of cache occupancy
1053system.cpu1.l2cache.tags.occ_percent::total 0.796195 # Average percentage of cache occupancy
1054system.cpu1.l2cache.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id
1055system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15820 # Occupied blocks per task id
1056system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
1057system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 29 # Occupied blocks per task id
1058system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
1059system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
1060system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 398 # Occupied blocks per task id
1061system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id
1062system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7364 # Occupied blocks per task id
1063system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id
1064system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1830 # Occupied blocks per task id
1065system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
1066system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.965576 # Percentage of cache occupancy per task id
1067system.cpu1.l2cache.tags.tag_accesses 376404615 # Number of tag accesses
1068system.cpu1.l2cache.tags.data_accesses 376404615 # Number of data accesses
1069system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1070system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 350077 # number of ReadReq hits
1071system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155851 # number of ReadReq hits
1072system.cpu1.l2cache.ReadReq_hits::total 505928 # number of ReadReq hits
1073system.cpu1.l2cache.WritebackDirty_hits::writebacks 4161473 # number of WritebackDirty hits
1074system.cpu1.l2cache.WritebackDirty_hits::total 4161473 # number of WritebackDirty hits
1075system.cpu1.l2cache.WritebackClean_hits::writebacks 6795092 # number of WritebackClean hits
1076system.cpu1.l2cache.WritebackClean_hits::total 6795092 # number of WritebackClean hits
1077system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621244 # number of ReadExReq hits
1078system.cpu1.l2cache.ReadExReq_hits::total 621244 # number of ReadExReq hits
1079system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4351439 # number of ReadCleanReq hits
1080system.cpu1.l2cache.ReadCleanReq_hits::total 4351439 # number of ReadCleanReq hits
1081system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3193387 # number of ReadSharedReq hits
1082system.cpu1.l2cache.ReadSharedReq_hits::total 3193387 # number of ReadSharedReq hits
1083system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167103 # number of InvalidateReq hits
1084system.cpu1.l2cache.InvalidateReq_hits::total 167103 # number of InvalidateReq hits
1085system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 350077 # number of demand (read+write) hits
1086system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155851 # number of demand (read+write) hits
1087system.cpu1.l2cache.demand_hits::cpu1.inst 4351439 # number of demand (read+write) hits
1088system.cpu1.l2cache.demand_hits::cpu1.data 3814631 # number of demand (read+write) hits
1089system.cpu1.l2cache.demand_hits::total 8671998 # number of demand (read+write) hits
1090system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 350077 # number of overall hits
1091system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155851 # number of overall hits
1092system.cpu1.l2cache.overall_hits::cpu1.inst 4351439 # number of overall hits
1093system.cpu1.l2cache.overall_hits::cpu1.data 3814631 # number of overall hits
1094system.cpu1.l2cache.overall_hits::total 8671998 # number of overall hits
1095system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22799 # number of ReadReq misses
1096system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11519 # number of ReadReq misses
1097system.cpu1.l2cache.ReadReq_misses::total 34318 # number of ReadReq misses
1098system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141879 # number of UpgradeReq misses
1099system.cpu1.l2cache.UpgradeReq_misses::total 141879 # number of UpgradeReq misses
1100system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156847 # number of SCUpgradeReq misses
1101system.cpu1.l2cache.SCUpgradeReq_misses::total 156847 # number of SCUpgradeReq misses
1102system.cpu1.l2cache.ReadExReq_misses::cpu1.data 725316 # number of ReadExReq misses
1103system.cpu1.l2cache.ReadExReq_misses::total 725316 # number of ReadExReq misses
1104system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470835 # number of ReadCleanReq misses
1105system.cpu1.l2cache.ReadCleanReq_misses::total 470835 # number of ReadCleanReq misses
1106system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1244487 # number of ReadSharedReq misses
1107system.cpu1.l2cache.ReadSharedReq_misses::total 1244487 # number of ReadSharedReq misses
1108system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 273759 # number of InvalidateReq misses
1109system.cpu1.l2cache.InvalidateReq_misses::total 273759 # number of InvalidateReq misses
1110system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22799 # number of demand (read+write) misses
1111system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11519 # number of demand (read+write) misses
1112system.cpu1.l2cache.demand_misses::cpu1.inst 470835 # number of demand (read+write) misses
1113system.cpu1.l2cache.demand_misses::cpu1.data 1969803 # number of demand (read+write) misses
1114system.cpu1.l2cache.demand_misses::total 2474956 # number of demand (read+write) misses
1115system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22799 # number of overall misses
1116system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11519 # number of overall misses
1117system.cpu1.l2cache.overall_misses::cpu1.inst 470835 # number of overall misses
1118system.cpu1.l2cache.overall_misses::cpu1.data 1969803 # number of overall misses
1119system.cpu1.l2cache.overall_misses::total 2474956 # number of overall misses
1120system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 372876 # number of ReadReq accesses(hits+misses)
1121system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167370 # number of ReadReq accesses(hits+misses)
1122system.cpu1.l2cache.ReadReq_accesses::total 540246 # number of ReadReq accesses(hits+misses)
1123system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4161473 # number of WritebackDirty accesses(hits+misses)
1124system.cpu1.l2cache.WritebackDirty_accesses::total 4161473 # number of WritebackDirty accesses(hits+misses)
1125system.cpu1.l2cache.WritebackClean_accesses::writebacks 6795092 # number of WritebackClean accesses(hits+misses)
1126system.cpu1.l2cache.WritebackClean_accesses::total 6795092 # number of WritebackClean accesses(hits+misses)
1127system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 141879 # number of UpgradeReq accesses(hits+misses)
1128system.cpu1.l2cache.UpgradeReq_accesses::total 141879 # number of UpgradeReq accesses(hits+misses)
1129system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156847 # number of SCUpgradeReq accesses(hits+misses)
1130system.cpu1.l2cache.SCUpgradeReq_accesses::total 156847 # number of SCUpgradeReq accesses(hits+misses)
1131system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1346560 # number of ReadExReq accesses(hits+misses)
1132system.cpu1.l2cache.ReadExReq_accesses::total 1346560 # number of ReadExReq accesses(hits+misses)
1133system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4822274 # number of ReadCleanReq accesses(hits+misses)
1134system.cpu1.l2cache.ReadCleanReq_accesses::total 4822274 # number of ReadCleanReq accesses(hits+misses)
1135system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4437874 # number of ReadSharedReq accesses(hits+misses)
1136system.cpu1.l2cache.ReadSharedReq_accesses::total 4437874 # number of ReadSharedReq accesses(hits+misses)
1137system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 440862 # number of InvalidateReq accesses(hits+misses)
1138system.cpu1.l2cache.InvalidateReq_accesses::total 440862 # number of InvalidateReq accesses(hits+misses)
1139system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 372876 # number of demand (read+write) accesses
1140system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167370 # number of demand (read+write) accesses
1141system.cpu1.l2cache.demand_accesses::cpu1.inst 4822274 # number of demand (read+write) accesses
1142system.cpu1.l2cache.demand_accesses::cpu1.data 5784434 # number of demand (read+write) accesses
1143system.cpu1.l2cache.demand_accesses::total 11146954 # number of demand (read+write) accesses
1144system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 372876 # number of overall (read+write) accesses
1145system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167370 # number of overall (read+write) accesses
1146system.cpu1.l2cache.overall_accesses::cpu1.inst 4822274 # number of overall (read+write) accesses
1147system.cpu1.l2cache.overall_accesses::cpu1.data 5784434 # number of overall (read+write) accesses
1148system.cpu1.l2cache.overall_accesses::total 11146954 # number of overall (read+write) accesses
1149system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for ReadReq accesses
1150system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068824 # miss rate for ReadReq accesses
1151system.cpu1.l2cache.ReadReq_miss_rate::total 0.063523 # miss rate for ReadReq accesses
1152system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1153system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1154system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1155system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1156system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538644 # miss rate for ReadExReq accesses
1157system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538644 # miss rate for ReadExReq accesses
1158system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097638 # miss rate for ReadCleanReq accesses
1159system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097638 # miss rate for ReadCleanReq accesses
1160system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.280424 # miss rate for ReadSharedReq accesses
1161system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.280424 # miss rate for ReadSharedReq accesses
1162system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620963 # miss rate for InvalidateReq accesses
1163system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620963 # miss rate for InvalidateReq accesses
1164system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for demand accesses
1165system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068824 # miss rate for demand accesses
1166system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097638 # miss rate for demand accesses
1167system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340535 # miss rate for demand accesses
1168system.cpu1.l2cache.demand_miss_rate::total 0.222030 # miss rate for demand accesses
1169system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for overall accesses
1170system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068824 # miss rate for overall accesses
1171system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097638 # miss rate for overall accesses
1172system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340535 # miss rate for overall accesses
1173system.cpu1.l2cache.overall_miss_rate::total 0.222030 # miss rate for overall accesses
1174system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1175system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1176system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1177system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1178system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1179system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1180system.cpu1.l2cache.writebacks::writebacks 1247214 # number of writebacks
1181system.cpu1.l2cache.writebacks::total 1247214 # number of writebacks
1182system.cpu1.toL2Bus.snoop_filter.tot_requests 22589206 # Total number of requests made to the snoop filter.
1183system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11541877 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1184system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1185system.cpu1.toL2Bus.snoop_filter.tot_snoops 281509 # Total number of snoops made to the snoop filter.
1186system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 281509 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1187system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1188system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1189system.cpu1.toL2Bus.trans_dist::ReadReq 627108 # Transaction distribution
1190system.cpu1.toL2Bus.trans_dist::ReadResp 9887256 # Transaction distribution
1191system.cpu1.toL2Bus.trans_dist::WriteReq 6357 # Transaction distribution
1192system.cpu1.toL2Bus.trans_dist::WriteResp 6357 # Transaction distribution
1193system.cpu1.toL2Bus.trans_dist::WritebackDirty 4161473 # Transaction distribution
1194system.cpu1.toL2Bus.trans_dist::WritebackClean 6795458 # Transaction distribution
1195system.cpu1.toL2Bus.trans_dist::UpgradeReq 141879 # Transaction distribution
1196system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156847 # Transaction distribution
1197system.cpu1.toL2Bus.trans_dist::UpgradeResp 298726 # Transaction distribution
1198system.cpu1.toL2Bus.trans_dist::ReadExReq 1346560 # Transaction distribution
1199system.cpu1.toL2Bus.trans_dist::ReadExResp 1346560 # Transaction distribution
1200system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4822274 # Transaction distribution
1201system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4437874 # Transaction distribution
1202system.cpu1.toL2Bus.trans_dist::InvalidateReq 440862 # Transaction distribution
1203system.cpu1.toL2Bus.trans_dist::InvalidateResp 440862 # Transaction distribution
1204system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14466570 # Packet count per connected master and slave (bytes)
1205system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19208649 # Packet count per connected master and slave (bytes)
1206system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374184 # Packet count per connected master and slave (bytes)
1207system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 867050 # Packet count per connected master and slave (bytes)
1208system.cpu1.toL2Bus.pkt_count::total 34916453 # Packet count per connected master and slave (bytes)
1209system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617218824 # Cumulative packet size per connected master and slave (bytes)
1210system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 762892902 # Cumulative packet size per connected master and slave (bytes)
1211system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1496736 # Cumulative packet size per connected master and slave (bytes)
1212system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3468200 # Cumulative packet size per connected master and slave (bytes)
1213system.cpu1.toL2Bus.pkt_size::total 1385076662 # Cumulative packet size per connected master and slave (bytes)
1214system.cpu1.toL2Bus.snoops 4471176 # Total snoops (count)
1215system.cpu1.toL2Bus.snoopTraffic 86426880 # Total snoop traffic (bytes)
1216system.cpu1.toL2Bus.snoop_fanout::samples 27252775 # Request fanout histogram
1217system.cpu1.toL2Bus.snoop_fanout::mean 0.020850 # Request fanout histogram
1218system.cpu1.toL2Bus.snoop_fanout::stdev 0.142882 # Request fanout histogram
1219system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1220system.cpu1.toL2Bus.snoop_fanout::0 26684555 97.92% 97.92% # Request fanout histogram
1221system.cpu1.toL2Bus.snoop_fanout::1 568220 2.08% 100.00% # Request fanout histogram
1222system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1223system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1224system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1225system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1226system.cpu1.toL2Bus.snoop_fanout::total 27252775 # Request fanout histogram
1227system.iobus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1228system.iobus.trans_dist::ReadReq 40208 # Transaction distribution
1229system.iobus.trans_dist::ReadResp 40208 # Transaction distribution
1230system.iobus.trans_dist::WriteReq 136550 # Transaction distribution
1231system.iobus.trans_dist::WriteResp 136550 # Transaction distribution
1232system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47302 # Packet count per connected master and slave (bytes)
1233system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1234system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1235system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1236system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1237system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1238system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1239system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1240system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1241system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1242system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1243system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
1244system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1245system.iobus.pkt_count_system.bridge.master::total 122236 # Packet count per connected master and slave (bytes)
1246system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes)
1247system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes)
1248system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1249system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1250system.iobus.pkt_count::total 353516 # Packet count per connected master and slave (bytes)
1251system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47322 # Cumulative packet size per connected master and slave (bytes)
1252system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1253system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
1254system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1255system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1256system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1257system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1258system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1259system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1260system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1261system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1262system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
1263system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1264system.iobus.pkt_size_system.bridge.master::total 155343 # Cumulative packet size per connected master and slave (bytes)
1265system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes)
1266system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes)
1267system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1268system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1269system.iobus.pkt_size::total 7496245 # Cumulative packet size per connected master and slave (bytes)
1270system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1271system.iocache.tags.replacements 115580 # number of replacements
1272system.iocache.tags.tagsinuse 11.294790 # Cycle average of tags in use
1273system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1274system.iocache.tags.sampled_refs 115596 # Sample count of references to valid blocks.
1275system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1276system.iocache.tags.warmup_cycle 9107754177509 # Cycle when the warmup percentage was hit.
1277system.iocache.tags.occ_blocks::realview.ethernet 3.848737 # Average occupied blocks per requestor
1278system.iocache.tags.occ_blocks::realview.ide 7.446053 # Average occupied blocks per requestor
1279system.iocache.tags.occ_percent::realview.ethernet 0.240546 # Average percentage of cache occupancy
1280system.iocache.tags.occ_percent::realview.ide 0.465378 # Average percentage of cache occupancy
1281system.iocache.tags.occ_percent::total 0.705924 # Average percentage of cache occupancy
1282system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1283system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1284system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1285system.iocache.tags.tag_accesses 1040757 # Number of tag accesses
1286system.iocache.tags.data_accesses 1040757 # Number of data accesses
1287system.iocache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1288system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1289system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses
1290system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses
1291system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1292system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1293system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
1294system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
1295system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1296system.iocache.demand_misses::realview.ide 115600 # number of demand (read+write) misses
1297system.iocache.demand_misses::total 115640 # number of demand (read+write) misses
1298system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1299system.iocache.overall_misses::realview.ide 115600 # number of overall misses
1300system.iocache.overall_misses::total 115640 # number of overall misses
1301system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1302system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses)
1303system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses)
1304system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1305system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1306system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
1307system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
1308system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1309system.iocache.demand_accesses::realview.ide 115600 # number of demand (read+write) accesses
1310system.iocache.demand_accesses::total 115640 # number of demand (read+write) accesses
1311system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1312system.iocache.overall_accesses::realview.ide 115600 # number of overall (read+write) accesses
1313system.iocache.overall_accesses::total 115640 # number of overall (read+write) accesses
1314system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1315system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1316system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1317system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1318system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1319system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1320system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1321system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1322system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1323system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1324system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1325system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1326system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1327system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1328system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1329system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1330system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1331system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1332system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1333system.iocache.writebacks::writebacks 106693 # number of writebacks
1334system.iocache.writebacks::total 106693 # number of writebacks
1335system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1336system.l2c.tags.replacements 2000796 # number of replacements
1337system.l2c.tags.tagsinuse 65236.747854 # Cycle average of tags in use
1338system.l2c.tags.total_refs 5872089 # Total number of references to valid blocks.
1339system.l2c.tags.sampled_refs 2062236 # Sample count of references to valid blocks.
1340system.l2c.tags.avg_refs 2.847438 # Average number of references to valid blocks.
1341system.l2c.tags.warmup_cycle 458916500 # Cycle when the warmup percentage was hit.
1342system.l2c.tags.occ_blocks::writebacks 10773.265369 # Average occupied blocks per requestor
1343system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.425728 # Average occupied blocks per requestor
1344system.l2c.tags.occ_blocks::cpu0.itb.walker 60.472796 # Average occupied blocks per requestor
1345system.l2c.tags.occ_blocks::cpu0.inst 3088.117960 # Average occupied blocks per requestor
1346system.l2c.tags.occ_blocks::cpu0.data 16913.790714 # Average occupied blocks per requestor
1347system.l2c.tags.occ_blocks::cpu1.dtb.walker 343.005231 # Average occupied blocks per requestor
1348system.l2c.tags.occ_blocks::cpu1.itb.walker 383.707168 # Average occupied blocks per requestor
1349system.l2c.tags.occ_blocks::cpu1.inst 2970.710524 # Average occupied blocks per requestor
1350system.l2c.tags.occ_blocks::cpu1.data 30646.252365 # Average occupied blocks per requestor
1351system.l2c.tags.occ_percent::writebacks 0.164387 # Average percentage of cache occupancy
1352system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000876 # Average percentage of cache occupancy
1353system.l2c.tags.occ_percent::cpu0.itb.walker 0.000923 # Average percentage of cache occupancy
1354system.l2c.tags.occ_percent::cpu0.inst 0.047121 # Average percentage of cache occupancy
1355system.l2c.tags.occ_percent::cpu0.data 0.258084 # Average percentage of cache occupancy
1356system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005234 # Average percentage of cache occupancy
1357system.l2c.tags.occ_percent::cpu1.itb.walker 0.005855 # Average percentage of cache occupancy
1358system.l2c.tags.occ_percent::cpu1.inst 0.045329 # Average percentage of cache occupancy
1359system.l2c.tags.occ_percent::cpu1.data 0.467625 # Average percentage of cache occupancy
1360system.l2c.tags.occ_percent::total 0.995434 # Average percentage of cache occupancy
1361system.l2c.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id
1362system.l2c.tags.occ_task_id_blocks::1024 61204 # Occupied blocks per task id
1363system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
1364system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id
1365system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
1366system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
1367system.l2c.tags.age_task_id_blocks_1024::2 3527 # Occupied blocks per task id
1368system.l2c.tags.age_task_id_blocks_1024::3 4478 # Occupied blocks per task id
1369system.l2c.tags.age_task_id_blocks_1024::4 52898 # Occupied blocks per task id
1370system.l2c.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
1371system.l2c.tags.occ_task_id_percent::1024 0.933899 # Percentage of cache occupancy per task id
1372system.l2c.tags.tag_accesses 73224508 # Number of tag accesses
1373system.l2c.tags.data_accesses 73224508 # Number of data accesses
1374system.l2c.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1375system.l2c.WritebackDirty_hits::writebacks 2843148 # number of WritebackDirty hits
1376system.l2c.WritebackDirty_hits::total 2843148 # number of WritebackDirty hits
1377system.l2c.UpgradeReq_hits::cpu0.data 57335 # number of UpgradeReq hits
1378system.l2c.UpgradeReq_hits::cpu1.data 51488 # number of UpgradeReq hits
1379system.l2c.UpgradeReq_hits::total 108823 # number of UpgradeReq hits
1380system.l2c.SCUpgradeReq_hits::cpu0.data 8370 # number of SCUpgradeReq hits
1381system.l2c.SCUpgradeReq_hits::cpu1.data 7752 # number of SCUpgradeReq hits
1382system.l2c.SCUpgradeReq_hits::total 16122 # number of SCUpgradeReq hits
1383system.l2c.ReadExReq_hits::cpu0.data 205747 # number of ReadExReq hits
1384system.l2c.ReadExReq_hits::cpu1.data 172848 # number of ReadExReq hits
1385system.l2c.ReadExReq_hits::total 378595 # number of ReadExReq hits
1386system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13551 # number of ReadSharedReq hits
1387system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5506 # number of ReadSharedReq hits
1388system.l2c.ReadSharedReq_hits::cpu0.inst 436242 # number of ReadSharedReq hits
1389system.l2c.ReadSharedReq_hits::cpu0.data 735903 # number of ReadSharedReq hits
1390system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12336 # number of ReadSharedReq hits
1391system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4370 # number of ReadSharedReq hits
1392system.l2c.ReadSharedReq_hits::cpu1.inst 421904 # number of ReadSharedReq hits
1393system.l2c.ReadSharedReq_hits::cpu1.data 692405 # number of ReadSharedReq hits
1394system.l2c.ReadSharedReq_hits::total 2322217 # number of ReadSharedReq hits
1395system.l2c.InvalidateReq_hits::cpu0.data 112000 # number of InvalidateReq hits
1396system.l2c.InvalidateReq_hits::cpu1.data 99469 # number of InvalidateReq hits
1397system.l2c.InvalidateReq_hits::total 211469 # number of InvalidateReq hits
1398system.l2c.demand_hits::cpu0.dtb.walker 13551 # number of demand (read+write) hits
1399system.l2c.demand_hits::cpu0.itb.walker 5506 # number of demand (read+write) hits
1400system.l2c.demand_hits::cpu0.inst 436242 # number of demand (read+write) hits
1401system.l2c.demand_hits::cpu0.data 941650 # number of demand (read+write) hits
1402system.l2c.demand_hits::cpu1.dtb.walker 12336 # number of demand (read+write) hits
1403system.l2c.demand_hits::cpu1.itb.walker 4370 # number of demand (read+write) hits
1404system.l2c.demand_hits::cpu1.inst 421904 # number of demand (read+write) hits
1405system.l2c.demand_hits::cpu1.data 865253 # number of demand (read+write) hits
1406system.l2c.demand_hits::total 2700812 # number of demand (read+write) hits
1407system.l2c.overall_hits::cpu0.dtb.walker 13551 # number of overall hits
1408system.l2c.overall_hits::cpu0.itb.walker 5506 # number of overall hits
1409system.l2c.overall_hits::cpu0.inst 436242 # number of overall hits
1410system.l2c.overall_hits::cpu0.data 941650 # number of overall hits
1411system.l2c.overall_hits::cpu1.dtb.walker 12336 # number of overall hits
1412system.l2c.overall_hits::cpu1.itb.walker 4370 # number of overall hits
1413system.l2c.overall_hits::cpu1.inst 421904 # number of overall hits
1414system.l2c.overall_hits::cpu1.data 865253 # number of overall hits
1415system.l2c.overall_hits::total 2700812 # number of overall hits
1416system.l2c.UpgradeReq_misses::cpu0.data 20153 # number of UpgradeReq misses
1417system.l2c.UpgradeReq_misses::cpu1.data 22374 # number of UpgradeReq misses
1418system.l2c.UpgradeReq_misses::total 42527 # number of UpgradeReq misses
1419system.l2c.SCUpgradeReq_misses::cpu0.data 465 # number of SCUpgradeReq misses
1420system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses
1421system.l2c.SCUpgradeReq_misses::total 1417 # number of SCUpgradeReq misses
1422system.l2c.ReadExReq_misses::cpu0.data 404904 # number of ReadExReq misses
1423system.l2c.ReadExReq_misses::cpu1.data 443379 # number of ReadExReq misses
1424system.l2c.ReadExReq_misses::total 848283 # number of ReadExReq misses
1425system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2501 # number of ReadSharedReq misses
1426system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1981 # number of ReadSharedReq misses
1427system.l2c.ReadSharedReq_misses::cpu0.inst 60987 # number of ReadSharedReq misses
1428system.l2c.ReadSharedReq_misses::cpu0.data 188974 # number of ReadSharedReq misses
1429system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3841 # number of ReadSharedReq misses
1430system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3819 # number of ReadSharedReq misses
1431system.l2c.ReadSharedReq_misses::cpu1.inst 48931 # number of ReadSharedReq misses
1432system.l2c.ReadSharedReq_misses::cpu1.data 203657 # number of ReadSharedReq misses
1433system.l2c.ReadSharedReq_misses::total 514691 # number of ReadSharedReq misses
1434system.l2c.InvalidateReq_misses::cpu0.data 441546 # number of InvalidateReq misses
1435system.l2c.InvalidateReq_misses::cpu1.data 132806 # number of InvalidateReq misses
1436system.l2c.InvalidateReq_misses::total 574352 # number of InvalidateReq misses
1437system.l2c.demand_misses::cpu0.dtb.walker 2501 # number of demand (read+write) misses
1438system.l2c.demand_misses::cpu0.itb.walker 1981 # number of demand (read+write) misses
1439system.l2c.demand_misses::cpu0.inst 60987 # number of demand (read+write) misses
1440system.l2c.demand_misses::cpu0.data 593878 # number of demand (read+write) misses
1441system.l2c.demand_misses::cpu1.dtb.walker 3841 # number of demand (read+write) misses
1442system.l2c.demand_misses::cpu1.itb.walker 3819 # number of demand (read+write) misses
1443system.l2c.demand_misses::cpu1.inst 48931 # number of demand (read+write) misses
1444system.l2c.demand_misses::cpu1.data 647036 # number of demand (read+write) misses
1445system.l2c.demand_misses::total 1362974 # number of demand (read+write) misses
1446system.l2c.overall_misses::cpu0.dtb.walker 2501 # number of overall misses
1447system.l2c.overall_misses::cpu0.itb.walker 1981 # number of overall misses
1448system.l2c.overall_misses::cpu0.inst 60987 # number of overall misses
1449system.l2c.overall_misses::cpu0.data 593878 # number of overall misses
1450system.l2c.overall_misses::cpu1.dtb.walker 3841 # number of overall misses
1451system.l2c.overall_misses::cpu1.itb.walker 3819 # number of overall misses
1452system.l2c.overall_misses::cpu1.inst 48931 # number of overall misses
1453system.l2c.overall_misses::cpu1.data 647036 # number of overall misses
1454system.l2c.overall_misses::total 1362974 # number of overall misses
1455system.l2c.WritebackDirty_accesses::writebacks 2843148 # number of WritebackDirty accesses(hits+misses)
1456system.l2c.WritebackDirty_accesses::total 2843148 # number of WritebackDirty accesses(hits+misses)
1457system.l2c.UpgradeReq_accesses::cpu0.data 77488 # number of UpgradeReq accesses(hits+misses)
1458system.l2c.UpgradeReq_accesses::cpu1.data 73862 # number of UpgradeReq accesses(hits+misses)
1459system.l2c.UpgradeReq_accesses::total 151350 # number of UpgradeReq accesses(hits+misses)
1460system.l2c.SCUpgradeReq_accesses::cpu0.data 8835 # number of SCUpgradeReq accesses(hits+misses)
1461system.l2c.SCUpgradeReq_accesses::cpu1.data 8704 # number of SCUpgradeReq accesses(hits+misses)
1462system.l2c.SCUpgradeReq_accesses::total 17539 # number of SCUpgradeReq accesses(hits+misses)
1463system.l2c.ReadExReq_accesses::cpu0.data 610651 # number of ReadExReq accesses(hits+misses)
1464system.l2c.ReadExReq_accesses::cpu1.data 616227 # number of ReadExReq accesses(hits+misses)
1465system.l2c.ReadExReq_accesses::total 1226878 # number of ReadExReq accesses(hits+misses)
1466system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16052 # number of ReadSharedReq accesses(hits+misses)
1467system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7487 # number of ReadSharedReq accesses(hits+misses)
1468system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses)
1469system.l2c.ReadSharedReq_accesses::cpu0.data 924877 # number of ReadSharedReq accesses(hits+misses)
1470system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16177 # number of ReadSharedReq accesses(hits+misses)
1471system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8189 # number of ReadSharedReq accesses(hits+misses)
1472system.l2c.ReadSharedReq_accesses::cpu1.inst 470835 # number of ReadSharedReq accesses(hits+misses)
1473system.l2c.ReadSharedReq_accesses::cpu1.data 896062 # number of ReadSharedReq accesses(hits+misses)
1474system.l2c.ReadSharedReq_accesses::total 2836908 # number of ReadSharedReq accesses(hits+misses)
1475system.l2c.InvalidateReq_accesses::cpu0.data 553546 # number of InvalidateReq accesses(hits+misses)
1476system.l2c.InvalidateReq_accesses::cpu1.data 232275 # number of InvalidateReq accesses(hits+misses)
1477system.l2c.InvalidateReq_accesses::total 785821 # number of InvalidateReq accesses(hits+misses)
1478system.l2c.demand_accesses::cpu0.dtb.walker 16052 # number of demand (read+write) accesses
1479system.l2c.demand_accesses::cpu0.itb.walker 7487 # number of demand (read+write) accesses
1480system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses
1481system.l2c.demand_accesses::cpu0.data 1535528 # number of demand (read+write) accesses
1482system.l2c.demand_accesses::cpu1.dtb.walker 16177 # number of demand (read+write) accesses
1483system.l2c.demand_accesses::cpu1.itb.walker 8189 # number of demand (read+write) accesses
1484system.l2c.demand_accesses::cpu1.inst 470835 # number of demand (read+write) accesses
1485system.l2c.demand_accesses::cpu1.data 1512289 # number of demand (read+write) accesses
1486system.l2c.demand_accesses::total 4063786 # number of demand (read+write) accesses
1487system.l2c.overall_accesses::cpu0.dtb.walker 16052 # number of overall (read+write) accesses
1488system.l2c.overall_accesses::cpu0.itb.walker 7487 # number of overall (read+write) accesses
1489system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses
1490system.l2c.overall_accesses::cpu0.data 1535528 # number of overall (read+write) accesses
1491system.l2c.overall_accesses::cpu1.dtb.walker 16177 # number of overall (read+write) accesses
1492system.l2c.overall_accesses::cpu1.itb.walker 8189 # number of overall (read+write) accesses
1493system.l2c.overall_accesses::cpu1.inst 470835 # number of overall (read+write) accesses
1494system.l2c.overall_accesses::cpu1.data 1512289 # number of overall (read+write) accesses
1495system.l2c.overall_accesses::total 4063786 # number of overall (read+write) accesses
1496system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260079 # miss rate for UpgradeReq accesses
1497system.l2c.UpgradeReq_miss_rate::cpu1.data 0.302916 # miss rate for UpgradeReq accesses
1498system.l2c.UpgradeReq_miss_rate::total 0.280984 # miss rate for UpgradeReq accesses
1499system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.052632 # miss rate for SCUpgradeReq accesses
1500system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.109375 # miss rate for SCUpgradeReq accesses
1501system.l2c.SCUpgradeReq_miss_rate::total 0.080791 # miss rate for SCUpgradeReq accesses
1502system.l2c.ReadExReq_miss_rate::cpu0.data 0.663069 # miss rate for ReadExReq accesses
1503system.l2c.ReadExReq_miss_rate::cpu1.data 0.719506 # miss rate for ReadExReq accesses
1504system.l2c.ReadExReq_miss_rate::total 0.691416 # miss rate for ReadExReq accesses
1505system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for ReadSharedReq accesses
1506system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.264592 # miss rate for ReadSharedReq accesses
1507system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.122654 # miss rate for ReadSharedReq accesses
1508system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.204323 # miss rate for ReadSharedReq accesses
1509system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for ReadSharedReq accesses
1510system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.466357 # miss rate for ReadSharedReq accesses
1511system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.103924 # miss rate for ReadSharedReq accesses
1512system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.227280 # miss rate for ReadSharedReq accesses
1513system.l2c.ReadSharedReq_miss_rate::total 0.181427 # miss rate for ReadSharedReq accesses
1514system.l2c.InvalidateReq_miss_rate::cpu0.data 0.797668 # miss rate for InvalidateReq accesses
1515system.l2c.InvalidateReq_miss_rate::cpu1.data 0.571762 # miss rate for InvalidateReq accesses
1516system.l2c.InvalidateReq_miss_rate::total 0.730894 # miss rate for InvalidateReq accesses
1517system.l2c.demand_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for demand accesses
1518system.l2c.demand_miss_rate::cpu0.itb.walker 0.264592 # miss rate for demand accesses
1519system.l2c.demand_miss_rate::cpu0.inst 0.122654 # miss rate for demand accesses
1520system.l2c.demand_miss_rate::cpu0.data 0.386758 # miss rate for demand accesses
1521system.l2c.demand_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for demand accesses
1522system.l2c.demand_miss_rate::cpu1.itb.walker 0.466357 # miss rate for demand accesses
1523system.l2c.demand_miss_rate::cpu1.inst 0.103924 # miss rate for demand accesses
1524system.l2c.demand_miss_rate::cpu1.data 0.427852 # miss rate for demand accesses
1525system.l2c.demand_miss_rate::total 0.335395 # miss rate for demand accesses
1526system.l2c.overall_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for overall accesses
1527system.l2c.overall_miss_rate::cpu0.itb.walker 0.264592 # miss rate for overall accesses
1528system.l2c.overall_miss_rate::cpu0.inst 0.122654 # miss rate for overall accesses
1529system.l2c.overall_miss_rate::cpu0.data 0.386758 # miss rate for overall accesses
1530system.l2c.overall_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for overall accesses
1531system.l2c.overall_miss_rate::cpu1.itb.walker 0.466357 # miss rate for overall accesses
1532system.l2c.overall_miss_rate::cpu1.inst 0.103924 # miss rate for overall accesses
1533system.l2c.overall_miss_rate::cpu1.data 0.427852 # miss rate for overall accesses
1534system.l2c.overall_miss_rate::total 0.335395 # miss rate for overall accesses
1535system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1536system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1537system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1538system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1539system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1540system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1541system.l2c.writebacks::writebacks 1557006 # number of writebacks
1542system.l2c.writebacks::total 1557006 # number of writebacks
1543system.membus.snoop_filter.tot_requests 4511574 # Total number of requests made to the snoop filter.
1544system.membus.snoop_filter.hit_single_requests 2519656 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1545system.membus.snoop_filter.hit_multi_requests 3180 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1546system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1547system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1548system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1549system.membus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1550system.membus.trans_dist::ReadReq 43614 # Transaction distribution
1551system.membus.trans_dist::ReadResp 567214 # Transaction distribution
1552system.membus.trans_dist::WriteReq 38678 # Transaction distribution
1553system.membus.trans_dist::WriteResp 38678 # Transaction distribution
1554system.membus.trans_dist::WritebackDirty 1663699 # Transaction distribution
1555system.membus.trans_dist::CleanEvict 266504 # Transaction distribution
1556system.membus.trans_dist::UpgradeReq 223308 # Transaction distribution
1557system.membus.trans_dist::SCUpgradeReq 295373 # Transaction distribution
1558system.membus.trans_dist::UpgradeResp 46773 # Transaction distribution
1559system.membus.trans_dist::ReadExReq 849453 # Transaction distribution
1560system.membus.trans_dist::ReadExResp 845457 # Transaction distribution
1561system.membus.trans_dist::ReadSharedReq 523600 # Transaction distribution
1562system.membus.trans_dist::InvalidateReq 689636 # Transaction distribution
1563system.membus.trans_dist::InvalidateResp 681080 # Transaction distribution
1564system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122236 # Packet count per connected master and slave (bytes)
1565system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
1566system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27410 # Packet count per connected master and slave (bytes)
1567system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6276469 # Packet count per connected master and slave (bytes)
1568system.membus.pkt_count_system.l2c.mem_side::total 6426207 # Packet count per connected master and slave (bytes)
1569system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346860 # Packet count per connected master and slave (bytes)
1570system.membus.pkt_count_system.iocache.mem_side::total 346860 # Packet count per connected master and slave (bytes)
1571system.membus.pkt_count::total 6773067 # Packet count per connected master and slave (bytes)
1572system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155343 # Cumulative packet size per connected master and slave (bytes)
1573system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
1574system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54820 # Cumulative packet size per connected master and slave (bytes)
1575system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 186738012 # Cumulative packet size per connected master and slave (bytes)
1576system.membus.pkt_size_system.l2c.mem_side::total 186948379 # Cumulative packet size per connected master and slave (bytes)
1577system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398528 # Cumulative packet size per connected master and slave (bytes)
1578system.membus.pkt_size_system.iocache.mem_side::total 7398528 # Cumulative packet size per connected master and slave (bytes)
1579system.membus.pkt_size::total 194346907 # Cumulative packet size per connected master and slave (bytes)
1580system.membus.snoops 0 # Total snoops (count)
1581system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1582system.membus.snoop_fanout::samples 4593865 # Request fanout histogram
1583system.membus.snoop_fanout::mean 0.007098 # Request fanout histogram
1584system.membus.snoop_fanout::stdev 0.083952 # Request fanout histogram
1585system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1586system.membus.snoop_fanout::0 4561256 99.29% 99.29% # Request fanout histogram
1587system.membus.snoop_fanout::1 32609 0.71% 100.00% # Request fanout histogram
1588system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1589system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1590system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1591system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1592system.membus.snoop_fanout::total 4593865 # Request fanout histogram
1593system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1594system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1595system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1596system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1597system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1598system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1599system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1600system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1601system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1602system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1603system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1604system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1605system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1606system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1607system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1608system.realview.ethernet.txBytes 966 # Bytes Transmitted
1609system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1610system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1611system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1612system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1613system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1614system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1615system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

--- 26 unchanged lines hidden (view full) ---

1642system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1643system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1644system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1645system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1646system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1647system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1648system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1649system.realview.ethernet.droppedPackets 0 # number of packets dropped
1650system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1651system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1652system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1653system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1654system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1655system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1656system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1657system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1658system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1659system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1660system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1661system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1662system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1663system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1664system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1665system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1666system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1667system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1668system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1669system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1670system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1671system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1672system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1673system.toL2Bus.snoop_filter.tot_requests 11315905 # Total number of requests made to the snoop filter.
1674system.toL2Bus.snoop_filter.hit_single_requests 5737208 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1675system.toL2Bus.snoop_filter.hit_multi_requests 1831359 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1676system.toL2Bus.snoop_filter.tot_snoops 298423 # Total number of snoops made to the snoop filter.
1677system.toL2Bus.snoop_filter.hit_single_snoops 272858 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1678system.toL2Bus.snoop_filter.hit_multi_snoops 25565 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1679system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states
1680system.toL2Bus.trans_dist::ReadReq 43616 # Transaction distribution
1681system.toL2Bus.trans_dist::ReadResp 3567484 # Transaction distribution
1682system.toL2Bus.trans_dist::WriteReq 38678 # Transaction distribution
1683system.toL2Bus.trans_dist::WriteResp 38678 # Transaction distribution
1684system.toL2Bus.trans_dist::WritebackDirty 2843148 # Transaction distribution
1685system.toL2Bus.trans_dist::CleanEvict 2033600 # Transaction distribution
1686system.toL2Bus.trans_dist::UpgradeReq 329302 # Transaction distribution
1687system.toL2Bus.trans_dist::SCUpgradeReq 311495 # Transaction distribution
1688system.toL2Bus.trans_dist::UpgradeResp 640797 # Transaction distribution
1689system.toL2Bus.trans_dist::ReadExReq 1403084 # Transaction distribution
1690system.toL2Bus.trans_dist::ReadExResp 1403084 # Transaction distribution
1691system.toL2Bus.trans_dist::ReadSharedReq 3523868 # Transaction distribution
1692system.toL2Bus.trans_dist::InvalidateReq 871405 # Transaction distribution
1693system.toL2Bus.trans_dist::InvalidateResp 871405 # Transaction distribution
1694system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9542040 # Packet count per connected master and slave (bytes)
1695system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8377604 # Packet count per connected master and slave (bytes)
1696system.toL2Bus.pkt_count::total 17919644 # Packet count per connected master and slave (bytes)
1697system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260882877 # Cumulative packet size per connected master and slave (bytes)
1698system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 236654062 # Cumulative packet size per connected master and slave (bytes)
1699system.toL2Bus.pkt_size::total 497536939 # Cumulative packet size per connected master and slave (bytes)
1700system.toL2Bus.snoops 2048171 # Total snoops (count)
1701system.toL2Bus.snoopTraffic 99695936 # Total snoop traffic (bytes)
1702system.toL2Bus.snoop_fanout::samples 13430913 # Request fanout histogram
1703system.toL2Bus.snoop_fanout::mean 0.303362 # Request fanout histogram
1704system.toL2Bus.snoop_fanout::stdev 0.463832 # Request fanout histogram
1705system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1706system.toL2Bus.snoop_fanout::0 9382052 69.85% 69.85% # Request fanout histogram
1707system.toL2Bus.snoop_fanout::1 4023296 29.96% 99.81% # Request fanout histogram
1708system.toL2Bus.snoop_fanout::2 25565 0.19% 100.00% # Request fanout histogram
1709system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1710system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1711system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1712system.toL2Bus.snoop_fanout::total 13430913 # Request fanout histogram
1713
1714---------- End Simulation Statistics ----------