| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.327140 # Number of seconds simulated 4sim_ticks 51327139864000 # Number of ticks simulated 5final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.327140 # Number of seconds simulated 4sim_ticks 51327139864000 # Number of ticks simulated 5final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 184861 # Simulator instruction rate (inst/s) 8host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11186950873 # Simulator tick rate (ticks/s) 10host_mem_usage 729056 # Number of bytes of host memory used 11host_seconds 4588.13 # Real time elapsed on the host | 7host_inst_rate 138298 # Simulator instruction rate (inst/s) 8host_op_rate 162502 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8369157499 # Simulator tick rate (ticks/s) 10host_mem_usage 688884 # Number of bytes of host memory used 11host_seconds 6132.89 # Real time elapsed on the host |
| 12sim_insts 848164321 # Number of instructions simulated 13sim_ops 996610207 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory --- 440 unchanged lines hidden (view full) --- 460system.cpu.dtb.read_hits 169398877 # DTB read hits 461system.cpu.dtb.read_misses 674798 # DTB read misses 462system.cpu.dtb.write_hits 147332912 # DTB write hits 463system.cpu.dtb.write_misses 272209 # DTB write misses 464system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 465system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 466system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 467system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID | 12sim_insts 848164321 # Number of instructions simulated 13sim_ops 996610207 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory --- 440 unchanged lines hidden (view full) --- 460system.cpu.dtb.read_hits 169398877 # DTB read hits 461system.cpu.dtb.read_misses 674798 # DTB read misses 462system.cpu.dtb.write_hits 147332912 # DTB write hits 463system.cpu.dtb.write_misses 272209 # DTB write misses 464system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 465system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 466system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 467system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID |
| 468system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB | 468system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB |
| 469system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions 470system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch 471system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 472system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions 473system.cpu.dtb.read_accesses 170073675 # DTB read accesses 474system.cpu.dtb.write_accesses 147605121 # DTB write accesses 475system.cpu.dtb.inst_accesses 0 # ITB inst accesses 476system.cpu.dtb.hits 316731789 # DTB hits --- 92 unchanged lines hidden (view full) --- 569system.cpu.itb.read_hits 0 # DTB read hits 570system.cpu.itb.read_misses 0 # DTB read misses 571system.cpu.itb.write_hits 0 # DTB write hits 572system.cpu.itb.write_misses 0 # DTB write misses 573system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 574system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 576system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID | 469system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions 470system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch 471system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 472system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions 473system.cpu.dtb.read_accesses 170073675 # DTB read accesses 474system.cpu.dtb.write_accesses 147605121 # DTB write accesses 475system.cpu.dtb.inst_accesses 0 # ITB inst accesses 476system.cpu.dtb.hits 316731789 # DTB hits --- 92 unchanged lines hidden (view full) --- 569system.cpu.itb.read_hits 0 # DTB read hits 570system.cpu.itb.read_misses 0 # DTB read misses 571system.cpu.itb.write_hits 0 # DTB write hits 572system.cpu.itb.write_misses 0 # DTB write misses 573system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 574system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID 576system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID |
| 577system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB | 577system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB |
| 578system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions 582system.cpu.itb.read_accesses 0 # DTB read accesses 583system.cpu.itb.write_accesses 0 # DTB write accesses 584system.cpu.itb.inst_accesses 357169890 # ITB inst accesses 585system.cpu.itb.hits 357007788 # DTB hits --- 1376 unchanged lines hidden --- | 578system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions 582system.cpu.itb.read_accesses 0 # DTB read accesses 583system.cpu.itb.write_accesses 0 # DTB write accesses 584system.cpu.itb.inst_accesses 357169890 # ITB inst accesses 585system.cpu.itb.hits 357007788 # DTB hits --- 1376 unchanged lines hidden --- |