| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.327140 # Number of seconds simulated 4sim_ticks 51327139864000 # Number of ticks simulated 5final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.327140 # Number of seconds simulated 4sim_ticks 51327139864000 # Number of ticks simulated 5final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 139665 # Simulator instruction rate (inst/s) 8host_op_rate 164109 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8451911555 # Simulator tick rate (ticks/s) 10host_mem_usage 688288 # Number of bytes of host memory used 11host_seconds 6072.84 # Real time elapsed on the host | 7host_inst_rate 139449 # Simulator instruction rate (inst/s) 8host_op_rate 163855 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8438816943 # Simulator tick rate (ticks/s) 10host_mem_usage 688284 # Number of bytes of host memory used 11host_seconds 6082.27 # Real time elapsed on the host |
| 12sim_insts 848164321 # Number of instructions simulated 13sim_ops 996610207 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory --- 554 unchanged lines hidden (view full) --- 574system.cpu.itb.write_accesses 0 # DTB write accesses 575system.cpu.itb.inst_accesses 357169890 # ITB inst accesses 576system.cpu.itb.hits 357007788 # DTB hits 577system.cpu.itb.misses 162102 # DTB misses 578system.cpu.itb.accesses 357169890 # DTB accesses 579system.cpu.numCycles 1631144067 # number of cpu cycles simulated 580system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 12sim_insts 848164321 # Number of instructions simulated 13sim_ops 996610207 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory --- 554 unchanged lines hidden (view full) --- 574system.cpu.itb.write_accesses 0 # DTB write accesses 575system.cpu.itb.inst_accesses 357169890 # ITB inst accesses 576system.cpu.itb.hits 357007788 # DTB hits 577system.cpu.itb.misses 162102 # DTB misses 578system.cpu.itb.accesses 357169890 # DTB accesses 579system.cpu.numCycles 1631144067 # number of cpu cycles simulated 580system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 582system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss | 582system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss |
| 583system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed 584system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered 585system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken 586system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked 587system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing 588system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb 589system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 590system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps 591system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions 592system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR 593system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched 594system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed 595system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed | 583system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed 584system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered 585system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken 586system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked 587system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing 588system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb 589system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 590system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps 591system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions 592system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR 593system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched 594system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed 595system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed |
| 596system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total) | 596system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total) |
| 597system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 597system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 600system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total) | 600system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total) |
| 601system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 605system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 606system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 601system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 605system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 606system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 607system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total) | 607system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total) |
| 608system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle 609system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle | 608system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle 609system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle |
| 610system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle | 610system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle |
| 611system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked 612system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running 613system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking 614system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing 615system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch 616system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction 617system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode 618system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode 619system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing | 611system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked 612system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running 613system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking 614system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing 615system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch 616system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction 617system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode 618system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode 619system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing |
| 620system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle | 620system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle |
| 621system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking 622system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst 623system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running 624system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking | 621system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking 622system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst 623system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running 624system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking |
| 625system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename | 625system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename |
| 626system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename 627system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full 628system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full 629system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full | 626system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename 627system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full 628system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full 629system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full |
| 630system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full | 630system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full |
| 631system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers | 631system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers |
| 632system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed 633system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made 634system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups | 632system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed 633system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made 634system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups |
| 635system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups 636system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed | 635system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups 636system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed |
| 637system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing | 637system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing |
| 638system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed 639system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed | 638system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed 639system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed |
| 640system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer | 640system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer |
| 641system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. 642system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. 643system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. 644system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. 645system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) 646system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ 647system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued 648system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued 649system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling 650system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph 651system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed | 641system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit. 642system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit. 643system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads. 644system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores. 645system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec) 646system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ 647system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued 648system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued 649system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling 650system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph 651system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed |
| 652system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle | 652system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle |
| 653system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 653system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 656system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle | 656system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle |
| 657system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 665system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 666system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 667system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 657system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 665system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 666system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 667system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 668system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle | 668system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle |
| 669system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 670system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available 671system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available 672system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available 673system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available 674system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available 675system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available 676system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 733system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued 734system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued 735system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 736system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 737system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued 738system.cpu.iq.rate 0.641106 # Inst issue rate 739system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested 740system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) | 669system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 670system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available 671system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available 672system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available 673system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available 674system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available 675system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available 676system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 733system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued 734system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued 735system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 736system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 737system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued 738system.cpu.iq.rate 0.641106 # Inst issue rate 739system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested 740system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst) |
| 741system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads | 741system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads |
| 742system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes 743system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses 744system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads 745system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes 746system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses 747system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses 748system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses 749system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores 750system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 751system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed 752system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed 753system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations 754system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed 755system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 756system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 757system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled | 742system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes 743system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses 744system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads 745system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes 746system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses 747system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses 748system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses 749system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores 750system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 751system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed 752system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed 753system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations 754system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed 755system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 756system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 757system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled |
| 758system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked | 758system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked |
| 759system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 760system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing 761system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking 762system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking 763system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ 764system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 765system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions 766system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions --- 17 unchanged lines hidden (view full) --- 784system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back 785system.cpu.iew.wb_producers 437817967 # num instructions producing a value 786system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value 787system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle 788system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back 789system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit 790system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards 791system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted | 759system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 760system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing 761system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking 762system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking 763system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ 764system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 765system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions 766system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions --- 17 unchanged lines hidden (view full) --- 784system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back 785system.cpu.iew.wb_producers 437817967 # num instructions producing a value 786system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value 787system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle 788system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back 789system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit 790system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards 791system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted |
| 792system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle | 792system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle |
| 793system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 793system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 796system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle | 796system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle |
| 797system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle 803system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle 805system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 806system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 807system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 797system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle 803system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle 805system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 806system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 807system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 808system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle | 808system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle |
| 809system.cpu.commit.committedInsts 848164321 # Number of instructions committed 810system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed 811system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 812system.cpu.commit.refs 304407284 # Number of memory references committed 813system.cpu.commit.loads 159650119 # Number of loads committed 814system.cpu.commit.membars 6926917 # Number of memory barriers committed 815system.cpu.commit.branches 189306416 # Number of branches committed 816system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 847system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 848system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 849system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction 850system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction 851system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 852system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 853system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction 854system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached | 809system.cpu.commit.committedInsts 848164321 # Number of instructions committed 810system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed 811system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 812system.cpu.commit.refs 304407284 # Number of memory references committed 813system.cpu.commit.loads 159650119 # Number of loads committed 814system.cpu.commit.membars 6926917 # Number of memory barriers committed 815system.cpu.commit.branches 189306416 # Number of branches committed 816system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 847system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction 848system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction 849system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction 850system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction 851system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 852system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 853system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction 854system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached |
| 855system.cpu.rob.rob_reads 2588836198 # The number of ROB reads | 855system.cpu.rob.rob_reads 2588836134 # The number of ROB reads |
| 856system.cpu.rob.rob_writes 2108972650 # The number of ROB writes | 856system.cpu.rob.rob_writes 2108972650 # The number of ROB writes |
| 857system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself 858system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling | 857system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself 858system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 859system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 860system.cpu.committedInsts 848164321 # Number of Instructions Simulated 861system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated 862system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction 863system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads 864system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle 865system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads 866system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads 867system.cpu.int_regfile_writes 731349757 # number of integer regfile writes 868system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads 869system.cpu.fp_regfile_writes 780384 # number of floating regfile writes 870system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads 871system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes | 859system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 860system.cpu.committedInsts 848164321 # Number of Instructions Simulated 861system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated 862system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction 863system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads 864system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle 865system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads 866system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads 867system.cpu.int_regfile_writes 731349757 # number of integer regfile writes 868system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads 869system.cpu.fp_regfile_writes 780384 # number of floating regfile writes 870system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads 871system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes |
| 872system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads | 872system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads |
| 873system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes 874system.cpu.dcache.tags.replacements 9706309 # number of replacements 875system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use 876system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. 877system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. 878system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. 879system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. 880system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 894system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits 895system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits 896system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits 897system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits 898system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits 899system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits 900system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits 901system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits | 873system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes 874system.cpu.dcache.tags.replacements 9706309 # number of replacements 875system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use 876system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. 877system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks. 878system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks. 879system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. 880system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 894system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits 895system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits 896system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits 897system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits 898system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295516 # number of LoadLockedReq hits 899system.cpu.dcache.LoadLockedReq_hits::total 3295516 # number of LoadLockedReq hits 900system.cpu.dcache.StoreCondReq_hits::cpu.data 3691142 # number of StoreCondReq hits 901system.cpu.dcache.StoreCondReq_hits::total 3691142 # number of StoreCondReq hits |
| 902system.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits 903system.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits 904system.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits 905system.cpu.dcache.overall_hits::total 275804158 # number of overall hits | 902system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits 903system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits 904system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits 905system.cpu.dcache.overall_hits::total 276127624 # number of overall hits |
| 906system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses 907system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses 908system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses 909system.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses 910system.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses 911system.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses 912system.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses 913system.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses 914system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses 915system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses 916system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses 917system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses | 906system.cpu.dcache.ReadReq_misses::cpu.data 9582006 # number of ReadReq misses 907system.cpu.dcache.ReadReq_misses::total 9582006 # number of ReadReq misses 908system.cpu.dcache.WriteReq_misses::cpu.data 11252664 # number of WriteReq misses 909system.cpu.dcache.WriteReq_misses::total 11252664 # number of WriteReq misses 910system.cpu.dcache.SoftPFReq_misses::cpu.data 1170750 # number of SoftPFReq misses 911system.cpu.dcache.SoftPFReq_misses::total 1170750 # number of SoftPFReq misses 912system.cpu.dcache.WriteLineReq_misses::cpu.data 1233990 # number of WriteLineReq misses 913system.cpu.dcache.WriteLineReq_misses::total 1233990 # number of WriteLineReq misses 914system.cpu.dcache.LoadLockedReq_misses::cpu.data 446459 # number of LoadLockedReq misses 915system.cpu.dcache.LoadLockedReq_misses::total 446459 # number of LoadLockedReq misses 916system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses 917system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses |
| 918system.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses 919system.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses 920system.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses 921system.cpu.dcache.overall_misses::total 22005420 # number of overall misses | 918system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses 919system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses 920system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses 921system.cpu.dcache.overall_misses::total 23239410 # number of overall misses |
| 922system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles 923system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles 924system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles 925system.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles 926system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles 927system.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles 928system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles 929system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles 930system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles 931system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles | 922system.cpu.dcache.ReadReq_miss_latency::cpu.data 168553352000 # number of ReadReq miss cycles 923system.cpu.dcache.ReadReq_miss_latency::total 168553352000 # number of ReadReq miss cycles 924system.cpu.dcache.WriteReq_miss_latency::cpu.data 444283559827 # number of WriteReq miss cycles 925system.cpu.dcache.WriteReq_miss_latency::total 444283559827 # number of WriteReq miss cycles 926system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52343559973 # number of WriteLineReq miss cycles 927system.cpu.dcache.WriteLineReq_miss_latency::total 52343559973 # number of WriteLineReq miss cycles 928system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6881905000 # number of LoadLockedReq miss cycles 929system.cpu.dcache.LoadLockedReq_miss_latency::total 6881905000 # number of LoadLockedReq miss cycles 930system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 299500 # number of StoreCondReq miss cycles 931system.cpu.dcache.StoreCondReq_miss_latency::total 299500 # number of StoreCondReq miss cycles |
| 932system.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles 933system.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles 934system.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles 935system.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles | 932system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles 933system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles 934system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles 935system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles |
| 936system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) 937system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) 938system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) 939system.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) 940system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) 941system.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) 942system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) 943system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) 944system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) 945system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) 946system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) 947system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) | 936system.cpu.dcache.ReadReq_accesses::cpu.data 156764287 # number of ReadReq accesses(hits+misses) 937system.cpu.dcache.ReadReq_accesses::total 156764287 # number of ReadReq accesses(hits+misses) 938system.cpu.dcache.WriteReq_accesses::cpu.data 139496788 # number of WriteReq accesses(hits+misses) 939system.cpu.dcache.WriteReq_accesses::total 139496788 # number of WriteReq accesses(hits+misses) 940system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548503 # number of SoftPFReq accesses(hits+misses) 941system.cpu.dcache.SoftPFReq_accesses::total 1548503 # number of SoftPFReq accesses(hits+misses) 942system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses) 943system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses) 944system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3741975 # number of LoadLockedReq accesses(hits+misses) 945system.cpu.dcache.LoadLockedReq_accesses::total 3741975 # number of LoadLockedReq accesses(hits+misses) 946system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691149 # number of StoreCondReq accesses(hits+misses) 947system.cpu.dcache.StoreCondReq_accesses::total 3691149 # number of StoreCondReq accesses(hits+misses) |
| 948system.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses 949system.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses 950system.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses 951system.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses | 948system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses 949system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses 950system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses 951system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses |
| 952system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses 953system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses 954system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses 955system.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses 956system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses 957system.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses 958system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses 959system.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses 960system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses 961system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses 962system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses 963system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses | 952system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061124 # miss rate for ReadReq accesses 953system.cpu.dcache.ReadReq_miss_rate::total 0.061124 # miss rate for ReadReq accesses 954system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080666 # miss rate for WriteReq accesses 955system.cpu.dcache.WriteReq_miss_rate::total 0.080666 # miss rate for WriteReq accesses 956system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756053 # miss rate for SoftPFReq accesses 957system.cpu.dcache.SoftPFReq_miss_rate::total 0.756053 # miss rate for SoftPFReq accesses 958system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792311 # miss rate for WriteLineReq accesses 959system.cpu.dcache.WriteLineReq_miss_rate::total 0.792311 # miss rate for WriteLineReq accesses 960system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119311 # miss rate for LoadLockedReq accesses 961system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119311 # miss rate for LoadLockedReq accesses 962system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses 963system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses |
| 964system.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses 965system.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses 966system.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses 967system.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses | 964system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses 965system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses 966system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses 967system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses |
| 968system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency 969system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency 970system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency 971system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency 972system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency 973system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency 974system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency 975system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency 976system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency 977system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency | 968system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17590.612237 # average ReadReq miss latency 969system.cpu.dcache.ReadReq_avg_miss_latency::total 17590.612237 # average ReadReq miss latency 970system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39482.522523 # average WriteReq miss latency 971system.cpu.dcache.WriteReq_avg_miss_latency::total 39482.522523 # average WriteReq miss latency 972system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42418.139509 # average WriteLineReq miss latency 973system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42418.139509 # average WriteLineReq miss latency 974system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15414.416553 # average LoadLockedReq miss latency 975system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15414.416553 # average LoadLockedReq miss latency 976system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42785.714286 # average StoreCondReq miss latency 977system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42785.714286 # average StoreCondReq miss latency |
| 978system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency 979system.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency 980system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency 981system.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency | 978system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency 979system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency 980system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency 981system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency |
| 982system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked 983system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 984system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked 985system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 986system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked 987system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 982system.cpu.dcache.blocked_cycles::no_mshrs 32180640 # number of cycles access was blocked 983system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 984system.cpu.dcache.blocked::no_mshrs 1601871 # number of cycles access was blocked 985system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 986system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089408 # average number of cycles each access was blocked 987system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 988system.cpu.dcache.fast_writes 0 # number of fast writes performed 989system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 990system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks 991system.cpu.dcache.writebacks::total 7511281 # number of writebacks 992system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits 993system.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits 994system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits 995system.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits 996system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits 997system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits 998system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits 999system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits | 988system.cpu.dcache.writebacks::writebacks 7511281 # number of writebacks 989system.cpu.dcache.writebacks::total 7511281 # number of writebacks 990system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4454269 # number of ReadReq MSHR hits 991system.cpu.dcache.ReadReq_mshr_hits::total 4454269 # number of ReadReq MSHR hits 992system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9249122 # number of WriteReq MSHR hits 993system.cpu.dcache.WriteReq_mshr_hits::total 9249122 # number of WriteReq MSHR hits 994system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7130 # number of WriteLineReq MSHR hits 995system.cpu.dcache.WriteLineReq_mshr_hits::total 7130 # number of WriteLineReq MSHR hits 996system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218050 # number of LoadLockedReq MSHR hits 997system.cpu.dcache.LoadLockedReq_mshr_hits::total 218050 # number of LoadLockedReq MSHR hits |
| 1000system.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # number of demand (read+write) MSHR hits 1001system.cpu.dcache.demand_mshr_hits::total 13703391 # number of demand (read+write) MSHR hits 1002system.cpu.dcache.overall_mshr_hits::cpu.data 13703391 # number of overall MSHR hits 1003system.cpu.dcache.overall_mshr_hits::total 13703391 # number of overall MSHR hits | 998system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits 999system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits 1000system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits 1001system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits |
| 1004system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses 1005system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses 1006system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses 1007system.cpu.dcache.WriteReq_mshr_misses::total 2003542 # number of WriteReq MSHR misses 1008system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163937 # number of SoftPFReq MSHR misses 1009system.cpu.dcache.SoftPFReq_mshr_misses::total 1163937 # number of SoftPFReq MSHR misses 1010system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226860 # number of WriteLineReq MSHR misses 1011system.cpu.dcache.WriteLineReq_mshr_misses::total 1226860 # number of WriteLineReq MSHR misses 1012system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409 # number of LoadLockedReq MSHR misses 1013system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses 1014system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses 1015system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses | 1002system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5127737 # number of ReadReq MSHR misses 1003system.cpu.dcache.ReadReq_mshr_misses::total 5127737 # number of ReadReq MSHR misses 1004system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003542 # number of WriteReq MSHR misses 1005system.cpu.dcache.WriteReq_mshr_misses::total 2003542 # number of WriteReq MSHR misses 1006system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163937 # number of SoftPFReq MSHR misses 1007system.cpu.dcache.SoftPFReq_mshr_misses::total 1163937 # number of SoftPFReq MSHR misses 1008system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226860 # number of WriteLineReq MSHR misses 1009system.cpu.dcache.WriteLineReq_mshr_misses::total 1226860 # number of WriteLineReq MSHR misses 1010system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 228409 # number of LoadLockedReq MSHR misses 1011system.cpu.dcache.LoadLockedReq_mshr_misses::total 228409 # number of LoadLockedReq MSHR misses 1012system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses 1013system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses |
| 1016system.cpu.dcache.demand_mshr_misses::cpu.data 7131279 # number of demand (read+write) MSHR misses 1017system.cpu.dcache.demand_mshr_misses::total 7131279 # number of demand (read+write) MSHR misses 1018system.cpu.dcache.overall_mshr_misses::cpu.data 8295216 # number of overall MSHR misses 1019system.cpu.dcache.overall_mshr_misses::total 8295216 # number of overall MSHR misses | 1014system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses 1015system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses 1016system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses 1017system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses |
| 1020system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 1021system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable 1022system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 1023system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 1024system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 1025system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses 1026system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles 1027system.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles 1028system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles 1029system.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles 1030system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles 1031system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles 1032system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles 1033system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles 1034system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles 1035system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles 1036system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles 1037system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles | 1018system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 1019system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable 1020system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 1021system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 1022system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 1023system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses 1024system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84965736000 # number of ReadReq MSHR miss cycles 1025system.cpu.dcache.ReadReq_mshr_miss_latency::total 84965736000 # number of ReadReq MSHR miss cycles 1026system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77538140437 # number of WriteReq MSHR miss cycles 1027system.cpu.dcache.WriteReq_mshr_miss_latency::total 77538140437 # number of WriteReq MSHR miss cycles 1028system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23685156500 # number of SoftPFReq MSHR miss cycles 1029system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23685156500 # number of SoftPFReq MSHR miss cycles 1030system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles 1031system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50670413473 # number of WriteLineReq MSHR miss cycles 1032system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3210622500 # number of LoadLockedReq MSHR miss cycles 1033system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3210622500 # number of LoadLockedReq MSHR miss cycles 1034system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 292500 # number of StoreCondReq MSHR miss cycles 1035system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles |
| 1038system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles 1039system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles 1040system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles 1041system.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles | 1036system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles 1037system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles 1038system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles 1039system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles |
| 1042system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles 1043system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles | 1040system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles 1041system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192022000 # number of ReadReq MSHR uncacheable cycles |
| 1044system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles 1045system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles 1046system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles 1047system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles | 1042system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles 1043system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles |
| 1048system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses 1049system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses 1050system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses 1051system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses 1052system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses 1053system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses 1054system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses 1055system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses 1056system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses 1057system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses 1058system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses 1059system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses | 1044system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032710 # mshr miss rate for ReadReq accesses 1045system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses 1046system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014363 # mshr miss rate for WriteReq accesses 1047system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014363 # mshr miss rate for WriteReq accesses 1048system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751653 # mshr miss rate for SoftPFReq accesses 1049system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751653 # mshr miss rate for SoftPFReq accesses 1050system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787733 # mshr miss rate for WriteLineReq accesses 1051system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787733 # mshr miss rate for WriteLineReq accesses 1052system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061040 # mshr miss rate for LoadLockedReq accesses 1053system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061040 # mshr miss rate for LoadLockedReq accesses 1054system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses 1055system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses |
| 1060system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses 1061system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses 1062system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses 1063system.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses | 1056system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses 1057system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses 1058system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses 1059system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses |
| 1064system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency 1065system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency 1066system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency 1067system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency 1068system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency 1069system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency 1070system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency 1071system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency 1072system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency 1073system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency 1074system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency 1075system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency | 1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency 1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency 1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38700.531577 # average WriteReq mshr miss latency 1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency 1064system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency 1065system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency 1066system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency 1067system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency 1068system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14056.462311 # average LoadLockedReq mshr miss latency 1069system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency 1070system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency 1071system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency |
| 1076system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency 1077system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency 1078system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency 1079system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency | 1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency 1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency 1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency 1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency |
| 1080system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency 1081system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency | 1076system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency 1077system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency |
| 1082system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency 1083system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency 1084system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency 1085system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency 1086system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1078system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency 1079system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency |
| 1087system.cpu.icache.tags.replacements 15141033 # number of replacements 1088system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use 1089system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. 1090system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. 1091system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. 1092system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. 1093system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor 1094system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1137system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency 1138system.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency 1139system.cpu.icache.blocked_cycles::no_mshrs 23721 # number of cycles access was blocked 1140system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1141system.cpu.icache.blocked::no_mshrs 1460 # number of cycles access was blocked 1142system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1143system.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked 1144system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1080system.cpu.icache.tags.replacements 15141033 # number of replacements 1081system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use 1082system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. 1083system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks. 1084system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks. 1085system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. 1086system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor 1087system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1130system.cpu.icache.overall_avg_miss_latency::cpu.inst 13524.334496 # average overall miss latency 1131system.cpu.icache.overall_avg_miss_latency::total 13524.334496 # average overall miss latency 1132system.cpu.icache.blocked_cycles::no_mshrs 23721 # number of cycles access was blocked 1133system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1134system.cpu.icache.blocked::no_mshrs 1460 # number of cycles access was blocked 1135system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1136system.cpu.icache.avg_blocked_cycles::no_mshrs 16.247260 # average number of cycles each access was blocked 1137system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1145system.cpu.icache.fast_writes 0 # number of fast writes performed 1146system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 1147system.cpu.icache.writebacks::writebacks 15141033 # number of writebacks 1148system.cpu.icache.writebacks::total 15141033 # number of writebacks 1149system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits 1150system.cpu.icache.ReadReq_mshr_hits::total 752570 # number of ReadReq MSHR hits 1151system.cpu.icache.demand_mshr_hits::cpu.inst 752570 # number of demand (read+write) MSHR hits 1152system.cpu.icache.demand_mshr_hits::total 752570 # number of demand (read+write) MSHR hits 1153system.cpu.icache.overall_mshr_hits::cpu.inst 752570 # number of overall MSHR hits 1154system.cpu.icache.overall_mshr_hits::total 752570 # number of overall MSHR hits --- 28 unchanged lines hidden (view full) --- 1183system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency 1184system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency 1185system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency 1186system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency 1187system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency 1188system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency 1189system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency 1190system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency | 1138system.cpu.icache.writebacks::writebacks 15141033 # number of writebacks 1139system.cpu.icache.writebacks::total 15141033 # number of writebacks 1140system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752570 # number of ReadReq MSHR hits 1141system.cpu.icache.ReadReq_mshr_hits::total 752570 # number of ReadReq MSHR hits 1142system.cpu.icache.demand_mshr_hits::cpu.inst 752570 # number of demand (read+write) MSHR hits 1143system.cpu.icache.demand_mshr_hits::total 752570 # number of demand (read+write) MSHR hits 1144system.cpu.icache.overall_mshr_hits::cpu.inst 752570 # number of overall MSHR hits 1145system.cpu.icache.overall_mshr_hits::total 752570 # number of overall MSHR hits --- 28 unchanged lines hidden (view full) --- 1174system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency 1175system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency 1176system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency 1177system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency 1178system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency 1179system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency 1180system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency 1181system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency |
| 1191system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1192system.cpu.l2cache.tags.replacements 1146896 # number of replacements 1193system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use 1194system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks. 1195system.cpu.l2cache.tags.sampled_refs 1209243 # Sample count of references to valid blocks. 1196system.cpu.l2cache.tags.avg_refs 38.281145 # Average number of references to valid blocks. 1197system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit. 1198system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589 # Average occupied blocks per requestor 1199system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 299.826567 # Average occupied blocks per requestor --- 178 unchanged lines hidden (view full) --- 1378system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139399.326292 # average overall miss latency 1379system.cpu.l2cache.overall_avg_miss_latency::total 138874.326532 # average overall miss latency 1380system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1381system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1382system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1383system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1384system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1385system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1182system.cpu.l2cache.tags.replacements 1146896 # number of replacements 1183system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use 1184system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks. 1185system.cpu.l2cache.tags.sampled_refs 1209243 # Sample count of references to valid blocks. 1186system.cpu.l2cache.tags.avg_refs 38.281145 # Average number of references to valid blocks. 1187system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit. 1188system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589 # Average occupied blocks per requestor 1189system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 299.826567 # Average occupied blocks per requestor --- 178 unchanged lines hidden (view full) --- 1368system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139399.326292 # average overall miss latency 1369system.cpu.l2cache.overall_avg_miss_latency::total 138874.326532 # average overall miss latency 1370system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1371system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1372system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1373system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1374system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1375system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1386system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1387system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1388system.cpu.l2cache.writebacks::writebacks 961909 # number of writebacks 1389system.cpu.l2cache.writebacks::total 961909 # number of writebacks 1390system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits 1391system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1392system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1393system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1394system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits 1395system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits --- 59 unchanged lines hidden (view full) --- 1455system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 452886511 # number of overall MSHR miss cycles 1456system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 431525000 # number of overall MSHR miss cycles 1457system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10385630163 # number of overall MSHR miss cycles 1458system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84237421779 # number of overall MSHR miss cycles 1459system.cpu.l2cache.overall_mshr_miss_latency::total 95507463453 # number of overall MSHR miss cycles 1460system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763500 # number of ReadReq MSHR uncacheable cycles 1461system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770895500 # number of ReadReq MSHR uncacheable cycles 1462system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189659000 # number of ReadReq MSHR uncacheable cycles | 1376system.cpu.l2cache.writebacks::writebacks 961909 # number of writebacks 1377system.cpu.l2cache.writebacks::total 961909 # number of writebacks 1378system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits 1379system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1380system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1381system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1382system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits 1383system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits --- 59 unchanged lines hidden (view full) --- 1443system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 452886511 # number of overall MSHR miss cycles 1444system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 431525000 # number of overall MSHR miss cycles 1445system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10385630163 # number of overall MSHR miss cycles 1446system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84237421779 # number of overall MSHR miss cycles 1447system.cpu.l2cache.overall_mshr_miss_latency::total 95507463453 # number of overall MSHR miss cycles 1448system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763500 # number of ReadReq MSHR uncacheable cycles 1449system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770895500 # number of ReadReq MSHR uncacheable cycles 1450system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189659000 # number of ReadReq MSHR uncacheable cycles |
| 1463system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836145500 # number of WriteReq MSHR uncacheable cycles 1464system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836145500 # number of WriteReq MSHR uncacheable cycles | |
| 1465system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles | 1451system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles |
| 1466system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607041000 # number of overall MSHR uncacheable cycles 1467system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025804500 # number of overall MSHR uncacheable cycles | 1452system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770895500 # number of overall MSHR uncacheable cycles 1453system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189659000 # number of overall MSHR uncacheable cycles |
| 1468system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for ReadReq accesses 1469system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for ReadReq accesses 1470system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006451 # mshr miss rate for ReadReq accesses 1471system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1472system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1473system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784612 # mshr miss rate for UpgradeReq accesses 1474system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784612 # mshr miss rate for UpgradeReq accesses 1475system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses --- 39 unchanged lines hidden (view full) --- 1515system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency 1516system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency 1517system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency 1518system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency 1519system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency 1520system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency 1521system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency 1522system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency | 1454system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for ReadReq accesses 1455system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for ReadReq accesses 1456system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006451 # mshr miss rate for ReadReq accesses 1457system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1458system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1459system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784612 # mshr miss rate for UpgradeReq accesses 1460system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784612 # mshr miss rate for UpgradeReq accesses 1461system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses --- 39 unchanged lines hidden (view full) --- 1501system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency 1502system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency 1503system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency 1504system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency 1505system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency 1506system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency 1507system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency 1508system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency |
| 1523system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency 1524system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency | |
| 1525system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency | 1509system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency |
| 1526system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency 1527system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency 1528system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1510system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency 1511system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency |
| 1529system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. 1530system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1531system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1532system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. 1533system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1534system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1535system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution 1536system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution --- 140 unchanged lines hidden (view full) --- 1677system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1678system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses 1679system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses 1680system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1681system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1682system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1683system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1684system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 1512system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter. 1513system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1514system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1515system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. 1516system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1517system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1518system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution 1519system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution --- 140 unchanged lines hidden (view full) --- 1660system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1661system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses 1662system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses 1663system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1664system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1665system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1666system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1667system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 1685system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses 1686system.iocache.demand_misses::total 8854 # number of demand (read+write) misses | 1668system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses 1669system.iocache.demand_misses::total 115518 # number of demand (read+write) misses |
| 1687system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 1670system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 1688system.iocache.overall_misses::realview.ide 8814 # number of overall misses 1689system.iocache.overall_misses::total 8854 # number of overall misses | 1671system.iocache.overall_misses::realview.ide 115478 # number of overall misses 1672system.iocache.overall_misses::total 115518 # number of overall misses |
| 1690system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles 1691system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles 1692system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles 1693system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1694system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1695system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles 1696system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles 1697system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles | 1673system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles 1674system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles 1675system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles 1676system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1677system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1678system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles 1679system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles 1680system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles |
| 1698system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles 1699system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles | 1681system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles 1682system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles |
| 1700system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles | 1683system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles |
| 1701system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles 1702system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles | 1684system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles 1685system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles |
| 1703system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1704system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) 1705system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) 1706system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1707system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1708system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1709system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1710system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 1686system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1687system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) 1688system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) 1689system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1690system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1691system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1692system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1693system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 1711system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses 1712system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses | 1694system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses 1695system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses |
| 1713system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 1696system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 1714system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses 1715system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses | 1697system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses 1698system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses |
| 1716system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1717system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1718system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1719system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1720system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1721system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1722system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1723system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1729system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency 1730system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency 1731system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency 1732system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1733system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1734system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency 1735system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency 1736system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency | 1699system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1700system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1701system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1702system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1703system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1704system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1705system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1706system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1712system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency 1713system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency 1714system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency 1715system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1716system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1717system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency 1718system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency 1719system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency |
| 1737system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency 1738system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency | 1720system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency 1721system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency |
| 1739system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency | 1722system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency |
| 1740system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency 1741system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency | 1723system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency 1724system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency |
| 1742system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked 1743system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1744system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked 1745system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1746system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked 1747system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1725system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked 1726system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1727system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked 1728system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1729system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked 1730system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1748system.iocache.fast_writes 0 # number of fast writes performed 1749system.iocache.cache_copies 0 # number of cache copies performed | |
| 1750system.iocache.writebacks::writebacks 106630 # number of writebacks 1751system.iocache.writebacks::total 106630 # number of writebacks 1752system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1753system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses 1754system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses 1755system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1756system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1757system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1758system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1759system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 1731system.iocache.writebacks::writebacks 106630 # number of writebacks 1732system.iocache.writebacks::total 106630 # number of writebacks 1733system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1734system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses 1735system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses 1736system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1737system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1738system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1739system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1740system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 1760system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses 1761system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses | 1741system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses 1742system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses |
| 1762system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 1743system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 1763system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses 1764system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses | 1744system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses 1745system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses |
| 1765system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles 1766system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles 1767system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles 1768system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1769system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1770system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles 1771system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles 1772system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles | 1746system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles 1747system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles 1748system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles 1749system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1750system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1751system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles 1752system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles 1753system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles |
| 1773system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles 1774system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles | 1754system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles 1755system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles |
| 1775system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles | 1756system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles |
| 1776system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles 1777system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles | 1757system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles 1758system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles |
| 1778system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1779system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1780system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1781system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1782system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1783system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1784system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1785system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1791system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency 1792system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency 1793system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency 1794system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1795system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1796system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency 1797system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency 1798system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency | 1759system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1760system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1761system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1762system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1763system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1764system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1765system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1766system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 1772system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency 1773system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency 1774system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency 1775system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1776system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1777system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency 1778system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency 1779system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency |
| 1799system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency 1800system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency | 1780system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency 1781system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency |
| 1801system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency | 1782system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency |
| 1802system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency 1803system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency 1804system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1783system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency 1784system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency |
| 1805system.membus.trans_dist::ReadReq 54972 # Transaction distribution 1806system.membus.trans_dist::ReadResp 410008 # Transaction distribution 1807system.membus.trans_dist::WriteReq 33696 # Transaction distribution 1808system.membus.trans_dist::WriteResp 33696 # Transaction distribution 1809system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution 1810system.membus.trans_dist::CleanEvict 192763 # Transaction distribution 1811system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution 1812system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution --- 29 unchanged lines hidden (view full) --- 1842system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1843system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1844system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1845system.membus.snoop_fanout::total 2739791 # Request fanout histogram 1846system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) 1847system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1848system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) 1849system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1785system.membus.trans_dist::ReadReq 54972 # Transaction distribution 1786system.membus.trans_dist::ReadResp 410008 # Transaction distribution 1787system.membus.trans_dist::WriteReq 33696 # Transaction distribution 1788system.membus.trans_dist::WriteResp 33696 # Transaction distribution 1789system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution 1790system.membus.trans_dist::CleanEvict 192763 # Transaction distribution 1791system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution 1792system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution --- 29 unchanged lines hidden (view full) --- 1822system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1823system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1824system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1825system.membus.snoop_fanout::total 2739791 # Request fanout histogram 1826system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks) 1827system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1828system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) 1829system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1850system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks) | 1830system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks) |
| 1851system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1852system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) 1853system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1854system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) 1855system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1856system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) 1857system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1858system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks --- 55 unchanged lines hidden --- | 1831system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1832system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks) 1833system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1834system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks) 1835system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1836system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) 1837system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1838system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks --- 55 unchanged lines hidden --- |