| stats.txt (10798:74e3c7359393) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.320469 # Number of seconds simulated 4sim_ticks 51320468905000 # Number of ticks simulated 5final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.320469 # Number of seconds simulated 4sim_ticks 51320468905000 # Number of ticks simulated 5final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 112338 # Simulator instruction rate (inst/s) 8host_op_rate 131995 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6738935517 # Simulator tick rate (ticks/s) 10host_mem_usage 657468 # Number of bytes of host memory used 11host_seconds 7615.52 # Real time elapsed on the host | 7host_inst_rate 115752 # Simulator instruction rate (inst/s) 8host_op_rate 136007 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6943747154 # Simulator tick rate (ticks/s) 10host_mem_usage 724128 # Number of bytes of host memory used 11host_seconds 7390.89 # Real time elapsed on the host |
| 12sim_insts 855512158 # Number of instructions simulated 13sim_ops 1005211605 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory --- 976 unchanged lines hidden (view full) --- 996system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses 997system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses 998system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses 999system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses 1000system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses 1002system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses 1003system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses | 12sim_insts 855512158 # Number of instructions simulated 13sim_ops 1005211605 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory --- 976 unchanged lines hidden (view full) --- 996system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses 997system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses 998system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses 999system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses 1000system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses 1002system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses 1003system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses |
| 1004system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable 1005system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable 1006system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable 1007system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable 1008system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses 1009system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses |
|
| 1004system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles 1009system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles 1010system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles 1011system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles --- 38 unchanged lines hidden (view full) --- 1050system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency 1051system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency 1052system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency 1053system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency 1054system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency 1055system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency 1056system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency 1057system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency | 1010system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles 1011system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles 1012system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles 1013system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles 1014system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles 1015system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles 1016system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles 1017system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles --- 38 unchanged lines hidden (view full) --- 1056system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency 1057system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency 1058system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency 1059system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency 1060system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency 1061system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency 1062system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency 1063system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency |
| 1058system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1059system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1060system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1061system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1062system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1063system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1064system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency 1065system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency 1066system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency 1067system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency 1068system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency 1069system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency |
| 1064system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1065system.cpu.icache.tags.replacements 15070815 # number of replacements 1066system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use 1067system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. 1068system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. 1069system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. 1070system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. 1071system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor --- 57 unchanged lines hidden (view full) --- 1129system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits 1130system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits 1131system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses 1132system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses 1133system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses 1134system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses 1135system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses 1136system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses | 1070system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1071system.cpu.icache.tags.replacements 15070815 # number of replacements 1072system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use 1073system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. 1074system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. 1075system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. 1076system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. 1077system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor --- 57 unchanged lines hidden (view full) --- 1135system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits 1136system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits 1137system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses 1138system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses 1139system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses 1140system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses 1141system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses 1142system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses |
| 1143system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable 1144system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable 1145system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses 1146system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses |
|
| 1137system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles 1138system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles 1139system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles 1140system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles 1141system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles 1142system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles 1143system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles 1144system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 1151system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses 1152system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses 1153system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency 1154system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency 1155system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency 1156system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency 1157system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency 1158system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency | 1147system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles 1148system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles 1149system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles 1150system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles 1151system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles 1152system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles 1153system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles 1154system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 1161system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses 1162system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses 1163system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency 1164system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency 1165system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency 1166system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency 1167system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency 1168system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency |
| 1159system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1160system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1161system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1162system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1169system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency 1170system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency 1171system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency 1172system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency |
| 1163system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1164system.cpu.l2cache.tags.replacements 1159288 # number of replacements 1165system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use 1166system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks. 1167system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks. 1168system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. 1169system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. 1170system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor --- 195 unchanged lines hidden (view full) --- 1366system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses 1367system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses 1368system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses 1369system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses 1370system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses 1371system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses 1372system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses 1373system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses | 1173system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1174system.cpu.l2cache.tags.replacements 1159288 # number of replacements 1175system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use 1176system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks. 1177system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks. 1178system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. 1179system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. 1180system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor --- 195 unchanged lines hidden (view full) --- 1376system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses 1377system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses 1378system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses 1379system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses 1380system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses 1381system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses 1382system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses 1383system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses |
| 1384system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable 1385system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable 1386system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable 1387system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable 1388system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable 1389system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses 1390system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses 1391system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses |
|
| 1374system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles 1375system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles 1376system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles 1377system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles 1378system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles 1379system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles 1380system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles 1381system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles --- 61 unchanged lines hidden (view full) --- 1443system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency 1444system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency 1445system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency 1446system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency 1447system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency 1448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency 1449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency 1450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency | 1392system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles 1393system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles 1394system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles 1395system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles 1396system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles 1397system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles 1398system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles 1399system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles --- 61 unchanged lines hidden (view full) --- 1461system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency 1462system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency 1463system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency 1464system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency 1465system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency 1466system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency 1467system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency 1468system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency |
| 1451system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1452system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1453system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1454system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1455system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1456system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1457system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1458system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1469system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency 1470system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency 1471system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency 1472system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency 1473system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency 1474system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency 1475system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency 1476system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency |
| 1459system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1460system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution 1461system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution 1462system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution 1463system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution 1464system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution 1465system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution 1466system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution --- 8 unchanged lines hidden (view full) --- 1475system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) 1476system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) 1477system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) 1478system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) 1479system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) 1480system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) 1481system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) 1482system.cpu.toL2Bus.snoops 583028 # Total snoops (count) | 1477system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1478system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution 1481system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution 1482system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution 1483system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution 1484system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution --- 8 unchanged lines hidden (view full) --- 1493system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) 1494system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) 1495system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) 1496system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) 1499system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) 1500system.cpu.toL2Bus.snoops 583028 # Total snoops (count) |
| 1483system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram 1484system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram 1485system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram | 1501system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram 1502system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram 1503system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram |
| 1486system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1487system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1504system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1488system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1489system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1490system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram 1491system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram | 1506system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram 1507system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram |
| 1492system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1508system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1493system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1494system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1495system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram | 1509system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1510system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1511system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram |
| 1496system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) 1497system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1498system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) 1499system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1500system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) 1501system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1502system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) 1503system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 254 unchanged lines hidden (view full) --- 1758system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) 1759system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) 1760system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) 1761system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) 1762system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) 1763system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) 1764system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) 1765system.membus.snoops 3023 # Total snoops (count) | 1512system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) 1513system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1514system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) 1515system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1516system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) 1517system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1518system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) 1519system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) --- 254 unchanged lines hidden (view full) --- 1774system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) 1775system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) 1776system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) 1777system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) 1778system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) 1779system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) 1780system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) 1781system.membus.snoops 3023 # Total snoops (count) |
| 1766system.membus.snoop_fanout::samples 2488136 # Request fanout histogram | 1782system.membus.snoop_fanout::samples 2576774 # Request fanout histogram |
| 1767system.membus.snoop_fanout::mean 1 # Request fanout histogram 1768system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1769system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1770system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1783system.membus.snoop_fanout::mean 1 # Request fanout histogram 1784system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1785system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1786system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1771system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram | 1787system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram |
| 1772system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1773system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1774system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1775system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1788system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1789system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1790system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1791system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1776system.membus.snoop_fanout::total 2488136 # Request fanout histogram | 1792system.membus.snoop_fanout::total 2576774 # Request fanout histogram |
| 1777system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) 1778system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1779system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) 1780system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1781system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) 1782system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1783system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) 1784system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 50 unchanged lines hidden --- | 1793system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) 1794system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1795system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) 1796system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1797system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) 1798system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1799system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) 1800system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) --- 50 unchanged lines hidden --- |