1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 51.558690 # Number of seconds simulated 4sim_ticks 51558690384000 # Number of ticks simulated 5final_tick 51558690384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 207581 # Simulator instruction rate (inst/s) 8host_op_rate 243983 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9602431196 # Simulator tick rate (ticks/s) 10host_mem_usage 695472 # Number of bytes of host memory used 11host_seconds 5369.34 # Real time elapsed on the host 12sim_insts 1114574366 # Number of instructions simulated 13sim_ops 1310024478 # Number of ops (including micro ops) simulated |
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 681408 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 573376 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 6481504 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 112175560 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 429184 # Number of bytes read from this memory 22system.physmem.bytes_read::total 120341032 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 6481504 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 6481504 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 141267776 # Number of bytes written to this memory |
26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory |
27system.physmem.bytes_written::total 141288356 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 10647 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 8959 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 117226 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1752756 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6706 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1896294 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 2207309 # Number of write requests responded to by this memory |
35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory |
36system.physmem.num_writes::total 2209882 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 13216 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 11121 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 125711 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2175687 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 8324 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 2334059 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 125711 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 125711 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2739941 # Write bandwidth from this memory (bytes/s) |
46system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) |
47system.physmem.bw_write::total 2740340 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2739941 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 13216 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 11121 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 125711 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2176086 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 8324 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 5074399 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 1896294 # Number of read requests accepted 56system.physmem.writeReqs 2209882 # Number of write requests accepted 57system.physmem.readBursts 1896294 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 2209882 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 121325696 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue 61system.physmem.bytesWritten 141284736 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 120341032 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 141288356 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one |
66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
67system.physmem.perBankRdBursts::0 112674 # Per bank write bursts 68system.physmem.perBankRdBursts::1 120331 # Per bank write bursts 69system.physmem.perBankRdBursts::2 120633 # Per bank write bursts 70system.physmem.perBankRdBursts::3 114638 # Per bank write bursts 71system.physmem.perBankRdBursts::4 113111 # Per bank write bursts 72system.physmem.perBankRdBursts::5 123581 # Per bank write bursts 73system.physmem.perBankRdBursts::6 115477 # Per bank write bursts 74system.physmem.perBankRdBursts::7 120263 # Per bank write bursts 75system.physmem.perBankRdBursts::8 112291 # Per bank write bursts 76system.physmem.perBankRdBursts::9 145720 # Per bank write bursts 77system.physmem.perBankRdBursts::10 114582 # Per bank write bursts 78system.physmem.perBankRdBursts::11 120005 # Per bank write bursts 79system.physmem.perBankRdBursts::12 112695 # Per bank write bursts 80system.physmem.perBankRdBursts::13 118645 # Per bank write bursts 81system.physmem.perBankRdBursts::14 113317 # Per bank write bursts 82system.physmem.perBankRdBursts::15 117751 # Per bank write bursts 83system.physmem.perBankWrBursts::0 133340 # Per bank write bursts 84system.physmem.perBankWrBursts::1 139177 # Per bank write bursts 85system.physmem.perBankWrBursts::2 138321 # Per bank write bursts 86system.physmem.perBankWrBursts::3 137224 # Per bank write bursts 87system.physmem.perBankWrBursts::4 136590 # Per bank write bursts 88system.physmem.perBankWrBursts::5 143143 # Per bank write bursts 89system.physmem.perBankWrBursts::6 136203 # Per bank write bursts 90system.physmem.perBankWrBursts::7 139934 # Per bank write bursts 91system.physmem.perBankWrBursts::8 134977 # Per bank write bursts 92system.physmem.perBankWrBursts::9 143618 # Per bank write bursts 93system.physmem.perBankWrBursts::10 135619 # Per bank write bursts 94system.physmem.perBankWrBursts::11 140132 # Per bank write bursts 95system.physmem.perBankWrBursts::12 134815 # Per bank write bursts 96system.physmem.perBankWrBursts::13 138770 # Per bank write bursts 97system.physmem.perBankWrBursts::14 136807 # Per bank write bursts 98system.physmem.perBankWrBursts::15 138904 # Per bank write bursts |
99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
100system.physmem.numWrRetry 518 # Number of times write queue was full causing retry 101system.physmem.totGap 51558689064500 # Total gap between requests |
102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 0 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 21272 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
108system.physmem.readPktSize::6 1875009 # Read request sizes (log2) |
109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
115system.physmem.writePktSize::6 2207309 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 1116053 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 690517 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 59727 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 23803 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 610 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 601 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 516 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1044 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 687 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 311 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 237 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see |
138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
163system.physmem.wrQLenPdf::15 28211 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 35428 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 83457 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 116558 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 125148 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 129368 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 131713 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 136998 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 138946 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 135798 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 138971 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 141020 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 132458 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 131167 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 132874 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 144896 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 126854 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 129875 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 5862 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 4328 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 3576 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 3183 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 2815 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see |
187system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see |
188system.physmem.wrQLenPdf::40 2421 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 2341 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 2185 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 2246 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 2284 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 1940 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 1877 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 1876 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 1719 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 1742 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 1766 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 1651 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 1663 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 1721 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 1785 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 1763 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 1973 # What write queue length does an incoming req see |
205system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see |
206system.physmem.wrQLenPdf::58 1272 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 1576 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 2263 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 1461 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 706 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 1209 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 930002 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 282.376133 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 167.748609 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 309.895017 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 369309 39.71% 39.71% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 231862 24.93% 64.64% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 88277 9.49% 74.13% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 51814 5.57% 79.71% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 37452 4.03% 83.73% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 26213 2.82% 86.55% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 21092 2.27% 88.82% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 17823 1.92% 90.74% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 86160 9.26% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 930002 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 116289 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 16.301748 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 52.348914 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-511 116283 99.99% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes |
231system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes |
234system.physmem.rdPerTurnAround::total 116289 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 116288 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::mean 18.983653 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::gmean 17.436820 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::stdev 18.158845 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::0-31 112077 96.38% 96.38% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-63 1857 1.60% 97.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::64-95 1248 1.07% 99.05% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::96-127 622 0.53% 99.58% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::128-159 199 0.17% 99.75% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-191 102 0.09% 99.84% # Writes before turning the bus around for reads |
245system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads |
262system.physmem.wrPerTurnAround::total 116288 # Writes before turning the bus around for reads 263system.physmem.totQLat 70130172482 # Total ticks spent queuing 264system.physmem.totMemAccLat 105674809982 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 9478570000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 36994.07 # Average queueing delay per DRAM burst |
267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
268system.physmem.avgMemAccLat 55744.07 # Average memory access latency per DRAM burst 269system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 2.74 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 2.33 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s |
273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.04 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
277system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 26.06 # Average write queue length when enqueuing 279system.physmem.readRowHits 1529656 # Number of row buffer hits during reads 280system.physmem.writeRowHits 1643629 # Number of row buffer hits during writes 281system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 74.45 # Row buffer hit rate for writes 283system.physmem.avgGap 12556375.83 # Average gap between requests 284system.physmem.pageHitRate 77.33 # Row buffer hit rate, read and write combined 285system.physmem_0.actEnergy 3321699360 # Energy for activate commands per rank (pJ) 286system.physmem_0.preEnergy 1765517490 # Energy for precharge commands per rank (pJ) 287system.physmem_0.readEnergy 6716655120 # Energy for read commands per rank (pJ) 288system.physmem_0.writeEnergy 5762509380 # Energy for write commands per rank (pJ) 289system.physmem_0.refreshEnergy 51680160480.000015 # Energy for refresh commands per rank (pJ) 290system.physmem_0.actBackEnergy 50972480280 # Energy for active background per rank (pJ) 291system.physmem_0.preBackEnergy 3129835680 # Energy for precharge background per rank (pJ) 292system.physmem_0.actPowerDownEnergy 101675150490 # Energy for active power-down per rank (pJ) 293system.physmem_0.prePowerDownEnergy 76210464000 # Energy for precharge power-down per rank (pJ) 294system.physmem_0.selfRefreshEnergy 12252798333465 # Energy for self refresh per rank (pJ) 295system.physmem_0.totalEnergy 12554072367525 # Total energy per rank (pJ) 296system.physmem_0.averagePower 243.490909 # Core power per rank (mW) 297system.physmem_0.totalIdleTime 51438669732358 # Total Idle time Per DRAM Rank 298system.physmem_0.memoryStateTime::IDLE 5228340749 # Time in different power states 299system.physmem_0.memoryStateTime::REF 21959504000 # Time in different power states 300system.physmem_0.memoryStateTime::SREF 51017233392500 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 198464631937 # Time in different power states 302system.physmem_0.memoryStateTime::ACT 92832806893 # Time in different power states 303system.physmem_0.memoryStateTime::ACT_PDN 222971707921 # Time in different power states 304system.physmem_1.actEnergy 3318507780 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 1763828715 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 6818742840 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 5761011240 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 51892211280.000015 # Energy for refresh commands per rank (pJ) 309system.physmem_1.actBackEnergy 51236173110 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 3081583200 # Energy for precharge background per rank (pJ) 311system.physmem_1.actPowerDownEnergy 102800614920 # Energy for active power-down per rank (pJ) 312system.physmem_1.prePowerDownEnergy 76208995200 # Energy for precharge power-down per rank (pJ) 313system.physmem_1.selfRefreshEnergy 12252080918985 # Energy for self refresh per rank (pJ) 314system.physmem_1.totalEnergy 12555002532930 # Total energy per rank (pJ) 315system.physmem_1.averagePower 243.508949 # Core power per rank (mW) 316system.physmem_1.totalIdleTime 51438215485769 # Total Idle time Per DRAM Rank 317system.physmem_1.memoryStateTime::IDLE 5081473992 # Time in different power states 318system.physmem_1.memoryStateTime::REF 22049198000 # Time in different power states 319system.physmem_1.memoryStateTime::SREF 51014315527500 # Time in different power states 320system.physmem_1.memoryStateTime::PRE_PDN 198460418659 # Time in different power states 321system.physmem_1.memoryStateTime::ACT 93344226239 # Time in different power states 322system.physmem_1.memoryStateTime::ACT_PDN 225439539610 # Time in different power states 323system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
324system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 329system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 330system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 332system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
340system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 341system.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 342system.bridge.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
343system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 344system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 345system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 346system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 347system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 348system.cf0.dma_write_txs 1669 # Number of DMA write transactions. |
349system.cpu.branchPred.lookups 292068322 # Number of BP lookups 350system.cpu.branchPred.condPredicted 199851600 # Number of conditional branches predicted 351system.cpu.branchPred.condIncorrect 13713135 # Number of conditional branches incorrect 352system.cpu.branchPred.BTBLookups 209724607 # Number of BTB lookups 353system.cpu.branchPred.BTBHits 131462172 # Number of BTB hits |
354system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
355system.cpu.branchPred.BTBHitPct 62.683237 # BTB Hit Percentage 356system.cpu.branchPred.usedRAS 37751449 # Number of times the RAS was used to get a target. 357system.cpu.branchPred.RASInCorrect 403092 # Number of incorrect RAS predictions. 358system.cpu.branchPred.indirectLookups 8173057 # Number of indirect predictor lookups. 359system.cpu.branchPred.indirectHits 6085508 # Number of indirect target hits. 360system.cpu.branchPred.indirectMisses 2087549 # Number of indirect misses. 361system.cpu.branchPredindirectMispredicted 802881 # Number of mispredicted indirect branches. |
362system.cpu_clk_domain.clock 500 # Clock period in ticks |
363system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
364system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 385system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
393system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 394system.cpu.dtb.walker.walks 1435892 # Table walker walks requested 395system.cpu.dtb.walker.walksLong 1435892 # Table walker walks initiated with long descriptors 396system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31985 # Level at which table walker walks with long descriptors terminate 397system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277981 # Level at which table walker walks with long descriptors terminate 398system.cpu.dtb.walker.walksSquashedBefore 675717 # Table walks squashed before starting 399system.cpu.dtb.walker.walkWaitTime::samples 760175 # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::mean 2830.191074 # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::stdev 21829.241774 # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::0-65535 752984 99.05% 99.05% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::65536-131071 4669 0.61% 99.67% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::131072-196607 1022 0.13% 99.80% # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::196608-262143 473 0.06% 99.86% # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::262144-327679 342 0.04% 99.91% # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.00% 99.91% # Table walker wait (enqueue to first request) latency 408system.cpu.dtb.walker.walkWaitTime::393216-458751 237 0.03% 99.95% # Table walker wait (enqueue to first request) latency 409system.cpu.dtb.walker.walkWaitTime::458752-524287 34 0.00% 99.95% # Table walker wait (enqueue to first request) latency 410system.cpu.dtb.walker.walkWaitTime::524288-589823 14 0.00% 99.95% # Table walker wait (enqueue to first request) latency 411system.cpu.dtb.walker.walkWaitTime::589824-655359 355 0.05% 100.00% # Table walker wait (enqueue to first request) latency 412system.cpu.dtb.walker.walkWaitTime::655360-720895 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
413system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
414system.cpu.dtb.walker.walkWaitTime::786432-851967 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 415system.cpu.dtb.walker.walkWaitTime::total 760175 # Table walker wait (enqueue to first request) latency 416system.cpu.dtb.walker.walkCompletionTime::samples 806276 # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::mean 26170.477603 # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::gmean 21293.851875 # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::stdev 20136.943306 # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::0-65535 787717 97.70% 97.70% # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walkCompletionTime::65536-131071 14855 1.84% 99.54% # Table walker service (enqueue to completion) latency 422system.cpu.dtb.walker.walkCompletionTime::131072-196607 1801 0.22% 99.76% # Table walker service (enqueue to completion) latency 423system.cpu.dtb.walker.walkCompletionTime::196608-262143 1099 0.14% 99.90% # Table walker service (enqueue to completion) latency 424system.cpu.dtb.walker.walkCompletionTime::262144-327679 441 0.05% 99.95% # Table walker service (enqueue to completion) latency 425system.cpu.dtb.walker.walkCompletionTime::327680-393215 139 0.02% 99.97% # Table walker service (enqueue to completion) latency 426system.cpu.dtb.walker.walkCompletionTime::393216-458751 81 0.01% 99.98% # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::458752-524287 59 0.01% 99.99% # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency 429system.cpu.dtb.walker.walkCompletionTime::589824-655359 68 0.01% 100.00% # Table walker service (enqueue to completion) latency 430system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 431system.cpu.dtb.walker.walkCompletionTime::total 806276 # Table walker service (enqueue to completion) latency 432system.cpu.dtb.walker.walksPending::samples 1071348818020 # Table walker pending requests distribution 433system.cpu.dtb.walker.walksPending::mean 0.742300 # Table walker pending requests distribution 434system.cpu.dtb.walker.walksPending::stdev 0.520529 # Table walker pending requests distribution 435system.cpu.dtb.walker.walksPending::0-1 1067163432520 99.61% 99.61% # Table walker pending requests distribution 436system.cpu.dtb.walker.walksPending::2-3 2639718000 0.25% 99.86% # Table walker pending requests distribution 437system.cpu.dtb.walker.walksPending::4-5 767294500 0.07% 99.93% # Table walker pending requests distribution 438system.cpu.dtb.walker.walksPending::6-7 303032500 0.03% 99.96% # Table walker pending requests distribution 439system.cpu.dtb.walker.walksPending::8-9 205205000 0.02% 99.97% # Table walker pending requests distribution 440system.cpu.dtb.walker.walksPending::10-11 125461000 0.01% 99.99% # Table walker pending requests distribution 441system.cpu.dtb.walker.walksPending::12-13 48256000 0.00% 99.99% # Table walker pending requests distribution 442system.cpu.dtb.walker.walksPending::14-15 92861500 0.01% 100.00% # Table walker pending requests distribution 443system.cpu.dtb.walker.walksPending::16-17 3532500 0.00% 100.00% # Table walker pending requests distribution 444system.cpu.dtb.walker.walksPending::18-19 24500 0.00% 100.00% # Table walker pending requests distribution 445system.cpu.dtb.walker.walksPending::total 1071348818020 # Table walker pending requests distribution 446system.cpu.dtb.walker.walkPageSizes::4K 277982 89.68% 89.68% # Table walker page sizes translated 447system.cpu.dtb.walker.walkPageSizes::2M 31985 10.32% 100.00% # Table walker page sizes translated 448system.cpu.dtb.walker.walkPageSizes::total 309967 # Table walker page sizes translated 449system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1435892 # Table walker requests started/completed, data/inst |
450system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
451system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1435892 # Table walker requests started/completed, data/inst 452system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309967 # Table walker requests started/completed, data/inst |
453system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
454system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309967 # Table walker requests started/completed, data/inst 455system.cpu.dtb.walker.walkRequestOrigin::total 1745859 # Table walker requests started/completed, data/inst |
456system.cpu.dtb.inst_hits 0 # ITB inst hits 457system.cpu.dtb.inst_misses 0 # ITB inst misses |
458system.cpu.dtb.read_hits 219013119 # DTB read hits 459system.cpu.dtb.read_misses 1011306 # DTB read misses 460system.cpu.dtb.write_hits 193770026 # DTB write hits 461system.cpu.dtb.write_misses 424586 # DTB write misses |
462system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 463system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
464system.cpu.dtb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID |
465system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID |
466system.cpu.dtb.flush_entries 88767 # Number of entries that have been flushed from TLB 467system.cpu.dtb.align_faults 111 # Number of TLB faults due to alignment restrictions 468system.cpu.dtb.prefetch_faults 16184 # Number of TLB faults due to prefetch |
469system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
470system.cpu.dtb.perms_faults 85758 # Number of TLB faults due to permissions restrictions 471system.cpu.dtb.read_accesses 220024425 # DTB read accesses 472system.cpu.dtb.write_accesses 194194612 # DTB write accesses |
473system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
474system.cpu.dtb.hits 412783145 # DTB hits 475system.cpu.dtb.misses 1435892 # DTB misses 476system.cpu.dtb.accesses 414219037 # DTB accesses 477system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
478system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 479system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 480system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 482system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 483system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 485system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 499system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 500system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 501system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 502system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 503system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 504system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 505system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 506system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
507system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 508system.cpu.itb.walker.walks 178617 # Table walker walks requested 509system.cpu.itb.walker.walksLong 178617 # Table walker walks initiated with long descriptors 510system.cpu.itb.walker.walksLongTerminationLevel::Level2 1509 # Level at which table walker walks with long descriptors terminate 511system.cpu.itb.walker.walksLongTerminationLevel::Level3 129197 # Level at which table walker walks with long descriptors terminate 512system.cpu.itb.walker.walksSquashedBefore 20173 # Table walks squashed before starting 513system.cpu.itb.walker.walkWaitTime::samples 158444 # Table walker wait (enqueue to first request) latency 514system.cpu.itb.walker.walkWaitTime::mean 1791.778168 # Table walker wait (enqueue to first request) latency 515system.cpu.itb.walker.walkWaitTime::stdev 17776.926489 # Table walker wait (enqueue to first request) latency 516system.cpu.itb.walker.walkWaitTime::0-65535 157195 99.21% 99.21% # Table walker wait (enqueue to first request) latency 517system.cpu.itb.walker.walkWaitTime::65536-131071 1061 0.67% 99.88% # Table walker wait (enqueue to first request) latency 518system.cpu.itb.walker.walkWaitTime::131072-196607 49 0.03% 99.91% # Table walker wait (enqueue to first request) latency 519system.cpu.itb.walker.walkWaitTime::196608-262143 23 0.01% 99.93% # Table walker wait (enqueue to first request) latency 520system.cpu.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.93% # Table walker wait (enqueue to first request) latency 521system.cpu.itb.walker.walkWaitTime::327680-393215 12 0.01% 99.94% # Table walker wait (enqueue to first request) latency 522system.cpu.itb.walker.walkWaitTime::393216-458751 2 0.00% 99.94% # Table walker wait (enqueue to first request) latency 523system.cpu.itb.walker.walkWaitTime::524288-589823 45 0.03% 99.97% # Table walker wait (enqueue to first request) latency 524system.cpu.itb.walker.walkWaitTime::589824-655359 46 0.03% 100.00% # Table walker wait (enqueue to first request) latency 525system.cpu.itb.walker.walkWaitTime::total 158444 # Table walker wait (enqueue to first request) latency 526system.cpu.itb.walker.walkCompletionTime::samples 150879 # Table walker service (enqueue to completion) latency 527system.cpu.itb.walker.walkCompletionTime::mean 29477.399108 # Table walker service (enqueue to completion) latency 528system.cpu.itb.walker.walkCompletionTime::gmean 23380.752932 # Table walker service (enqueue to completion) latency 529system.cpu.itb.walker.walkCompletionTime::stdev 29925.423831 # Table walker service (enqueue to completion) latency 530system.cpu.itb.walker.walkCompletionTime::0-65535 144789 95.96% 95.96% # Table walker service (enqueue to completion) latency 531system.cpu.itb.walker.walkCompletionTime::65536-131071 5035 3.34% 99.30% # Table walker service (enqueue to completion) latency 532system.cpu.itb.walker.walkCompletionTime::131072-196607 407 0.27% 99.57% # Table walker service (enqueue to completion) latency 533system.cpu.itb.walker.walkCompletionTime::196608-262143 355 0.24% 99.81% # Table walker service (enqueue to completion) latency 534system.cpu.itb.walker.walkCompletionTime::262144-327679 85 0.06% 99.86% # Table walker service (enqueue to completion) latency 535system.cpu.itb.walker.walkCompletionTime::327680-393215 65 0.04% 99.91% # Table walker service (enqueue to completion) latency 536system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.92% # Table walker service (enqueue to completion) latency 537system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.92% # Table walker service (enqueue to completion) latency 538system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.92% # Table walker service (enqueue to completion) latency 539system.cpu.itb.walker.walkCompletionTime::589824-655359 82 0.05% 99.98% # Table walker service (enqueue to completion) latency |
540system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency 541system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency |
542system.cpu.itb.walker.walkCompletionTime::total 150879 # Table walker service (enqueue to completion) latency 543system.cpu.itb.walker.walksPending::samples 908136653272 # Table walker pending requests distribution 544system.cpu.itb.walker.walksPending::mean 0.948518 # Table walker pending requests distribution 545system.cpu.itb.walker.walksPending::stdev 0.221299 # Table walker pending requests distribution 546system.cpu.itb.walker.walksPending::0 46816690152 5.16% 5.16% # Table walker pending requests distribution 547system.cpu.itb.walker.walksPending::1 861256760620 94.84% 99.99% # Table walker pending requests distribution 548system.cpu.itb.walker.walksPending::2 62690500 0.01% 100.00% # Table walker pending requests distribution 549system.cpu.itb.walker.walksPending::3 511000 0.00% 100.00% # Table walker pending requests distribution 550system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution 551system.cpu.itb.walker.walksPending::total 908136653272 # Table walker pending requests distribution 552system.cpu.itb.walker.walkPageSizes::4K 129197 98.85% 98.85% # Table walker page sizes translated 553system.cpu.itb.walker.walkPageSizes::2M 1509 1.15% 100.00% # Table walker page sizes translated 554system.cpu.itb.walker.walkPageSizes::total 130706 # Table walker page sizes translated |
555system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
556system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178617 # Table walker requests started/completed, data/inst 557system.cpu.itb.walker.walkRequestOrigin_Requested::total 178617 # Table walker requests started/completed, data/inst |
558system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
559system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130706 # Table walker requests started/completed, data/inst 560system.cpu.itb.walker.walkRequestOrigin_Completed::total 130706 # Table walker requests started/completed, data/inst 561system.cpu.itb.walker.walkRequestOrigin::total 309323 # Table walker requests started/completed, data/inst 562system.cpu.itb.inst_hits 465622680 # ITB inst hits 563system.cpu.itb.inst_misses 178617 # ITB inst misses |
564system.cpu.itb.read_hits 0 # DTB read hits 565system.cpu.itb.read_misses 0 # DTB read misses 566system.cpu.itb.write_hits 0 # DTB write hits 567system.cpu.itb.write_misses 0 # DTB write misses 568system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 569system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
570system.cpu.itb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID |
571system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID |
572system.cpu.itb.flush_entries 62354 # Number of entries that have been flushed from TLB |
573system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 574system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 575system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
576system.cpu.itb.perms_faults 442443 # Number of TLB faults due to permissions restrictions |
577system.cpu.itb.read_accesses 0 # DTB read accesses 578system.cpu.itb.write_accesses 0 # DTB write accesses |
579system.cpu.itb.inst_accesses 465801297 # ITB inst accesses 580system.cpu.itb.hits 465622680 # DTB hits 581system.cpu.itb.misses 178617 # DTB misses 582system.cpu.itb.accesses 465801297 # DTB accesses 583system.cpu.numPwrStateTransitions 34330 # Number of power state transitions 584system.cpu.pwrStateClkGateDist::samples 17165 # Distribution of time spent in the clock gated state 585system.cpu.pwrStateClkGateDist::mean 2940001446.310807 # Distribution of time spent in the clock gated state 586system.cpu.pwrStateClkGateDist::stdev 58531807829.842911 # Distribution of time spent in the clock gated state 587system.cpu.pwrStateClkGateDist::underflows 7841 45.68% 45.68% # Distribution of time spent in the clock gated state 588system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.11% 99.79% # Distribution of time spent in the clock gated state 589system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state |
590system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state 591system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 592system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state |
593system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 594system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 595system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 596system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state |
597system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state 598system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state 599system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
600system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state 601system.cpu.pwrStateClkGateDist::total 17165 # Distribution of time spent in the clock gated state 602system.cpu.pwrStateResidencyTicks::ON 1093565558075 # Cumulative time (in ticks) in various power states 603system.cpu.pwrStateResidencyTicks::CLK_GATED 50465124825925 # Cumulative time (in ticks) in various power states 604system.cpu.numCycles 2187140442 # number of cpu cycles simulated |
605system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 606system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
607system.cpu.fetch.icacheStallCycles 793785781 # Number of cycles fetch is stalled on an Icache miss 608system.cpu.fetch.Insts 1302631708 # Number of instructions fetch has processed 609system.cpu.fetch.Branches 292068322 # Number of branches that fetch encountered 610system.cpu.fetch.predictedBranches 175299129 # Number of branches that fetch has predicted taken 611system.cpu.fetch.Cycles 1300965183 # Number of cycles fetch has run and was not squashing or blocked 612system.cpu.fetch.SquashCycles 29519562 # Number of cycles fetch has spent squashing 613system.cpu.fetch.TlbCycles 4657753 # Number of cycles fetch has spent waiting for tlb 614system.cpu.fetch.MiscStallCycles 25879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 615system.cpu.fetch.PendingTrapStallCycles 11707627 # Number of stall cycles due to pending traps 616system.cpu.fetch.PendingQuiesceStallCycles 1236073 # Number of stall cycles due to pending quiesce instructions 617system.cpu.fetch.IcacheWaitRetryStallCycles 927 # Number of stall cycles due to full MSHR 618system.cpu.fetch.CacheLines 465162073 # Number of cache lines fetched 619system.cpu.fetch.IcacheSquashes 6904477 # Number of outstanding Icache misses that were squashed 620system.cpu.fetch.ItlbSquashes 52597 # Number of outstanding ITLB misses that were squashed 621system.cpu.fetch.rateDist::samples 2127139004 # Number of instructions fetched each cycle (Total) 622system.cpu.fetch.rateDist::mean 0.717629 # Number of instructions fetched each cycle (Total) 623system.cpu.fetch.rateDist::stdev 1.134701 # Number of instructions fetched each cycle (Total) |
624system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
625system.cpu.fetch.rateDist::0 1399565872 65.80% 65.80% # Number of instructions fetched each cycle (Total) 626system.cpu.fetch.rateDist::1 283601888 13.33% 79.13% # Number of instructions fetched each cycle (Total) 627system.cpu.fetch.rateDist::2 89018844 4.18% 83.31% # Number of instructions fetched each cycle (Total) 628system.cpu.fetch.rateDist::3 354952400 16.69% 100.00% # Number of instructions fetched each cycle (Total) |
629system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 630system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 631system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
632system.cpu.fetch.rateDist::total 2127139004 # Number of instructions fetched each cycle (Total) 633system.cpu.fetch.branchRate 0.133539 # Number of branch fetches per cycle 634system.cpu.fetch.rate 0.595587 # Number of inst fetches per cycle 635system.cpu.decode.IdleCycles 615428593 # Number of cycles decode is idle 636system.cpu.decode.BlockedCycles 884736584 # Number of cycles decode is blocked 637system.cpu.decode.RunCycles 543030027 # Number of cycles decode is running 638system.cpu.decode.UnblockCycles 73193860 # Number of cycles decode is unblocking 639system.cpu.decode.SquashCycles 10749940 # Number of cycles decode is squashing 640system.cpu.decode.BranchResolved 41477613 # Number of times decode resolved a branch 641system.cpu.decode.BranchMispred 4067608 # Number of times decode detected a branch misprediction 642system.cpu.decode.DecodedInsts 1417243244 # Number of instructions handled by decode 643system.cpu.decode.SquashedInsts 33090232 # Number of squashed instructions handled by decode 644system.cpu.rename.SquashCycles 10749940 # Number of cycles rename is squashing 645system.cpu.rename.IdleCycles 678230325 # Number of cycles rename is idle 646system.cpu.rename.BlockCycles 91937865 # Number of cycles rename is blocking 647system.cpu.rename.serializeStallCycles 569242294 # count of cycles rename stalled for serializing inst 648system.cpu.rename.RunCycles 557610269 # Number of cycles rename is running 649system.cpu.rename.UnblockCycles 219368311 # Number of cycles rename is unblocking 650system.cpu.rename.RenamedInsts 1392930802 # Number of instructions processed by rename 651system.cpu.rename.SquashedInsts 8136567 # Number of squashed instructions processed by rename 652system.cpu.rename.ROBFullEvents 7440637 # Number of times rename has blocked due to ROB full 653system.cpu.rename.IQFullEvents 990068 # Number of times rename has blocked due to IQ full 654system.cpu.rename.LQFullEvents 1113298 # Number of times rename has blocked due to LQ full 655system.cpu.rename.SQFullEvents 139552598 # Number of times rename has blocked due to SQ full 656system.cpu.rename.FullRegisterEvents 22837 # Number of times there has been no free registers 657system.cpu.rename.RenamedOperands 1342716381 # Number of destination operands rename has renamed 658system.cpu.rename.RenameLookups 2216807318 # Number of register rename lookups that rename has made 659system.cpu.rename.int_rename_lookups 1652527627 # Number of integer rename lookups 660system.cpu.rename.fp_rename_lookups 1431919 # Number of floating rename lookups 661system.cpu.rename.CommittedMaps 1263732146 # Number of HB maps that are committed 662system.cpu.rename.UndoneMaps 78984232 # Number of HB maps that are undone due to squashing 663system.cpu.rename.serializingInsts 44095214 # count of serializing insts renamed 664system.cpu.rename.tempSerializingInsts 39617186 # count of temporary serializing insts renamed 665system.cpu.rename.skidInsts 160769192 # count of insts added to the skid buffer 666system.cpu.memDep0.insertedLoads 224047664 # Number of loads inserted to the mem dependence unit. 667system.cpu.memDep0.insertedStores 198221089 # Number of stores inserted to the mem dependence unit. 668system.cpu.memDep0.conflictingLoads 12872997 # Number of conflicting loads. 669system.cpu.memDep0.conflictingStores 11132343 # Number of conflicting stores. 670system.cpu.iq.iqInstsAdded 1339626168 # Number of instructions added to the IQ (excludes non-spec) 671system.cpu.iq.iqNonSpecInstsAdded 44413765 # Number of non-speculative instructions added to the IQ 672system.cpu.iq.iqInstsIssued 1369656198 # Number of instructions issued 673system.cpu.iq.iqSquashedInstsIssued 4234304 # Number of squashed instructions issued 674system.cpu.iq.iqSquashedInstsExamined 74015451 # Number of squashed instructions iterated over during squash; mainly for profiling 675system.cpu.iq.iqSquashedOperandsExamined 42135581 # Number of squashed operands that are examined and possibly removed from graph 676system.cpu.iq.iqSquashedNonSpecRemoved 368828 # Number of squashed non-spec instructions that were removed 677system.cpu.iq.issued_per_cycle::samples 2127139004 # Number of insts issued each cycle 678system.cpu.iq.issued_per_cycle::mean 0.643896 # Number of insts issued each cycle 679system.cpu.iq.issued_per_cycle::stdev 0.914248 # Number of insts issued each cycle |
680system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
681system.cpu.iq.issued_per_cycle::0 1274738634 59.93% 59.93% # Number of insts issued each cycle 682system.cpu.iq.issued_per_cycle::1 452592629 21.28% 81.20% # Number of insts issued each cycle 683system.cpu.iq.issued_per_cycle::2 292740987 13.76% 94.97% # Number of insts issued each cycle 684system.cpu.iq.issued_per_cycle::3 96714663 4.55% 99.51% # Number of insts issued each cycle 685system.cpu.iq.issued_per_cycle::4 10322849 0.49% 100.00% # Number of insts issued each cycle 686system.cpu.iq.issued_per_cycle::5 29242 0.00% 100.00% # Number of insts issued each cycle |
687system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 688system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 689system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 690system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 691system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 692system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
693system.cpu.iq.issued_per_cycle::total 2127139004 # Number of insts issued each cycle |
694system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
695system.cpu.iq.fu_full::IntAlu 74109343 33.81% 33.81% # attempts to use FU when none available 696system.cpu.iq.fu_full::IntMult 90161 0.04% 33.85% # attempts to use FU when none available 697system.cpu.iq.fu_full::IntDiv 26765 0.01% 33.87% # attempts to use FU when none available 698system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available 699system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available 700system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available 701system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available 702system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available 703system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available 704system.cpu.iq.fu_full::FloatMisc 458 0.00% 33.87% # attempts to use FU when none available 705system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available 706system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available 707system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available 708system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available 709system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available 710system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available 711system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available 712system.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available 713system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available 714system.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available 715system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available 716system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available 717system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available 718system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available 719system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available 720system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available 721system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available 722system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available 723system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available 724system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available 725system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available 726system.cpu.iq.fu_full::MemRead 59034015 26.93% 60.80% # attempts to use FU when none available 727system.cpu.iq.fu_full::MemWrite 85210307 38.88% 99.68% # attempts to use FU when none available 728system.cpu.iq.fu_full::FloatMemRead 64791 0.03% 99.71% # attempts to use FU when none available 729system.cpu.iq.fu_full::FloatMemWrite 640346 0.29% 100.00% # attempts to use FU when none available |
730system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 731system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
732system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued 733system.cpu.iq.FU_type_0::IntAlu 946221695 69.08% 69.08% # Type of FU issued 734system.cpu.iq.FU_type_0::IntMult 2942835 0.21% 69.30% # Type of FU issued 735system.cpu.iq.FU_type_0::IntDiv 130438 0.01% 69.31% # Type of FU issued 736system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 69.31% # Type of FU issued 737system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued 738system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued |
739system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued |
740system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued |
741system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued |
742system.cpu.iq.FU_type_0::FloatMisc 112188 0.01% 69.32% # Type of FU issued 743system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued 744system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued 745system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued 746system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued 747system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued 748system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued 749system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued 750system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued 751system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued 752system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued 753system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued 754system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued 755system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued 756system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued 757system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued 758system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued 759system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued 760system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued |
761system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued 762system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued 763system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued |
764system.cpu.iq.FU_type_0::MemRead 223953856 16.35% 85.67% # Type of FU issued 765system.cpu.iq.FU_type_0::MemWrite 195515958 14.27% 99.94% # Type of FU issued 766system.cpu.iq.FU_type_0::FloatMemRead 118365 0.01% 99.95% # Type of FU issued 767system.cpu.iq.FU_type_0::FloatMemWrite 660412 0.05% 100.00% # Type of FU issued |
768system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 769system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
770system.cpu.iq.FU_type_0::total 1369656198 # Type of FU issued 771system.cpu.iq.rate 0.626231 # Inst issue rate 772system.cpu.iq.fu_busy_cnt 219176186 # FU busy when requested 773system.cpu.iq.fu_busy_rate 0.160023 # FU busy rate (busy events/executed inst) 774system.cpu.iq.int_inst_queue_reads 5087371498 # Number of integer instruction queue reads 775system.cpu.iq.int_inst_queue_writes 1457327579 # Number of integer instruction queue writes 776system.cpu.iq.int_inst_queue_wakeup_accesses 1347394357 # Number of integer instruction queue wakeup accesses 777system.cpu.iq.fp_inst_queue_reads 2490391 # Number of floating instruction queue reads 778system.cpu.iq.fp_inst_queue_writes 913879 # Number of floating instruction queue writes 779system.cpu.iq.fp_inst_queue_wakeup_accesses 884967 # Number of floating instruction queue wakeup accesses 780system.cpu.iq.int_alu_accesses 1587235373 # Number of integer alu accesses 781system.cpu.iq.fp_alu_accesses 1596980 # Number of floating point alu accesses 782system.cpu.iew.lsq.thread0.forwLoads 5732534 # Number of loads that had data forwarded from stores |
783system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
784system.cpu.iew.lsq.thread0.squashedLoads 17426729 # Number of loads squashed 785system.cpu.iew.lsq.thread0.ignoredResponses 22539 # Number of memory responses ignored because the instruction is squashed 786system.cpu.iew.lsq.thread0.memOrderViolation 187787 # Number of memory ordering violations 787system.cpu.iew.lsq.thread0.squashedStores 8018407 # Number of stores squashed |
788system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 789system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
790system.cpu.iew.lsq.thread0.rescheduledLoads 3639533 # Number of loads that were rescheduled 791system.cpu.iew.lsq.thread0.cacheBlocked 2053743 # Number of times an access to memory failed due to the cache being blocked |
792system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
793system.cpu.iew.iewSquashCycles 10749940 # Number of cycles IEW is squashing 794system.cpu.iew.iewBlockCycles 12646274 # Number of cycles IEW is blocking 795system.cpu.iew.iewUnblockCycles 5267578 # Number of cycles IEW is unblocking 796system.cpu.iew.iewDispatchedInsts 1384326807 # Number of instructions dispatched to IQ |
797system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
798system.cpu.iew.iewDispLoadInsts 224047664 # Number of dispatched load instructions 799system.cpu.iew.iewDispStoreInsts 198221089 # Number of dispatched store instructions 800system.cpu.iew.iewDispNonSpecInsts 39077844 # Number of dispatched non-speculative instructions 801system.cpu.iew.iewIQFullEvents 183202 # Number of times the IQ has become full, causing a stall 802system.cpu.iew.iewLSQFullEvents 4894696 # Number of times the LSQ has become full, causing a stall 803system.cpu.iew.memOrderViolationEvents 187787 # Number of memory order violations 804system.cpu.iew.predictedTakenIncorrect 4060868 # Number of branches that were predicted taken incorrectly 805system.cpu.iew.predictedNotTakenIncorrect 6118781 # Number of branches that were predicted not taken incorrectly 806system.cpu.iew.branchMispredicts 10179649 # Number of branch mispredicts detected at execute 807system.cpu.iew.iewExecutedInsts 1355949241 # Number of executed instructions 808system.cpu.iew.iewExecLoadInsts 219017773 # Number of load instructions executed 809system.cpu.iew.iewExecSquashedInsts 12300796 # Number of squashed instructions skipped in execute |
810system.cpu.iew.exec_swp 0 # number of swp insts executed |
811system.cpu.iew.exec_nop 286874 # number of nop insts executed 812system.cpu.iew.exec_refs 412797364 # number of memory reference insts executed 813system.cpu.iew.exec_branches 257488143 # Number of branches executed 814system.cpu.iew.exec_stores 193779591 # Number of stores executed 815system.cpu.iew.exec_rate 0.619964 # Inst execution rate 816system.cpu.iew.wb_sent 1349320641 # cumulative count of insts sent to commit 817system.cpu.iew.wb_count 1348279324 # cumulative count of insts written-back 818system.cpu.iew.wb_producers 576318139 # num instructions producing a value 819system.cpu.iew.wb_consumers 948680474 # num instructions consuming a value 820system.cpu.iew.wb_rate 0.616458 # insts written-back per cycle 821system.cpu.iew.wb_fanout 0.607494 # average fanout of values written-back 822system.cpu.commit.commitSquashedInsts 63090267 # The number of squashed insts skipped by commit 823system.cpu.commit.commitNonSpecStalls 44044937 # The number of times commit has been forced to stall to communicate backwards 824system.cpu.commit.branchMispredicts 9703294 # The number of times a branch was mispredicted 825system.cpu.commit.committed_per_cycle::samples 2112894773 # Number of insts commited each cycle 826system.cpu.commit.committed_per_cycle::mean 0.620014 # Number of insts commited each cycle 827system.cpu.commit.committed_per_cycle::stdev 1.265043 # Number of insts commited each cycle |
828system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
829system.cpu.commit.committed_per_cycle::0 1431908907 67.77% 67.77% # Number of insts commited each cycle 830system.cpu.commit.committed_per_cycle::1 397571073 18.82% 86.59% # Number of insts commited each cycle 831system.cpu.commit.committed_per_cycle::2 150815124 7.14% 93.72% # Number of insts commited each cycle 832system.cpu.commit.committed_per_cycle::3 44594147 2.11% 95.83% # Number of insts commited each cycle 833system.cpu.commit.committed_per_cycle::4 36107553 1.71% 97.54% # Number of insts commited each cycle 834system.cpu.commit.committed_per_cycle::5 18031210 0.85% 98.40% # Number of insts commited each cycle 835system.cpu.commit.committed_per_cycle::6 11307158 0.54% 98.93% # Number of insts commited each cycle 836system.cpu.commit.committed_per_cycle::7 5865302 0.28% 99.21% # Number of insts commited each cycle 837system.cpu.commit.committed_per_cycle::8 16694299 0.79% 100.00% # Number of insts commited each cycle |
838system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 839system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 840system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
841system.cpu.commit.committed_per_cycle::total 2112894773 # Number of insts commited each cycle 842system.cpu.commit.committedInsts 1114574366 # Number of instructions committed 843system.cpu.commit.committedOps 1310024478 # Number of ops (including micro ops) committed |
844system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
845system.cpu.commit.refs 396823616 # Number of memory references committed 846system.cpu.commit.loads 206620934 # Number of loads committed 847system.cpu.commit.membars 9197183 # Number of memory barriers committed 848system.cpu.commit.branches 249169048 # Number of branches committed 849system.cpu.commit.fp_insts 873305 # Number of committed floating point instructions. 850system.cpu.commit.int_insts 1197213012 # Number of committed integer instructions. 851system.cpu.commit.function_calls 31117535 # Number of function calls committed. |
852system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
853system.cpu.commit.op_class_0::IntAlu 910437285 69.50% 69.50% # Class of committed instruction 854system.cpu.commit.op_class_0::IntMult 2553089 0.19% 69.69% # Class of committed instruction 855system.cpu.commit.op_class_0::IntDiv 104752 0.01% 69.70% # Class of committed instruction 856system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction 857system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction 858system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction |
859system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction |
860system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction |
861system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction |
862system.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction 863system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction 864system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction 865system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction 866system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction 867system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction 868system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction 869system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction 870system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction 871system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction 872system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction 873system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction 874system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction 875system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction 876system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction 877system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction 878system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction 879system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction 880system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction |
881system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction 882system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction 883system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction |
884system.cpu.commit.op_class_0::MemRead 206508219 15.76% 85.47% # Class of committed instruction 885system.cpu.commit.op_class_0::MemWrite 189547828 14.47% 99.94% # Class of committed instruction 886system.cpu.commit.op_class_0::FloatMemRead 112715 0.01% 99.95% # Class of committed instruction 887system.cpu.commit.op_class_0::FloatMemWrite 654854 0.05% 100.00% # Class of committed instruction |
888system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 889system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
890system.cpu.commit.op_class_0::total 1310024478 # Class of committed instruction 891system.cpu.commit.bw_lim_events 16694299 # number cycles where commit BW limit reached 892system.cpu.rob.rob_reads 3459813368 # The number of ROB reads 893system.cpu.rob.rob_writes 2760364536 # The number of ROB writes 894system.cpu.timesIdled 9090851 # Number of times that the entire CPU went into an idle state and unscheduled itself 895system.cpu.idleCycles 60001438 # Total number of cycles that the CPU has spent unscheduled due to idling 896system.cpu.quiesceCycles 100930240360 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 897system.cpu.committedInsts 1114574366 # Number of Instructions Simulated 898system.cpu.committedOps 1310024478 # Number of Ops (including micro ops) Simulated 899system.cpu.cpi 1.962310 # CPI: Cycles Per Instruction 900system.cpu.cpi_total 1.962310 # CPI: Total CPI of All Threads 901system.cpu.ipc 0.509603 # IPC: Instructions Per Cycle 902system.cpu.ipc_total 0.509603 # IPC: Total IPC of All Threads 903system.cpu.int_regfile_reads 1610546046 # number of integer regfile reads 904system.cpu.int_regfile_writes 949011498 # number of integer regfile writes 905system.cpu.fp_regfile_reads 1420249 # number of floating regfile reads 906system.cpu.fp_regfile_writes 762248 # number of floating regfile writes 907system.cpu.cc_regfile_reads 314797086 # number of cc regfile reads 908system.cpu.cc_regfile_writes 315669715 # number of cc regfile writes 909system.cpu.misc_regfile_reads 3475493523 # number of misc regfile reads 910system.cpu.misc_regfile_writes 44962873 # number of misc regfile writes 911system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 912system.cpu.dcache.tags.replacements 13773422 # number of replacements 913system.cpu.dcache.tags.tagsinuse 511.982216 # Cycle average of tags in use 914system.cpu.dcache.tags.total_refs 363599894 # Total number of references to valid blocks. 915system.cpu.dcache.tags.sampled_refs 13773934 # Sample count of references to valid blocks. 916system.cpu.dcache.tags.avg_refs 26.397679 # Average number of references to valid blocks. |
917system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. |
918system.cpu.dcache.tags.occ_blocks::cpu.data 511.982216 # Average occupied blocks per requestor |
919system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy 920system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy 921system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
922system.cpu.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 923system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 924system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id |
925system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
926system.cpu.dcache.tags.tag_accesses 1610515756 # Number of tag accesses 927system.cpu.dcache.tags.data_accesses 1610515756 # Number of data accesses 928system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 929system.cpu.dcache.ReadReq_hits::cpu.data 188193818 # number of ReadReq hits 930system.cpu.dcache.ReadReq_hits::total 188193818 # number of ReadReq hits 931system.cpu.dcache.WriteReq_hits::cpu.data 164381838 # number of WriteReq hits 932system.cpu.dcache.WriteReq_hits::total 164381838 # number of WriteReq hits 933system.cpu.dcache.SoftPFReq_hits::cpu.data 464944 # number of SoftPFReq hits 934system.cpu.dcache.SoftPFReq_hits::total 464944 # number of SoftPFReq hits 935system.cpu.dcache.WriteLineReq_hits::cpu.data 334105 # number of WriteLineReq hits 936system.cpu.dcache.WriteLineReq_hits::total 334105 # number of WriteLineReq hits 937system.cpu.dcache.LoadLockedReq_hits::cpu.data 4846159 # number of LoadLockedReq hits 938system.cpu.dcache.LoadLockedReq_hits::total 4846159 # number of LoadLockedReq hits 939system.cpu.dcache.StoreCondReq_hits::cpu.data 5335614 # number of StoreCondReq hits 940system.cpu.dcache.StoreCondReq_hits::total 5335614 # number of StoreCondReq hits 941system.cpu.dcache.demand_hits::cpu.data 352909761 # number of demand (read+write) hits 942system.cpu.dcache.demand_hits::total 352909761 # number of demand (read+write) hits 943system.cpu.dcache.overall_hits::cpu.data 353374705 # number of overall hits 944system.cpu.dcache.overall_hits::total 353374705 # number of overall hits 945system.cpu.dcache.ReadReq_misses::cpu.data 12874356 # number of ReadReq misses 946system.cpu.dcache.ReadReq_misses::total 12874356 # number of ReadReq misses 947system.cpu.dcache.WriteReq_misses::cpu.data 18866989 # number of WriteReq misses 948system.cpu.dcache.WriteReq_misses::total 18866989 # number of WriteReq misses 949system.cpu.dcache.SoftPFReq_misses::cpu.data 2064832 # number of SoftPFReq misses 950system.cpu.dcache.SoftPFReq_misses::total 2064832 # number of SoftPFReq misses 951system.cpu.dcache.WriteLineReq_misses::cpu.data 1271634 # number of WriteLineReq misses 952system.cpu.dcache.WriteLineReq_misses::total 1271634 # number of WriteLineReq misses 953system.cpu.dcache.LoadLockedReq_misses::cpu.data 551153 # number of LoadLockedReq misses 954system.cpu.dcache.LoadLockedReq_misses::total 551153 # number of LoadLockedReq misses |
955system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses 956system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses |
957system.cpu.dcache.demand_misses::cpu.data 33012979 # number of demand (read+write) misses 958system.cpu.dcache.demand_misses::total 33012979 # number of demand (read+write) misses 959system.cpu.dcache.overall_misses::cpu.data 35077811 # number of overall misses 960system.cpu.dcache.overall_misses::total 35077811 # number of overall misses 961system.cpu.dcache.ReadReq_miss_latency::cpu.data 223063102000 # number of ReadReq miss cycles 962system.cpu.dcache.ReadReq_miss_latency::total 223063102000 # number of ReadReq miss cycles 963system.cpu.dcache.WriteReq_miss_latency::cpu.data 1108624638487 # number of WriteReq miss cycles 964system.cpu.dcache.WriteReq_miss_latency::total 1108624638487 # number of WriteReq miss cycles 965system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30055916196 # number of WriteLineReq miss cycles 966system.cpu.dcache.WriteLineReq_miss_latency::total 30055916196 # number of WriteLineReq miss cycles 967system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9351183000 # number of LoadLockedReq miss cycles 968system.cpu.dcache.LoadLockedReq_miss_latency::total 9351183000 # number of LoadLockedReq miss cycles 969system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles 970system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles 971system.cpu.dcache.demand_miss_latency::cpu.data 1361743656683 # number of demand (read+write) miss cycles 972system.cpu.dcache.demand_miss_latency::total 1361743656683 # number of demand (read+write) miss cycles 973system.cpu.dcache.overall_miss_latency::cpu.data 1361743656683 # number of overall miss cycles 974system.cpu.dcache.overall_miss_latency::total 1361743656683 # number of overall miss cycles 975system.cpu.dcache.ReadReq_accesses::cpu.data 201068174 # number of ReadReq accesses(hits+misses) 976system.cpu.dcache.ReadReq_accesses::total 201068174 # number of ReadReq accesses(hits+misses) 977system.cpu.dcache.WriteReq_accesses::cpu.data 183248827 # number of WriteReq accesses(hits+misses) 978system.cpu.dcache.WriteReq_accesses::total 183248827 # number of WriteReq accesses(hits+misses) 979system.cpu.dcache.SoftPFReq_accesses::cpu.data 2529776 # number of SoftPFReq accesses(hits+misses) 980system.cpu.dcache.SoftPFReq_accesses::total 2529776 # number of SoftPFReq accesses(hits+misses) 981system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605739 # number of WriteLineReq accesses(hits+misses) 982system.cpu.dcache.WriteLineReq_accesses::total 1605739 # number of WriteLineReq accesses(hits+misses) 983system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5397312 # number of LoadLockedReq accesses(hits+misses) 984system.cpu.dcache.LoadLockedReq_accesses::total 5397312 # number of LoadLockedReq accesses(hits+misses) 985system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335622 # number of StoreCondReq accesses(hits+misses) 986system.cpu.dcache.StoreCondReq_accesses::total 5335622 # number of StoreCondReq accesses(hits+misses) 987system.cpu.dcache.demand_accesses::cpu.data 385922740 # number of demand (read+write) accesses 988system.cpu.dcache.demand_accesses::total 385922740 # number of demand (read+write) accesses 989system.cpu.dcache.overall_accesses::cpu.data 388452516 # number of overall (read+write) accesses 990system.cpu.dcache.overall_accesses::total 388452516 # number of overall (read+write) accesses 991system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064030 # miss rate for ReadReq accesses 992system.cpu.dcache.ReadReq_miss_rate::total 0.064030 # miss rate for ReadReq accesses 993system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102958 # miss rate for WriteReq accesses 994system.cpu.dcache.WriteReq_miss_rate::total 0.102958 # miss rate for WriteReq accesses 995system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816211 # miss rate for SoftPFReq accesses 996system.cpu.dcache.SoftPFReq_miss_rate::total 0.816211 # miss rate for SoftPFReq accesses 997system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791931 # miss rate for WriteLineReq accesses 998system.cpu.dcache.WriteLineReq_miss_rate::total 0.791931 # miss rate for WriteLineReq accesses 999system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102116 # miss rate for LoadLockedReq accesses 1000system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102116 # miss rate for LoadLockedReq accesses |
1001system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 1002system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses |
1003system.cpu.dcache.demand_miss_rate::cpu.data 0.085543 # miss rate for demand accesses 1004system.cpu.dcache.demand_miss_rate::total 0.085543 # miss rate for demand accesses 1005system.cpu.dcache.overall_miss_rate::cpu.data 0.090301 # miss rate for overall accesses 1006system.cpu.dcache.overall_miss_rate::total 0.090301 # miss rate for overall accesses 1007system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17326.156120 # average ReadReq miss latency 1008system.cpu.dcache.ReadReq_avg_miss_latency::total 17326.156120 # average ReadReq miss latency 1009system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58760.019338 # average WriteReq miss latency 1010system.cpu.dcache.WriteReq_avg_miss_latency::total 58760.019338 # average WriteReq miss latency 1011system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23635.665762 # average WriteLineReq miss latency 1012system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23635.665762 # average WriteLineReq miss latency 1013system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16966.582782 # average LoadLockedReq miss latency 1014system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16966.582782 # average LoadLockedReq miss latency 1015system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35687.500000 # average StoreCondReq miss latency 1016system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35687.500000 # average StoreCondReq miss latency 1017system.cpu.dcache.demand_avg_miss_latency::cpu.data 41248.736041 # average overall miss latency 1018system.cpu.dcache.demand_avg_miss_latency::total 41248.736041 # average overall miss latency 1019system.cpu.dcache.overall_avg_miss_latency::cpu.data 38820.656645 # average overall miss latency 1020system.cpu.dcache.overall_avg_miss_latency::total 38820.656645 # average overall miss latency 1021system.cpu.dcache.blocked_cycles::no_mshrs 28867036 # number of cycles access was blocked |
1022system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1023system.cpu.dcache.blocked::no_mshrs 2109714 # number of cycles access was blocked |
1024system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
1025system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.682914 # average number of cycles each access was blocked |
1026system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1027system.cpu.dcache.writebacks::writebacks 10417036 # number of writebacks 1028system.cpu.dcache.writebacks::total 10417036 # number of writebacks 1029system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5763320 # number of ReadReq MSHR hits 1030system.cpu.dcache.ReadReq_mshr_hits::total 5763320 # number of ReadReq MSHR hits 1031system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15767233 # number of WriteReq MSHR hits 1032system.cpu.dcache.WriteReq_mshr_hits::total 15767233 # number of WriteReq MSHR hits 1033system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7067 # number of WriteLineReq MSHR hits 1034system.cpu.dcache.WriteLineReq_mshr_hits::total 7067 # number of WriteLineReq MSHR hits 1035system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 267203 # number of LoadLockedReq MSHR hits 1036system.cpu.dcache.LoadLockedReq_mshr_hits::total 267203 # number of LoadLockedReq MSHR hits 1037system.cpu.dcache.demand_mshr_hits::cpu.data 21537620 # number of demand (read+write) MSHR hits 1038system.cpu.dcache.demand_mshr_hits::total 21537620 # number of demand (read+write) MSHR hits 1039system.cpu.dcache.overall_mshr_hits::cpu.data 21537620 # number of overall MSHR hits 1040system.cpu.dcache.overall_mshr_hits::total 21537620 # number of overall MSHR hits 1041system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111036 # number of ReadReq MSHR misses 1042system.cpu.dcache.ReadReq_mshr_misses::total 7111036 # number of ReadReq MSHR misses 1043system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099756 # number of WriteReq MSHR misses 1044system.cpu.dcache.WriteReq_mshr_misses::total 3099756 # number of WriteReq MSHR misses 1045system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2058030 # number of SoftPFReq MSHR misses 1046system.cpu.dcache.SoftPFReq_mshr_misses::total 2058030 # number of SoftPFReq MSHR misses 1047system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1264567 # number of WriteLineReq MSHR misses 1048system.cpu.dcache.WriteLineReq_mshr_misses::total 1264567 # number of WriteLineReq MSHR misses 1049system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283950 # number of LoadLockedReq MSHR misses 1050system.cpu.dcache.LoadLockedReq_mshr_misses::total 283950 # number of LoadLockedReq MSHR misses |
1051system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses 1052system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses |
1053system.cpu.dcache.demand_mshr_misses::cpu.data 11475359 # number of demand (read+write) MSHR misses 1054system.cpu.dcache.demand_mshr_misses::total 11475359 # number of demand (read+write) MSHR misses 1055system.cpu.dcache.overall_mshr_misses::cpu.data 13533389 # number of overall MSHR misses 1056system.cpu.dcache.overall_mshr_misses::total 13533389 # number of overall MSHR misses |
1057system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable 1058system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable 1059system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable 1060system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable 1061system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses 1062system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses |
1063system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 117823858000 # number of ReadReq MSHR miss cycles 1064system.cpu.dcache.ReadReq_mshr_miss_latency::total 117823858000 # number of ReadReq MSHR miss cycles 1065system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163535842014 # number of WriteReq MSHR miss cycles 1066system.cpu.dcache.WriteReq_mshr_miss_latency::total 163535842014 # number of WriteReq MSHR miss cycles 1067system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34754745000 # number of SoftPFReq MSHR miss cycles 1068system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34754745000 # number of SoftPFReq MSHR miss cycles 1069system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28487682196 # number of WriteLineReq MSHR miss cycles 1070system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28487682196 # number of WriteLineReq MSHR miss cycles 1071system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4220692000 # number of LoadLockedReq MSHR miss cycles 1072system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4220692000 # number of LoadLockedReq MSHR miss cycles 1073system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles 1074system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles 1075system.cpu.dcache.demand_mshr_miss_latency::cpu.data 309847382210 # number of demand (read+write) MSHR miss cycles 1076system.cpu.dcache.demand_mshr_miss_latency::total 309847382210 # number of demand (read+write) MSHR miss cycles 1077system.cpu.dcache.overall_mshr_miss_latency::cpu.data 344602127210 # number of overall MSHR miss cycles 1078system.cpu.dcache.overall_mshr_miss_latency::total 344602127210 # number of overall MSHR miss cycles 1079system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225657500 # number of ReadReq MSHR uncacheable cycles 1080system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225657500 # number of ReadReq MSHR uncacheable cycles 1081system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225657500 # number of overall MSHR uncacheable cycles 1082system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225657500 # number of overall MSHR uncacheable cycles 1083system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035366 # mshr miss rate for ReadReq accesses 1084system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035366 # mshr miss rate for ReadReq accesses |
1085system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses 1086system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses |
1087system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813523 # mshr miss rate for SoftPFReq accesses 1088system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813523 # mshr miss rate for SoftPFReq accesses 1089system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787530 # mshr miss rate for WriteLineReq accesses 1090system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787530 # mshr miss rate for WriteLineReq accesses 1091system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052610 # mshr miss rate for LoadLockedReq accesses 1092system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052610 # mshr miss rate for LoadLockedReq accesses |
1093system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 1094system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses |
1095system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029735 # mshr miss rate for demand accesses 1096system.cpu.dcache.demand_mshr_miss_rate::total 0.029735 # mshr miss rate for demand accesses 1097system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034839 # mshr miss rate for overall accesses 1098system.cpu.dcache.overall_mshr_miss_rate::total 0.034839 # mshr miss rate for overall accesses 1099system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.155043 # average ReadReq mshr miss latency 1100system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.155043 # average ReadReq mshr miss latency 1101system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52757.649961 # average WriteReq mshr miss latency 1102system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52757.649961 # average WriteReq mshr miss latency 1103system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16887.385024 # average SoftPFReq mshr miss latency 1104system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16887.385024 # average SoftPFReq mshr miss latency 1105system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22527.617909 # average WriteLineReq mshr miss latency 1106system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22527.617909 # average WriteLineReq mshr miss latency 1107system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14864.208487 # average LoadLockedReq mshr miss latency 1108system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14864.208487 # average LoadLockedReq mshr miss latency 1109system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34687.500000 # average StoreCondReq mshr miss latency 1110system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34687.500000 # average StoreCondReq mshr miss latency 1111system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27001.105779 # average overall mshr miss latency 1112system.cpu.dcache.demand_avg_mshr_miss_latency::total 27001.105779 # average overall mshr miss latency 1113system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25463.106633 # average overall mshr miss latency 1114system.cpu.dcache.overall_avg_mshr_miss_latency::total 25463.106633 # average overall mshr miss latency 1115system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184781.476315 # average ReadReq mshr uncacheable latency 1116system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184781.476315 # average ReadReq mshr uncacheable latency 1117system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.658432 # average overall mshr uncacheable latency 1118system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.658432 # average overall mshr uncacheable latency 1119system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1120system.cpu.icache.tags.replacements 16948036 # number of replacements 1121system.cpu.icache.tags.tagsinuse 511.953468 # Cycle average of tags in use 1122system.cpu.icache.tags.total_refs 447400638 # Total number of references to valid blocks. 1123system.cpu.icache.tags.sampled_refs 16948548 # Sample count of references to valid blocks. 1124system.cpu.icache.tags.avg_refs 26.397579 # Average number of references to valid blocks. |
1125system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit. |
1126system.cpu.icache.tags.occ_blocks::cpu.inst 511.953468 # Average occupied blocks per requestor |
1127system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy 1128system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy 1129system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
1130system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 1131system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id 1132system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id |
1133system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
1134system.cpu.icache.tags.tag_accesses 482089545 # Number of tag accesses 1135system.cpu.icache.tags.data_accesses 482089545 # Number of data accesses 1136system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1137system.cpu.icache.ReadReq_hits::cpu.inst 447400638 # number of ReadReq hits 1138system.cpu.icache.ReadReq_hits::total 447400638 # number of ReadReq hits 1139system.cpu.icache.demand_hits::cpu.inst 447400638 # number of demand (read+write) hits 1140system.cpu.icache.demand_hits::total 447400638 # number of demand (read+write) hits 1141system.cpu.icache.overall_hits::cpu.inst 447400638 # number of overall hits 1142system.cpu.icache.overall_hits::total 447400638 # number of overall hits 1143system.cpu.icache.ReadReq_misses::cpu.inst 17740135 # number of ReadReq misses 1144system.cpu.icache.ReadReq_misses::total 17740135 # number of ReadReq misses 1145system.cpu.icache.demand_misses::cpu.inst 17740135 # number of demand (read+write) misses 1146system.cpu.icache.demand_misses::total 17740135 # number of demand (read+write) misses 1147system.cpu.icache.overall_misses::cpu.inst 17740135 # number of overall misses 1148system.cpu.icache.overall_misses::total 17740135 # number of overall misses 1149system.cpu.icache.ReadReq_miss_latency::cpu.inst 237745686369 # number of ReadReq miss cycles 1150system.cpu.icache.ReadReq_miss_latency::total 237745686369 # number of ReadReq miss cycles 1151system.cpu.icache.demand_miss_latency::cpu.inst 237745686369 # number of demand (read+write) miss cycles 1152system.cpu.icache.demand_miss_latency::total 237745686369 # number of demand (read+write) miss cycles 1153system.cpu.icache.overall_miss_latency::cpu.inst 237745686369 # number of overall miss cycles 1154system.cpu.icache.overall_miss_latency::total 237745686369 # number of overall miss cycles 1155system.cpu.icache.ReadReq_accesses::cpu.inst 465140773 # number of ReadReq accesses(hits+misses) 1156system.cpu.icache.ReadReq_accesses::total 465140773 # number of ReadReq accesses(hits+misses) 1157system.cpu.icache.demand_accesses::cpu.inst 465140773 # number of demand (read+write) accesses 1158system.cpu.icache.demand_accesses::total 465140773 # number of demand (read+write) accesses 1159system.cpu.icache.overall_accesses::cpu.inst 465140773 # number of overall (read+write) accesses 1160system.cpu.icache.overall_accesses::total 465140773 # number of overall (read+write) accesses 1161system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038139 # miss rate for ReadReq accesses 1162system.cpu.icache.ReadReq_miss_rate::total 0.038139 # miss rate for ReadReq accesses 1163system.cpu.icache.demand_miss_rate::cpu.inst 0.038139 # miss rate for demand accesses 1164system.cpu.icache.demand_miss_rate::total 0.038139 # miss rate for demand accesses 1165system.cpu.icache.overall_miss_rate::cpu.inst 0.038139 # miss rate for overall accesses 1166system.cpu.icache.overall_miss_rate::total 0.038139 # miss rate for overall accesses 1167system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13401.571429 # average ReadReq miss latency 1168system.cpu.icache.ReadReq_avg_miss_latency::total 13401.571429 # average ReadReq miss latency 1169system.cpu.icache.demand_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency 1170system.cpu.icache.demand_avg_miss_latency::total 13401.571429 # average overall miss latency 1171system.cpu.icache.overall_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency 1172system.cpu.icache.overall_avg_miss_latency::total 13401.571429 # average overall miss latency 1173system.cpu.icache.blocked_cycles::no_mshrs 22866 # number of cycles access was blocked |
1174system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1175system.cpu.icache.blocked::no_mshrs 1431 # number of cycles access was blocked |
1176system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
1177system.cpu.icache.avg_blocked_cycles::no_mshrs 15.979036 # average number of cycles each access was blocked |
1178system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1179system.cpu.icache.writebacks::writebacks 16948036 # number of writebacks 1180system.cpu.icache.writebacks::total 16948036 # number of writebacks 1181system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791363 # number of ReadReq MSHR hits 1182system.cpu.icache.ReadReq_mshr_hits::total 791363 # number of ReadReq MSHR hits 1183system.cpu.icache.demand_mshr_hits::cpu.inst 791363 # number of demand (read+write) MSHR hits 1184system.cpu.icache.demand_mshr_hits::total 791363 # number of demand (read+write) MSHR hits 1185system.cpu.icache.overall_mshr_hits::cpu.inst 791363 # number of overall MSHR hits 1186system.cpu.icache.overall_mshr_hits::total 791363 # number of overall MSHR hits 1187system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16948772 # number of ReadReq MSHR misses 1188system.cpu.icache.ReadReq_mshr_misses::total 16948772 # number of ReadReq MSHR misses 1189system.cpu.icache.demand_mshr_misses::cpu.inst 16948772 # number of demand (read+write) MSHR misses 1190system.cpu.icache.demand_mshr_misses::total 16948772 # number of demand (read+write) MSHR misses 1191system.cpu.icache.overall_mshr_misses::cpu.inst 16948772 # number of overall MSHR misses 1192system.cpu.icache.overall_mshr_misses::total 16948772 # number of overall MSHR misses |
1193system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 1194system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable 1195system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 1196system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses |
1197system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213645244880 # number of ReadReq MSHR miss cycles 1198system.cpu.icache.ReadReq_mshr_miss_latency::total 213645244880 # number of ReadReq MSHR miss cycles 1199system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213645244880 # number of demand (read+write) MSHR miss cycles 1200system.cpu.icache.demand_mshr_miss_latency::total 213645244880 # number of demand (read+write) MSHR miss cycles 1201system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213645244880 # number of overall MSHR miss cycles 1202system.cpu.icache.overall_mshr_miss_latency::total 213645244880 # number of overall MSHR miss cycles |
1203system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles 1204system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles 1205system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles 1206system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles |
1207system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for ReadReq accesses 1208system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036438 # mshr miss rate for ReadReq accesses 1209system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for demand accesses 1210system.cpu.icache.demand_mshr_miss_rate::total 0.036438 # mshr miss rate for demand accesses 1211system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for overall accesses 1212system.cpu.icache.overall_mshr_miss_rate::total 0.036438 # mshr miss rate for overall accesses 1213system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12605.352463 # average ReadReq mshr miss latency 1214system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12605.352463 # average ReadReq mshr miss latency 1215system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency 1216system.cpu.icache.demand_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency 1217system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency 1218system.cpu.icache.overall_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency |
1219system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency 1220system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency 1221system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency 1222system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency |
1223system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1224system.cpu.l2cache.tags.replacements 2368264 # number of replacements 1225system.cpu.l2cache.tags.tagsinuse 65438.912903 # Cycle average of tags in use 1226system.cpu.l2cache.tags.total_refs 59342443 # Total number of references to valid blocks. 1227system.cpu.l2cache.tags.sampled_refs 2431405 # Sample count of references to valid blocks. 1228system.cpu.l2cache.tags.avg_refs 24.406647 # Average number of references to valid blocks. |
1229system.cpu.l2cache.tags.warmup_cycle 2677802000 # Cycle when the warmup percentage was hit. |
1230system.cpu.l2cache.tags.occ_blocks::writebacks 9464.122529 # Average occupied blocks per requestor 1231system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 393.883765 # Average occupied blocks per requestor 1232system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.035779 # Average occupied blocks per requestor 1233system.cpu.l2cache.tags.occ_blocks::cpu.inst 6680.528058 # Average occupied blocks per requestor 1234system.cpu.l2cache.tags.occ_blocks::cpu.data 48467.342772 # Average occupied blocks per requestor 1235system.cpu.l2cache.tags.occ_percent::writebacks 0.144411 # Average percentage of cache occupancy 1236system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006010 # Average percentage of cache occupancy 1237system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006608 # Average percentage of cache occupancy 1238system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101937 # Average percentage of cache occupancy 1239system.cpu.l2cache.tags.occ_percent::cpu.data 0.739553 # Average percentage of cache occupancy 1240system.cpu.l2cache.tags.occ_percent::total 0.998519 # Average percentage of cache occupancy 1241system.cpu.l2cache.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id 1242system.cpu.l2cache.tags.occ_task_id_blocks::1024 62889 # Occupied blocks per task id 1243system.cpu.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 1244system.cpu.l2cache.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id 1245system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 1246system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 1247system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1015 # Occupied blocks per task id 1248system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5647 # Occupied blocks per task id 1249system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55838 # Occupied blocks per task id 1250system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id 1251system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959610 # Percentage of cache occupancy per task id 1252system.cpu.l2cache.tags.tag_accesses 508088213 # Number of tag accesses 1253system.cpu.l2cache.tags.data_accesses 508088213 # Number of data accesses 1254system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1255system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1306072 # number of ReadReq hits 1256system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 309439 # number of ReadReq hits 1257system.cpu.l2cache.ReadReq_hits::total 1615511 # number of ReadReq hits 1258system.cpu.l2cache.WritebackDirty_hits::writebacks 10417036 # number of WritebackDirty hits 1259system.cpu.l2cache.WritebackDirty_hits::total 10417036 # number of WritebackDirty hits 1260system.cpu.l2cache.WritebackClean_hits::writebacks 16945412 # number of WritebackClean hits 1261system.cpu.l2cache.WritebackClean_hits::total 16945412 # number of WritebackClean hits 1262system.cpu.l2cache.UpgradeReq_hits::cpu.data 39342 # number of UpgradeReq hits 1263system.cpu.l2cache.UpgradeReq_hits::total 39342 # number of UpgradeReq hits |
1264system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits 1265system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits |
1266system.cpu.l2cache.ReadExReq_hits::cpu.data 1735264 # number of ReadExReq hits 1267system.cpu.l2cache.ReadExReq_hits::total 1735264 # number of ReadExReq hits 1268system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16852583 # number of ReadCleanReq hits 1269system.cpu.l2cache.ReadCleanReq_hits::total 16852583 # number of ReadCleanReq hits 1270system.cpu.l2cache.ReadSharedReq_hits::cpu.data 9020162 # number of ReadSharedReq hits 1271system.cpu.l2cache.ReadSharedReq_hits::total 9020162 # number of ReadSharedReq hits 1272system.cpu.l2cache.InvalidateReq_hits::cpu.data 672287 # number of InvalidateReq hits 1273system.cpu.l2cache.InvalidateReq_hits::total 672287 # number of InvalidateReq hits 1274system.cpu.l2cache.demand_hits::cpu.dtb.walker 1306072 # number of demand (read+write) hits 1275system.cpu.l2cache.demand_hits::cpu.itb.walker 309439 # number of demand (read+write) hits 1276system.cpu.l2cache.demand_hits::cpu.inst 16852583 # number of demand (read+write) hits 1277system.cpu.l2cache.demand_hits::cpu.data 10755426 # number of demand (read+write) hits 1278system.cpu.l2cache.demand_hits::total 29223520 # number of demand (read+write) hits 1279system.cpu.l2cache.overall_hits::cpu.dtb.walker 1306072 # number of overall hits 1280system.cpu.l2cache.overall_hits::cpu.itb.walker 309439 # number of overall hits 1281system.cpu.l2cache.overall_hits::cpu.inst 16852583 # number of overall hits 1282system.cpu.l2cache.overall_hits::cpu.data 10755426 # number of overall hits 1283system.cpu.l2cache.overall_hits::total 29223520 # number of overall hits 1284system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10647 # number of ReadReq misses 1285system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8959 # number of ReadReq misses 1286system.cpu.l2cache.ReadReq_misses::total 19606 # number of ReadReq misses 1287system.cpu.l2cache.UpgradeReq_misses::cpu.data 4043 # number of UpgradeReq misses 1288system.cpu.l2cache.UpgradeReq_misses::total 4043 # number of UpgradeReq misses |
1289system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses 1290system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses |
1291system.cpu.l2cache.ReadExReq_misses::cpu.data 1337553 # number of ReadExReq misses 1292system.cpu.l2cache.ReadExReq_misses::total 1337553 # number of ReadExReq misses 1293system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95970 # number of ReadCleanReq misses 1294system.cpu.l2cache.ReadCleanReq_misses::total 95970 # number of ReadCleanReq misses 1295system.cpu.l2cache.ReadSharedReq_misses::cpu.data 416410 # number of ReadSharedReq misses 1296system.cpu.l2cache.ReadSharedReq_misses::total 416410 # number of ReadSharedReq misses 1297system.cpu.l2cache.InvalidateReq_misses::cpu.data 592280 # number of InvalidateReq misses 1298system.cpu.l2cache.InvalidateReq_misses::total 592280 # number of InvalidateReq misses 1299system.cpu.l2cache.demand_misses::cpu.dtb.walker 10647 # number of demand (read+write) misses 1300system.cpu.l2cache.demand_misses::cpu.itb.walker 8959 # number of demand (read+write) misses 1301system.cpu.l2cache.demand_misses::cpu.inst 95970 # number of demand (read+write) misses 1302system.cpu.l2cache.demand_misses::cpu.data 1753963 # number of demand (read+write) misses 1303system.cpu.l2cache.demand_misses::total 1869539 # number of demand (read+write) misses 1304system.cpu.l2cache.overall_misses::cpu.dtb.walker 10647 # number of overall misses 1305system.cpu.l2cache.overall_misses::cpu.itb.walker 8959 # number of overall misses 1306system.cpu.l2cache.overall_misses::cpu.inst 95970 # number of overall misses 1307system.cpu.l2cache.overall_misses::cpu.data 1753963 # number of overall misses 1308system.cpu.l2cache.overall_misses::total 1869539 # number of overall misses 1309system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1464838500 # number of ReadReq miss cycles 1310system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 979350000 # number of ReadReq miss cycles 1311system.cpu.l2cache.ReadReq_miss_latency::total 2444188500 # number of ReadReq miss cycles 1312system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73726500 # number of UpgradeReq miss cycles 1313system.cpu.l2cache.UpgradeReq_miss_latency::total 73726500 # number of UpgradeReq miss cycles 1314system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles 1315system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles 1316system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 139978365500 # number of ReadExReq miss cycles 1317system.cpu.l2cache.ReadExReq_miss_latency::total 139978365500 # number of ReadExReq miss cycles 1318system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10559308500 # number of ReadCleanReq miss cycles 1319system.cpu.l2cache.ReadCleanReq_miss_latency::total 10559308500 # number of ReadCleanReq miss cycles 1320system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46880784000 # number of ReadSharedReq miss cycles 1321system.cpu.l2cache.ReadSharedReq_miss_latency::total 46880784000 # number of ReadSharedReq miss cycles 1322system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 453500 # number of InvalidateReq miss cycles 1323system.cpu.l2cache.InvalidateReq_miss_latency::total 453500 # number of InvalidateReq miss cycles 1324system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1464838500 # number of demand (read+write) miss cycles 1325system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 979350000 # number of demand (read+write) miss cycles 1326system.cpu.l2cache.demand_miss_latency::cpu.inst 10559308500 # number of demand (read+write) miss cycles 1327system.cpu.l2cache.demand_miss_latency::cpu.data 186859149500 # number of demand (read+write) miss cycles 1328system.cpu.l2cache.demand_miss_latency::total 199862646500 # number of demand (read+write) miss cycles 1329system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1464838500 # number of overall miss cycles 1330system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 979350000 # number of overall miss cycles 1331system.cpu.l2cache.overall_miss_latency::cpu.inst 10559308500 # number of overall miss cycles 1332system.cpu.l2cache.overall_miss_latency::cpu.data 186859149500 # number of overall miss cycles 1333system.cpu.l2cache.overall_miss_latency::total 199862646500 # number of overall miss cycles 1334system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1316719 # number of ReadReq accesses(hits+misses) 1335system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 318398 # number of ReadReq accesses(hits+misses) 1336system.cpu.l2cache.ReadReq_accesses::total 1635117 # number of ReadReq accesses(hits+misses) 1337system.cpu.l2cache.WritebackDirty_accesses::writebacks 10417036 # number of WritebackDirty accesses(hits+misses) 1338system.cpu.l2cache.WritebackDirty_accesses::total 10417036 # number of WritebackDirty accesses(hits+misses) 1339system.cpu.l2cache.WritebackClean_accesses::writebacks 16945412 # number of WritebackClean accesses(hits+misses) 1340system.cpu.l2cache.WritebackClean_accesses::total 16945412 # number of WritebackClean accesses(hits+misses) 1341system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43385 # number of UpgradeReq accesses(hits+misses) 1342system.cpu.l2cache.UpgradeReq_accesses::total 43385 # number of UpgradeReq accesses(hits+misses) |
1343system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses) 1344system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) |
1345system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072817 # number of ReadExReq accesses(hits+misses) 1346system.cpu.l2cache.ReadExReq_accesses::total 3072817 # number of ReadExReq accesses(hits+misses) 1347system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16948553 # number of ReadCleanReq accesses(hits+misses) 1348system.cpu.l2cache.ReadCleanReq_accesses::total 16948553 # number of ReadCleanReq accesses(hits+misses) 1349system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9436572 # number of ReadSharedReq accesses(hits+misses) 1350system.cpu.l2cache.ReadSharedReq_accesses::total 9436572 # number of ReadSharedReq accesses(hits+misses) 1351system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1264567 # number of InvalidateReq accesses(hits+misses) 1352system.cpu.l2cache.InvalidateReq_accesses::total 1264567 # number of InvalidateReq accesses(hits+misses) 1353system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1316719 # number of demand (read+write) accesses 1354system.cpu.l2cache.demand_accesses::cpu.itb.walker 318398 # number of demand (read+write) accesses 1355system.cpu.l2cache.demand_accesses::cpu.inst 16948553 # number of demand (read+write) accesses 1356system.cpu.l2cache.demand_accesses::cpu.data 12509389 # number of demand (read+write) accesses 1357system.cpu.l2cache.demand_accesses::total 31093059 # number of demand (read+write) accesses 1358system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1316719 # number of overall (read+write) accesses 1359system.cpu.l2cache.overall_accesses::cpu.itb.walker 318398 # number of overall (read+write) accesses 1360system.cpu.l2cache.overall_accesses::cpu.inst 16948553 # number of overall (read+write) accesses 1361system.cpu.l2cache.overall_accesses::cpu.data 12509389 # number of overall (read+write) accesses 1362system.cpu.l2cache.overall_accesses::total 31093059 # number of overall (read+write) accesses 1363system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008086 # miss rate for ReadReq accesses 1364system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028138 # miss rate for ReadReq accesses 1365system.cpu.l2cache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses 1366system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093189 # miss rate for UpgradeReq accesses 1367system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093189 # miss rate for UpgradeReq accesses |
1368system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 1369system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses |
1370system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435286 # miss rate for ReadExReq accesses 1371system.cpu.l2cache.ReadExReq_miss_rate::total 0.435286 # miss rate for ReadExReq accesses 1372system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005662 # miss rate for ReadCleanReq accesses 1373system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005662 # miss rate for ReadCleanReq accesses 1374system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses 1375system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses 1376system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.468366 # miss rate for InvalidateReq accesses 1377system.cpu.l2cache.InvalidateReq_miss_rate::total 0.468366 # miss rate for InvalidateReq accesses 1378system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008086 # miss rate for demand accesses 1379system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028138 # miss rate for demand accesses 1380system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005662 # miss rate for demand accesses 1381system.cpu.l2cache.demand_miss_rate::cpu.data 0.140212 # miss rate for demand accesses 1382system.cpu.l2cache.demand_miss_rate::total 0.060127 # miss rate for demand accesses 1383system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008086 # miss rate for overall accesses 1384system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028138 # miss rate for overall accesses 1385system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005662 # miss rate for overall accesses 1386system.cpu.l2cache.overall_miss_rate::cpu.data 0.140212 # miss rate for overall accesses 1387system.cpu.l2cache.overall_miss_rate::total 0.060127 # miss rate for overall accesses 1388system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137582.276698 # average ReadReq miss latency 1389system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109314.655654 # average ReadReq miss latency 1390system.cpu.l2cache.ReadReq_avg_miss_latency::total 124665.332041 # average ReadReq miss latency 1391system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18235.592382 # average UpgradeReq miss latency 1392system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18235.592382 # average UpgradeReq miss latency 1393system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency 1394system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency 1395system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104652.574889 # average ReadExReq miss latency 1396system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104652.574889 # average ReadExReq miss latency 1397system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110027.180369 # average ReadCleanReq miss latency 1398system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110027.180369 # average ReadCleanReq miss latency 1399system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112583.232871 # average ReadSharedReq miss latency 1400system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112583.232871 # average ReadSharedReq miss latency 1401system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.765685 # average InvalidateReq miss latency 1402system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.765685 # average InvalidateReq miss latency 1403system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency 1404system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency 1405system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency 1406system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency 1407system.cpu.l2cache.demand_avg_miss_latency::total 106904.775188 # average overall miss latency 1408system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency 1409system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency 1410system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency 1411system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency 1412system.cpu.l2cache.overall_avg_miss_latency::total 106904.775188 # average overall miss latency |
1413system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1414system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1415system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1416system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1417system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1418system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1419system.cpu.l2cache.writebacks::writebacks 2100679 # number of writebacks 1420system.cpu.l2cache.writebacks::total 2100679 # number of writebacks |
1421system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1422system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits |
1423system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits |
1424system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits |
1425system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits |
1426system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits 1427system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10647 # number of ReadReq MSHR misses 1428system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8959 # number of ReadReq MSHR misses 1429system.cpu.l2cache.ReadReq_mshr_misses::total 19606 # number of ReadReq MSHR misses 1430system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 1431system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 1432system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4043 # number of UpgradeReq MSHR misses 1433system.cpu.l2cache.UpgradeReq_mshr_misses::total 4043 # number of UpgradeReq MSHR misses |
1434system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses 1435system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses |
1436system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1337553 # number of ReadExReq MSHR misses 1437system.cpu.l2cache.ReadExReq_mshr_misses::total 1337553 # number of ReadExReq MSHR misses 1438system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95970 # number of ReadCleanReq MSHR misses 1439system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95970 # number of ReadCleanReq MSHR misses 1440system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 416389 # number of ReadSharedReq MSHR misses 1441system.cpu.l2cache.ReadSharedReq_mshr_misses::total 416389 # number of ReadSharedReq MSHR misses 1442system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 592280 # number of InvalidateReq MSHR misses 1443system.cpu.l2cache.InvalidateReq_mshr_misses::total 592280 # number of InvalidateReq MSHR misses 1444system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10647 # number of demand (read+write) MSHR misses 1445system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8959 # number of demand (read+write) MSHR misses 1446system.cpu.l2cache.demand_mshr_misses::cpu.inst 95970 # number of demand (read+write) MSHR misses 1447system.cpu.l2cache.demand_mshr_misses::cpu.data 1753942 # number of demand (read+write) MSHR misses 1448system.cpu.l2cache.demand_mshr_misses::total 1869518 # number of demand (read+write) MSHR misses 1449system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10647 # number of overall MSHR misses 1450system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8959 # number of overall MSHR misses 1451system.cpu.l2cache.overall_mshr_misses::cpu.inst 95970 # number of overall MSHR misses 1452system.cpu.l2cache.overall_mshr_misses::cpu.data 1753942 # number of overall MSHR misses 1453system.cpu.l2cache.overall_mshr_misses::total 1869518 # number of overall MSHR misses |
1454system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 1455system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable 1456system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable 1457system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable 1458system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable 1459system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 1460system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses 1461system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses |
1462system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of ReadReq MSHR miss cycles 1463system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 889760000 # number of ReadReq MSHR miss cycles 1464system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2248128500 # number of ReadReq MSHR miss cycles 1465system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77144500 # number of UpgradeReq MSHR miss cycles 1466system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77144500 # number of UpgradeReq MSHR miss cycles 1467system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles 1468system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles 1469system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126602809555 # number of ReadExReq MSHR miss cycles 1470system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126602809555 # number of ReadExReq MSHR miss cycles 1471system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9599588543 # number of ReadCleanReq MSHR miss cycles 1472system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9599588543 # number of ReadCleanReq MSHR miss cycles 1473system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42714761570 # number of ReadSharedReq MSHR miss cycles 1474system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42714761570 # number of ReadSharedReq MSHR miss cycles 1475system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12256085002 # number of InvalidateReq MSHR miss cycles 1476system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12256085002 # number of InvalidateReq MSHR miss cycles 1477system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of demand (read+write) MSHR miss cycles 1478system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 889760000 # number of demand (read+write) MSHR miss cycles 1479system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9599588543 # number of demand (read+write) MSHR miss cycles 1480system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169317571125 # number of demand (read+write) MSHR miss cycles 1481system.cpu.l2cache.demand_mshr_miss_latency::total 181165288168 # number of demand (read+write) MSHR miss cycles 1482system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of overall MSHR miss cycles 1483system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 889760000 # number of overall MSHR miss cycles 1484system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9599588543 # number of overall MSHR miss cycles 1485system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169317571125 # number of overall MSHR miss cycles 1486system.cpu.l2cache.overall_mshr_miss_latency::total 181165288168 # number of overall MSHR miss cycles |
1487system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles |
1488system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804371500 # number of ReadReq MSHR uncacheable cycles 1489system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290859000 # number of ReadReq MSHR uncacheable cycles |
1490system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles |
1491system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804371500 # number of overall MSHR uncacheable cycles 1492system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290859000 # number of overall MSHR uncacheable cycles 1493system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for ReadReq accesses 1494system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for ReadReq accesses 1495system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011991 # mshr miss rate for ReadReq accesses |
1496system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1497system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
1498system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093189 # mshr miss rate for UpgradeReq accesses 1499system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093189 # mshr miss rate for UpgradeReq accesses |
1500system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1501system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses |
1502system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435286 # mshr miss rate for ReadExReq accesses 1503system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435286 # mshr miss rate for ReadExReq accesses 1504system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for ReadCleanReq accesses 1505system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005662 # mshr miss rate for ReadCleanReq accesses 1506system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044125 # mshr miss rate for ReadSharedReq accesses 1507system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044125 # mshr miss rate for ReadSharedReq accesses 1508system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.468366 # mshr miss rate for InvalidateReq accesses 1509system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.468366 # mshr miss rate for InvalidateReq accesses 1510system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for demand accesses 1511system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for demand accesses 1512system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for demand accesses 1513system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for demand accesses 1514system.cpu.l2cache.demand_mshr_miss_rate::total 0.060127 # mshr miss rate for demand accesses 1515system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for overall accesses 1516system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for overall accesses 1517system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for overall accesses 1518system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for overall accesses 1519system.cpu.l2cache.overall_mshr_miss_rate::total 0.060127 # mshr miss rate for overall accesses 1520system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average ReadReq mshr miss latency 1521system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average ReadReq mshr miss latency 1522system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 114665.332041 # average ReadReq mshr miss latency 1523system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19081.004205 # average UpgradeReq mshr miss latency 1524system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19081.004205 # average UpgradeReq mshr miss latency 1525system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency 1526system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency 1527system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94652.555491 # average ReadExReq mshr miss latency 1528system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94652.555491 # average ReadExReq mshr miss latency 1529system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100026.972418 # average ReadCleanReq mshr miss latency 1530system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100026.972418 # average ReadCleanReq mshr miss latency 1531system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102583.789605 # average ReadSharedReq mshr miss latency 1532system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102583.789605 # average ReadSharedReq mshr miss latency 1533system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20693.059030 # average InvalidateReq mshr miss latency 1534system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20693.059030 # average InvalidateReq mshr miss latency 1535system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency 1536system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency 1537system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency 1538system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency 1539system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency 1540system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency 1541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency 1542system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency 1543system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency 1544system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency |
1545system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency |
1546system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.439748 # average ReadReq mshr uncacheable latency 1547system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.824137 # average ReadReq mshr uncacheable latency |
1548system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency |
1549system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.660583 # average overall mshr uncacheable latency 1550system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.026802 # average overall mshr uncacheable latency 1551system.cpu.toL2Bus.snoop_filter.tot_requests 62411777 # Total number of requests made to the snoop filter. 1552system.cpu.toL2Bus.snoop_filter.hit_single_requests 31689071 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1553system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1554system.cpu.toL2Bus.snoop_filter.tot_snoops 2067 # Total number of snoops made to the snoop filter. 1555system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2067 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
1556system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
1557system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1558system.cpu.toL2Bus.trans_dist::ReadReq 2264077 # Transaction distribution 1559system.cpu.toL2Bus.trans_dist::ReadResp 28650207 # Transaction distribution |
1560system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution 1561system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution |
1562system.cpu.toL2Bus.trans_dist::WritebackDirty 12517715 # Transaction distribution 1563system.cpu.toL2Bus.trans_dist::WritebackClean 16948036 # Transaction distribution 1564system.cpu.toL2Bus.trans_dist::CleanEvict 3623971 # Transaction distribution 1565system.cpu.toL2Bus.trans_dist::UpgradeReq 43388 # Transaction distribution |
1566system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution |
1567system.cpu.toL2Bus.trans_dist::UpgradeResp 43396 # Transaction distribution 1568system.cpu.toL2Bus.trans_dist::ReadExReq 3072817 # Transaction distribution 1569system.cpu.toL2Bus.trans_dist::ReadExResp 3072817 # Transaction distribution 1570system.cpu.toL2Bus.trans_dist::ReadCleanReq 16948772 # Transaction distribution 1571system.cpu.toL2Bus.trans_dist::ReadSharedReq 9438927 # Transaction distribution 1572system.cpu.toL2Bus.trans_dist::InvalidateReq 1295442 # Transaction distribution 1573system.cpu.toL2Bus.trans_dist::InvalidateResp 1264567 # Transaction distribution 1574system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50887949 # Packet count per connected master and slave (bytes) 1575system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41543699 # Packet count per connected master and slave (bytes) 1576system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 787064 # Packet count per connected master and slave (bytes) 1577system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3057144 # Packet count per connected master and slave (bytes) 1578system.cpu.toL2Bus.pkt_count::total 96275856 # Packet count per connected master and slave (bytes) 1579system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169722400 # Cumulative packet size per connected master and slave (bytes) 1580system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467531890 # Cumulative packet size per connected master and slave (bytes) 1581system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2547184 # Cumulative packet size per connected master and slave (bytes) 1582system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10533752 # Cumulative packet size per connected master and slave (bytes) 1583system.cpu.toL2Bus.pkt_size::total 3650335226 # Cumulative packet size per connected master and slave (bytes) 1584system.cpu.toL2Bus.snoops 2976479 # Total snoops (count) 1585system.cpu.toL2Bus.snoopTraffic 139099568 # Total snoop traffic (bytes) 1586system.cpu.toL2Bus.snoop_fanout::samples 35465406 # Request fanout histogram 1587system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram 1588system.cpu.toL2Bus.snoop_fanout::stdev 0.159793 # Request fanout histogram |
1589system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
1590system.cpu.toL2Bus.snoop_fanout::0 34535454 97.38% 97.38% # Request fanout histogram 1591system.cpu.toL2Bus.snoop_fanout::1 929952 2.62% 100.00% # Request fanout histogram |
1592system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1593system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1594system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1595system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
1596system.cpu.toL2Bus.snoop_fanout::total 35465406 # Request fanout histogram 1597system.cpu.toL2Bus.reqLayer0.occupancy 59274617984 # Layer occupancy (ticks) |
1598system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
1599system.cpu.toL2Bus.snoopLayer0.occupancy 1490379 # Layer occupancy (ticks) |
1600system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
1601system.cpu.toL2Bus.respLayer0.occupancy 25454807175 # Layer occupancy (ticks) |
1602system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
1603system.cpu.toL2Bus.respLayer1.occupancy 19473878402 # Layer occupancy (ticks) |
1604system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
1605system.cpu.toL2Bus.respLayer2.occupancy 469039231 # Layer occupancy (ticks) |
1606system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
1607system.cpu.toL2Bus.respLayer3.occupancy 1741050209 # Layer occupancy (ticks) |
1608system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
1609system.iobus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1610system.iobus.trans_dist::ReadReq 40296 # Transaction distribution 1611system.iobus.trans_dist::ReadResp 40296 # Transaction distribution |
1612system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1613system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1614system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1615system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1616system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1617system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1618system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1619system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1620system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1621system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1622system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1623system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1624system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1625system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1626system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1627system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) |
1628system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) 1629system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) |
1630system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1631system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
1632system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) |
1633system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1634system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1635system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1636system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1637system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1638system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1639system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1640system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1641system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1642system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1643system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1644system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1645system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1646system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) |
1647system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) 1648system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) |
1649system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1650system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
1651system.iobus.pkt_size::total 7492152 # Cumulative packet size per connected master and slave (bytes) 1652system.iobus.reqLayer0.occupancy 41892500 # Layer occupancy (ticks) |
1653system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1654system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1655system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1656system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks) 1657system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1658system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 1659system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1660system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1666system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1667system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1668system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1669system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1670system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) 1671system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1672system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1673system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
1674system.iobus.reqLayer23.occupancy 25201500 # Layer occupancy (ticks) |
1675system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
1676system.iobus.reqLayer24.occupancy 36497000 # Layer occupancy (ticks) |
1677system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
1678system.iobus.reqLayer25.occupancy 569294464 # Layer occupancy (ticks) |
1679system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1680system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1681system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
1682system.iobus.respLayer3.occupancy 147710000 # Layer occupancy (ticks) |
1683system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1684system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1685system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
1686system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1687system.iocache.tags.replacements 115456 # number of replacements 1688system.iocache.tags.tagsinuse 10.450363 # Cycle average of tags in use |
1689system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
1690system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. |
1691system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1692system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit. |
1693system.iocache.tags.occ_blocks::realview.ethernet 3.528284 # Average occupied blocks per requestor 1694system.iocache.tags.occ_blocks::realview.ide 6.922079 # Average occupied blocks per requestor 1695system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy 1696system.iocache.tags.occ_percent::realview.ide 0.432630 # Average percentage of cache occupancy 1697system.iocache.tags.occ_percent::total 0.653148 # Average percentage of cache occupancy |
1698system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1699system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1700system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
1701system.iocache.tags.tag_accesses 1039632 # Number of tag accesses 1702system.iocache.tags.data_accesses 1039632 # Number of data accesses 1703system.iocache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
1704system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
1705system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses 1706system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses |
1707system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1708system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1709system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1710system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1711system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
1712system.iocache.demand_misses::realview.ide 115475 # number of demand (read+write) misses 1713system.iocache.demand_misses::total 115515 # number of demand (read+write) misses |
1714system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
1715system.iocache.overall_misses::realview.ide 115475 # number of overall misses 1716system.iocache.overall_misses::total 115515 # number of overall misses |
1717system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles |
1718system.iocache.ReadReq_miss_latency::realview.ide 1862993006 # number of ReadReq miss cycles 1719system.iocache.ReadReq_miss_latency::total 1868078506 # number of ReadReq miss cycles |
1720system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1721system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles |
1722system.iocache.WriteLineReq_miss_latency::realview.ide 13281113958 # number of WriteLineReq miss cycles 1723system.iocache.WriteLineReq_miss_latency::total 13281113958 # number of WriteLineReq miss cycles |
1724system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles |
1725system.iocache.demand_miss_latency::realview.ide 15144106964 # number of demand (read+write) miss cycles 1726system.iocache.demand_miss_latency::total 15149543464 # number of demand (read+write) miss cycles |
1727system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles |
1728system.iocache.overall_miss_latency::realview.ide 15144106964 # number of overall miss cycles 1729system.iocache.overall_miss_latency::total 15149543464 # number of overall miss cycles |
1730system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
1731system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) 1732system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) |
1733system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1734system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1735system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1736system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1737system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
1738system.iocache.demand_accesses::realview.ide 115475 # number of demand (read+write) accesses 1739system.iocache.demand_accesses::total 115515 # number of demand (read+write) accesses |
1740system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
1741system.iocache.overall_accesses::realview.ide 115475 # number of overall (read+write) accesses 1742system.iocache.overall_accesses::total 115515 # number of overall (read+write) accesses |
1743system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1744system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1745system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1746system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1747system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1748system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1749system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1750system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1751system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1752system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1753system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1754system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1755system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1756system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency |
1757system.iocache.ReadReq_avg_miss_latency::realview.ide 211439.451368 # average ReadReq miss latency 1758system.iocache.ReadReq_avg_miss_latency::total 211130.030063 # average ReadReq miss latency |
1759system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1760system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency |
1761system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124513.556195 # average WriteLineReq miss latency 1762system.iocache.WriteLineReq_avg_miss_latency::total 124513.556195 # average WriteLineReq miss latency |
1763system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency |
1764system.iocache.demand_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency 1765system.iocache.demand_avg_miss_latency::total 131147.846288 # average overall miss latency |
1766system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency |
1767system.iocache.overall_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency 1768system.iocache.overall_avg_miss_latency::total 131147.846288 # average overall miss latency 1769system.iocache.blocked_cycles::no_mshrs 44063 # number of cycles access was blocked |
1770system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
1771system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked |
1772system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
1773system.iocache.avg_blocked_cycles::no_mshrs 12.567884 # average number of cycles each access was blocked |
1774system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1775system.iocache.writebacks::writebacks 106630 # number of writebacks 1776system.iocache.writebacks::total 106630 # number of writebacks 1777system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
1778system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses 1779system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses |
1780system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1781system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1782system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1783system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1784system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
1785system.iocache.demand_mshr_misses::realview.ide 115475 # number of demand (read+write) MSHR misses 1786system.iocache.demand_mshr_misses::total 115515 # number of demand (read+write) MSHR misses |
1787system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
1788system.iocache.overall_mshr_misses::realview.ide 115475 # number of overall MSHR misses 1789system.iocache.overall_mshr_misses::total 115515 # number of overall MSHR misses |
1790system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles |
1791system.iocache.ReadReq_mshr_miss_latency::realview.ide 1422443006 # number of ReadReq MSHR miss cycles 1792system.iocache.ReadReq_mshr_miss_latency::total 1425678506 # number of ReadReq MSHR miss cycles |
1793system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1794system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles |
1795system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7941073224 # number of WriteLineReq MSHR miss cycles 1796system.iocache.WriteLineReq_mshr_miss_latency::total 7941073224 # number of WriteLineReq MSHR miss cycles |
1797system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles |
1798system.iocache.demand_mshr_miss_latency::realview.ide 9363516230 # number of demand (read+write) MSHR miss cycles 1799system.iocache.demand_mshr_miss_latency::total 9366952730 # number of demand (read+write) MSHR miss cycles |
1800system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles |
1801system.iocache.overall_mshr_miss_latency::realview.ide 9363516230 # number of overall MSHR miss cycles 1802system.iocache.overall_mshr_miss_latency::total 9366952730 # number of overall MSHR miss cycles |
1803system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1804system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1805system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1806system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1807system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1808system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1809system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1810system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1811system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1812system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1813system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1814system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1815system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1816system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency |
1817system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 161439.451368 # average ReadReq mshr miss latency 1818system.iocache.ReadReq_avg_mshr_miss_latency::total 161130.030063 # average ReadReq mshr miss latency |
1819system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1820system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency |
1821system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74449.422711 # average WriteLineReq mshr miss latency 1822system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74449.422711 # average WriteLineReq mshr miss latency |
1823system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency |
1824system.iocache.demand_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency 1825system.iocache.demand_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency |
1826system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency |
1827system.iocache.overall_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency 1828system.iocache.overall_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency 1829system.membus.snoop_filter.tot_requests 5064341 # Total number of requests made to the snoop filter. 1830system.membus.snoop_filter.hit_single_requests 2518493 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1831system.membus.snoop_filter.hit_multi_requests 2998 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
1832system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1833system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1834system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
1835system.membus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
1836system.membus.trans_dist::ReadReq 54986 # Transaction distribution |
1837system.membus.trans_dist::ReadResp 595799 # Transaction distribution |
1838system.membus.trans_dist::WriteReq 33703 # Transaction distribution 1839system.membus.trans_dist::WriteResp 33703 # Transaction distribution |
1840system.membus.trans_dist::WritebackDirty 2207309 # Transaction distribution 1841system.membus.trans_dist::CleanEvict 275154 # Transaction distribution 1842system.membus.trans_dist::UpgradeReq 4609 # Transaction distribution |
1843system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution 1844system.membus.trans_dist::UpgradeResp 8 # Transaction distribution |
1845system.membus.trans_dist::ReadExReq 1336997 # Transaction distribution 1846system.membus.trans_dist::ReadExResp 1336997 # Transaction distribution 1847system.membus.trans_dist::ReadSharedReq 540813 # Transaction distribution 1848system.membus.trans_dist::InvalidateReq 698937 # Transaction distribution |
1849system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1850system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1851system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) |
1852system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6748871 # Packet count per connected master and slave (bytes) 1853system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6878533 # Packet count per connected master and slave (bytes) 1854system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237677 # Packet count per connected master and slave (bytes) 1855system.membus.pkt_count_system.iocache.mem_side::total 237677 # Packet count per connected master and slave (bytes) 1856system.membus.pkt_count::total 7116210 # Packet count per connected master and slave (bytes) |
1857system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1858system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) 1859system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) |
1860system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254375884 # Cumulative packet size per connected master and slave (bytes) 1861system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254545938 # Cumulative packet size per connected master and slave (bytes) 1862system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253504 # Cumulative packet size per connected master and slave (bytes) 1863system.membus.pkt_size_system.iocache.mem_side::total 7253504 # Cumulative packet size per connected master and slave (bytes) 1864system.membus.pkt_size::total 261799442 # Cumulative packet size per connected master and slave (bytes) 1865system.membus.snoops 2809 # Total snoops (count) 1866system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) 1867system.membus.snoop_fanout::samples 2670049 # Request fanout histogram 1868system.membus.snoop_fanout::mean 0.012702 # Request fanout histogram 1869system.membus.snoop_fanout::stdev 0.111987 # Request fanout histogram |
1870system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
1871system.membus.snoop_fanout::0 2636133 98.73% 98.73% # Request fanout histogram 1872system.membus.snoop_fanout::1 33916 1.27% 100.00% # Request fanout histogram |
1873system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1874system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1875system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1876system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
1877system.membus.snoop_fanout::total 2670049 # Request fanout histogram 1878system.membus.reqLayer0.occupancy 104027000 # Layer occupancy (ticks) |
1879system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1880system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) 1881system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
1882system.membus.reqLayer2.occupancy 5600000 # Layer occupancy (ticks) |
1883system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
1884system.membus.reqLayer5.occupancy 14297533259 # Layer occupancy (ticks) |
1885system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
1886system.membus.respLayer2.occupancy 10011316944 # Layer occupancy (ticks) |
1887system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
1888system.membus.respLayer3.occupancy 44794763 # Layer occupancy (ticks) |
1889system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
1890system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1891system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1892system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1893system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1894system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1895system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1896system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
1897system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1898system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1899system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1900system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1901system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1902system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
1903system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1904system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
1905system.realview.ethernet.txBytes 966 # Bytes Transmitted 1906system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1907system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1908system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1909system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1910system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1911system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1912system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 1939system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1940system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1941system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1942system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1943system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1944system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1945system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1946system.realview.ethernet.droppedPackets 0 # number of packets dropped |
1947system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1948system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1949system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1950system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1951system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1952system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1953system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
1954system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1955system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1956system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1957system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
1958system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1959system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1960system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1961system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1962system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1963system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1964system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1965system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1966system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1967system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1968system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states 1969system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states |
1970system.cpu.kern.inst.arm 0 # number of arm instructions executed |
1971system.cpu.kern.inst.quiesce 17165 # number of quiesce instructions executed |
1972 1973---------- End Simulation Statistics ---------- |