4,5c4,5
< sim_ticks 51558690384000 # Number of ticks simulated
< final_tick 51558690384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 51558689626000 # Number of ticks simulated
> final_tick 51558689626000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 207581 # Simulator instruction rate (inst/s)
< host_op_rate 243983 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9602431196 # Simulator tick rate (ticks/s)
< host_mem_usage 695472 # Number of bytes of host memory used
< host_seconds 5369.34 # Real time elapsed on the host
< sim_insts 1114574366 # Number of instructions simulated
< sim_ops 1310024478 # Number of ops (including micro ops) simulated
---
> host_inst_rate 210245 # Simulator instruction rate (inst/s)
> host_op_rate 247121 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9737217389 # Simulator tick rate (ticks/s)
> host_mem_usage 695392 # Number of bytes of host memory used
> host_seconds 5295.01 # Real time elapsed on the host
> sim_insts 1113248331 # Number of instructions simulated
> sim_ops 1308509399 # Number of ops (including micro ops) simulated
16,25c16,25
< system.physmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 681408 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 573376 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 6481504 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 112175560 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 429184 # Number of bytes read from this memory
< system.physmem.bytes_read::total 120341032 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 6481504 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 6481504 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 141267776 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 688064 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 572736 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 6466080 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 114242184 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 427328 # Number of bytes read from this memory
> system.physmem.bytes_read::total 122396392 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 6466080 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6466080 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 142998784 # Number of bytes written to this memory
27,34c27,34
< system.physmem.bytes_written::total 141288356 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 10647 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 8959 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 117226 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1752756 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6706 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1896294 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 2207309 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 143019364 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 10751 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 8949 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 116985 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1785047 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6677 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1928409 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 2234356 # Number of write requests responded to by this memory
36,45c36,45
< system.physmem.num_writes::total 2209882 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 13216 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 11121 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 125711 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2175687 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8324 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2334059 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 125711 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 125711 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2739941 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 2236929 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 13345 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 11108 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 125412 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2215770 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8288 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2373924 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 125412 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 125412 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2773515 # Write bandwidth from this memory (bytes/s)
47,65c47,65
< system.physmem.bw_write::total 2740340 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2739941 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 13216 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 11121 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 125711 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2176086 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8324 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 5074399 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1896294 # Number of read requests accepted
< system.physmem.writeReqs 2209882 # Number of write requests accepted
< system.physmem.readBursts 1896294 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 2209882 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 121325696 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue
< system.physmem.bytesWritten 141284736 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 120341032 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 141288356 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 2773914 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2773515 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 13345 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 11108 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 125412 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2216169 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8288 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5147838 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1928410 # Number of read requests accepted
> system.physmem.writeReqs 2236929 # Number of write requests accepted
> system.physmem.readBursts 1928410 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 2236929 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 123382976 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 35200 # Total number of bytes read from write queue
> system.physmem.bytesWritten 143016896 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 122396456 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 143019364 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 550 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one
67,98c67,98
< system.physmem.perBankRdBursts::0 112674 # Per bank write bursts
< system.physmem.perBankRdBursts::1 120331 # Per bank write bursts
< system.physmem.perBankRdBursts::2 120633 # Per bank write bursts
< system.physmem.perBankRdBursts::3 114638 # Per bank write bursts
< system.physmem.perBankRdBursts::4 113111 # Per bank write bursts
< system.physmem.perBankRdBursts::5 123581 # Per bank write bursts
< system.physmem.perBankRdBursts::6 115477 # Per bank write bursts
< system.physmem.perBankRdBursts::7 120263 # Per bank write bursts
< system.physmem.perBankRdBursts::8 112291 # Per bank write bursts
< system.physmem.perBankRdBursts::9 145720 # Per bank write bursts
< system.physmem.perBankRdBursts::10 114582 # Per bank write bursts
< system.physmem.perBankRdBursts::11 120005 # Per bank write bursts
< system.physmem.perBankRdBursts::12 112695 # Per bank write bursts
< system.physmem.perBankRdBursts::13 118645 # Per bank write bursts
< system.physmem.perBankRdBursts::14 113317 # Per bank write bursts
< system.physmem.perBankRdBursts::15 117751 # Per bank write bursts
< system.physmem.perBankWrBursts::0 133340 # Per bank write bursts
< system.physmem.perBankWrBursts::1 139177 # Per bank write bursts
< system.physmem.perBankWrBursts::2 138321 # Per bank write bursts
< system.physmem.perBankWrBursts::3 137224 # Per bank write bursts
< system.physmem.perBankWrBursts::4 136590 # Per bank write bursts
< system.physmem.perBankWrBursts::5 143143 # Per bank write bursts
< system.physmem.perBankWrBursts::6 136203 # Per bank write bursts
< system.physmem.perBankWrBursts::7 139934 # Per bank write bursts
< system.physmem.perBankWrBursts::8 134977 # Per bank write bursts
< system.physmem.perBankWrBursts::9 143618 # Per bank write bursts
< system.physmem.perBankWrBursts::10 135619 # Per bank write bursts
< system.physmem.perBankWrBursts::11 140132 # Per bank write bursts
< system.physmem.perBankWrBursts::12 134815 # Per bank write bursts
< system.physmem.perBankWrBursts::13 138770 # Per bank write bursts
< system.physmem.perBankWrBursts::14 136807 # Per bank write bursts
< system.physmem.perBankWrBursts::15 138904 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 114164 # Per bank write bursts
> system.physmem.perBankRdBursts::1 120325 # Per bank write bursts
> system.physmem.perBankRdBursts::2 121021 # Per bank write bursts
> system.physmem.perBankRdBursts::3 117289 # Per bank write bursts
> system.physmem.perBankRdBursts::4 115474 # Per bank write bursts
> system.physmem.perBankRdBursts::5 125294 # Per bank write bursts
> system.physmem.perBankRdBursts::6 117554 # Per bank write bursts
> system.physmem.perBankRdBursts::7 120469 # Per bank write bursts
> system.physmem.perBankRdBursts::8 115697 # Per bank write bursts
> system.physmem.perBankRdBursts::9 146662 # Per bank write bursts
> system.physmem.perBankRdBursts::10 119160 # Per bank write bursts
> system.physmem.perBankRdBursts::11 123181 # Per bank write bursts
> system.physmem.perBankRdBursts::12 118002 # Per bank write bursts
> system.physmem.perBankRdBursts::13 121360 # Per bank write bursts
> system.physmem.perBankRdBursts::14 114093 # Per bank write bursts
> system.physmem.perBankRdBursts::15 118114 # Per bank write bursts
> system.physmem.perBankWrBursts::0 133629 # Per bank write bursts
> system.physmem.perBankWrBursts::1 139072 # Per bank write bursts
> system.physmem.perBankWrBursts::2 140295 # Per bank write bursts
> system.physmem.perBankWrBursts::3 139312 # Per bank write bursts
> system.physmem.perBankWrBursts::4 138711 # Per bank write bursts
> system.physmem.perBankWrBursts::5 145043 # Per bank write bursts
> system.physmem.perBankWrBursts::6 137653 # Per bank write bursts
> system.physmem.perBankWrBursts::7 140751 # Per bank write bursts
> system.physmem.perBankWrBursts::8 137271 # Per bank write bursts
> system.physmem.perBankWrBursts::9 144471 # Per bank write bursts
> system.physmem.perBankWrBursts::10 139139 # Per bank write bursts
> system.physmem.perBankWrBursts::11 142751 # Per bank write bursts
> system.physmem.perBankWrBursts::12 139024 # Per bank write bursts
> system.physmem.perBankWrBursts::13 141466 # Per bank write bursts
> system.physmem.perBankWrBursts::14 137078 # Per bank write bursts
> system.physmem.perBankWrBursts::15 138973 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 518 # Number of times write queue was full causing retry
< system.physmem.totGap 51558689064500 # Total gap between requests
---
> system.physmem.numWrRetry 512 # Number of times write queue was full causing retry
> system.physmem.totGap 51558688241500 # Total gap between requests
108c108
< system.physmem.readPktSize::6 1875009 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1907125 # Read request sizes (log2)
115,137c115,137
< system.physmem.writePktSize::6 2207309 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1116053 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 690517 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 59727 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 23803 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 610 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 601 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 516 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1044 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 687 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 311 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 237 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 2234356 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1137157 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 697006 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 62243 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 25848 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 659 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 474 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 617 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 529 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 986 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 614 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 299 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 219 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 172 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 146 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
163,185c163,185
< system.physmem.wrQLenPdf::15 28211 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 35428 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 83457 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 116558 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 125148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 129368 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 131713 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 136998 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 138946 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 135798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 138971 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 141020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 132458 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 131167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 132874 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 144896 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 126854 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 129875 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 5862 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 4328 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 3576 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 3183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2815 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 28528 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 36181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 84750 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 118181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 127464 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 131678 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 133520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 138083 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 140930 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 136900 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 140021 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 142369 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 134210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 132730 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 134518 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 146577 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 128734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 131799 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 5920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 4225 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 3385 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2939 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2825 # What write queue length does an incoming req see
187,230c187,230
< system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2421 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 2341 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 2185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 2246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 2284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1940 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1877 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1876 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1719 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1742 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1766 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1651 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1663 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 1721 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 1785 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 1763 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 1973 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 1272 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 1576 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 2263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1461 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 706 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 1209 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 930002 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 282.376133 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 167.748609 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 309.895017 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 369309 39.71% 39.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 231862 24.93% 64.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 88277 9.49% 74.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 51814 5.57% 79.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 37452 4.03% 83.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 26213 2.82% 86.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 21092 2.27% 88.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 17823 1.92% 90.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 86160 9.26% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 930002 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 116289 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 16.301748 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 52.348914 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 116283 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::39 2591 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2354 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 2282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2240 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2238 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 2279 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1968 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1976 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1926 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1784 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 2020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1898 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 1774 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 1771 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 1642 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 1664 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 1959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 1560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 1314 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 1520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 1794 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1483 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 726 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1159 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 946985 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 281.313381 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 167.848752 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 307.664857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 373897 39.48% 39.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 237629 25.09% 64.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 90926 9.60% 74.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 53224 5.62% 79.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 39122 4.13% 83.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 27360 2.89% 86.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 21677 2.29% 89.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 17745 1.87% 90.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 85405 9.02% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 946985 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 117910 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 16.350064 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 51.964300 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 117905 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
234,266c234,283
< system.physmem.rdPerTurnAround::total 116289 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 116288 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18.983653 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.436820 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 18.158845 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::0-31 112077 96.38% 96.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-63 1857 1.60% 97.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-95 1248 1.07% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-127 622 0.53% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-159 199 0.17% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-191 102 0.09% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 116288 # Writes before turning the bus around for reads
< system.physmem.totQLat 70130172482 # Total ticks spent queuing
< system.physmem.totMemAccLat 105674809982 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 9478570000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 36994.07 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 117910 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 117910 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.952074 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.420057 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 17.842093 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 113720 96.45% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 1383 1.17% 97.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 426 0.36% 97.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 819 0.69% 98.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 466 0.40% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 257 0.22% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 350 0.30% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 159 0.13% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 44 0.04% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 53 0.04% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 45 0.04% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 26 0.02% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 14 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 12 0.01% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 23 0.02% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 25 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 22 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 13 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 4 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 3 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 7 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 3 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::624-639 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::640-655 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::752-767 3 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 117910 # Writes before turning the bus around for reads
> system.physmem.totQLat 71195410655 # Total ticks spent queuing
> system.physmem.totMemAccLat 107342766905 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 9639295000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 36929.76 # Average queueing delay per DRAM burst
268,272c285,289
< system.physmem.avgMemAccLat 55744.07 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.74 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.33 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 55679.75 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.39 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.77 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s
277,323c294,340
< system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.06 # Average write queue length when enqueuing
< system.physmem.readRowHits 1529656 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1643629 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.45 # Row buffer hit rate for writes
< system.physmem.avgGap 12556375.83 # Average gap between requests
< system.physmem.pageHitRate 77.33 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3321699360 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1765517490 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6716655120 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5762509380 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 51680160480.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 50972480280 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 3129835680 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 101675150490 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 76210464000 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 12252798333465 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 12554072367525 # Total energy per rank (pJ)
< system.physmem_0.averagePower 243.490909 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 51438669732358 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 5228340749 # Time in different power states
< system.physmem_0.memoryStateTime::REF 21959504000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 51017233392500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 198464631937 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 92832806893 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 222971707921 # Time in different power states
< system.physmem_1.actEnergy 3318507780 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1763828715 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6818742840 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 5761011240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 51892211280.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 51236173110 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3081583200 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 102800614920 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 76208995200 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 12252080918985 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 12555002532930 # Total energy per rank (pJ)
< system.physmem_1.averagePower 243.508949 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 51438215485769 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 5081473992 # Time in different power states
< system.physmem_1.memoryStateTime::REF 22049198000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 51014315527500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 198460418659 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 93344226239 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 225439539610 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing
> system.physmem.readRowHits 1556076 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1659436 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.72 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.26 # Row buffer hit rate for writes
> system.physmem.avgGap 12378029.31 # Average gap between requests
> system.physmem.pageHitRate 77.25 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3355628640 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1783558920 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6794352600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 5817512520 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 51361776960.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 51335807970 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 3128372160 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 100703099850 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 75728818080 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 12253311191655 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 12553360719255 # Total energy per rank (pJ)
> system.physmem_0.averagePower 243.477109 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 51437874182990 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 5229192000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 21823720000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 51019823371500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 197210375905 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 93762531010 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 220840435585 # Time in different power states
> system.physmem_1.actEnergy 3405851400 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1810249155 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 6970560660 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5847303060 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 52613798640.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 52063882650 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3186128160 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 104825729160 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 76862967360 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 12250174362465 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 12557802494490 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.563259 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 51436124881809 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 5313449750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 22355242000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 51006079595250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 200164062707 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 94896006191 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 229881270102 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
340,342c357,359
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
349,353c366,370
< system.cpu.branchPred.lookups 292068322 # Number of BP lookups
< system.cpu.branchPred.condPredicted 199851600 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 13713135 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 209724607 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 131462172 # Number of BTB hits
---
> system.cpu.branchPred.lookups 291746368 # Number of BP lookups
> system.cpu.branchPred.condPredicted 199670043 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 13704274 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 209695065 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 131330914 # Number of BTB hits
355,361c372,378
< system.cpu.branchPred.BTBHitPct 62.683237 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 37751449 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 403092 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 8173057 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 6085508 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 2087549 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 802881 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 62.629473 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 37689025 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 403296 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 8150983 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 6071547 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 2079436 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 799941 # Number of mispredicted indirect branches.
363c380
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
393,412c410,429
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 1435892 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 1435892 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31985 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277981 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 675717 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 760175 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 2830.191074 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 21829.241774 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-65535 752984 99.05% 99.05% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::65536-131071 4669 0.61% 99.67% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::131072-196607 1022 0.13% 99.80% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::196608-262143 473 0.06% 99.86% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::262144-327679 342 0.04% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.00% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::393216-458751 237 0.03% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::458752-524287 34 0.00% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::524288-589823 14 0.00% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::589824-655359 355 0.05% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::655360-720895 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 1432753 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 1432753 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31582 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277767 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 672727 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 760026 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 2835.541153 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 21869.031891 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-65535 752912 99.06% 99.06% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::65536-131071 4648 0.61% 99.68% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::131072-196607 979 0.13% 99.80% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::196608-262143 465 0.06% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::262144-327679 329 0.04% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.00% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::393216-458751 227 0.03% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::458752-524287 31 0.00% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::524288-589823 15 0.00% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::589824-655359 373 0.05% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::655360-720895 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency
414,427c431,444
< system.cpu.dtb.walker.walkWaitTime::786432-851967 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 760175 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 806276 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 26170.477603 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 21293.851875 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 20136.943306 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 787717 97.70% 97.70% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 14855 1.84% 99.54% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 1801 0.22% 99.76% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 1099 0.14% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 441 0.05% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 139 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 81 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 59 0.01% 99.99% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 760026 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 802864 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 26261.811465 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 21447.525498 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 20174.954942 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 783898 97.64% 97.64% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 15255 1.90% 99.54% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 1830 0.23% 99.77% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 1111 0.14% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 417 0.05% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 138 0.02% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 67 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 44 0.01% 99.99% # Table walker service (enqueue to completion) latency
429,449c446,468
< system.cpu.dtb.walker.walkCompletionTime::589824-655359 68 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 806276 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 1071348818020 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.742300 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.520529 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 1067163432520 99.61% 99.61% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 2639718000 0.25% 99.86% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 767294500 0.07% 99.93% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 303032500 0.03% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 205205000 0.02% 99.97% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 125461000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 48256000 0.00% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 92861500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::16-17 3532500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::18-19 24500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 1071348818020 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 277982 89.68% 89.68% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 31985 10.32% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 309967 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1435892 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 88 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 802864 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 1071344974520 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.740930 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.520683 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 1067157103520 99.61% 99.61% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 2648963000 0.25% 99.86% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 765456500 0.07% 99.93% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 299226500 0.03% 99.96% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 205947000 0.02% 99.97% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 124770000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 49360500 0.00% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 91134000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::16-17 2962000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::18-19 28500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 1071344974520 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 277768 89.79% 89.79% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 31582 10.21% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 309350 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1432753 # Table walker requests started/completed, data/inst
451,452c470,471
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1435892 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309967 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1432753 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309350 # Table walker requests started/completed, data/inst
454,455c473,474
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309967 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 1745859 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309350 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 1742103 # Table walker requests started/completed, data/inst
458,461c477,480
< system.cpu.dtb.read_hits 219013119 # DTB read hits
< system.cpu.dtb.read_misses 1011306 # DTB read misses
< system.cpu.dtb.write_hits 193770026 # DTB write hits
< system.cpu.dtb.write_misses 424586 # DTB write misses
---
> system.cpu.dtb.read_hits 218702786 # DTB read hits
> system.cpu.dtb.read_misses 1008685 # DTB read misses
> system.cpu.dtb.write_hits 193509885 # DTB write hits
> system.cpu.dtb.write_misses 424068 # DTB write misses
464c483
< system.cpu.dtb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
466,468c485,487
< system.cpu.dtb.flush_entries 88767 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 111 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 16184 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 88843 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 16314 # Number of TLB faults due to prefetch
470,472c489,491
< system.cpu.dtb.perms_faults 85758 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 220024425 # DTB read accesses
< system.cpu.dtb.write_accesses 194194612 # DTB write accesses
---
> system.cpu.dtb.perms_faults 85947 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 219711471 # DTB read accesses
> system.cpu.dtb.write_accesses 193933953 # DTB write accesses
474,477c493,496
< system.cpu.dtb.hits 412783145 # DTB hits
< system.cpu.dtb.misses 1435892 # DTB misses
< system.cpu.dtb.accesses 414219037 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 412212671 # DTB hits
> system.cpu.dtb.misses 1432753 # DTB misses
> system.cpu.dtb.accesses 413645424 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
507,554c526,577
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 178617 # Table walker walks requested
< system.cpu.itb.walker.walksLong 178617 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1509 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 129197 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 20173 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 158444 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 1791.778168 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 17776.926489 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-65535 157195 99.21% 99.21% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::65536-131071 1061 0.67% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::131072-196607 49 0.03% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::196608-262143 23 0.01% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::327680-393215 12 0.01% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::393216-458751 2 0.00% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::524288-589823 45 0.03% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::589824-655359 46 0.03% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 158444 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 150879 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 29477.399108 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 23380.752932 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 29925.423831 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 144789 95.96% 95.96% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 5035 3.34% 99.30% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 407 0.27% 99.57% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 355 0.24% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 85 0.06% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 65 0.04% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::589824-655359 82 0.05% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 150879 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 908136653272 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.948518 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.221299 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 46816690152 5.16% 5.16% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 861256760620 94.84% 99.99% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 62690500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 511000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 908136653272 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 129197 98.85% 98.85% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1509 1.15% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 130706 # Table walker page sizes translated
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 178667 # Table walker walks requested
> system.cpu.itb.walker.walksLong 178667 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1505 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 129431 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 20285 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 158382 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 1812.216666 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 18363.278107 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-65535 157121 99.20% 99.20% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::65536-131071 1064 0.67% 99.88% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::131072-196607 45 0.03% 99.90% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::327680-393215 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::393216-458751 4 0.00% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::524288-589823 38 0.02% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::589824-655359 58 0.04% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 158382 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 151221 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 29741.047870 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 23638.717531 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 30785.807578 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 145088 95.94% 95.94% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 5051 3.34% 99.28% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 405 0.27% 99.55% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 372 0.25% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 84 0.06% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 62 0.04% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::589824-655359 89 0.06% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::655360-720895 6 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::720896-786431 31 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 151221 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 912431133568 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.946195 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.225953 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 49158537652 5.39% 5.39% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 863207621416 94.61% 99.99% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 64327000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::3 645500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 912431133568 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 129431 98.85% 98.85% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1505 1.15% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 130936 # Table walker page sizes translated
556,557c579,580
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178617 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 178617 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178667 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 178667 # Table walker requests started/completed, data/inst
559,563c582,586
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130706 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 130706 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 309323 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 465622680 # ITB inst hits
< system.cpu.itb.inst_misses 178617 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130936 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 130936 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 309603 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 465155459 # ITB inst hits
> system.cpu.itb.inst_misses 178667 # ITB inst misses
570c593
< system.cpu.itb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
572c595
< system.cpu.itb.flush_entries 62354 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 62700 # Number of entries that have been flushed from TLB
576c599
< system.cpu.itb.perms_faults 442443 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 443616 # Number of TLB faults due to permissions restrictions
579,588c602,611
< system.cpu.itb.inst_accesses 465801297 # ITB inst accesses
< system.cpu.itb.hits 465622680 # DTB hits
< system.cpu.itb.misses 178617 # DTB misses
< system.cpu.itb.accesses 465801297 # DTB accesses
< system.cpu.numPwrStateTransitions 34330 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 17165 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 2940001446.310807 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 58531807829.842911 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 7841 45.68% 45.68% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.11% 99.79% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.inst_accesses 465334126 # ITB inst accesses
> system.cpu.itb.hits 465155459 # DTB hits
> system.cpu.itb.misses 178667 # DTB misses
> system.cpu.itb.accesses 465334126 # DTB accesses
> system.cpu.numPwrStateTransitions 34326 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 17163 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 2940291030.619589 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 58535247231.170448 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 7840 45.68% 45.68% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.11% 99.79% # Distribution of time spent in the clock gated state
601,604c624,627
< system.cpu.pwrStateClkGateDist::total 17165 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 1093565558075 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 50465124825925 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2187140442 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::total 17163 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 1094474667476 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 50464214958524 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2188958665 # number of cpu cycles simulated
607,623c630,646
< system.cpu.fetch.icacheStallCycles 793785781 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1302631708 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 292068322 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 175299129 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 1300965183 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 29519562 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 4657753 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 25879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 11707627 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1236073 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 927 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 465162073 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 6904477 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 52597 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 2127139004 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.717629 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.134701 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 793327228 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1301291266 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 291746368 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 175091486 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1303318637 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29494258 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 4691335 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 27171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 11697076 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 1210879 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 1191 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 464693718 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 6899661 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 52634 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 2129020646 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.716284 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.134063 # Number of instructions fetched each cycle (Total)
625,628c648,651
< system.cpu.fetch.rateDist::0 1399565872 65.80% 65.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 283601888 13.33% 79.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 89018844 4.18% 83.31% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 354952400 16.69% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 1402178691 65.86% 65.86% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 283295913 13.31% 79.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 88951632 4.18% 83.34% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 354594410 16.66% 100.00% # Number of instructions fetched each cycle (Total)
632,679c655,702
< system.cpu.fetch.rateDist::total 2127139004 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.133539 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.595587 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 615428593 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 884736584 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 543030027 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 73193860 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 10749940 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 41477613 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 4067608 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 1417243244 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 33090232 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 10749940 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 678230325 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 91937865 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 569242294 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 557610269 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 219368311 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1392930802 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 8136567 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 7440637 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 990068 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1113298 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 139552598 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 22837 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 1342716381 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2216807318 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1652527627 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1431919 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 1263732146 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 78984232 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 44095214 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 39617186 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 160769192 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 224047664 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 198221089 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12872997 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 11132343 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1339626168 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 44413765 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1369656198 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 4234304 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 74015451 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 42135581 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 368828 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 2127139004 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.643896 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.914248 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 2129020646 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.133281 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.594480 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 614901243 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 887926164 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 542267168 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 73189541 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 10736530 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 41417664 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 4068147 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 1415615504 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 33076716 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 10736530 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 677683388 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 94369025 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 569420569 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 556850066 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 219961068 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1391316215 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 8139294 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 7433415 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 989914 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1107412 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 140152556 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 22881 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 1341380585 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2214711658 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1650667847 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1431319 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 1262462841 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 78917741 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 44085987 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 39608884 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 160777326 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 223759172 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 197950271 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12848262 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11112686 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1338031616 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 44396038 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1368016868 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 4222413 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 73918251 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 42115616 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 367601 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 2129020646 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.642557 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.913774 # Number of insts issued each cycle
681,686c704,709
< system.cpu.iq.issued_per_cycle::0 1274738634 59.93% 59.93% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 452592629 21.28% 81.20% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 292740987 13.76% 94.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 96714663 4.55% 99.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10322849 0.49% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 29242 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 1277602195 60.01% 60.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 452152764 21.24% 81.25% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 292326493 13.73% 94.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 96574735 4.54% 99.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10335382 0.49% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 29077 0.00% 100.00% # Number of insts issued each cycle
693c716
< system.cpu.iq.issued_per_cycle::total 2127139004 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 2129020646 # Number of insts issued each cycle
695,697c718,720
< system.cpu.iq.fu_full::IntAlu 74109343 33.81% 33.81% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 90161 0.04% 33.85% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 26765 0.01% 33.87% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 73998347 33.81% 33.81% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 90252 0.04% 33.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 26750 0.01% 33.87% # attempts to use FU when none available
704c727
< system.cpu.iq.fu_full::FloatMisc 458 0.00% 33.87% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::FloatMisc 451 0.00% 33.87% # attempts to use FU when none available
726,729c749,752
< system.cpu.iq.fu_full::MemRead 59034015 26.93% 60.80% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 85210307 38.88% 99.68% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 64791 0.03% 99.71% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 640346 0.29% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 58933248 26.93% 60.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 85092406 38.88% 99.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 64953 0.03% 99.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 641116 0.29% 100.00% # attempts to use FU when none available
732,736c755,759
< system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 946221695 69.08% 69.08% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2942835 0.21% 69.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 130438 0.01% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 69.31% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 945166591 69.09% 69.09% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2943445 0.22% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 129819 0.01% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 69.31% # Type of FU issued
742c765
< system.cpu.iq.FU_type_0::FloatMisc 112188 0.01% 69.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatMisc 112220 0.01% 69.32% # Type of FU issued
764,767c787,790
< system.cpu.iq.FU_type_0::MemRead 223953856 16.35% 85.67% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 195515958 14.27% 99.94% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 118365 0.01% 99.95% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemWrite 660412 0.05% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 223636421 16.35% 85.67% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 195247662 14.27% 99.94% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 119006 0.01% 99.95% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemWrite 661615 0.05% 100.00% # Type of FU issued
770,782c793,805
< system.cpu.iq.FU_type_0::total 1369656198 # Type of FU issued
< system.cpu.iq.rate 0.626231 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 219176186 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.160023 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5087371498 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1457327579 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1347394357 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 2490391 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 913879 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 884967 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1587235373 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1596980 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5732534 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1368016868 # Type of FU issued
> system.cpu.iq.rate 0.624962 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 218847523 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.159974 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5085629992 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1455613237 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1345805572 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 2494325 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 915085 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 886623 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1585264941 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1599409 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5699315 # Number of loads that had data forwarded from stores
784,787c807,810
< system.cpu.iew.lsq.thread0.squashedLoads 17426729 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 22539 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 187787 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 8018407 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 17397321 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 21752 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 184120 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 8002822 # Number of stores squashed
790,791c813,814
< system.cpu.iew.lsq.thread0.rescheduledLoads 3639533 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 2053743 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 3610863 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 2045833 # Number of times an access to memory failed due to the cache being blocked
793,796c816,819
< system.cpu.iew.iewSquashCycles 10749940 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 12646274 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 5267578 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1384326807 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 10736530 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 13380632 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 5317474 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1382714005 # Number of instructions dispatched to IQ
798,809c821,832
< system.cpu.iew.iewDispLoadInsts 224047664 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 198221089 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 39077844 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 183202 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 4894696 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 187787 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4060868 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 6118781 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 10179649 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1355949241 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 219017773 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 12300796 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 223759172 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 197950271 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 39068255 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 183844 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 4942045 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 184120 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4054774 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 6111734 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 10166508 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1354334153 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 218708027 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 12279784 # Number of squashed instructions skipped in execute
811,827c834,850
< system.cpu.iew.exec_nop 286874 # number of nop insts executed
< system.cpu.iew.exec_refs 412797364 # number of memory reference insts executed
< system.cpu.iew.exec_branches 257488143 # Number of branches executed
< system.cpu.iew.exec_stores 193779591 # Number of stores executed
< system.cpu.iew.exec_rate 0.619964 # Inst execution rate
< system.cpu.iew.wb_sent 1349320641 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1348279324 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 576318139 # num instructions producing a value
< system.cpu.iew.wb_consumers 948680474 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.616458 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.607494 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 63090267 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 44044937 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 9703294 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 2112894773 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.620014 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.265043 # Number of insts commited each cycle
---
> system.cpu.iew.exec_nop 286351 # number of nop insts executed
> system.cpu.iew.exec_refs 412227919 # number of memory reference insts executed
> system.cpu.iew.exec_branches 257147927 # Number of branches executed
> system.cpu.iew.exec_stores 193519892 # Number of stores executed
> system.cpu.iew.exec_rate 0.618712 # Inst execution rate
> system.cpu.iew.wb_sent 1347736728 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1346692195 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 575598964 # num instructions producing a value
> system.cpu.iew.wb_consumers 947631330 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.615220 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.607408 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 63004798 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 44028437 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 9693675 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 2114795220 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.618740 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.263829 # Number of insts commited each cycle
829,837c852,860
< system.cpu.commit.committed_per_cycle::0 1431908907 67.77% 67.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 397571073 18.82% 86.59% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 150815124 7.14% 93.72% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 44594147 2.11% 95.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 36107553 1.71% 97.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 18031210 0.85% 98.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 11307158 0.54% 98.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 5865302 0.28% 99.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 16694299 0.79% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1434472892 67.83% 67.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 397205670 18.78% 86.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 150685224 7.13% 93.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 44578118 2.11% 95.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 36046556 1.70% 97.55% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 18010679 0.85% 98.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 11270632 0.53% 98.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 5868076 0.28% 99.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 16657373 0.79% 100.00% # Number of insts commited each cycle
841,843c864,866
< system.cpu.commit.committed_per_cycle::total 2112894773 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 1114574366 # Number of instructions committed
< system.cpu.commit.committedOps 1310024478 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 2114795220 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 1113248331 # Number of instructions committed
> system.cpu.commit.committedOps 1308509399 # Number of ops (including micro ops) committed
845,851c868,874
< system.cpu.commit.refs 396823616 # Number of memory references committed
< system.cpu.commit.loads 206620934 # Number of loads committed
< system.cpu.commit.membars 9197183 # Number of memory barriers committed
< system.cpu.commit.branches 249169048 # Number of branches committed
< system.cpu.commit.fp_insts 873305 # Number of committed floating point instructions.
< system.cpu.commit.int_insts 1197213012 # Number of committed integer instructions.
< system.cpu.commit.function_calls 31117535 # Number of function calls committed.
---
> system.cpu.commit.refs 396309299 # Number of memory references committed
> system.cpu.commit.loads 206361850 # Number of loads committed
> system.cpu.commit.membars 9184659 # Number of memory barriers committed
> system.cpu.commit.branches 248844974 # Number of branches committed
> system.cpu.commit.fp_insts 874713 # Number of committed floating point instructions.
> system.cpu.commit.int_insts 1195788175 # Number of committed integer instructions.
> system.cpu.commit.function_calls 31054705 # Number of function calls committed.
853,855c876,878
< system.cpu.commit.op_class_0::IntAlu 910437285 69.50% 69.50% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 2553089 0.19% 69.69% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 104752 0.01% 69.70% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 909436322 69.50% 69.50% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 2554044 0.20% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 103998 0.01% 69.70% # Class of committed instruction
884,887c907,910
< system.cpu.commit.op_class_0::MemRead 206508219 15.76% 85.47% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 189547828 14.47% 99.94% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatMemRead 112715 0.01% 99.95% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatMemWrite 654854 0.05% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 206248879 15.76% 85.48% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 189291443 14.47% 99.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMemRead 112971 0.01% 99.95% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMemWrite 656006 0.05% 100.00% # Class of committed instruction
890,916c913,939
< system.cpu.commit.op_class_0::total 1310024478 # Class of committed instruction
< system.cpu.commit.bw_lim_events 16694299 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 3459813368 # The number of ROB reads
< system.cpu.rob.rob_writes 2760364536 # The number of ROB writes
< system.cpu.timesIdled 9090851 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 60001438 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 100930240360 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 1114574366 # Number of Instructions Simulated
< system.cpu.committedOps 1310024478 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.962310 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.962310 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.509603 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.509603 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1610546046 # number of integer regfile reads
< system.cpu.int_regfile_writes 949011498 # number of integer regfile writes
< system.cpu.fp_regfile_reads 1420249 # number of floating regfile reads
< system.cpu.fp_regfile_writes 762248 # number of floating regfile writes
< system.cpu.cc_regfile_reads 314797086 # number of cc regfile reads
< system.cpu.cc_regfile_writes 315669715 # number of cc regfile writes
< system.cpu.misc_regfile_reads 3475493523 # number of misc regfile reads
< system.cpu.misc_regfile_writes 44962873 # number of misc regfile writes
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 13773422 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.982216 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 363599894 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 13773934 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 26.397679 # Average number of references to valid blocks.
---
> system.cpu.commit.op_class_0::total 1308509399 # Class of committed instruction
> system.cpu.commit.bw_lim_events 16657373 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3460150362 # The number of ROB reads
> system.cpu.rob.rob_writes 2757143126 # The number of ROB writes
> system.cpu.timesIdled 9093879 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 59938019 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 100928420629 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 1113248331 # Number of Instructions Simulated
> system.cpu.committedOps 1308509399 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.966281 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.966281 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.508574 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.508574 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1608691208 # number of integer regfile reads
> system.cpu.int_regfile_writes 947917634 # number of integer regfile writes
> system.cpu.fp_regfile_reads 1422673 # number of floating regfile reads
> system.cpu.fp_regfile_writes 763952 # number of floating regfile writes
> system.cpu.cc_regfile_reads 314581614 # number of cc regfile reads
> system.cpu.cc_regfile_writes 315450766 # number of cc regfile writes
> system.cpu.misc_regfile_reads 3476012517 # number of misc regfile reads
> system.cpu.misc_regfile_writes 44950556 # number of misc regfile writes
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 13775006 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.982219 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 363107662 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 13775518 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 26.358912 # Average number of references to valid blocks.
918c941
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.982216 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.982219 # Average occupied blocks per requestor
922,924c945,947
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
926,954c949,977
< system.cpu.dcache.tags.tag_accesses 1610515756 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1610515756 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 188193818 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 188193818 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 164381838 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 164381838 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 464944 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 464944 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 334105 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 334105 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4846159 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4846159 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 5335614 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 5335614 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 352909761 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 352909761 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 353374705 # number of overall hits
< system.cpu.dcache.overall_hits::total 353374705 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 12874356 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 12874356 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 18866989 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 18866989 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 2064832 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 2064832 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1271634 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1271634 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 551153 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 551153 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 1608531103 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1608531103 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 187963659 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 187963659 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 164128124 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 164128124 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 464529 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 464529 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 334911 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 334911 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4841304 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4841304 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 5331661 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 5331661 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 352426694 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 352426694 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 352891223 # number of overall hits
> system.cpu.dcache.overall_hits::total 352891223 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 12866276 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 12866276 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 18869425 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 18869425 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 2066021 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 2066021 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1270837 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1270837 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 552138 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 552138 # number of LoadLockedReq misses
957,1021c980,1044
< system.cpu.dcache.demand_misses::cpu.data 33012979 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 33012979 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 35077811 # number of overall misses
< system.cpu.dcache.overall_misses::total 35077811 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 223063102000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 223063102000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1108624638487 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1108624638487 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30055916196 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 30055916196 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9351183000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 9351183000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 1361743656683 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 1361743656683 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 1361743656683 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 1361743656683 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 201068174 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 201068174 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 183248827 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 183248827 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2529776 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2529776 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605739 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1605739 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5397312 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 5397312 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335622 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 5335622 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 385922740 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 385922740 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 388452516 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 388452516 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064030 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.064030 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102958 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.102958 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816211 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.816211 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791931 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.791931 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102116 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102116 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.085543 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.085543 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.090301 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.090301 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17326.156120 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17326.156120 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58760.019338 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 58760.019338 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23635.665762 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23635.665762 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16966.582782 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16966.582782 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35687.500000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35687.500000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 41248.736041 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 41248.736041 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 38820.656645 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 38820.656645 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 28867036 # number of cycles access was blocked
---
> system.cpu.dcache.demand_misses::cpu.data 33006538 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 33006538 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 35072559 # number of overall misses
> system.cpu.dcache.overall_misses::total 35072559 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 225016613000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 225016613000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113555465610 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1113555465610 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30066239407 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 30066239407 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9389478000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 9389478000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 268500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 268500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 1368638318017 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 1368638318017 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 1368638318017 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 1368638318017 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 200829935 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 200829935 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 182997549 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 182997549 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2530550 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2530550 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605748 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1605748 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5393442 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 5393442 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 5331669 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 5331669 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 385433232 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 385433232 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 387963782 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 387963782 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064066 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.064066 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103113 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.103113 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816432 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.816432 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791430 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.791430 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102372 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102372 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.085635 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.085635 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.090402 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.090402 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17488.868807 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17488.868807 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59013.746609 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 59013.746609 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23658.611928 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23658.611928 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17005.672495 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17005.672495 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33562.500000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33562.500000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41465.673195 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41465.673195 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39023.052695 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39023.052695 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 29226576 # number of cycles access was blocked
1023c1046
< system.cpu.dcache.blocked::no_mshrs 2109714 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 2109542 # number of cycles access was blocked
1025c1048
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.682914 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.854465 # average number of cycles each access was blocked
1027,1050c1050,1073
< system.cpu.dcache.writebacks::writebacks 10417036 # number of writebacks
< system.cpu.dcache.writebacks::total 10417036 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5763320 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 5763320 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15767233 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 15767233 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7067 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 7067 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 267203 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 267203 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 21537620 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 21537620 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 21537620 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 21537620 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111036 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7111036 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099756 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 3099756 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2058030 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 2058030 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1264567 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1264567 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283950 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 283950 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 10412623 # number of writebacks
> system.cpu.dcache.writebacks::total 10412623 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5753869 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 5753869 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15770096 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 15770096 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6914 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 6914 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 268040 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 268040 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 21530879 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 21530879 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 21530879 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 21530879 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7112407 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7112407 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099329 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 3099329 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2059217 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 2059217 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263923 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1263923 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284098 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 284098 # number of LoadLockedReq MSHR misses
1053,1056c1076,1079
< system.cpu.dcache.demand_mshr_misses::cpu.data 11475359 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 11475359 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 13533389 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 13533389 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 11475659 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 11475659 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 13534876 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 13534876 # number of overall MSHR misses
1063,1126c1086,1149
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 117823858000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 117823858000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163535842014 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 163535842014 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34754745000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34754745000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28487682196 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28487682196 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4220692000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4220692000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 309847382210 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 309847382210 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 344602127210 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 344602127210 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225657500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225657500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225657500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225657500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035366 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035366 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813523 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813523 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787530 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787530 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052610 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052610 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029735 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.029735 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034839 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.034839 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.155043 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.155043 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52757.649961 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52757.649961 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16887.385024 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16887.385024 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22527.617909 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22527.617909 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14864.208487 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14864.208487 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34687.500000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34687.500000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27001.105779 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 27001.105779 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25463.106633 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 25463.106633 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184781.476315 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184781.476315 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.658432 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.658432 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 16948036 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.953468 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 447400638 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 16948548 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 26.397579 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.953468 # Average occupied blocks per requestor
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 119879387000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 119879387000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164321917838 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 164321917838 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34890815500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34890815500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28496186907 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28496186907 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4243086000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4243086000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 260500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 260500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312697491745 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 312697491745 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 347588307245 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 347588307245 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225622500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225622500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225622500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225622500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035415 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035415 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016936 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016936 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813743 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813743 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787124 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787124 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052675 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052675 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029773 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.029773 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034887 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.034887 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16854.967242 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16854.967242 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53018.546220 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53018.546220 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16943.729340 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16943.729340 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22545.825107 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22545.825107 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14935.289935 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14935.289935 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32562.500000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32562.500000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27248.761204 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 27248.761204 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25680.937693 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 25680.937693 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184780.437493 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184780.437493 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.139105 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.139105 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 16945634 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.953469 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 446936468 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 16946146 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 26.373930 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 13767479500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.953469 # Average occupied blocks per requestor
1130,1132c1153,1155
< system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
1134,1173c1157,1196
< system.cpu.icache.tags.tag_accesses 482089545 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 482089545 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 447400638 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 447400638 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 447400638 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 447400638 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 447400638 # number of overall hits
< system.cpu.icache.overall_hits::total 447400638 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 17740135 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 17740135 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 17740135 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 17740135 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 17740135 # number of overall misses
< system.cpu.icache.overall_misses::total 17740135 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 237745686369 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 237745686369 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 237745686369 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 237745686369 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 237745686369 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 237745686369 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 465140773 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 465140773 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 465140773 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 465140773 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 465140773 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 465140773 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038139 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.038139 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.038139 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.038139 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.038139 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.038139 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13401.571429 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13401.571429 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13401.571429 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13401.571429 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 22866 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 481618789 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 481618789 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 446936468 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 446936468 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 446936468 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 446936468 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 446936468 # number of overall hits
> system.cpu.icache.overall_hits::total 446936468 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 17735952 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 17735952 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 17735952 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 17735952 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 17735952 # number of overall misses
> system.cpu.icache.overall_misses::total 17735952 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 237635395867 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 237635395867 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 237635395867 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 237635395867 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 237635395867 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 237635395867 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 464672420 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 464672420 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 464672420 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 464672420 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 464672420 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 464672420 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038169 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.038169 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.038169 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.038169 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.038169 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.038169 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13398.513701 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13398.513701 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13398.513701 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13398.513701 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 21075 # number of cycles access was blocked
1175c1198
< system.cpu.icache.blocked::no_mshrs 1431 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 1467 # number of cycles access was blocked
1177c1200
< system.cpu.icache.avg_blocked_cycles::no_mshrs 15.979036 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 14.366053 # average number of cycles each access was blocked
1179,1192c1202,1215
< system.cpu.icache.writebacks::writebacks 16948036 # number of writebacks
< system.cpu.icache.writebacks::total 16948036 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791363 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 791363 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 791363 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 791363 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 791363 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 791363 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16948772 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 16948772 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 16948772 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 16948772 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 16948772 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 16948772 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 16945634 # number of writebacks
> system.cpu.icache.writebacks::total 16945634 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789581 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 789581 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 789581 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 789581 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 789581 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 789581 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16946371 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16946371 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16946371 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16946371 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16946371 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16946371 # number of overall MSHR misses
1197,1202c1220,1225
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213645244880 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 213645244880 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213645244880 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 213645244880 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213645244880 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 213645244880 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213535123378 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 213535123378 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213535123378 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 213535123378 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213535123378 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 213535123378 # number of overall MSHR miss cycles
1207,1218c1230,1241
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036438 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.036438 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.036438 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12605.352463 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12605.352463 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036470 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.036470 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.036470 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12600.640183 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12600.640183 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency
1223,1342c1246,1362
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 2368264 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65438.912903 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 59342443 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2431405 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.406647 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2677802000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 9464.122529 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 393.883765 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.035779 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 6680.528058 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 48467.342772 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.144411 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006010 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006608 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101937 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.739553 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998519 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 62889 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1015 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5647 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55838 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959610 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 508088213 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 508088213 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1306072 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 309439 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1615511 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 10417036 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 10417036 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 16945412 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 16945412 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 39342 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 39342 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1735264 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1735264 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16852583 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 16852583 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 9020162 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 9020162 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 672287 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 672287 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 1306072 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 309439 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 16852583 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 10755426 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 29223520 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 1306072 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 309439 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 16852583 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 10755426 # number of overall hits
< system.cpu.l2cache.overall_hits::total 29223520 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10647 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8959 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 19606 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 4043 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 4043 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 1337553 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 1337553 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95970 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 95970 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 416410 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 416410 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 592280 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 592280 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 10647 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 8959 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 95970 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1753963 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1869539 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 10647 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 8959 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 95970 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1753963 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1869539 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1464838500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 979350000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2444188500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73726500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 73726500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 139978365500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 139978365500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10559308500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 10559308500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46880784000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 46880784000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 453500 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 453500 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1464838500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 979350000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 10559308500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 186859149500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 199862646500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1464838500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 979350000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 10559308500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 186859149500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 199862646500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1316719 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 318398 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1635117 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 10417036 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 10417036 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 16945412 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 16945412 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43385 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 43385 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 2400192 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65402.662910 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 59310777 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2462586 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.084754 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2677803000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 9273.019739 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 380.440424 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.878818 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6709.693607 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48618.630322 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.141495 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005805 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006422 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.102382 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.741861 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.997965 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 239 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 62155 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 998 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5581 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55200 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003647 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948410 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 508162919 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 508162919 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1310607 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 311860 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1622467 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 10412623 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 10412623 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 16942916 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 16942916 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 39365 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 39365 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1729760 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1729760 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16850415 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 16850415 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8995594 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 8995594 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 670573 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 670573 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 1310607 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 311860 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 16850415 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 10725354 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 29198236 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 1310607 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 311860 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 16850415 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 10725354 # number of overall hits
> system.cpu.l2cache.overall_hits::total 29198236 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10751 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8953 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 19704 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 4081 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 4081 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 1342610 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 1342610 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95730 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 95730 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 443644 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 443644 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 593350 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 593350 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 10751 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 8953 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 95730 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1786254 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1901688 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 10751 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 8953 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 95730 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1786254 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1901688 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1481609000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 989051000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2470660000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73641000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 73641000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140820985000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 140820985000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10474446000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 10474446000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49360603500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 49360603500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1481609000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 989051000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 10474446000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 190181588500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 203126694500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1481609000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 989051000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 10474446000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 190181588500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 203126694500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1321358 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 320813 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1642171 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 10412623 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 10412623 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 16942916 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 16942916 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43446 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 43446 # number of UpgradeReq accesses(hits+misses)
1345,1412c1365,1430
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072817 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 3072817 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16948553 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 16948553 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9436572 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 9436572 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1264567 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1264567 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1316719 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 318398 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 16948553 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 12509389 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 31093059 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1316719 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 318398 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 16948553 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 12509389 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 31093059 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008086 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028138 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093189 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093189 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435286 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.435286 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005662 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005662 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.468366 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.468366 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008086 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028138 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005662 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.140212 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.060127 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008086 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028138 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005662 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.140212 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.060127 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137582.276698 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109314.655654 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 124665.332041 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18235.592382 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18235.592382 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104652.574889 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104652.574889 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110027.180369 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110027.180369 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112583.232871 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112583.232871 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.765685 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.765685 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 106904.775188 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 106904.775188 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072370 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 3072370 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16946145 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 16946145 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439238 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 9439238 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263923 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1263923 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1321358 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 320813 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 16946145 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 12511608 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 31099924 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1321358 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 320813 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16946145 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 12511608 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 31099924 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008136 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027907 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.011999 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093933 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093933 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.375000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.375000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436995 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.436995 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005649 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005649 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047000 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047000 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.469451 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.469451 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008136 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027907 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005649 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.142768 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.061148 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008136 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027907 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005649 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.142768 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.061148 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137811.273370 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 110471.462080 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 125388.753553 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18044.841951 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18044.841951 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54166.666667 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54166.666667 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104885.994444 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104885.994444 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109416.546537 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109416.546537 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111261.740269 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111261.740269 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 106813.890870 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 106813.890870 # average overall miss latency
1419,1420c1437,1440
< system.cpu.l2cache.writebacks::writebacks 2100679 # number of writebacks
< system.cpu.l2cache.writebacks::total 2100679 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 2127726 # number of writebacks
> system.cpu.l2cache.writebacks::total 2127726 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 4 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
1422a1443
> system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 4 # number of demand (read+write) MSHR hits
1424c1445,1446
< system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 4 # number of overall MSHR hits
1426,1453c1448,1475
< system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10647 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8959 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 19606 # number of ReadReq MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4043 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 4043 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1337553 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1337553 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95970 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95970 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 416389 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 416389 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 592280 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 592280 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10647 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8959 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 95970 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1753942 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1869518 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10647 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8959 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 95970 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1753942 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1869518 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10751 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8949 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 19700 # number of ReadReq MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4081 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 4081 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1342610 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1342610 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95730 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95730 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 443623 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 443623 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 593350 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 593350 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10751 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8949 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 95730 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1786233 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1901663 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10751 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8949 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 95730 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1786233 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1901663 # number of overall MSHR misses
1462,1486c1484,1508
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 889760000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2248128500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77144500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77144500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126602809555 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126602809555 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9599588543 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9599588543 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42714761570 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42714761570 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12256085002 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12256085002 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 889760000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9599588543 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169317571125 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 181165288168 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 889760000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9599588543 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169317571125 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 181165288168 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 899358000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2273457000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77835000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77835000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127394865041 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127394865041 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9517134048 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9517134048 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 44922827064 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 44922827064 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12274426752 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12274426752 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 899358000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9517134048 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172317692105 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 184108283153 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 899358000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9517134048 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172317692105 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 184108283153 # number of overall MSHR miss cycles
1488,1489c1510,1511
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804371500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290859000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804330500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290818000 # number of ReadReq MSHR uncacheable cycles
1491,1495c1513,1517
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804371500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290859000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011991 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804330500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290818000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011996 # mshr miss rate for ReadReq accesses
1498,1544c1520,1566
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093189 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093189 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435286 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435286 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005662 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044125 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044125 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.468366 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.468366 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060127 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.060127 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 114665.332041 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19081.004205 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19081.004205 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94652.555491 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94652.555491 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100026.972418 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100026.972418 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102583.789605 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102583.789605 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20693.059030 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20693.059030 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093933 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093933 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.375000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436995 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436995 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005649 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.046998 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.046998 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.469451 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.469451 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.061147 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.061147 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115403.908629 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19072.531242 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19072.531242 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94885.979578 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94885.979578 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99416.421686 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99416.421686 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101263.521197 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101263.521197 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.655013 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.655013 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency
1546,1547c1568,1569
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.439748 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.824137 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172276.222842 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.078493 # average ReadReq mshr uncacheable latency
1549,1555c1571,1577
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.660583 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.026802 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 62411777 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 31689071 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2067 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2067 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.052229 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82206.564512 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 62406736 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 31684635 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4771 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2157 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2157 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1557,1559c1579,1581
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 2264077 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 28650207 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 2262463 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 28648866 # Transaction distribution
1562,1565c1584,1587
< system.cpu.toL2Bus.trans_dist::WritebackDirty 12517715 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 16948036 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 3623971 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 43388 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 12540349 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 16945634 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 3634849 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 43449 # Transaction distribution
1567,1588c1589,1610
< system.cpu.toL2Bus.trans_dist::UpgradeResp 43396 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 3072817 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 3072817 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 16948772 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 9438927 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1295442 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1264567 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50887949 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41543699 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 787064 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3057144 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 96275856 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169722400 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467531890 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2547184 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10533752 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 3650335226 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 2976479 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 139099568 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 35465406 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.159793 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 43457 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 3072370 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 3072370 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 16946371 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441630 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1296845 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1263929 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880736 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41548571 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 789343 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3060305 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 96278955 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169414432 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467392114 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2566504 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10570864 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 3649943914 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 3001846 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 140762320 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 35497041 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.026133 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.159532 # Request fanout histogram
1590,1591c1612,1613
< system.cpu.toL2Bus.snoop_fanout::0 34535454 97.38% 97.38% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 929952 2.62% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 34569387 97.39% 97.39% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 927654 2.61% 100.00% # Request fanout histogram
1596,1597c1618,1619
< system.cpu.toL2Bus.snoop_fanout::total 35465406 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 59274617984 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 35497041 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 59266206483 # Layer occupancy (ticks)
1599c1621
< system.cpu.toL2Bus.snoopLayer0.occupancy 1490379 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1503389 # Layer occupancy (ticks)
1601c1623
< system.cpu.toL2Bus.respLayer0.occupancy 25454807175 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 25451406259 # Layer occupancy (ticks)
1603c1625
< system.cpu.toL2Bus.respLayer1.occupancy 19473878402 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 19476952327 # Layer occupancy (ticks)
1605c1627
< system.cpu.toL2Bus.respLayer2.occupancy 469039231 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 468902194 # Layer occupancy (ticks)
1607c1629
< system.cpu.toL2Bus.respLayer3.occupancy 1741050209 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1739672503 # Layer occupancy (ticks)
1609,1611c1631,1633
< system.iobus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40296 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40296 # Transaction distribution
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40306 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40306 # Transaction distribution
1628,1629c1650,1651
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes)
1632c1654
< system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes)
1647,1648c1669,1670
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes)
1651,1652c1673,1674
< system.iobus.pkt_size::total 7492152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 41892500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 41898000 # Layer occupancy (ticks)
1654c1676
< system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
1656c1678
< system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 340000 # Layer occupancy (ticks)
1674c1696
< system.iobus.reqLayer23.occupancy 25201500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25176500 # Layer occupancy (ticks)
1676c1698
< system.iobus.reqLayer24.occupancy 36497000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36502500 # Layer occupancy (ticks)
1678c1700
< system.iobus.reqLayer25.occupancy 569294464 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 568938305 # Layer occupancy (ticks)
1682c1704
< system.iobus.respLayer3.occupancy 147710000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks)
1686,1688c1708,1710
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115456 # number of replacements
< system.iocache.tags.tagsinuse 10.450363 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115466 # number of replacements
> system.iocache.tags.tagsinuse 10.450358 # Cycle average of tags in use
1690c1712
< system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks.
1692,1694c1714,1716
< system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.528284 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.922079 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 13091904723000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.528286 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.922072 # Average occupied blocks per requestor
1696,1697c1718,1719
< system.iocache.tags.occ_percent::realview.ide 0.432630 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.653148 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_percent::realview.ide 0.432629 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy
1701,1703c1723,1725
< system.iocache.tags.tag_accesses 1039632 # Number of tag accesses
< system.iocache.tags.data_accesses 1039632 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1039722 # Number of tag accesses
> system.iocache.tags.data_accesses 1039722 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
1705,1706c1727,1728
< system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses
1712,1713c1734,1735
< system.iocache.demand_misses::realview.ide 115475 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115515 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115525 # number of demand (read+write) misses
1715,1716c1737,1738
< system.iocache.overall_misses::realview.ide 115475 # number of overall misses
< system.iocache.overall_misses::total 115515 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115485 # number of overall misses
> system.iocache.overall_misses::total 115525 # number of overall misses
1718,1719c1740,1741
< system.iocache.ReadReq_miss_latency::realview.ide 1862993006 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1868078506 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1915316073 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1920401573 # number of ReadReq miss cycles
1722,1723c1744,1745
< system.iocache.WriteLineReq_miss_latency::realview.ide 13281113958 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13281113958 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13385817732 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13385817732 # number of WriteLineReq miss cycles
1725,1726c1747,1748
< system.iocache.demand_miss_latency::realview.ide 15144106964 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 15149543464 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15301133805 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15306570305 # number of demand (read+write) miss cycles
1728,1729c1750,1751
< system.iocache.overall_miss_latency::realview.ide 15144106964 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 15149543464 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15301133805 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15306570305 # number of overall miss cycles
1731,1732c1753,1754
< system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses)
1738,1739c1760,1761
< system.iocache.demand_accesses::realview.ide 115475 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115515 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses
1741,1742c1763,1764
< system.iocache.overall_accesses::realview.ide 115475 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115515 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses
1757,1758c1779,1780
< system.iocache.ReadReq_avg_miss_latency::realview.ide 211439.451368 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 211130.030063 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 217131.399274 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 216798.551930 # average ReadReq miss latency
1761,1762c1783,1784
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124513.556195 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 124513.556195 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125495.178617 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125495.178617 # average WriteLineReq miss latency
1764,1765c1786,1787
< system.iocache.demand_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 131147.846288 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 132495.739494 # average overall miss latency
1767,1769c1789,1791
< system.iocache.overall_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 131147.846288 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 44063 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 132495.739494 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 46527 # number of cycles access was blocked
1771c1793
< system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked
1773c1795
< system.iocache.avg_blocked_cycles::no_mshrs 12.567884 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 13.537096 # average number of cycles each access was blocked
1778,1779c1800,1801
< system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses
1785,1786c1807,1808
< system.iocache.demand_mshr_misses::realview.ide 115475 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115515 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115485 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115525 # number of demand (read+write) MSHR misses
1788,1789c1810,1811
< system.iocache.overall_mshr_misses::realview.ide 115475 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115515 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115485 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115525 # number of overall MSHR misses
1791,1792c1813,1814
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1422443006 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1425678506 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1474266073 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1477501573 # number of ReadReq MSHR miss cycles
1795,1796c1817,1818
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7941073224 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7941073224 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8047307820 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8047307820 # number of WriteLineReq MSHR miss cycles
1798,1799c1820,1821
< system.iocache.demand_mshr_miss_latency::realview.ide 9363516230 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9366952730 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9521573893 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9525010393 # number of demand (read+write) MSHR miss cycles
1801,1802c1823,1824
< system.iocache.overall_mshr_miss_latency::realview.ide 9363516230 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9366952730 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9521573893 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9525010393 # number of overall MSHR miss cycles
1817,1818c1839,1840
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 161439.451368 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 161130.030063 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167131.399274 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 166798.551930 # average ReadReq mshr miss latency
1821,1822c1843,1844
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74449.422711 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74449.422711 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75445.396947 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75445.396947 # average WriteLineReq mshr miss latency
1824,1825c1846,1847
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency
1827,1831c1849,1853
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 5064341 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 2518493 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 2998 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 5129530 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 2552281 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3338 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1835c1857
< system.membus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
1837c1859
< system.membus.trans_dist::ReadResp 595799 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 622896 # Transaction distribution
1840,1843c1862,1865
< system.membus.trans_dist::WritebackDirty 2207309 # Transaction distribution
< system.membus.trans_dist::CleanEvict 275154 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4609 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 2234356 # Transaction distribution
> system.membus.trans_dist::CleanEvict 280040 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4640 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
1845,1848c1867,1871
< system.membus.trans_dist::ReadExReq 1336997 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1336997 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 540813 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 698937 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 1342054 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1342054 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 567911 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 700014 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 32639 # Transaction distribution
1852,1856c1875,1879
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6748871 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6878533 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237677 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237677 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7116210 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6846190 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6975852 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237668 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237668 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7213520 # Packet count per connected master and slave (bytes)
1860,1869c1883,1892
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254375884 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254545938 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253504 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7253504 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 261799442 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 2809 # Total snoops (count)
< system.membus.snoopTraffic 179264 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 2670049 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.012702 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.111987 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258164108 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 258334162 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251648 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7251648 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 265585810 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 35487 # Total snoops (count)
> system.membus.snoopTraffic 181760 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 2703311 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.013318 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.114632 # Request fanout histogram
1871,1872c1894,1895
< system.membus.snoop_fanout::0 2636133 98.73% 98.73% # Request fanout histogram
< system.membus.snoop_fanout::1 33916 1.27% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 2667309 98.67% 98.67% # Request fanout histogram
> system.membus.snoop_fanout::1 36002 1.33% 100.00% # Request fanout histogram
1877,1878c1900,1901
< system.membus.snoop_fanout::total 2670049 # Request fanout histogram
< system.membus.reqLayer0.occupancy 104027000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2703311 # Request fanout histogram
> system.membus.reqLayer0.occupancy 104009500 # Layer occupancy (ticks)
1882c1905
< system.membus.reqLayer2.occupancy 5600000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5608500 # Layer occupancy (ticks)
1884c1907
< system.membus.reqLayer5.occupancy 14297533259 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 14476553313 # Layer occupancy (ticks)
1886c1909
< system.membus.respLayer2.occupancy 10011316944 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 10180600996 # Layer occupancy (ticks)
1888c1911
< system.membus.respLayer3.occupancy 44794763 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 79038203 # Layer occupancy (ticks)
1890,1896c1913,1919
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
1903,1904c1926,1927
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
1947,1953c1970,1976
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
1958,1969c1981,1992
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states
1971c1994
< system.cpu.kern.inst.quiesce 17165 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 17163 # number of quiesce instructions executed