3,5c3,5
< sim_seconds 51.558698 # Number of seconds simulated
< sim_ticks 51558697863000 # Number of ticks simulated
< final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.558690 # Number of seconds simulated
> sim_ticks 51558690384000 # Number of ticks simulated
> final_tick 51558690384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 167711 # Simulator instruction rate (inst/s)
< host_op_rate 197118 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 7760882097 # Simulator tick rate (ticks/s)
< host_mem_usage 692228 # Number of bytes of host memory used
< host_seconds 6643.41 # Real time elapsed on the host
< sim_insts 1114173091 # Number of instructions simulated
< sim_ops 1309536110 # Number of ops (including micro ops) simulated
---
> host_inst_rate 207581 # Simulator instruction rate (inst/s)
> host_op_rate 243983 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9602431196 # Simulator tick rate (ticks/s)
> host_mem_usage 695472 # Number of bytes of host memory used
> host_seconds 5369.34 # Real time elapsed on the host
> sim_insts 1114574366 # Number of instructions simulated
> sim_ops 1310024478 # Number of ops (including micro ops) simulated
16,25c16,25
< system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory
< system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 681408 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 573376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 6481504 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 112175560 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 429184 # Number of bytes read from this memory
> system.physmem.bytes_read::total 120341032 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 6481504 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6481504 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 141267776 # Number of bytes written to this memory
27,34c27,34
< system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 141288356 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 10647 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 8959 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 117226 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1752756 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6706 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1896294 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 2207309 # Number of write requests responded to by this memory
36,45c36,45
< system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 2209882 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 13216 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 11121 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 125711 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2175687 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8324 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2334059 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 125711 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 125711 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2739941 # Write bandwidth from this memory (bytes/s)
47,65c47,65
< system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1935081 # Number of read requests accepted
< system.physmem.writeReqs 2243085 # Number of write requests accepted
< system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue
< system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 2740340 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2739941 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 13216 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 11121 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 125711 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2176086 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8324 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5074399 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1896294 # Number of read requests accepted
> system.physmem.writeReqs 2209882 # Number of write requests accepted
> system.physmem.readBursts 1896294 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 2209882 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 121325696 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue
> system.physmem.bytesWritten 141284736 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 120341032 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 141288356 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one
67,98c67,98
< system.physmem.perBankRdBursts::0 114857 # Per bank write bursts
< system.physmem.perBankRdBursts::1 123887 # Per bank write bursts
< system.physmem.perBankRdBursts::2 121380 # Per bank write bursts
< system.physmem.perBankRdBursts::3 115864 # Per bank write bursts
< system.physmem.perBankRdBursts::4 115150 # Per bank write bursts
< system.physmem.perBankRdBursts::5 124779 # Per bank write bursts
< system.physmem.perBankRdBursts::6 116343 # Per bank write bursts
< system.physmem.perBankRdBursts::7 120532 # Per bank write bursts
< system.physmem.perBankRdBursts::8 117169 # Per bank write bursts
< system.physmem.perBankRdBursts::9 147715 # Per bank write bursts
< system.physmem.perBankRdBursts::10 116324 # Per bank write bursts
< system.physmem.perBankRdBursts::11 125031 # Per bank write bursts
< system.physmem.perBankRdBursts::12 116553 # Per bank write bursts
< system.physmem.perBankRdBursts::13 122187 # Per bank write bursts
< system.physmem.perBankRdBursts::14 118707 # Per bank write bursts
< system.physmem.perBankRdBursts::15 117850 # Per bank write bursts
< system.physmem.perBankWrBursts::0 135590 # Per bank write bursts
< system.physmem.perBankWrBursts::1 141676 # Per bank write bursts
< system.physmem.perBankWrBursts::2 140587 # Per bank write bursts
< system.physmem.perBankWrBursts::3 138605 # Per bank write bursts
< system.physmem.perBankWrBursts::4 137623 # Per bank write bursts
< system.physmem.perBankWrBursts::5 144276 # Per bank write bursts
< system.physmem.perBankWrBursts::6 136529 # Per bank write bursts
< system.physmem.perBankWrBursts::7 140386 # Per bank write bursts
< system.physmem.perBankWrBursts::8 138327 # Per bank write bursts
< system.physmem.perBankWrBursts::9 145050 # Per bank write bursts
< system.physmem.perBankWrBursts::10 137213 # Per bank write bursts
< system.physmem.perBankWrBursts::11 144076 # Per bank write bursts
< system.physmem.perBankWrBursts::12 138694 # Per bank write bursts
< system.physmem.perBankWrBursts::13 142077 # Per bank write bursts
< system.physmem.perBankWrBursts::14 140963 # Per bank write bursts
< system.physmem.perBankWrBursts::15 139115 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 112674 # Per bank write bursts
> system.physmem.perBankRdBursts::1 120331 # Per bank write bursts
> system.physmem.perBankRdBursts::2 120633 # Per bank write bursts
> system.physmem.perBankRdBursts::3 114638 # Per bank write bursts
> system.physmem.perBankRdBursts::4 113111 # Per bank write bursts
> system.physmem.perBankRdBursts::5 123581 # Per bank write bursts
> system.physmem.perBankRdBursts::6 115477 # Per bank write bursts
> system.physmem.perBankRdBursts::7 120263 # Per bank write bursts
> system.physmem.perBankRdBursts::8 112291 # Per bank write bursts
> system.physmem.perBankRdBursts::9 145720 # Per bank write bursts
> system.physmem.perBankRdBursts::10 114582 # Per bank write bursts
> system.physmem.perBankRdBursts::11 120005 # Per bank write bursts
> system.physmem.perBankRdBursts::12 112695 # Per bank write bursts
> system.physmem.perBankRdBursts::13 118645 # Per bank write bursts
> system.physmem.perBankRdBursts::14 113317 # Per bank write bursts
> system.physmem.perBankRdBursts::15 117751 # Per bank write bursts
> system.physmem.perBankWrBursts::0 133340 # Per bank write bursts
> system.physmem.perBankWrBursts::1 139177 # Per bank write bursts
> system.physmem.perBankWrBursts::2 138321 # Per bank write bursts
> system.physmem.perBankWrBursts::3 137224 # Per bank write bursts
> system.physmem.perBankWrBursts::4 136590 # Per bank write bursts
> system.physmem.perBankWrBursts::5 143143 # Per bank write bursts
> system.physmem.perBankWrBursts::6 136203 # Per bank write bursts
> system.physmem.perBankWrBursts::7 139934 # Per bank write bursts
> system.physmem.perBankWrBursts::8 134977 # Per bank write bursts
> system.physmem.perBankWrBursts::9 143618 # Per bank write bursts
> system.physmem.perBankWrBursts::10 135619 # Per bank write bursts
> system.physmem.perBankWrBursts::11 140132 # Per bank write bursts
> system.physmem.perBankWrBursts::12 134815 # Per bank write bursts
> system.physmem.perBankWrBursts::13 138770 # Per bank write bursts
> system.physmem.perBankWrBursts::14 136807 # Per bank write bursts
> system.physmem.perBankWrBursts::15 138904 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 498 # Number of times write queue was full causing retry
< system.physmem.totGap 51558696478500 # Total gap between requests
---
> system.physmem.numWrRetry 518 # Number of times write queue was full causing retry
> system.physmem.totGap 51558689064500 # Total gap between requests
108c108
< system.physmem.readPktSize::6 1913796 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1875009 # Read request sizes (log2)
115,137c115,137
< system.physmem.writePktSize::6 2240512 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 2207309 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1116053 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 690517 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 59727 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 23803 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 610 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 601 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 516 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1044 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 687 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 311 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 237 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
163,186c163,186
< system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 28211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 35428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 83457 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 116558 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 125148 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 129368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 131713 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 136998 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 138946 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 135798 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 138971 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 141020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 132458 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 131167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 132874 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 144896 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 126854 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 129875 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 5862 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 4328 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 3576 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 3183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2815 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see
188,204c188,204
< system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::40 2421 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 2341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 2284 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1940 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1877 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1876 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1719 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1742 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1766 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1651 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 1663 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 1721 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 1785 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 1763 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 1973 # What write queue length does an incoming req see
206,230c206,230
< system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::58 1272 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 1576 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 2263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1461 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 706 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1209 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 930002 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 282.376133 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 167.748609 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 309.895017 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 369309 39.71% 39.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 231862 24.93% 64.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 88277 9.49% 74.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 51814 5.57% 79.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 37452 4.03% 83.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 26213 2.82% 86.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 21092 2.27% 88.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 17823 1.92% 90.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 86160 9.26% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 930002 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 116289 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 16.301748 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 52.348914 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 116283 99.99% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
234,244c234,244
< system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 116289 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 116288 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.983653 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.436820 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 18.158845 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::0-31 112077 96.38% 96.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-63 1857 1.60% 97.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-95 1248 1.07% 99.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-127 622 0.53% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-159 199 0.17% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-191 102 0.09% 99.84% # Writes before turning the bus around for reads
262,266c262,266
< system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads
< system.physmem.totQLat 71570448504 # Total ticks spent queuing
< system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 116288 # Writes before turning the bus around for reads
> system.physmem.totQLat 70130172482 # Total ticks spent queuing
> system.physmem.totMemAccLat 105674809982 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 9478570000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 36994.07 # Average queueing delay per DRAM burst
268,272c268,272
< system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 55744.07 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.74 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.33 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s
277,323c277,323
< system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing
< system.physmem.readRowHits 1560611 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes
< system.physmem.avgGap 12340030.64 # Average gap between requests
< system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ)
< system.physmem_0.averagePower 243.508122 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states
< system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states
< system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ)
< system.physmem_1.averagePower 243.602662 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.06 # Average write queue length when enqueuing
> system.physmem.readRowHits 1529656 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1643629 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.45 # Row buffer hit rate for writes
> system.physmem.avgGap 12556375.83 # Average gap between requests
> system.physmem.pageHitRate 77.33 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3321699360 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1765517490 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6716655120 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 5762509380 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 51680160480.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 50972480280 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 3129835680 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 101675150490 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 76210464000 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 12252798333465 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 12554072367525 # Total energy per rank (pJ)
> system.physmem_0.averagePower 243.490909 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 51438669732358 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 5228340749 # Time in different power states
> system.physmem_0.memoryStateTime::REF 21959504000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 51017233392500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 198464631937 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 92832806893 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 222971707921 # Time in different power states
> system.physmem_1.actEnergy 3318507780 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1763828715 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 6818742840 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5761011240 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 51892211280.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 51236173110 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3081583200 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 102800614920 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 76208995200 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 12252080918985 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 12555002532930 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.508949 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 51438215485769 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 5081473992 # Time in different power states
> system.physmem_1.memoryStateTime::REF 22049198000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 51014315527500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 198460418659 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 93344226239 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 225439539610 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
340,342c340,342
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
349,353c349,353
< system.cpu.branchPred.lookups 292003156 # Number of BP lookups
< system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits
---
> system.cpu.branchPred.lookups 292068322 # Number of BP lookups
> system.cpu.branchPred.condPredicted 199851600 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 13713135 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 209724607 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 131462172 # Number of BTB hits
355,361c355,361
< system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 62.683237 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 37751449 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 403092 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 8173057 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 6085508 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 2087549 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 802881 # Number of mispredicted indirect branches.
363c363
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
393,412c393,412
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 1433016 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 1435892 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 1435892 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31985 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277981 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 675717 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 760175 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 2830.191074 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 21829.241774 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-65535 752984 99.05% 99.05% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::65536-131071 4669 0.61% 99.67% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::131072-196607 1022 0.13% 99.80% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::196608-262143 473 0.06% 99.86% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::262144-327679 342 0.04% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.00% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::393216-458751 237 0.03% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::458752-524287 34 0.00% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::524288-589823 14 0.00% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::589824-655359 355 0.05% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::655360-720895 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
414,448c414,449
< system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkWaitTime::786432-851967 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 760175 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 806276 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 26170.477603 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 21293.851875 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 20136.943306 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 787717 97.70% 97.70% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 14855 1.84% 99.54% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 1801 0.22% 99.76% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 1099 0.14% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 441 0.05% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 139 0.02% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 81 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 59 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 68 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 806276 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 1071348818020 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.742300 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.520529 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 1067163432520 99.61% 99.61% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 2639718000 0.25% 99.86% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 767294500 0.07% 99.93% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 303032500 0.03% 99.96% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 205205000 0.02% 99.97% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 125461000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 48256000 0.00% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 92861500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::16-17 3532500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::18-19 24500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 1071348818020 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 277982 89.68% 89.68% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 31985 10.32% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 309967 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1435892 # Table walker requests started/completed, data/inst
450,451c451,452
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1435892 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309967 # Table walker requests started/completed, data/inst
453,454c454,455
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309967 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 1745859 # Table walker requests started/completed, data/inst
457,460c458,461
< system.cpu.dtb.read_hits 218874380 # DTB read hits
< system.cpu.dtb.read_misses 1009020 # DTB read misses
< system.cpu.dtb.write_hits 193682033 # DTB write hits
< system.cpu.dtb.write_misses 423996 # DTB write misses
---
> system.cpu.dtb.read_hits 219013119 # DTB read hits
> system.cpu.dtb.read_misses 1011306 # DTB read misses
> system.cpu.dtb.write_hits 193770026 # DTB write hits
> system.cpu.dtb.write_misses 424586 # DTB write misses
463c464
< system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu.dtb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID
465,467c466,468
< system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 88767 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 111 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 16184 # Number of TLB faults due to prefetch
469,471c470,472
< system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 219883400 # DTB read accesses
< system.cpu.dtb.write_accesses 194106029 # DTB write accesses
---
> system.cpu.dtb.perms_faults 85758 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 220024425 # DTB read accesses
> system.cpu.dtb.write_accesses 194194612 # DTB write accesses
473,476c474,477
< system.cpu.dtb.hits 412556413 # DTB hits
< system.cpu.dtb.misses 1433016 # DTB misses
< system.cpu.dtb.accesses 413989429 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 412783145 # DTB hits
> system.cpu.dtb.misses 1435892 # DTB misses
> system.cpu.dtb.accesses 414219037 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
506,540c507,539
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 178466 # Table walker walks requested
< system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 178617 # Table walker walks requested
> system.cpu.itb.walker.walksLong 178617 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1509 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 129197 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 20173 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 158444 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 1791.778168 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 17776.926489 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-65535 157195 99.21% 99.21% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::65536-131071 1061 0.67% 99.88% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::131072-196607 49 0.03% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::196608-262143 23 0.01% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::327680-393215 12 0.01% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::393216-458751 2 0.00% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::524288-589823 45 0.03% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::589824-655359 46 0.03% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 158444 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 150879 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 29477.399108 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 23380.752932 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 29925.423831 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 144789 95.96% 95.96% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 5035 3.34% 99.30% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 407 0.27% 99.57% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 355 0.24% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 85 0.06% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 65 0.04% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::589824-655359 82 0.05% 99.98% # Table walker service (enqueue to completion) latency
543,557c542,554
< system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkCompletionTime::total 150879 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 908136653272 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.948518 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.221299 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 46816690152 5.16% 5.16% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 861256760620 94.84% 99.99% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 62690500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::3 511000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 908136653272 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 129197 98.85% 98.85% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1509 1.15% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 130706 # Table walker page sizes translated
559,560c556,557
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178617 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 178617 # Table walker requests started/completed, data/inst
562,566c559,563
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 465485773 # ITB inst hits
< system.cpu.itb.inst_misses 178466 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130706 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 130706 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 309323 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 465622680 # ITB inst hits
> system.cpu.itb.inst_misses 178617 # ITB inst misses
573c570
< system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
---
> system.cpu.itb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID
575c572
< system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 62354 # Number of entries that have been flushed from TLB
579c576
< system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 442443 # Number of TLB faults due to permissions restrictions
582,592c579,589
< system.cpu.itb.inst_accesses 465664239 # ITB inst accesses
< system.cpu.itb.hits 465485773 # DTB hits
< system.cpu.itb.misses 178466 # DTB misses
< system.cpu.itb.accesses 465664239 # DTB accesses
< system.cpu.numPwrStateTransitions 34324 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.inst_accesses 465801297 # ITB inst accesses
> system.cpu.itb.hits 465622680 # DTB hits
> system.cpu.itb.misses 178617 # DTB misses
> system.cpu.itb.accesses 465801297 # DTB accesses
> system.cpu.numPwrStateTransitions 34330 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 17165 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 2940001446.310807 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 58531807829.842911 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 7841 45.68% 45.68% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.11% 99.79% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state
596,598c593,596
< system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
602,606c600,604
< system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2190964579 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::total 17165 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 1093565558075 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 50465124825925 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2187140442 # number of cpu cycles simulated
609,625c607,623
< system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 793785781 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1302631708 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 292068322 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 175299129 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1300965183 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29519562 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 4657753 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 25879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 11707627 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 1236073 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 927 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 465162073 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 6904477 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 52597 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 2127139004 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.717629 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.134701 # Number of instructions fetched each cycle (Total)
627,630c625,628
< system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 1399565872 65.80% 65.80% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 283601888 13.33% 79.13% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 89018844 4.18% 83.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 354952400 16.69% 100.00% # Number of instructions fetched each cycle (Total)
634,681c632,679
< system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 2127139004 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.133539 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.595587 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 615428593 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 884736584 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 543030027 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 73193860 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 10749940 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 41477613 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 4067608 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 1417243244 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 33090232 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 10749940 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 678230325 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 91937865 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 569242294 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 557610269 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 219368311 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1392930802 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 8136567 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 7440637 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 990068 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1113298 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 139552598 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 22837 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 1342716381 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2216807318 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1652527627 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1431919 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 1263732146 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 78984232 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 44095214 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 39617186 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 160769192 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 224047664 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 198221089 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12872997 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11132343 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1339626168 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 44413765 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1369656198 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 4234304 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 74015451 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 42135581 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 368828 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 2127139004 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.643896 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.914248 # Number of insts issued each cycle
683,688c681,686
< system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 1274738634 59.93% 59.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 452592629 21.28% 81.20% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 292740987 13.76% 94.97% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 96714663 4.55% 99.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10322849 0.49% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 29242 0.00% 100.00% # Number of insts issued each cycle
695c693
< system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 2127139004 # Number of insts issued each cycle
697,727c695,729
< system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 74109343 33.81% 33.81% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 90161 0.04% 33.85% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 26765 0.01% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 458 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 59034015 26.93% 60.80% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 85210307 38.88% 99.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 64791 0.03% 99.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 640346 0.29% 100.00% # attempts to use FU when none available
730,736c732,738
< system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 946221695 69.08% 69.08% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2942835 0.21% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 130438 0.01% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued
737a740
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued
739,756c742,760
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatMisc 112188 0.01% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued
760,761c764,767
< system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 223953856 16.35% 85.67% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 195515958 14.27% 99.94% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 118365 0.01% 99.95% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemWrite 660412 0.05% 100.00% # Type of FU issued
764,776c770,782
< system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued
< system.cpu.iq.rate 0.624874 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1369656198 # Type of FU issued
> system.cpu.iq.rate 0.626231 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 219176186 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.160023 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5087371498 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1457327579 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1347394357 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 2490391 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 913879 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 884967 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1587235373 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1596980 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5732534 # Number of loads that had data forwarded from stores
778,781c784,787
< system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 17426729 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 22539 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 187787 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 8018407 # Number of stores squashed
784,785c790,791
< system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 3639533 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 2053743 # Number of times an access to memory failed due to the cache being blocked
787,790c793,796
< system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 10749940 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 12646274 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 5267578 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1384326807 # Number of instructions dispatched to IQ
792,803c798,809
< system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 224047664 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 198221089 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 39077844 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 183202 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 4894696 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 187787 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4060868 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 6118781 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 10179649 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1355949241 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 219017773 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 12300796 # Number of squashed instructions skipped in execute
805,821c811,827
< system.cpu.iew.exec_nop 286256 # number of nop insts executed
< system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed
< system.cpu.iew.exec_branches 257403074 # Number of branches executed
< system.cpu.iew.exec_stores 193692050 # Number of stores executed
< system.cpu.iew.exec_rate 0.618622 # Inst execution rate
< system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 576070929 # num instructions producing a value
< system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle
---
> system.cpu.iew.exec_nop 286874 # number of nop insts executed
> system.cpu.iew.exec_refs 412797364 # number of memory reference insts executed
> system.cpu.iew.exec_branches 257488143 # Number of branches executed
> system.cpu.iew.exec_stores 193779591 # Number of stores executed
> system.cpu.iew.exec_rate 0.619964 # Inst execution rate
> system.cpu.iew.wb_sent 1349320641 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1348279324 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 576318139 # num instructions producing a value
> system.cpu.iew.wb_consumers 948680474 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.616458 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.607494 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 63090267 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 44044937 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 9703294 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 2112894773 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.620014 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.265043 # Number of insts commited each cycle
823,831c829,837
< system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1431908907 67.77% 67.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 397571073 18.82% 86.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 150815124 7.14% 93.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 44594147 2.11% 95.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 36107553 1.71% 97.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 18031210 0.85% 98.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 11307158 0.54% 98.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 5865302 0.28% 99.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 16694299 0.79% 100.00% # Number of insts commited each cycle
835,837c841,843
< system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 1114173091 # Number of instructions committed
< system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 2112894773 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 1114574366 # Number of instructions committed
> system.cpu.commit.committedOps 1310024478 # Number of ops (including micro ops) committed
839,845c845,851
< system.cpu.commit.refs 396642479 # Number of memory references committed
< system.cpu.commit.loads 206522790 # Number of loads committed
< system.cpu.commit.membars 9192719 # Number of memory barriers committed
< system.cpu.commit.branches 249090207 # Number of branches committed
< system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions.
< system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions.
< system.cpu.commit.function_calls 31104441 # Number of function calls committed.
---
> system.cpu.commit.refs 396823616 # Number of memory references committed
> system.cpu.commit.loads 206620934 # Number of loads committed
> system.cpu.commit.membars 9197183 # Number of memory barriers committed
> system.cpu.commit.branches 249169048 # Number of branches committed
> system.cpu.commit.fp_insts 873305 # Number of committed floating point instructions.
> system.cpu.commit.int_insts 1197213012 # Number of committed integer instructions.
> system.cpu.commit.function_calls 31117535 # Number of function calls committed.
847,852c853,858
< system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 910437285 69.50% 69.50% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 2553089 0.19% 69.69% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 104752 0.01% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction
853a860
> system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction
855,872c862,880
< system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction
---
> system.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction
876,877c884,887
< system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 206508219 15.76% 85.47% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 189547828 14.47% 99.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMemRead 112715 0.01% 99.95% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMemWrite 654854 0.05% 100.00% # Class of committed instruction
880,906c890,916
< system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction
< system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 3462896243 # The number of ROB reads
< system.cpu.rob.rob_writes 2759222856 # The number of ROB writes
< system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 1114173091 # Number of Instructions Simulated
< system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads
< system.cpu.int_regfile_writes 948614350 # number of integer regfile writes
< system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads
< system.cpu.fp_regfile_writes 763660 # number of floating regfile writes
< system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads
< system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes
< system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads
< system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 13773933 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks.
---
> system.cpu.commit.op_class_0::total 1310024478 # Class of committed instruction
> system.cpu.commit.bw_lim_events 16694299 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3459813368 # The number of ROB reads
> system.cpu.rob.rob_writes 2760364536 # The number of ROB writes
> system.cpu.timesIdled 9090851 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 60001438 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 100930240360 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 1114574366 # Number of Instructions Simulated
> system.cpu.committedOps 1310024478 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.962310 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.962310 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.509603 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.509603 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1610546046 # number of integer regfile reads
> system.cpu.int_regfile_writes 949011498 # number of integer regfile writes
> system.cpu.fp_regfile_reads 1420249 # number of floating regfile reads
> system.cpu.fp_regfile_writes 762248 # number of floating regfile writes
> system.cpu.cc_regfile_reads 314797086 # number of cc regfile reads
> system.cpu.cc_regfile_writes 315669715 # number of cc regfile writes
> system.cpu.misc_regfile_reads 3475493523 # number of misc regfile reads
> system.cpu.misc_regfile_writes 44962873 # number of misc regfile writes
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 13773422 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.982216 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 363599894 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 13773934 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 26.397679 # Average number of references to valid blocks.
908c918
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.982216 # Average occupied blocks per requestor
912,914c922,924
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
916,944c926,954
< system.cpu.dcache.tags.tag_accesses 1609792532 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1609792532 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 188105539 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 188105539 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 164299305 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 164299305 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits
< system.cpu.dcache.overall_hits::total 353204181 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 12867394 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 18868212 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 18868212 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 2064415 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 2064415 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1270711 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1270711 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 552556 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 552556 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 1610515756 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1610515756 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 188193818 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 188193818 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 164381838 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 164381838 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 464944 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 464944 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 334105 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 334105 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4846159 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4846159 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 5335614 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 5335614 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 352909761 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 352909761 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 353374705 # number of overall hits
> system.cpu.dcache.overall_hits::total 353374705 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 12874356 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 12874356 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 18866989 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 18866989 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 2064832 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 2064832 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1271634 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1271634 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 551153 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 551153 # number of LoadLockedReq misses
947,990c957,1000
< system.cpu.dcache.demand_misses::cpu.data 33006317 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 33006317 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 35070732 # number of overall misses
< system.cpu.dcache.overall_misses::total 35070732 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 226129752000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1113756894884 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30103485720 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 30103485720 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9429427500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 9429427500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 286500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 286500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 1369990132604 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 1369990132604 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 1369990132604 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 200972933 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 200972933 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 183167517 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 183167517 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2528713 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2528713 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605750 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1605750 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5395669 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 5395669 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 5333936 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 5333936 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 385746200 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 385746200 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 388274913 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 388274913 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064026 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.064026 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103011 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.103011 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816390 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.816390 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791350 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.791350 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102407 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102407 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 33012979 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 33012979 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 35077811 # number of overall misses
> system.cpu.dcache.overall_misses::total 35077811 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 223063102000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 223063102000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1108624638487 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1108624638487 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30055916196 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 30055916196 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9351183000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 9351183000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 1361743656683 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 1361743656683 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 1361743656683 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 1361743656683 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 201068174 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 201068174 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 183248827 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 183248827 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2529776 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2529776 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605739 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1605739 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5397312 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 5397312 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335622 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 5335622 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 385922740 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 385922740 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 388452516 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 388452516 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064030 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.064030 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102958 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.102958 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816211 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.816211 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791931 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.791931 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102116 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102116 # miss rate for LoadLockedReq accesses
993,1011c1003,1021
< system.cpu.dcache.demand_miss_rate::cpu.data 0.085565 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.085565 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.090324 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.090324 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17573.857768 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 17573.857768 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59028.216075 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 59028.216075 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23690.269243 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23690.269243 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 41506.907075 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39063.630967 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 29294390 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.085543 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.085543 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.090301 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.090301 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17326.156120 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17326.156120 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58760.019338 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 58760.019338 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23635.665762 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23635.665762 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16966.582782 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16966.582782 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35687.500000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35687.500000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41248.736041 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41248.736041 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 38820.656645 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 38820.656645 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 28867036 # number of cycles access was blocked
1013c1023
< system.cpu.dcache.blocked::no_mshrs 2113869 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 2109714 # number of cycles access was blocked
1015c1025
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.858186 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.682914 # average number of cycles each access was blocked
1017,1040c1027,1050
< system.cpu.dcache.writebacks::writebacks 10422476 # number of writebacks
< system.cpu.dcache.writebacks::total 10422476 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5755479 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 5755479 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15769683 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 15769683 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6881 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 6881 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 266620 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 266620 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 21532043 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 21532043 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 21532043 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 21532043 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111915 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7111915 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3098529 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 3098529 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2057605 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 2057605 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263830 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1263830 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 285936 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 285936 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 10417036 # number of writebacks
> system.cpu.dcache.writebacks::total 10417036 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5763320 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 5763320 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15767233 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 15767233 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7067 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 7067 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 267203 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 267203 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 21537620 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 21537620 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 21537620 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 21537620 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111036 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7111036 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099756 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 3099756 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2058030 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 2058030 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1264567 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1264567 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283950 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 283950 # number of LoadLockedReq MSHR misses
1043,1046c1053,1056
< system.cpu.dcache.demand_mshr_misses::cpu.data 11474274 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 11474274 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 13531879 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 13531879 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 11475359 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 11475359 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 13533389 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 13533389 # number of overall MSHR misses
1053,1074c1063,1084
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 35080858000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 35080858000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28539216720 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28539216720 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4259524000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4259524000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 278500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 278500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 312987144940 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 348068002940 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225685500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225685500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225685500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225685500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035387 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035387 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 117823858000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 117823858000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163535842014 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 163535842014 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34754745000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34754745000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28487682196 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28487682196 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4220692000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4220692000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 309847382210 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 309847382210 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 344602127210 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 344602127210 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225657500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225657500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225657500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225657500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035366 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035366 # mshr miss rate for ReadReq accesses
1077,1082c1087,1092
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813523 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813523 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787530 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787530 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052610 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052610 # mshr miss rate for LoadLockedReq accesses
1085,1114c1095,1124
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 16962264 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029735 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.029735 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034839 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.034839 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.155043 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.155043 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52757.649961 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52757.649961 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16887.385024 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16887.385024 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22527.617909 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22527.617909 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14864.208487 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14864.208487 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34687.500000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34687.500000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27001.105779 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 27001.105779 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25463.106633 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 25463.106633 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184781.476315 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184781.476315 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.658432 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.658432 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 16948036 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.953468 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 447400638 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 16948548 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 26.397579 # Average number of references to valid blocks.
1116c1126
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.953468 # Average occupied blocks per requestor
1120,1122c1130,1132
< system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id
1124,1163c1134,1173
< system.cpu.icache.tags.tag_accesses 481966186 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 481966186 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 447249112 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 447249112 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 447249112 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 447249112 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 447249112 # number of overall hits
< system.cpu.icache.overall_hits::total 447249112 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 17754074 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 17754074 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 17754074 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 17754074 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 17754074 # number of overall misses
< system.cpu.icache.overall_misses::total 17754074 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 238230546873 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 238230546873 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 238230546873 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 238230546873 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 238230546873 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 465003186 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 465003186 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 465003186 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 465003186 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 465003186 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 465003186 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038181 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.038181 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.038181 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.038181 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.038181 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.038181 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13418.359463 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13418.359463 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13418.359463 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13418.359463 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 22063 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 482089545 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 482089545 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 447400638 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 447400638 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 447400638 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 447400638 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 447400638 # number of overall hits
> system.cpu.icache.overall_hits::total 447400638 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 17740135 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 17740135 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 17740135 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 17740135 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 17740135 # number of overall misses
> system.cpu.icache.overall_misses::total 17740135 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 237745686369 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 237745686369 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 237745686369 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 237745686369 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 237745686369 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 237745686369 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 465140773 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 465140773 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 465140773 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 465140773 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 465140773 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 465140773 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038139 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.038139 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.038139 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.038139 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.038139 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.038139 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13401.571429 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13401.571429 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13401.571429 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13401.571429 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 22866 # number of cycles access was blocked
1165c1175
< system.cpu.icache.blocked::no_mshrs 1484 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 1431 # number of cycles access was blocked
1167c1177
< system.cpu.icache.avg_blocked_cycles::no_mshrs 14.867251 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 15.979036 # average number of cycles each access was blocked
1169,1182c1179,1192
< system.cpu.icache.writebacks::writebacks 16962264 # number of writebacks
< system.cpu.icache.writebacks::total 16962264 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791074 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 791074 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 791074 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 791074 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 791074 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 791074 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963000 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 16963000 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 16963000 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 16963000 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 16963000 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 16963000 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 16948036 # number of writebacks
> system.cpu.icache.writebacks::total 16948036 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791363 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 791363 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 791363 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 791363 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 791363 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 791363 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16948772 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16948772 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16948772 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16948772 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16948772 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16948772 # number of overall MSHR misses
1187,1192c1197,1202
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 214024505887 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 214024505887 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 214024505887 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 214024505887 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 214024505887 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 214024505887 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213645244880 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 213645244880 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213645244880 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 213645244880 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213645244880 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 213645244880 # number of overall MSHR miss cycles
1197,1208c1207,1218
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036479 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.036479 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.036479 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12617.137646 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12617.137646 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036438 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.036438 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036438 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.036438 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12605.352463 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12605.352463 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12605.352463 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12605.352463 # average overall mshr miss latency
1213,1218c1223,1228
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 2409655 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65438.820576 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 59303582 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2471799 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 23.992073 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 2368264 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65438.912903 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 59342443 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2431405 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 24.406647 # Average number of references to valid blocks.
1220,1252c1230,1263
< system.cpu.l2cache.tags.occ_blocks::writebacks 9434.053113 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 385.411867 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 416.493163 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.865899 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.143952 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005881 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006355 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101789 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.740539 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 61860 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 284 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1041 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5649 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54812 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943909 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 508249108 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 508249108 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1295823 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 305430 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1601253 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 10422476 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 10422476 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 16959660 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 16959660 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 39331 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 39331 # number of UpgradeReq hits
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9464.122529 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 393.883765 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.035779 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6680.528058 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48467.342772 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.144411 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006010 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006608 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101937 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.739553 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998519 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 62889 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1015 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5647 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55838 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959610 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 508088213 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 508088213 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1306072 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 309439 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1615511 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 10417036 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 10417036 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 16945412 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 16945412 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 39342 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 39342 # number of UpgradeReq hits
1255,1277c1266,1288
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1728598 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1728598 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16865372 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 16865372 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8990828 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 8990828 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 668361 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 668361 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 1295823 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 305430 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 16865372 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 10719426 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 29186051 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 1295823 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 305430 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 16865372 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 10719426 # number of overall hits
< system.cpu.l2cache.overall_hits::total 29186051 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10808 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8922 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 19730 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 4027 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 4027 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1735264 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1735264 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16852583 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 16852583 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 9020162 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 9020162 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 672287 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 672287 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 1306072 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 309439 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 16852583 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 10755426 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 29223520 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 1306072 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 309439 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 16852583 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 10755426 # number of overall hits
> system.cpu.l2cache.overall_hits::total 29223520 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10647 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8959 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 19606 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 4043 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 4043 # number of UpgradeReq misses
1280,1331c1291,1342
< system.cpu.l2cache.ReadExReq_misses::cpu.data 1343031 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 1343031 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 97409 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 97409 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 448173 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 448173 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 595469 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 595469 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 10808 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 8922 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 97409 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1791204 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1908343 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 10808 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 8922 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 97409 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1791204 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1908343 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1486458000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 980532000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2466990000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73290500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 73290500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 192000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 192000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140749219500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 140749219500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10783493000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 10783493000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49949086500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 49949086500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 569000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 569000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1486458000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 980532000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 10783493000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 190698306000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 203948789000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1486458000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 980532000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 10783493000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 190698306000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 203948789000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1306631 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 314352 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1620983 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 10422476 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 10422476 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 16959660 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 16959660 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43358 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 43358 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 1337553 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 1337553 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95970 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 95970 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 416410 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 416410 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 592280 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 592280 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 10647 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 8959 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 95970 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1753963 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1869539 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 10647 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 8959 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 95970 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1753963 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1869539 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1464838500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 979350000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2444188500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73726500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 73726500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 139978365500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 139978365500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10559308500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 10559308500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46880784000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 46880784000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 453500 # number of InvalidateReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::total 453500 # number of InvalidateReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1464838500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 979350000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 10559308500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 186859149500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 199862646500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1464838500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 979350000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 10559308500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 186859149500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 199862646500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1316719 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 318398 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1635117 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 10417036 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 10417036 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 16945412 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 16945412 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43385 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 43385 # number of UpgradeReq accesses(hits+misses)
1334,1356c1345,1367
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 3071629 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 3071629 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16962781 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 16962781 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439001 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 9439001 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263830 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1263830 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1306631 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 314352 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 16962781 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 12510630 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 31094394 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1306631 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 314352 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 16962781 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 12510630 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 31094394 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008272 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028382 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.012172 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.092878 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.092878 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072817 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 3072817 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16948553 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 16948553 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9436572 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 9436572 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1264567 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1264567 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1316719 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 318398 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 16948553 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 12509389 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 31093059 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1316719 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 318398 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16948553 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 12509389 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 31093059 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008086 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028138 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093189 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093189 # miss rate for UpgradeReq accesses
1359,1401c1370,1412
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437237 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.437237 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005743 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005743 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047481 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047481 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.471162 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.471162 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008272 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028382 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005743 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.143175 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.061373 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008272 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028382 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005743 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.143175 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.061373 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137533.123612 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109900.470746 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 125037.506336 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18199.776509 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18199.776509 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 48000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 48000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104799.680350 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104799.680350 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110703.251240 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110703.251240 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111450.458863 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111450.458863 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.955549 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.955549 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 106872.186499 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 106872.186499 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435286 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.435286 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005662 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005662 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.468366 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.468366 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008086 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028138 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005662 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.140212 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.060127 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008086 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028138 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005662 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.140212 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.060127 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137582.276698 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109314.655654 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 124665.332041 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18235.592382 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18235.592382 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104652.574889 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104652.574889 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110027.180369 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110027.180369 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112583.232871 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112583.232871 # average ReadSharedReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.765685 # average InvalidateReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.765685 # average InvalidateReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 106904.775188 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137582.276698 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109314.655654 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110027.180369 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106535.399835 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 106904.775188 # average overall miss latency
1408,1411c1419,1420
< system.cpu.l2cache.writebacks::writebacks 2133882 # number of writebacks
< system.cpu.l2cache.writebacks::total 2133882 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 2100679 # number of writebacks
> system.cpu.l2cache.writebacks::total 2100679 # number of writebacks
1414d1422
< system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits
1416,1417c1424
< system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
1419,1426c1426,1433
< system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10808 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8921 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 19729 # number of ReadReq MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4027 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 4027 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10647 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8959 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 19606 # number of ReadReq MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4043 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 4043 # number of UpgradeReq MSHR misses
1429,1446c1436,1453
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1343031 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1343031 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 97409 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 97409 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 448152 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 448152 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 595469 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 595469 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10808 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8921 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 97409 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1791183 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1908321 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10808 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8921 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 97409 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1791183 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1908321 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1337553 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1337553 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95970 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95970 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 416389 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 416389 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 592280 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 592280 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10647 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8959 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 95970 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1753942 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1869518 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10647 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8959 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 95970 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1753942 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1869518 # number of overall MSHR misses
1455,1479c1462,1486
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 891304000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2269682000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76822000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76822000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 182500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 182500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127318887048 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127318887048 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9809383542 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9809383542 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 45465885070 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 45465885070 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12316948002 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12316948002 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 891304000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9809383542 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172784772118 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 184863837660 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 891304000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9809383542 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172784772118 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 184863837660 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 889760000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2248128500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77144500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77144500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126602809555 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126602809555 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9599588543 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9599588543 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42714761570 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42714761570 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12256085002 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12256085002 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 889760000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9599588543 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 169317571125 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 181165288168 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1358368500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 889760000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9599588543 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 169317571125 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 181165288168 # number of overall MSHR miss cycles
1481,1482c1488,1489
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804372500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290860000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804371500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290859000 # number of ReadReq MSHR uncacheable cycles
1484,1488c1491,1495
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804372500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290860000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012171 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804371500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290859000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011991 # mshr miss rate for ReadReq accesses
1491,1492c1498,1499
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093189 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093189 # mshr miss rate for UpgradeReq accesses
1495,1537c1502,1544
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435286 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435286 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005662 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044125 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044125 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.468366 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.468366 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060127 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.060127 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 114665.332041 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19081.004205 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19081.004205 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94652.555491 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94652.555491 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100026.972418 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100026.972418 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102583.789605 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102583.789605 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20693.059030 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20693.059030 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency
1539,1540c1546,1547
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.439748 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.824137 # average ReadReq mshr uncacheable latency
1542,1548c1549,1555
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.660583 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.026802 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 62411777 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 31689071 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2067 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2067 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1550,1552c1557,1559
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 2264077 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 28650207 # Transaction distribution
1555,1558c1562,1565
< system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 12517715 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 16948036 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 3623971 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 43388 # Transaction distribution
1560,1581c1567,1588
< system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 3035082 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 43396 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 3072817 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 3072817 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 16948772 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 9438927 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1295442 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1264567 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50887949 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41543699 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 787064 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3057144 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 96275856 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169722400 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467531890 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2547184 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10533752 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 3650335226 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 2976479 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 139099568 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 35465406 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.159793 # Request fanout histogram
1583,1584c1590,1591
< system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 34535454 97.38% 97.38% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 929952 2.62% 100.00% # Request fanout histogram
1589,1590c1596,1597
< system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 35465406 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 59274617984 # Layer occupancy (ticks)
1592c1599
< system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1490379 # Layer occupancy (ticks)
1594c1601
< system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 25454807175 # Layer occupancy (ticks)
1596c1603
< system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 19473878402 # Layer occupancy (ticks)
1598c1605
< system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 469039231 # Layer occupancy (ticks)
1600c1607
< system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1741050209 # Layer occupancy (ticks)
1602,1604c1609,1611
< system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40296 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40296 # Transaction distribution
1621,1622c1628,1629
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes)
1625c1632
< system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes)
1640,1641c1647,1648
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes)
1644,1645c1651,1652
< system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 41892500 # Layer occupancy (ticks)
1667c1674
< system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25201500 # Layer occupancy (ticks)
1669c1676
< system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36497000 # Layer occupancy (ticks)
1671c1678
< system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 569294464 # Layer occupancy (ticks)
1675c1682
< system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147710000 # Layer occupancy (ticks)
1679,1681c1686,1688
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115471 # number of replacements
< system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115456 # number of replacements
> system.iocache.tags.tagsinuse 10.450363 # Cycle average of tags in use
1683c1690
< system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks.
1686,1690c1693,1697
< system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::realview.ethernet 3.528284 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.922079 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.432630 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.653148 # Average percentage of cache occupancy
1694,1696c1701,1703
< system.iocache.tags.tag_accesses 1039767 # Number of tag accesses
< system.iocache.tags.data_accesses 1039767 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1039632 # Number of tag accesses
> system.iocache.tags.data_accesses 1039632 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
1698,1699c1705,1706
< system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses
1705,1706c1712,1713
< system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115530 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115475 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115515 # number of demand (read+write) misses
1708,1709c1715,1716
< system.iocache.overall_misses::realview.ide 115490 # number of overall misses
< system.iocache.overall_misses::total 115530 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115475 # number of overall misses
> system.iocache.overall_misses::total 115515 # number of overall misses
1711,1712c1718,1719
< system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1862993006 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1868078506 # number of ReadReq miss cycles
1715,1716c1722,1723
< system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13281113958 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13281113958 # number of WriteLineReq miss cycles
1718,1719c1725,1726
< system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15144106964 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15149543464 # number of demand (read+write) miss cycles
1721,1722c1728,1729
< system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15144106964 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15149543464 # number of overall miss cycles
1724,1725c1731,1732
< system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses)
1731,1732c1738,1739
< system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115475 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115515 # number of demand (read+write) accesses
1734,1735c1741,1742
< system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115475 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115515 # number of overall (read+write) accesses
1750,1751c1757,1758
< system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 211439.451368 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 211130.030063 # average ReadReq miss latency
1754,1755c1761,1762
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124513.556195 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 124513.556195 # average WriteLineReq miss latency
1757,1758c1764,1765
< system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131147.846288 # average overall miss latency
1760,1762c1767,1769
< system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131147.846288 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 44063 # number of cycles access was blocked
1764c1771
< system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked
1766c1773
< system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 12.567884 # average number of cycles each access was blocked
1771,1772c1778,1779
< system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses
1778,1779c1785,1786
< system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115475 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115515 # number of demand (read+write) MSHR misses
1781,1782c1788,1789
< system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115475 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115515 # number of overall MSHR misses
1784,1785c1791,1792
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1422443006 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1425678506 # number of ReadReq MSHR miss cycles
1788,1789c1795,1796
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7941073224 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 7941073224 # number of WriteLineReq MSHR miss cycles
1791,1792c1798,1799
< system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9363516230 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9366952730 # number of demand (read+write) MSHR miss cycles
1794,1795c1801,1802
< system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9363516230 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9366952730 # number of overall MSHR miss cycles
1810,1811c1817,1818
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 161439.451368 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 161130.030063 # average ReadReq mshr miss latency
1814,1815c1821,1822
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74449.422711 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74449.422711 # average WriteLineReq mshr miss latency
1817,1818c1824,1825
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency
1820,1824c1827,1831
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 5064341 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 2518493 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 2998 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1828c1835
< system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
1830c1837
< system.membus.trans_dist::ReadResp 629139 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 595799 # Transaction distribution
1833,1835c1840,1842
< system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution
< system.membus.trans_dist::CleanEvict 283345 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 2207309 # Transaction distribution
> system.membus.trans_dist::CleanEvict 275154 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4609 # Transaction distribution
1838,1841c1845,1848
< system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 1336997 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1336997 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 540813 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 698937 # Transaction distribution
1845,1849c1852,1856
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6748871 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6878533 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237677 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237677 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7116210 # Packet count per connected master and slave (bytes)
1853,1862c1860,1869
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 2841 # Total snoops (count)
< system.membus.snoopTraffic 181312 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 2712040 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254375884 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254545938 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253504 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7253504 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 261799442 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 2809 # Total snoops (count)
> system.membus.snoopTraffic 179264 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 2670049 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.012702 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.111987 # Request fanout histogram
1864,1865c1871,1872
< system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram
< system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 2636133 98.73% 98.73% # Request fanout histogram
> system.membus.snoop_fanout::1 33916 1.27% 100.00% # Request fanout histogram
1870,1871c1877,1878
< system.membus.snoop_fanout::total 2712040 # Request fanout histogram
< system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2670049 # Request fanout histogram
> system.membus.reqLayer0.occupancy 104027000 # Layer occupancy (ticks)
1875c1882
< system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5600000 # Layer occupancy (ticks)
1877c1884
< system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 14297533259 # Layer occupancy (ticks)
1879c1886
< system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 10011316944 # Layer occupancy (ticks)
1881c1888
< system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 44794763 # Layer occupancy (ticks)
1883,1889c1890,1896
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
1896,1897c1903,1904
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
1940,1946c1947,1953
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
1951,1962c1958,1969
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states
1964c1971
< system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 17165 # number of quiesce instructions executed