3,5c3,5
< sim_seconds 51.558015 # Number of seconds simulated
< sim_ticks 51558014828000 # Number of ticks simulated
< final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.558698 # Number of seconds simulated
> sim_ticks 51558697863000 # Number of ticks simulated
> final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 133865 # Simulator instruction rate (inst/s)
< host_op_rate 157345 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6235119796 # Simulator tick rate (ticks/s)
< host_mem_usage 696436 # Number of bytes of host memory used
< host_seconds 8268.97 # Real time elapsed on the host
< sim_insts 1106923026 # Number of instructions simulated
< sim_ops 1301083589 # Number of ops (including micro ops) simulated
---
> host_inst_rate 167711 # Simulator instruction rate (inst/s)
> host_op_rate 197118 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 7760882097 # Simulator tick rate (ticks/s)
> host_mem_usage 692228 # Number of bytes of host memory used
> host_seconds 6643.41 # Real time elapsed on the host
> sim_insts 1114173091 # Number of instructions simulated
> sim_ops 1309536110 # Number of ops (including micro ops) simulated
16,25c16,25
< system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory
< system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory
> system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory
27,34c27,34
< system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory
36,45c36,45
< system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s)
47,65c47,65
< system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1904301 # Number of read requests accepted
< system.physmem.writeReqs 2205028 # Number of write requests accepted
< system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue
< system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1935081 # Number of read requests accepted
> system.physmem.writeReqs 2243085 # Number of write requests accepted
> system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue
> system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one
67,98c67,98
< system.physmem.perBankRdBursts::0 114327 # Per bank write bursts
< system.physmem.perBankRdBursts::1 123692 # Per bank write bursts
< system.physmem.perBankRdBursts::2 118245 # Per bank write bursts
< system.physmem.perBankRdBursts::3 117057 # Per bank write bursts
< system.physmem.perBankRdBursts::4 115229 # Per bank write bursts
< system.physmem.perBankRdBursts::5 125268 # Per bank write bursts
< system.physmem.perBankRdBursts::6 115683 # Per bank write bursts
< system.physmem.perBankRdBursts::7 119593 # Per bank write bursts
< system.physmem.perBankRdBursts::8 115543 # Per bank write bursts
< system.physmem.perBankRdBursts::9 144676 # Per bank write bursts
< system.physmem.perBankRdBursts::10 112600 # Per bank write bursts
< system.physmem.perBankRdBursts::11 120122 # Per bank write bursts
< system.physmem.perBankRdBursts::12 113965 # Per bank write bursts
< system.physmem.perBankRdBursts::13 118266 # Per bank write bursts
< system.physmem.perBankRdBursts::14 113146 # Per bank write bursts
< system.physmem.perBankRdBursts::15 116309 # Per bank write bursts
< system.physmem.perBankWrBursts::0 135142 # Per bank write bursts
< system.physmem.perBankWrBursts::1 141643 # Per bank write bursts
< system.physmem.perBankWrBursts::2 136917 # Per bank write bursts
< system.physmem.perBankWrBursts::3 137997 # Per bank write bursts
< system.physmem.perBankWrBursts::4 135684 # Per bank write bursts
< system.physmem.perBankWrBursts::5 143871 # Per bank write bursts
< system.physmem.perBankWrBursts::6 135153 # Per bank write bursts
< system.physmem.perBankWrBursts::7 138864 # Per bank write bursts
< system.physmem.perBankWrBursts::8 135935 # Per bank write bursts
< system.physmem.perBankWrBursts::9 142790 # Per bank write bursts
< system.physmem.perBankWrBursts::10 134947 # Per bank write bursts
< system.physmem.perBankWrBursts::11 140191 # Per bank write bursts
< system.physmem.perBankWrBursts::12 134987 # Per bank write bursts
< system.physmem.perBankWrBursts::13 137976 # Per bank write bursts
< system.physmem.perBankWrBursts::14 134592 # Per bank write bursts
< system.physmem.perBankWrBursts::15 136075 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 114857 # Per bank write bursts
> system.physmem.perBankRdBursts::1 123887 # Per bank write bursts
> system.physmem.perBankRdBursts::2 121380 # Per bank write bursts
> system.physmem.perBankRdBursts::3 115864 # Per bank write bursts
> system.physmem.perBankRdBursts::4 115150 # Per bank write bursts
> system.physmem.perBankRdBursts::5 124779 # Per bank write bursts
> system.physmem.perBankRdBursts::6 116343 # Per bank write bursts
> system.physmem.perBankRdBursts::7 120532 # Per bank write bursts
> system.physmem.perBankRdBursts::8 117169 # Per bank write bursts
> system.physmem.perBankRdBursts::9 147715 # Per bank write bursts
> system.physmem.perBankRdBursts::10 116324 # Per bank write bursts
> system.physmem.perBankRdBursts::11 125031 # Per bank write bursts
> system.physmem.perBankRdBursts::12 116553 # Per bank write bursts
> system.physmem.perBankRdBursts::13 122187 # Per bank write bursts
> system.physmem.perBankRdBursts::14 118707 # Per bank write bursts
> system.physmem.perBankRdBursts::15 117850 # Per bank write bursts
> system.physmem.perBankWrBursts::0 135590 # Per bank write bursts
> system.physmem.perBankWrBursts::1 141676 # Per bank write bursts
> system.physmem.perBankWrBursts::2 140587 # Per bank write bursts
> system.physmem.perBankWrBursts::3 138605 # Per bank write bursts
> system.physmem.perBankWrBursts::4 137623 # Per bank write bursts
> system.physmem.perBankWrBursts::5 144276 # Per bank write bursts
> system.physmem.perBankWrBursts::6 136529 # Per bank write bursts
> system.physmem.perBankWrBursts::7 140386 # Per bank write bursts
> system.physmem.perBankWrBursts::8 138327 # Per bank write bursts
> system.physmem.perBankWrBursts::9 145050 # Per bank write bursts
> system.physmem.perBankWrBursts::10 137213 # Per bank write bursts
> system.physmem.perBankWrBursts::11 144076 # Per bank write bursts
> system.physmem.perBankWrBursts::12 138694 # Per bank write bursts
> system.physmem.perBankWrBursts::13 142077 # Per bank write bursts
> system.physmem.perBankWrBursts::14 140963 # Per bank write bursts
> system.physmem.perBankWrBursts::15 139115 # Per bank write bursts
100,101c100,101
< system.physmem.numWrRetry 125 # Number of times write queue was full causing retry
< system.physmem.totGap 51558013451500 # Total gap between requests
---
> system.physmem.numWrRetry 498 # Number of times write queue was full causing retry
> system.physmem.totGap 51558696478500 # Total gap between requests
108c108
< system.physmem.readPktSize::6 1883016 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1913796 # Read request sizes (log2)
115,130c115,130
< system.physmem.writePktSize::6 2202455 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 2240512 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see
132,133c132,133
< system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see
135,137c135,137
< system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
163,230c163,231
< system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
233,279c234,266
< system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads
< system.physmem.totQLat 42075497859 # Total ticks spent queuing
< system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads
> system.physmem.totQLat 71570448504 # Total ticks spent queuing
> system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst
281,285c268,272
< system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s
290,326c277,323
< system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing
< system.physmem.readRowHits 1533744 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes
< system.physmem.avgGap 12546577.18 # Average gap between requests
< system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.831109 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.833118 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing
> system.physmem.readRowHits 1560611 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes
> system.physmem.avgGap 12340030.64 # Average gap between requests
> system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ)
> system.physmem_0.averagePower 243.508122 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states
> system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states
> system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ)
> system.physmem_1.averagePower 243.602662 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
343,345c340,342
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
352,356c349,353
< system.cpu.branchPred.lookups 290131106 # Number of BP lookups
< system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits
---
> system.cpu.branchPred.lookups 292003156 # Number of BP lookups
> system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits
358,364c355,361
< system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches.
366c363
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
396,449c393,448
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.dtb.walker.walks 1423094 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.dtb.walker.walks 1433016 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst
451,452c450,451
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst
454,455c453,454
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst
458,461c457,460
< system.cpu.dtb.read_hits 217549636 # DTB read hits
< system.cpu.dtb.read_misses 1002675 # DTB read misses
< system.cpu.dtb.write_hits 192429615 # DTB write hits
< system.cpu.dtb.write_misses 420419 # DTB write misses
---
> system.cpu.dtb.read_hits 218874380 # DTB read hits
> system.cpu.dtb.read_misses 1009020 # DTB read misses
> system.cpu.dtb.write_hits 193682033 # DTB write hits
> system.cpu.dtb.write_misses 423996 # DTB write misses
464,468c463,467
< system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch
470,472c469,471
< system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 218552311 # DTB read accesses
< system.cpu.dtb.write_accesses 192850034 # DTB write accesses
---
> system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 219883400 # DTB read accesses
> system.cpu.dtb.write_accesses 194106029 # DTB write accesses
474,477c473,476
< system.cpu.dtb.hits 409979251 # DTB hits
< system.cpu.dtb.misses 1423094 # DTB misses
< system.cpu.dtb.accesses 411402345 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.hits 412556413 # DTB hits
> system.cpu.dtb.misses 1433016 # DTB misses
> system.cpu.dtb.accesses 413989429 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
507,554c506,557
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.itb.walker.walks 177767 # Table walker walks requested
< system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.itb.walker.walks 178466 # Table walker walks requested
> system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated
556,557c559,560
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst
559,563c562,566
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 462600046 # ITB inst hits
< system.cpu.itb.inst_misses 177767 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 465485773 # ITB inst hits
> system.cpu.itb.inst_misses 178466 # ITB inst misses
570,572c573,575
< system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB
576c579
< system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions
579,589c582,592
< system.cpu.itb.inst_accesses 462777813 # ITB inst accesses
< system.cpu.itb.hits 462600046 # DTB hits
< system.cpu.itb.misses 177767 # DTB misses
< system.cpu.itb.accesses 462777813 # DTB accesses
< system.cpu.numPwrStateTransitions 34262 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state
---
> system.cpu.itb.inst_accesses 465664239 # ITB inst accesses
> system.cpu.itb.hits 465485773 # DTB hits
> system.cpu.itb.misses 178466 # DTB misses
> system.cpu.itb.accesses 465664239 # DTB accesses
> system.cpu.numPwrStateTransitions 34324 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
593,598c596,600
< system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state
600,604c602,606
< system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2131080190 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2190964579 # number of cpu cycles simulated
607,623c609,625
< system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total)
625,628c627,630
< system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total)
632,679c634,681
< system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle
681,686c683,688
< system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle
693c695
< system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle
695,725c697,727
< system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available
728,731c730,733
< system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued
754c756
< system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued
758,759c760,761
< system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued
762,774c764,776
< system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued
< system.cpu.iq.rate 0.638398 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued
> system.cpu.iq.rate 0.624874 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores
776,779c778,781
< system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed
782,783c784,785
< system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked
785,788c787,790
< system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ
790,801c792,803
< system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute
803,819c805,821
< system.cpu.iew.exec_nop 285536 # number of nop insts executed
< system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed
< system.cpu.iew.exec_branches 255680172 # Number of branches executed
< system.cpu.iew.exec_stores 192439435 # Number of stores executed
< system.cpu.iew.exec_rate 0.631996 # Inst execution rate
< system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 574929948 # num instructions producing a value
< system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle
---
> system.cpu.iew.exec_nop 286256 # number of nop insts executed
> system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed
> system.cpu.iew.exec_branches 257403074 # Number of branches executed
> system.cpu.iew.exec_stores 193692050 # Number of stores executed
> system.cpu.iew.exec_rate 0.618622 # Inst execution rate
> system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 576070929 # num instructions producing a value
> system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle
821,829c823,831
< system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle
833,835c835,837
< system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 1106923026 # Number of instructions committed
< system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 1114173091 # Number of instructions committed
> system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed
837,843c839,845
< system.cpu.commit.refs 394099255 # Number of memory references committed
< system.cpu.commit.loads 205210646 # Number of loads committed
< system.cpu.commit.membars 9122435 # Number of memory barriers committed
< system.cpu.commit.branches 247396089 # Number of branches committed
< system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions.
< system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions.
< system.cpu.commit.function_calls 30973786 # Number of function calls committed.
---
> system.cpu.commit.refs 396642479 # Number of memory references committed
> system.cpu.commit.loads 206522790 # Number of loads committed
> system.cpu.commit.membars 9192719 # Number of memory barriers committed
> system.cpu.commit.branches 249090207 # Number of branches committed
> system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions.
> system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions.
> system.cpu.commit.function_calls 31104441 # Number of function calls committed.
845,847c847,849
< system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction
870c872
< system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction
---
> system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction
874,875c876,877
< system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction
878,908c880,910
< system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction
< system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 3398675710 # The number of ROB reads
< system.cpu.rob.rob_writes 2741957858 # The number of ROB writes
< system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 1106923026 # Number of Instructions Simulated
< system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads
< system.cpu.int_regfile_writes 942915680 # number of integer regfile writes
< system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads
< system.cpu.fp_regfile_writes 762380 # number of floating regfile writes
< system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads
< system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes
< system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads
< system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 13662519 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
---
> system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction
> system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3462896243 # The number of ROB reads
> system.cpu.rob.rob_writes 2759222856 # The number of ROB writes
> system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 1114173091 # Number of Instructions Simulated
> system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads
> system.cpu.int_regfile_writes 948614350 # number of integer regfile writes
> system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads
> system.cpu.fp_regfile_writes 763660 # number of floating regfile writes
> system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads
> system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes
> system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads
> system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 13773933 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
910,912c912,914
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
914,1009c916,1011
< system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 4793284 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 5278947 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 5278947 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 350624733 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 350624733 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 351088116 # number of overall hits
< system.cpu.dcache.overall_hits::total 351088116 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 12788061 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 12788061 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 18648516 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 18648516 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 2041461 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 2041461 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1270506 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1270506 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 548369 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 548369 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 32707083 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 32707083 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 34748544 # number of overall misses
< system.cpu.dcache.overall_misses::total 34748544 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 205827865000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 1003464059741 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 29968640002 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 29968640002 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8933513500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 8933513500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 300500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 300500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 1239260564743 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 1239260564743 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 199734647 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 199734647 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 181992675 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 181992675 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 2504844 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 2504844 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5341653 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 5341653 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 5278956 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 5278956 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 383331816 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 383331816 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 385836660 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 385836660 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064025 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.064025 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102468 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.102468 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.815005 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.815005 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791842 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.791842 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102659 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102659 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 1609792532 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1609792532 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 188105539 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 188105539 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 164299305 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 164299305 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits
> system.cpu.dcache.overall_hits::total 353204181 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 12867394 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 18868212 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 18868212 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 2064415 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 2064415 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1270711 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1270711 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 552556 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 552556 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 33006317 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 33006317 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 35070732 # number of overall misses
> system.cpu.dcache.overall_misses::total 35070732 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 226129752000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 1113756894884 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30103485720 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 30103485720 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9429427500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 9429427500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 286500 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 286500 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 1369990132604 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 1369990132604 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 1369990132604 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 200972933 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 200972933 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 183167517 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 183167517 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2528713 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2528713 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605750 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1605750 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5395669 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 5395669 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 5333936 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 5333936 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 385746200 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 385746200 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 388274913 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 388274913 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064026 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.064026 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103011 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.103011 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816390 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.816390 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791350 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.791350 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102407 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102407 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.085565 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.085565 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.090324 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.090324 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17573.857768 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 17573.857768 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59028.216075 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 59028.216075 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23690.269243 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23690.269243 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 41506.907075 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39063.630967 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 29294390 # number of cycles access was blocked
1011c1013
< system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 2113869 # number of cycles access was blocked
1013c1015
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.858186 # average number of cycles each access was blocked
1015,1044c1017,1046
< system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks
< system.cpu.dcache.writebacks::total 10319802 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 10422476 # number of writebacks
> system.cpu.dcache.writebacks::total 10422476 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5755479 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 5755479 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15769683 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 15769683 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6881 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 6881 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 266620 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 266620 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 21532043 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 21532043 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 21532043 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 21532043 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111915 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7111915 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3098529 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 3098529 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2057605 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 2057605 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263830 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1263830 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 285936 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 285936 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 11474274 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 11474274 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 13531879 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 13531879 # number of overall MSHR misses
1051,1116c1053,1118
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 16891256 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 35080858000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 35080858000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28539216720 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28539216720 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4259524000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4259524000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 278500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 278500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 312987144940 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 348068002940 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225685500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225685500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225685500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225685500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035387 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035387 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 16962264 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
1118,1120c1120,1122
< system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
1122,1161c1124,1163
< system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits
< system.cpu.icache.overall_hits::total 444441322 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 17679342 # number of overall misses
< system.cpu.icache.overall_misses::total 17679342 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 234300237389 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 234300237389 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 234300237389 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 234300237389 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.038257 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.038257 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.038257 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13252.769101 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13252.769101 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 16371 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 481966186 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 481966186 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 447249112 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 447249112 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 447249112 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 447249112 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 447249112 # number of overall hits
> system.cpu.icache.overall_hits::total 447249112 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 17754074 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 17754074 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 17754074 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 17754074 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 17754074 # number of overall misses
> system.cpu.icache.overall_misses::total 17754074 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 238230546873 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 238230546873 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 238230546873 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 238230546873 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 238230546873 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 465003186 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 465003186 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 465003186 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 465003186 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 465003186 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 465003186 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038181 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.038181 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.038181 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.038181 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.038181 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.038181 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13418.359463 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13418.359463 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13418.359463 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13418.359463 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 22063 # number of cycles access was blocked
1163c1165
< system.cpu.icache.blocked::no_mshrs 1212 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 1484 # number of cycles access was blocked
1165c1167
< system.cpu.icache.avg_blocked_cycles::no_mshrs 13.507426 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 14.867251 # average number of cycles each access was blocked
1167,1180c1169,1182
< system.cpu.icache.writebacks::writebacks 16891256 # number of writebacks
< system.cpu.icache.writebacks::total 16891256 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 787348 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 787348 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 787348 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 787348 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 787348 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 787348 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16891994 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 16891994 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 16891994 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 16891994 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 16891994 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 16891994 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 16962264 # number of writebacks
> system.cpu.icache.writebacks::total 16962264 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791074 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 791074 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 791074 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 791074 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 791074 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 791074 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963000 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16963000 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16963000 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16963000 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16963000 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16963000 # number of overall MSHR misses
1185,1275c1187,1277
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 210691534398 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 210691534398 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1610722500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1610722500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1610722500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 1610722500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036553 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.036553 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.036553 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 2372905 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 505094110 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 505094110 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1274032 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 302472 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1576504 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 10319802 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 10319802 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 16888637 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 16888637 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 38922 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 38922 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1712070 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1712070 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16794801 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 16794801 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8925946 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 8925946 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 673558 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 673558 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 1274032 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 302472 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 16794801 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 10638016 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 29009321 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 1274032 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 302472 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 16794801 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 10638016 # number of overall hits
< system.cpu.l2cache.overall_hits::total 29009321 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10437 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8742 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 19179 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 4078 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 4078 # number of UpgradeReq misses
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 214024505887 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 214024505887 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 214024505887 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 214024505887 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 214024505887 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 214024505887 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036479 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.036479 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.036479 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12617.137646 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12617.137646 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 2409655 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65438.820576 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 59303582 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2471799 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 23.992073 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2677802000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 9434.053113 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 385.411867 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 416.493163 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.865899 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.143952 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005881 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006355 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101789 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.740539 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 61860 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 284 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1041 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5649 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54812 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943909 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 508249108 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 508249108 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1295823 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 305430 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1601253 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 10422476 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 10422476 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 16959660 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 16959660 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 39331 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 39331 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1728598 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1728598 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16865372 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 16865372 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8990828 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 8990828 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 668361 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 668361 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 1295823 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 305430 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 16865372 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 10719426 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 29186051 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 1295823 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 305430 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 16865372 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 10719426 # number of overall hits
> system.cpu.l2cache.overall_hits::total 29186051 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10808 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8922 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 19730 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 4027 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 4027 # number of UpgradeReq misses
1278,1399c1280,1401
< system.cpu.l2cache.ReadExReq_misses::cpu.data 1333352 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 1333352 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 96984 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 96984 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 428025 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 428025 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 590099 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 590099 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 10437 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 8742 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 96984 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 1761377 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1877540 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 10437 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 8742 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 96984 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 1761377 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1877540 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 936727000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 780169000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1716896000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73235500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 73235500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123861773500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 123861773500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8301693500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 8301693500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38723437000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 38723437000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 483000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 483000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 936727000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 780169000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 8301693500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 162585210500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 172603800000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 936727000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 780169000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 8301693500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 162585210500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 172603800000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1284469 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 311214 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1595683 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 10319802 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 10319802 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 16888637 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 16888637 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43000 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 43000 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 3045422 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 3045422 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16891785 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 16891785 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9353971 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 9353971 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263657 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1263657 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1284469 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 311214 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 16891785 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 12399393 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 30886861 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1284469 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 311214 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 16891785 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 12399393 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 30886861 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008126 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028090 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.012019 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.094837 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.094837 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.444444 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.444444 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437822 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.437822 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005741 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005741 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045759 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045759 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.466977 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.466977 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008126 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028090 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005741 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.142053 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.060788 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008126 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028090 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005741 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.142053 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.060788 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89750.598831 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89243.765729 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 89519.578706 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17958.680726 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17958.680726 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92895.029595 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92895.029595 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.818507 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.818507 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 1343031 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 1343031 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 97409 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 97409 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 448173 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 448173 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 595469 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 595469 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 10808 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 8922 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 97409 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1791204 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1908343 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 10808 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 8922 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 97409 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1791204 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1908343 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1486458000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 980532000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2466990000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73290500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 73290500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 192000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 192000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140749219500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 140749219500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10783493000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 10783493000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49949086500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 49949086500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 569000 # number of InvalidateReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::total 569000 # number of InvalidateReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1486458000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 980532000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 10783493000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 190698306000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 203948789000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1486458000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 980532000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 10783493000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 190698306000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 203948789000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1306631 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 314352 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1620983 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 10422476 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 10422476 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 16959660 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 16959660 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43358 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 43358 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 3071629 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 3071629 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16962781 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 16962781 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439001 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 9439001 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263830 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1263830 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1306631 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 314352 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 16962781 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 12510630 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 31094394 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1306631 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 314352 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16962781 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 12510630 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 31094394 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008272 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028382 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.012172 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.092878 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.092878 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437237 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.437237 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005743 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005743 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047481 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047481 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.471162 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.471162 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008272 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028382 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005743 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.143175 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.061373 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008272 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028382 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005743 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.143175 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.061373 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137533.123612 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109900.470746 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 125037.506336 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18199.776509 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18199.776509 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 48000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 48000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104799.680350 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104799.680350 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110703.251240 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110703.251240 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111450.458863 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111450.458863 # average ReadSharedReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.955549 # average InvalidateReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.955549 # average InvalidateReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 106872.186499 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 106872.186499 # average overall miss latency
1406,1407c1408,1411
< system.cpu.l2cache.writebacks::writebacks 2095825 # number of writebacks
< system.cpu.l2cache.writebacks::total 2095825 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 2133882 # number of writebacks
> system.cpu.l2cache.writebacks::total 2133882 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1409a1414
> system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits
1411c1416,1417
< system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits
1413,1420c1419,1426
< system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10437 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8742 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 19179 # number of ReadReq MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4078 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 4078 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10808 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8921 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 19729 # number of ReadReq MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4027 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 4027 # number of UpgradeReq MSHR misses
1423,1440c1429,1446
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1333352 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 1333352 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 96984 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 96984 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 428004 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 428004 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590099 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 590099 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10437 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8742 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 96984 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 1761356 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1877519 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10437 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8742 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 96984 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 1761356 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1877519 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1343031 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1343031 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 97409 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 97409 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 448152 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 448152 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 595469 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 595469 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10808 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8921 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 97409 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1791183 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1908321 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10808 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8921 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 97409 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1791183 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1908321 # number of overall MSHR misses
1449,1482c1455,1488
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 832356501 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 692749000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1525105501 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77850000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77850000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7331831049 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7331831049 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34442081593 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34442081593 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12207320002 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12207320002 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 832356501 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 692749000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7331831049 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 832356501 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 692749000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7331831049 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 891304000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2269682000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76822000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76822000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 182500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 182500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127318887048 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127318887048 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9809383542 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9809383542 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 45465885070 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 45465885070 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12316948002 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12316948002 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 891304000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9809383542 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172784772118 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 184863837660 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 891304000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9809383542 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172784772118 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 184863837660 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804372500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290860000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804372500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290860000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012171 # mshr miss rate for ReadReq accesses
1485,1542c1491,1548
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1544,1546c1550,1552
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution
1549,1575c1555,1581
< system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 2999840 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 3035082 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram
1577,1578c1583,1584
< system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram
1583,1584c1589,1590
< system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks)
1586c1592
< system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks)
1588c1594
< system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks)
1590c1596
< system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks)
1592c1598
< system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks)
1594c1600
< system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks)
1596,1598c1602,1604
< system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40300 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40300 # Transaction distribution
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
1615,1616c1621,1622
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes)
1619c1625
< system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
1634,1635c1640,1641
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes)
1638,1639c1644,1645
< system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks)
1643c1649
< system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks)
1657c1663
< system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
1661c1667
< system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks)
1663c1669
< system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks)
1665c1671
< system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks)
1669c1675
< system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks)
1673,1675c1679,1681
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115465 # number of replacements
< system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115471 # number of replacements
> system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use
1677c1683
< system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks.
1679,1684c1685,1690
< system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy
1688,1690c1694,1696
< system.iocache.tags.tag_accesses 1039668 # Number of tag accesses
< system.iocache.tags.data_accesses 1039668 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1039767 # Number of tag accesses
> system.iocache.tags.data_accesses 1039767 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
1692,1693c1698,1699
< system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses
1699,1700c1705,1706
< system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115519 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115530 # number of demand (read+write) misses
1702,1706c1708,1712
< system.iocache.overall_misses::realview.ide 115479 # number of overall misses
< system.iocache.overall_misses::total 115519 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 115490 # number of overall misses
> system.iocache.overall_misses::total 115530 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles
1709,1716c1715,1722
< system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles
1718,1719c1724,1725
< system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses)
1725,1726c1731,1732
< system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses
1728,1729c1734,1735
< system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses
1743,1745c1749,1751
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency
1748,1756c1754,1762
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked
1758c1764
< system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked
1760c1766
< system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked
1765,1766c1771,1772
< system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses
1772,1773c1778,1779
< system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses
1775,1779c1781,1785
< system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles
1782,1789c1788,1795
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles
1803,1805c1809,1811
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency
1808,1818c1814,1824
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1822c1828
< system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
1824c1830
< system.membus.trans_dist::ReadResp 608005 # Transaction distribution
---
> system.membus.trans_dist::ReadResp 629139 # Transaction distribution
1827,1829c1833,1835
< system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution
< system.membus.trans_dist::CleanEvict 284620 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution
> system.membus.trans_dist::CleanEvict 283345 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
1832,1835c1838,1841
< system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution
< system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution
1839,1843c1845,1849
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes)
1847,1856c1853,1862
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 2809 # Total snoops (count)
< system.membus.snoopTraffic 179264 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 2675908 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 2841 # Total snoops (count)
> system.membus.snoopTraffic 181312 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 2712040 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram
1858,1859c1864,1865
< system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram
< system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram
> system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram
1864,1865c1870,1871
< system.membus.snoop_fanout::total 2675908 # Request fanout histogram
< system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2712040 # Request fanout histogram
> system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks)
1869c1875
< system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks)
1871c1877
< system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks)
1873c1879
< system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks)
1875c1881
< system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks)
1877,1883c1883,1889
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
1890,1891c1896,1897
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
1934,1940c1940,1946
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
1945,1956c1951,1962
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
1958c1964
< system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed