7,11c7,11
< host_inst_rate 139665 # Simulator instruction rate (inst/s)
< host_op_rate 164109 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 8451911555 # Simulator tick rate (ticks/s)
< host_mem_usage 688288 # Number of bytes of host memory used
< host_seconds 6072.84 # Real time elapsed on the host
---
> host_inst_rate 139449 # Simulator instruction rate (inst/s)
> host_op_rate 163855 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 8438816943 # Simulator tick rate (ticks/s)
> host_mem_usage 688284 # Number of bytes of host memory used
> host_seconds 6082.27 # Real time elapsed on the host
582c582
< system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss
596c596
< system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total)
600c600
< system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total)
607c607
< system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total)
610c610
< system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle
620c620
< system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle
625c625
< system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename
630c630
< system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full
632,634c632,634
< system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups
637c637
< system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing
640c640
< system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer
652c652
< system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle
656c656
< system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle
668c668
< system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle
741c741
< system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads
758c758
< system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked
792c792
< system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle
796c796
< system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle
808c808
< system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle
855c855
< system.cpu.rob.rob_reads 2588836198 # The number of ROB reads
---
> system.cpu.rob.rob_reads 2588836134 # The number of ROB reads
857,858c857,858
< system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling
872c872
< system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
902,905c902,905
< system.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits
< system.cpu.dcache.overall_hits::total 275804158 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits
> system.cpu.dcache.overall_hits::total 276127624 # number of overall hits
918,921c918,921
< system.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses
< system.cpu.dcache.overall_misses::total 22005420 # number of overall misses
---
> system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses
> system.cpu.dcache.overall_misses::total 23239410 # number of overall misses
932,935c932,935
< system.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles
948,951c948,951
< system.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses
964,967c964,967
< system.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses
978,981c978,981
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency
988,989d987
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
1000,1003c998,1001
< system.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 13703391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 13703391 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 13703391 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits
1016,1019c1014,1017
< system.cpu.dcache.demand_mshr_misses::cpu.data 7131279 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7131279 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 8295216 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 8295216 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses
1038,1041c1036,1039
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles
1044,1047c1042,1043
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles
1060,1063c1056,1059
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses
1076,1079c1072,1075
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency
1082,1086c1078,1079
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
1145,1146d1137
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
1191d1181
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1386,1387d1375
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1463,1464d1450
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836145500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836145500 # number of WriteReq MSHR uncacheable cycles
1466,1467c1452,1453
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607041000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025804500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770895500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189659000 # number of overall MSHR uncacheable cycles
1523,1524d1508
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency
1526,1528c1510,1511
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency
1685,1686c1668,1669
< system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115518 # number of demand (read+write) misses
1688,1689c1671,1672
< system.iocache.overall_misses::realview.ide 8814 # number of overall misses
< system.iocache.overall_misses::total 8854 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115478 # number of overall misses
> system.iocache.overall_misses::total 115518 # number of overall misses
1698,1699c1681,1682
< system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles
1701,1702c1684,1685
< system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles
1711,1712c1694,1695
< system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses
1714,1715c1697,1698
< system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses
1737,1738c1720,1721
< system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency
1740,1741c1723,1724
< system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency
1748,1749d1730
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1760,1761c1741,1742
< system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses
1763,1764c1744,1745
< system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses
1773,1774c1754,1755
< system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles
1776,1777c1757,1758
< system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles
1799,1800c1780,1781
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1802,1804c1783,1784
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1850c1830
< system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks)
< host_inst_rate 139665 # Simulator instruction rate (inst/s)
< host_op_rate 164109 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 8451911555 # Simulator tick rate (ticks/s)
< host_mem_usage 688288 # Number of bytes of host memory used
< host_seconds 6072.84 # Real time elapsed on the host
---
> host_inst_rate 139449 # Simulator instruction rate (inst/s)
> host_op_rate 163855 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 8438816943 # Simulator tick rate (ticks/s)
> host_mem_usage 688284 # Number of bytes of host memory used
> host_seconds 6082.27 # Real time elapsed on the host
582c582
< system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss
596c596
< system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 1571640484 # Number of instructions fetched each cycle (Total)
600c600
< system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 1013991341 64.52% 64.52% # Number of instructions fetched each cycle (Total)
607c607
< system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 1571640484 # Number of instructions fetched each cycle (Total)
610c610
< system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 526349563 # Number of cycles decode is idle
620c620
< system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 571291991 # Number of cycles rename is idle
625c625
< system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 1065686033 # Number of instructions processed by rename
630c630
< system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 63514970 # Number of times rename has blocked due to SQ full
632,634c632,634
< system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 1013378727 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1640198295 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1259502849 # Number of integer rename lookups
637c637
< system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 66192424 # Number of HB maps that are undone due to squashing
640c640
< system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 101754923 # count of insts added to the skid buffer
652c652
< system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1571640484 # Number of insts issued each cycle
656c656
< system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 924076917 58.80% 58.80% # Number of insts issued each cycle
668c668
< system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1571640484 # Number of insts issued each cycle
741c741
< system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 3828710820 # Number of integer instruction queue reads
758c758
< system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 1438756 # Number of times an access to memory failed due to the cache being blocked
792c792
< system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 1559580657 # Number of insts commited each cycle
796c796
< system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1047836774 67.19% 67.19% # Number of insts commited each cycle
808c808
< system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1559580657 # Number of insts commited each cycle
855c855
< system.cpu.rob.rob_reads 2588836198 # The number of ROB reads
---
> system.cpu.rob.rob_reads 2588836134 # The number of ROB reads
857,858c857,858
< system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 8176249 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 59503583 # Total number of cycles that the CPU has spent unscheduled due to idling
872c872
< system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
902,905c902,905
< system.cpu.dcache.demand_hits::cpu.data 275426405 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 275426405 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 275804158 # number of overall hits
< system.cpu.dcache.overall_hits::total 275804158 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 275749871 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 275749871 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 276127624 # number of overall hits
> system.cpu.dcache.overall_hits::total 276127624 # number of overall hits
918,921c918,921
< system.cpu.dcache.demand_misses::cpu.data 20834670 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 20834670 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 22005420 # number of overall misses
< system.cpu.dcache.overall_misses::total 22005420 # number of overall misses
---
> system.cpu.dcache.demand_misses::cpu.data 22068660 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 22068660 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 23239410 # number of overall misses
> system.cpu.dcache.overall_misses::total 23239410 # number of overall misses
932,935c932,935
< system.cpu.dcache.demand_miss_latency::cpu.data 612836911827 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 612836911827 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 612836911827 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 612836911827 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 665180471800 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 665180471800 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 665180471800 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 665180471800 # number of overall miss cycles
948,951c948,951
< system.cpu.dcache.demand_accesses::cpu.data 296261075 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 296261075 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 297809578 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 297809578 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 297818531 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 297818531 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 299367034 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 299367034 # number of overall (read+write) accesses
964,967c964,967
< system.cpu.dcache.demand_miss_rate::cpu.data 0.070325 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.070325 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.073891 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.073891 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074101 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074101 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.077628 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.077628 # miss rate for overall accesses
978,981c978,981
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29414.284547 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29414.284547 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 27849.362195 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 27849.362195 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 30141.407399 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 30141.407399 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28622.950058 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28622.950058 # average overall miss latency
988,989d987
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
1000,1003c998,1001
< system.cpu.dcache.demand_mshr_hits::cpu.data 13703391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 13703391 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 13703391 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 13703391 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 13710521 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 13710521 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 13710521 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 13710521 # number of overall MSHR hits
1016,1019c1014,1017
< system.cpu.dcache.demand_mshr_misses::cpu.data 7131279 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7131279 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 8295216 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 8295216 # number of overall MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 8358139 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 8358139 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9522076 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9522076 # number of overall MSHR misses
1038,1041c1036,1039
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162503876437 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 186189032937 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213174289910 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 213174289910 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236859446410 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 236859446410 # number of overall MSHR miss cycles
1044,1047c1042,1043
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228178464 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420200464 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420200464 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192022000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192022000 # number of overall MSHR uncacheable cycles
1060,1063c1056,1059
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027854 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027854 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028065 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.028065 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031807 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031807 # mshr miss rate for overall accesses
1076,1079c1072,1075
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.350783 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.350783 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency
1082,1086c1078,1079
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184834.356125 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.084395 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
1145,1146d1137
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
1191d1181
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1386,1387d1375
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1463,1464d1450
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836145500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836145500 # number of WriteReq MSHR uncacheable cycles
1466,1467c1452,1453
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607041000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025804500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770895500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189659000 # number of overall MSHR uncacheable cycles
1523,1524d1508
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency
1526,1528c1510,1511
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency
1685,1686c1668,1669
< system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115478 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115518 # number of demand (read+write) misses
1688,1689c1671,1672
< system.iocache.overall_misses::realview.ide 8814 # number of overall misses
< system.iocache.overall_misses::total 8854 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115478 # number of overall misses
> system.iocache.overall_misses::total 115518 # number of overall misses
1698,1699c1681,1682
< system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15094464998 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15099887998 # number of demand (read+write) miss cycles
1701,1702c1684,1685
< system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15094464998 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15099887998 # number of overall miss cycles
1711,1712c1694,1695
< system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115478 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115518 # number of demand (read+write) accesses
1714,1715c1697,1698
< system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115478 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115518 # number of overall (read+write) accesses
1737,1738c1720,1721
< system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 130714.589917 # average overall miss latency
1740,1741c1723,1724
< system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 130712.906337 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 130714.589917 # average overall miss latency
1748,1749d1730
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1760,1761c1741,1742
< system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115478 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115518 # number of demand (read+write) MSHR misses
1763,1764c1744,1745
< system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115478 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115518 # number of overall MSHR misses
1773,1774c1754,1755
< system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9315478547 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9318901547 # number of demand (read+write) MSHR miss cycles
1776,1777c1757,1758
< system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9315478547 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9318901547 # number of overall MSHR miss cycles
1799,1800c1780,1781
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1802,1804c1783,1784
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1850c1830
< system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks)