3,5c3,5
< sim_seconds 51.323721 # Number of seconds simulated
< sim_ticks 51323721423000 # Number of ticks simulated
< final_tick 51323721423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.562170 # Number of seconds simulated
> sim_ticks 51562169701000 # Number of ticks simulated
> final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 120356 # Simulator instruction rate (inst/s)
< host_op_rate 141420 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 7238849372 # Simulator tick rate (ticks/s)
< host_mem_usage 678076 # Number of bytes of host memory used
< host_seconds 7090.04 # Real time elapsed on the host
< sim_insts 853325819 # Number of instructions simulated
< sim_ops 1002674190 # Number of ops (including micro ops) simulated
---
> host_inst_rate 82472 # Simulator instruction rate (inst/s)
> host_op_rate 96938 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3850541751 # Simulator tick rate (ticks/s)
> host_mem_usage 726532 # Number of bytes of host memory used
> host_seconds 13390.89 # Real time elapsed on the host
> sim_insts 1104366834 # Number of instructions simulated
> sim_ops 1298086167 # Number of ops (including micro ops) simulated
16,24c16,24
< system.physmem.bytes_read::cpu.dtb.walker 203200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 189632 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 5727200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 73778504 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory
< system.physmem.bytes_read::total 80318312 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 5727200 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5727200 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 68723904 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory
> system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory
26,33c26,33
< system.physmem.bytes_written::total 68744484 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 3175 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 2963 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 105440 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 1152802 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1270939 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1073811 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory
35,97c35,97
< system.physmem.num_writes::total 1076384 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 3959 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 3695 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 111590 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1437513 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8179 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1564935 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 111590 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 111590 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1339028 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1339429 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1339028 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 3959 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 3695 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 111590 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1437914 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8179 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2904365 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1270939 # Number of read requests accepted
< system.physmem.writeReqs 1076384 # Number of write requests accepted
< system.physmem.readBursts 1270939 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1076384 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 81299584 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 40512 # Total number of bytes read from write queue
< system.physmem.bytesWritten 68742976 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 80318312 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 68744484 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 633 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 142017 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 76590 # Per bank write bursts
< system.physmem.perBankRdBursts::1 80112 # Per bank write bursts
< system.physmem.perBankRdBursts::2 82312 # Per bank write bursts
< system.physmem.perBankRdBursts::3 76894 # Per bank write bursts
< system.physmem.perBankRdBursts::4 75148 # Per bank write bursts
< system.physmem.perBankRdBursts::5 84486 # Per bank write bursts
< system.physmem.perBankRdBursts::6 75307 # Per bank write bursts
< system.physmem.perBankRdBursts::7 76047 # Per bank write bursts
< system.physmem.perBankRdBursts::8 76921 # Per bank write bursts
< system.physmem.perBankRdBursts::9 104197 # Per bank write bursts
< system.physmem.perBankRdBursts::10 75653 # Per bank write bursts
< system.physmem.perBankRdBursts::11 81028 # Per bank write bursts
< system.physmem.perBankRdBursts::12 74845 # Per bank write bursts
< system.physmem.perBankRdBursts::13 77383 # Per bank write bursts
< system.physmem.perBankRdBursts::14 76622 # Per bank write bursts
< system.physmem.perBankRdBursts::15 76761 # Per bank write bursts
< system.physmem.perBankWrBursts::0 64108 # Per bank write bursts
< system.physmem.perBankWrBursts::1 67910 # Per bank write bursts
< system.physmem.perBankWrBursts::2 69982 # Per bank write bursts
< system.physmem.perBankWrBursts::3 67432 # Per bank write bursts
< system.physmem.perBankWrBursts::4 65959 # Per bank write bursts
< system.physmem.perBankWrBursts::5 70786 # Per bank write bursts
< system.physmem.perBankWrBursts::6 64733 # Per bank write bursts
< system.physmem.perBankWrBursts::7 66187 # Per bank write bursts
< system.physmem.perBankWrBursts::8 67287 # Per bank write bursts
< system.physmem.perBankWrBursts::9 71812 # Per bank write bursts
< system.physmem.perBankWrBursts::10 65064 # Per bank write bursts
< system.physmem.perBankWrBursts::11 69201 # Per bank write bursts
< system.physmem.perBankWrBursts::12 65082 # Per bank write bursts
< system.physmem.perBankWrBursts::13 66370 # Per bank write bursts
< system.physmem.perBankWrBursts::14 66024 # Per bank write bursts
< system.physmem.perBankWrBursts::15 66172 # Per bank write bursts
---
> system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 2467786 # Number of read requests accepted
> system.physmem.writeReqs 2184211 # Number of write requests accepted
> system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue
> system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 149005 # Per bank write bursts
> system.physmem.perBankRdBursts::1 156339 # Per bank write bursts
> system.physmem.perBankRdBursts::2 155955 # Per bank write bursts
> system.physmem.perBankRdBursts::3 150628 # Per bank write bursts
> system.physmem.perBankRdBursts::4 148084 # Per bank write bursts
> system.physmem.perBankRdBursts::5 159303 # Per bank write bursts
> system.physmem.perBankRdBursts::6 149188 # Per bank write bursts
> system.physmem.perBankRdBursts::7 152515 # Per bank write bursts
> system.physmem.perBankRdBursts::8 150862 # Per bank write bursts
> system.physmem.perBankRdBursts::9 179370 # Per bank write bursts
> system.physmem.perBankRdBursts::10 150320 # Per bank write bursts
> system.physmem.perBankRdBursts::11 155893 # Per bank write bursts
> system.physmem.perBankRdBursts::12 152080 # Per bank write bursts
> system.physmem.perBankRdBursts::13 155961 # Per bank write bursts
> system.physmem.perBankRdBursts::14 150556 # Per bank write bursts
> system.physmem.perBankRdBursts::15 150970 # Per bank write bursts
> system.physmem.perBankWrBursts::0 132106 # Per bank write bursts
> system.physmem.perBankWrBursts::1 138501 # Per bank write bursts
> system.physmem.perBankWrBursts::2 137398 # Per bank write bursts
> system.physmem.perBankWrBursts::3 135602 # Per bank write bursts
> system.physmem.perBankWrBursts::4 133392 # Per bank write bursts
> system.physmem.perBankWrBursts::5 140433 # Per bank write bursts
> system.physmem.perBankWrBursts::6 132940 # Per bank write bursts
> system.physmem.perBankWrBursts::7 137025 # Per bank write bursts
> system.physmem.perBankWrBursts::8 135656 # Per bank write bursts
> system.physmem.perBankWrBursts::9 141181 # Per bank write bursts
> system.physmem.perBankWrBursts::10 134433 # Per bank write bursts
> system.physmem.perBankWrBursts::11 138339 # Per bank write bursts
> system.physmem.perBankWrBursts::12 136301 # Per bank write bursts
> system.physmem.perBankWrBursts::13 138853 # Per bank write bursts
> system.physmem.perBankWrBursts::14 135122 # Per bank write bursts
> system.physmem.perBankWrBursts::15 134659 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
< system.physmem.totGap 51323720227500 # Total gap between requests
---
> system.physmem.numWrRetry 21 # Number of times write queue was full causing retry
> system.physmem.totGap 51562168447500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 1249654 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 2446501 # Read request sizes (log2)
114,130c114,130
< system.physmem.writePktSize::6 1073811 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 646219 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 339232 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 151287 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 128129 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 684 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 489 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 533 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 812 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 936 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 392 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 166 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 2181638 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see
132,138c132,138
< system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 11927 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 14439 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 31518 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 44897 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 53343 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 63481 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 63532 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 67021 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 67803 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 70464 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 69167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 70329 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 66867 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 85010 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 86471 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 65847 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 69713 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 62929 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1006 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 572 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 637 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 503 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 386 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 415 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 475 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 414 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 338 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 319 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 278 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 294 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 265 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 481355 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 311.708207 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 178.914901 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 339.146013 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 186832 38.81% 38.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 113175 23.51% 62.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 45398 9.43% 71.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 23450 4.87% 76.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 18101 3.76% 80.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 11671 2.42% 82.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 10460 2.17% 84.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 8315 1.73% 86.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 63953 13.29% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 481355 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 61522 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 20.647411 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 265.936082 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 61519 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes
232,266c232,264
< system.physmem.rdPerTurnAround::total 61522 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 61522 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.458942 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.948779 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 6.823778 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 58490 95.07% 95.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 664 1.08% 96.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 448 0.73% 96.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 190 0.31% 97.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 308 0.50% 97.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 527 0.86% 98.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 143 0.23% 98.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 33 0.05% 98.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 36 0.06% 98.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 18 0.03% 98.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 32 0.05% 98.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 22 0.04% 99.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 426 0.69% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 45 0.07% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 33 0.05% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 35 0.06% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 13 0.02% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 31 0.05% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads
269,274c267,271
< system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 61522 # Writes before turning the bus around for reads
< system.physmem.totQLat 31530968444 # Total ticks spent queuing
< system.physmem.totMemAccLat 55349205944 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 6351530000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 24821.55 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads
> system.physmem.totQLat 61876185756 # Total ticks spent queuing
> system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst
276,280c273,277
< system.physmem.avgMemAccLat 43571.55 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.58 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.34 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.56 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.34 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s
282,284c279,281
< system.physmem.busUtil 0.02 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
---
> system.physmem.busUtil 0.05 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
286,303c283,300
< system.physmem.avgWrQLen 22.31 # Average write queue length when enqueuing
< system.physmem.readRowHits 1047361 # Number of row buffer hits during reads
< system.physmem.writeRowHits 815697 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 75.94 # Row buffer hit rate for writes
< system.physmem.avgGap 21864788.20 # Average gap between requests
< system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 1828287720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 997577625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 4889757600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3480388560 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1226219398425 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 29718601656750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 34308233025720 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.467372 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 49439480717043 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1713811840000 # Time in different power states
---
> system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
> system.physmem.readRowHits 2056722 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes
> system.physmem.avgGap 11083878.27 # Average gap between requests
> system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.871313 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states
305c302
< system.physmem_0.memoryStateTime::ACT 170428636707 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states
307,317c304,314
< system.physmem_1.actEnergy 1810756080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 988011750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 5018598000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3479837760 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3352215959040 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1228704019020 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 29716422156750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 34308639338400 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.475289 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 49435820968594 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1713811840000 # Time in different power states
---
> system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.883816 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states
319c316
< system.physmem_1.memoryStateTime::ACT 174088371406 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states
343,347c340,344
< system.cpu.branchPred.lookups 225557622 # Number of BP lookups
< system.cpu.branchPred.condPredicted 150824960 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12221670 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 159273353 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 104130221 # Number of BTB hits
---
> system.cpu.branchPred.lookups 288825634 # Number of BP lookups
> system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits
349,351c346,348
< system.cpu.branchPred.BTBHitPct 65.378307 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 30957399 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 344598 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions.
382,435c379,429
< system.cpu.dtb.walker.walks 951838 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 951838 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16475 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156308 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 435006 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 516832 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 1986.510123 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 12487.736879 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-32767 508349 98.36% 98.36% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::32768-65535 5443 1.05% 99.41% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::65536-98303 1244 0.24% 99.65% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::98304-131071 1085 0.21% 99.86% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::131072-163839 165 0.03% 99.89% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::163840-196607 178 0.03% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::196608-229375 121 0.02% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::229376-262143 54 0.01% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::262144-294911 95 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::294912-327679 7 0.00% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::327680-360447 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::360448-393215 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::393216-425983 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::425984-458751 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 516832 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 485267 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 21943.293074 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 17562.054008 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 15786.896980 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 475094 97.90% 97.90% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 9290 1.91% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 546 0.11% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 199 0.04% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 82 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 20 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 485267 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 776250627376 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.722476 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.519579 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 774163165376 99.73% 99.73% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 1120728500 0.14% 99.88% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 435636500 0.06% 99.93% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 187638500 0.02% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 148036000 0.02% 99.97% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 113935000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 26323500 0.00% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 52542500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::16-17 2621500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 776250627376 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 156309 90.46% 90.46% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 16475 9.54% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 172784 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951838 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walks 1430156 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst
437,438c431,432
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951838 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172784 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst
440,441c434,435
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172784 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 1124622 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst
444,448c438,442
< system.cpu.dtb.read_hits 170417440 # DTB read hits
< system.cpu.dtb.read_misses 677013 # DTB read misses
< system.cpu.dtb.write_hits 148384109 # DTB write hits
< system.cpu.dtb.write_misses 274825 # DTB write misses
< system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
---
> system.cpu.dtb.read_hits 217117628 # DTB read hits
> system.cpu.dtb.read_misses 1002788 # DTB read misses
> system.cpu.dtb.write_hits 192115888 # DTB write hits
> system.cpu.dtb.write_misses 427368 # DTB write misses
> system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
450,452c444,446
< system.cpu.dtb.flush_tlb_mva_asid 39714 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1025 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 72556 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB
454c448
< system.cpu.dtb.prefetch_faults 10696 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch
456,458c450,452
< system.cpu.dtb.perms_faults 70061 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 171094453 # DTB read accesses
< system.cpu.dtb.write_accesses 148658934 # DTB write accesses
---
> system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 218120416 # DTB read accesses
> system.cpu.dtb.write_accesses 192543256 # DTB write accesses
460,462c454,456
< system.cpu.dtb.hits 318801549 # DTB hits
< system.cpu.dtb.misses 951838 # DTB misses
< system.cpu.dtb.accesses 319753387 # DTB accesses
---
> system.cpu.dtb.hits 409233516 # DTB hits
> system.cpu.dtb.misses 1430156 # DTB misses
> system.cpu.dtb.accesses 410663672 # DTB accesses
492,508c486,502
< system.cpu.itb.walker.walks 162167 # Table walker walks requested
< system.cpu.itb.walker.walksLong 162167 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 122178 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 17760 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 144407 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 1087.128740 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 7079.961036 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-32767 143546 99.40% 99.40% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::32768-65535 491 0.34% 99.74% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::65536-98303 245 0.17% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::98304-131071 86 0.06% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::131072-163839 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu.itb.walker.walks 177415 # Table walker walks requested
> system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
510,523c504,517
< system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 144407 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 141371 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 27408.566821 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 23535.121999 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 16611.953111 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-65535 138940 98.28% 98.28% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-131071 2106 1.49% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-196607 209 0.15% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-262143 62 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
525,532c519,526
< system.cpu.itb.walker.walkCompletionTime::total 141371 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 655988501088 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.936740 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.243710 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 41542191152 6.33% 6.33% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 614402729936 93.66% 99.99% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 43110500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 467500 0.00% 100.00% # Table walker pending requests distribution
---
> system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution
534,537c528,531
< system.cpu.itb.walker.walksPending::total 655988501088 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 122178 98.84% 98.84% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 123611 # Table walker page sizes translated
---
> system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated
539,540c533,534
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162167 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 162167 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst
542,546c536,540
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123611 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 123611 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 285778 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 358625455 # ITB inst hits
< system.cpu.itb.inst_misses 162167 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 461294711 # ITB inst hits
> system.cpu.itb.inst_misses 177415 # ITB inst misses
551c545
< system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
---
> system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
553,555c547,549
< system.cpu.itb.flush_tlb_mva_asid 39714 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1025 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 53363 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB
559c553
< system.cpu.itb.perms_faults 372145 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions
562,566c556,560
< system.cpu.itb.inst_accesses 358787622 # ITB inst accesses
< system.cpu.itb.hits 358625455 # DTB hits
< system.cpu.itb.misses 162167 # DTB misses
< system.cpu.itb.accesses 358787622 # DTB accesses
< system.cpu.numCycles 1590418745 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 461472126 # ITB inst accesses
> system.cpu.itb.hits 461294711 # DTB hits
> system.cpu.itb.misses 177415 # DTB misses
> system.cpu.itb.accesses 461472126 # DTB accesses
> system.cpu.numCycles 2141240199 # number of cpu cycles simulated
569,585c563,579
< system.cpu.fetch.icacheStallCycles 646410999 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1006402404 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 225557622 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 135087620 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 866562323 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 26107474 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 3678311 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 25439 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 9275413 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1023850 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 676 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 358236204 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 6112300 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 49056 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 1540030748 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.765724 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.157325 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total)
587,590c581,584
< system.cpu.fetch.rateDist::0 979927440 63.63% 63.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 215057699 13.96% 77.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 70955696 4.61% 82.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 274089913 17.80% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total)
594,641c588,635
< system.cpu.fetch.rateDist::total 1540030748 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.141823 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.632791 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 525466953 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 519947088 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 434864784 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 50506307 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 9245616 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 33796734 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 3867997 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 1090931528 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 29050280 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 9245616 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 570424085 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 50840114 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 363017689 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 440398811 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 106104433 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1071115355 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 6801917 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 5040663 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 343395 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 645255 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 54344412 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 20434 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 1018974666 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1651092433 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1266893179 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1473696 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 953236782 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 65737881 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 27206823 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 23528426 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 103688094 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 174464093 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 151959443 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 9931077 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 9032567 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1035787653 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 27506074 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1051526043 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 3293799 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 60619533 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 33780075 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 314140 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 1540030748 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.682795 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.925415 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle
643,648c637,642
< system.cpu.iq.issued_per_cycle::0 888949202 57.72% 57.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 336251490 21.83% 79.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 235798342 15.31% 94.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 72468185 4.71% 99.57% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 6544331 0.42% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 19198 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle
655c649
< system.cpu.iq.issued_per_cycle::total 1540030748 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle
657,687c651,681
< system.cpu.iq.fu_full::IntAlu 58035888 35.01% 35.01% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 99674 0.06% 35.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 26738 0.02% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 574 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 44566242 26.88% 61.97% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 63041416 38.03% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available
690,721c684,715
< system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 724142674 68.87% 68.87% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2543730 0.24% 69.11% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 122779 0.01% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 376 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 121012 0.01% 69.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 174312709 16.58% 85.71% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 150282706 14.29% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued
724,736c718,730
< system.cpu.iq.FU_type_0::total 1051526043 # Type of FU issued
< system.cpu.iq.rate 0.661163 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 165770532 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.157648 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 3809671307 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1123107931 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1033541701 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 2475857 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 947397 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 910004 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1215741366 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1555198 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 4333965 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued
> system.cpu.iq.rate 0.633727 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores
738,741c732,735
< system.cpu.iew.lsq.thread0.squashedLoads 13839303 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 14833 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 143349 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 6338712 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed
744,745c738,739
< system.cpu.iew.lsq.thread0.rescheduledLoads 2540349 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 1552925 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked
747,750c741,744
< system.cpu.iew.iewSquashCycles 9245616 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 6389360 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 5797347 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1063516239 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ
752,763c746,757
< system.cpu.iew.iewDispLoadInsts 174464093 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 151959443 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 23100216 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 59008 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 5663632 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 143349 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3667729 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 5111764 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 8779493 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1040328227 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 170406440 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 10257681 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute
765,773c759,767
< system.cpu.iew.exec_nop 222512 # number of nop insts executed
< system.cpu.iew.exec_refs 318786335 # number of memory reference insts executed
< system.cpu.iew.exec_branches 197400349 # Number of branches executed
< system.cpu.iew.exec_stores 148379895 # Number of stores executed
< system.cpu.iew.exec_rate 0.654122 # Inst execution rate
< system.cpu.iew.wb_sent 1035262700 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1034451705 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 440415620 # num instructions producing a value
< system.cpu.iew.wb_consumers 712619707 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 272684 # number of nop insts executed
> system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed
> system.cpu.iew.exec_branches 255119365 # Number of branches executed
> system.cpu.iew.exec_stores 192124980 # Number of stores executed
> system.cpu.iew.exec_rate 0.627523 # Inst execution rate
> system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 573421420 # num instructions producing a value
> system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value
775,776c769,770
< system.cpu.iew.wb_rate 0.650427 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.618023 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back
778,783c772,777
< system.cpu.commit.commitSquashedInsts 51498978 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 27191934 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 8413549 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 1528028900 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.656188 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.286676 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle
785,793c779,787
< system.cpu.commit.committed_per_cycle::0 1013092181 66.30% 66.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 289858237 18.97% 85.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 121052617 7.92% 93.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 36682667 2.40% 95.59% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 28563883 1.87% 97.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 14105791 0.92% 98.39% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 8655946 0.57% 98.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 4198069 0.27% 99.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 11819509 0.77% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle
797,799c791,793
< system.cpu.commit.committed_per_cycle::total 1528028900 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 853325819 # Number of instructions committed
< system.cpu.commit.committedOps 1002674190 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 1104366834 # Number of instructions committed
> system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed
801,807c795,801
< system.cpu.commit.refs 306245520 # Number of memory references committed
< system.cpu.commit.loads 160624789 # Number of loads committed
< system.cpu.commit.membars 6977905 # Number of memory barriers committed
< system.cpu.commit.branches 190474151 # Number of branches committed
< system.cpu.commit.fp_insts 896785 # Number of committed floating point instructions.
< system.cpu.commit.int_insts 921116747 # Number of committed integer instructions.
< system.cpu.commit.function_calls 25400785 # Number of function calls committed.
---
> system.cpu.commit.refs 393173853 # Number of memory references committed
> system.cpu.commit.loads 204756836 # Number of loads committed
> system.cpu.commit.membars 9104821 # Number of memory barriers committed
> system.cpu.commit.branches 246834909 # Number of branches committed
> system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions.
> system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions.
> system.cpu.commit.function_calls 30876862 # Number of function calls committed.
809,839c803,833
< system.cpu.commit.op_class_0::IntAlu 694059947 69.22% 69.22% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 2158876 0.22% 69.44% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 98131 0.01% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMisc 111674 0.01% 69.46% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
< system.cpu.commit.op_class_0::MemRead 160624789 16.02% 85.48% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 145620731 14.52% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction
842,867c836,861
< system.cpu.commit.op_class_0::total 1002674190 # Class of committed instruction
< system.cpu.commit.bw_lim_events 11819509 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 2562796067 # The number of ROB reads
< system.cpu.rob.rob_writes 2120254358 # The number of ROB writes
< system.cpu.timesIdled 8129447 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 50387997 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 101057024238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 853325819 # Number of Instructions Simulated
< system.cpu.committedOps 1002674190 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.863788 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.863788 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.536542 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.536542 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1231590969 # number of integer regfile reads
< system.cpu.int_regfile_writes 735370525 # number of integer regfile writes
< system.cpu.fp_regfile_reads 1462122 # number of floating regfile reads
< system.cpu.fp_regfile_writes 782688 # number of floating regfile writes
< system.cpu.cc_regfile_reads 226859046 # number of cc regfile reads
< system.cpu.cc_regfile_writes 227515194 # number of cc regfile writes
< system.cpu.misc_regfile_reads 2534481060 # number of misc regfile reads
< system.cpu.misc_regfile_writes 27245755 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 9758519 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.983709 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 284707567 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9759031 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.173754 # Average number of references to valid blocks.
---
> system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction
> system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3405665880 # The number of ROB reads
> system.cpu.rob.rob_writes 2734432791 # The number of ROB writes
> system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 1104366834 # Number of Instructions Simulated
> system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads
> system.cpu.int_regfile_writes 940526203 # number of integer regfile writes
> system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads
> system.cpu.fp_regfile_writes 765828 # number of floating regfile writes
> system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads
> system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes
> system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads
> system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 13614186 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks.
869c863
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.983709 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor
873c867
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
875c869,870
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
877,904c872,899
< system.cpu.dcache.tags.tag_accesses 1243872376 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1243872376 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 147964440 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 147964440 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 128940955 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 128940955 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 380183 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 380183 # number of SoftPFReq hits
< system.cpu.dcache.WriteLineReq_hits::cpu.data 324678 # number of WriteLineReq hits
< system.cpu.dcache.WriteLineReq_hits::total 324678 # number of WriteLineReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 3327415 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 3327415 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 3725844 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 3725844 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 276905395 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 276905395 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 277285578 # number of overall hits
< system.cpu.dcache.overall_hits::total 277285578 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 9612542 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 9612542 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 11385353 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 11385353 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1184834 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1184834 # number of SoftPFReq misses
< system.cpu.dcache.WriteLineReq_misses::cpu.data 1232047 # number of WriteLineReq misses
< system.cpu.dcache.WriteLineReq_misses::total 1232047 # number of WriteLineReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 450033 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 450033 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits
> system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits
> system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits
> system.cpu.dcache.overall_hits::total 349835392 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses
> system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses
> system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses
907,918c902,913
< system.cpu.dcache.demand_misses::cpu.data 20997895 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 20997895 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 22182729 # number of overall misses
< system.cpu.dcache.overall_misses::total 22182729 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 144669003500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 144669003500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 330867751444 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 330867751444 # number of WriteReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 63675897168 # number of WriteLineReq miss cycles
< system.cpu.dcache.WriteLineReq_miss_latency::total 63675897168 # number of WriteLineReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6433485000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 6433485000 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 31348078 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 33384034 # number of overall misses
> system.cpu.dcache.overall_misses::total 33384034 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 203343916000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 979374659621 # number of WriteReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 74427778402 # number of WriteLineReq miss cycles
> system.cpu.dcache.WriteLineReq_miss_latency::total 74427778402 # number of WriteLineReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8800618500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 8800618500 # number of LoadLockedReq miss cycles
921,964c916,959
< system.cpu.dcache.demand_miss_latency::cpu.data 475536754944 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 475536754944 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 475536754944 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 475536754944 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 157576982 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 157576982 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 140326308 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 140326308 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 1565017 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 1565017 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::cpu.data 1556725 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.WriteLineReq_accesses::total 1556725 # number of WriteLineReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3777448 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 3777448 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 3725851 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 3725851 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 297903290 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 297903290 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 299468307 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 299468307 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061002 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.061002 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081135 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.081135 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757074 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.757074 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791435 # miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_miss_rate::total 0.791435 # miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119137 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119137 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.070486 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.070486 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074074 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074074 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15050.025633 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15050.025633 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29060.825031 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 29060.825031 # average WriteReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 51683.009794 # average WriteLineReq miss latency
< system.cpu.dcache.WriteLineReq_avg_miss_latency::total 51683.009794 # average WriteLineReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14295.584990 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14295.584990 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 199191319 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 199191319 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 181528758 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 181528758 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 2499349 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 2499349 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5334732 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 5334732 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 5271276 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 5271276 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 380720077 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 380720077 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 383219426 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 383219426 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063873 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.063873 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102601 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.102601 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.814595 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.082339 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.082339 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087115 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087115 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15982.387487 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15982.387487 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52583.654126 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 52583.654126 # average WriteReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 58582.915759 # average WriteLineReq miss latency
> system.cpu.dcache.WriteLineReq_avg_miss_latency::total 58582.915759 # average WriteLineReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16079.034778 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16079.034778 # average LoadLockedReq miss latency
967,971c962,966
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22646.877458 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22646.877458 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 21437.252150 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 21437.252150 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 35158879 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 37728.583412 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 37728.583412 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35427.671072 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35427.671072 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 46020939 # number of cycles access was blocked
973c968
< system.cpu.dcache.blocked::no_mshrs 1606955 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 2096301 # number of cycles access was blocked
975c970
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.879193 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.953402 # average number of cycles each access was blocked
979,1002c974,997
< system.cpu.dcache.writebacks::writebacks 7549082 # number of writebacks
< system.cpu.dcache.writebacks::total 7549082 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4467834 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 4467834 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9360902 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 9360902 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7079 # number of WriteLineReq MSHR hits
< system.cpu.dcache.WriteLineReq_mshr_hits::total 7079 # number of WriteLineReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219205 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 219205 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 13828736 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 13828736 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 13828736 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 13828736 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5144708 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5144708 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2024451 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2024451 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1178103 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1178103 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224968 # number of WriteLineReq MSHR misses
< system.cpu.dcache.WriteLineReq_mshr_misses::total 1224968 # number of WriteLineReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230828 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 230828 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 10299062 # number of writebacks
> system.cpu.dcache.writebacks::total 10299062 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5706012 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 5706012 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15543150 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 15543150 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7171 # number of WriteLineReq MSHR hits
> system.cpu.dcache.WriteLineReq_mshr_hits::total 7171 # number of WriteLineReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 263403 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 263403 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 21249162 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 21249162 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 21249162 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 21249162 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7016988 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7016988 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3081928 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 3081928 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2029224 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 2029224 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263298 # number of WriteLineReq MSHR misses
> system.cpu.dcache.WriteLineReq_mshr_misses::total 1263298 # number of WriteLineReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283932 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 283932 # number of LoadLockedReq MSHR misses
1005,1024c1000,1019
< system.cpu.dcache.demand_mshr_misses::cpu.data 7169159 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7169159 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 8347262 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 8347262 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75818409500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 75818409500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57062160713 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 57062160713 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20148080000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20148080000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 62191648168 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 62191648168 # number of WriteLineReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3063087000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3063087000 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 10098916 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 10098916 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 12128140 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 12128140 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109410315500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 109410315500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 144646896672 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 144646896672 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32373018500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32373018500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72874671402 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72874671402 # number of WriteLineReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4076865500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4076865500 # number of LoadLockedReq MSHR miss cycles
1027,1062c1022,1057
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 132880570213 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 132880570213 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 153028650213 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 153028650213 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5828327500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5828327500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5707957967 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5707957967 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11536285467 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11536285467 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032649 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032649 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014427 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014427 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752773 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752773 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786888 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786888 # mshr miss rate for WriteLineReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061107 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061107 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024065 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024065 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027874 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027874 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14737.164772 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14737.164772 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.486466 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.486466 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17102.137929 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17102.137929 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 50770.018619 # average WriteLineReq mshr miss latency
< system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 50770.018619 # average WriteLineReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13269.997574 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13269.997574 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 254057212172 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 254057212172 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286430230672 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 286430230672 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829096500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829096500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5708243467 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5708243467 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11537339967 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11537339967 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035227 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035227 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016978 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016978 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.811901 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.811901 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787350 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787350 # mshr miss rate for WriteLineReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053223 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053223 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency
> system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency
1065,1074c1060,1069
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18535.029034 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18535.029034 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18332.795857 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 18332.795857 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173060.380664 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173060.380664 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169395.713646 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169395.713646 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171227.557619 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171227.557619 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency
1076,1080c1071,1075
< system.cpu.icache.tags.replacements 15042093 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.944879 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 342405629 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 15042605 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 22.762389 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 16756542 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks.
1082,1084c1077,1079
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.944879 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999892 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy
1086,1088c1081,1083
< system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id
1090,1128c1085,1123
< system.cpu.icache.tags.tag_accesses 373257734 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 373257734 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 342405629 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 342405629 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 342405629 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 342405629 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 342405629 # number of overall hits
< system.cpu.icache.overall_hits::total 342405629 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 15809279 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 15809279 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 15809279 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 15809279 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 15809279 # number of overall misses
< system.cpu.icache.overall_misses::total 15809279 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 208403044384 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 208403044384 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 208403044384 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 208403044384 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 208403044384 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 208403044384 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 358214908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 358214908 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 358214908 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 358214908 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 358214908 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 358214908 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044134 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.044134 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.044134 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.044134 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.044134 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.044134 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13182.324405 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13182.324405 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13182.324405 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13182.324405 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13182.324405 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 15030 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits
> system.cpu.icache.overall_hits::total 443237235 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses
> system.cpu.icache.overall_misses::total 17559241 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 460796476 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked
1130c1125
< system.cpu.icache.blocked::no_mshrs 1210 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked
1132c1127
< system.cpu.icache.avg_blocked_cycles::no_mshrs 12.421488 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # average number of cycles each access was blocked
1136,1147c1131,1142
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766453 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 766453 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 766453 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 766453 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 766453 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 766453 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15042826 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 15042826 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 15042826 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 15042826 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 15042826 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 15042826 # number of overall MSHR misses
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 16757275 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 16757275 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 16757275 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 16757275 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 16757275 # number of overall MSHR misses
1152,1157c1147,1152
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186915451392 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 186915451392 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186915451392 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 186915451392 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186915451392 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 186915451392 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles
1162,1173c1157,1168
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041994 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.041994 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041994 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.041994 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12425.554307 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12425.554307 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12425.554307 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12425.554307 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036366 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.036366 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036366 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.036366 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12446.412492 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12446.412492 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency
1179,1183c1174,1178
< system.cpu.l2cache.tags.replacements 1148683 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65278.817014 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 46198537 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1210914 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 38.151790 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 2345734 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65318.237935 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 55622573 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2409067 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 23.088844 # Average number of references to valid blocks.
1185,1215c1180,1209
< system.cpu.l2cache.tags.occ_blocks::writebacks 37192.962627 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 301.460755 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 460.210435 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 7626.713626 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 19697.469572 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.567520 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004600 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007022 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116374 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.300560 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996076 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 380 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 61851 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 379 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2690 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5173 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53395 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943771 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 410382726 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 410382726 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 788948 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299798 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1088746 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 7549082 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 7549082 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 9455 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 9455 # number of UpgradeReq hits
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 35816.547430 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 265.508156 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 348.644093 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 6890.433367 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 21997.104889 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.546517 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004051 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005320 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.105140 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.335649 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996677 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 63093 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5217 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54586 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962723 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 506469360 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 506469360 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1313351 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 329734 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1643085 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 10299062 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 10299062 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 12887 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 12887 # number of UpgradeReq hits
1218,1240c1212,1234
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1576072 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1576072 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14958434 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 14958434 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6296354 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 6296354 # number of ReadSharedReq hits
< system.cpu.l2cache.InvalidateReq_hits::cpu.data 732370 # number of InvalidateReq hits
< system.cpu.l2cache.InvalidateReq_hits::total 732370 # number of InvalidateReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 788948 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 299798 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 14958434 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 7872426 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 23919606 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 788948 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 299798 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 14958434 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 7872426 # number of overall hits
< system.cpu.l2cache.overall_hits::total 23919606 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3175 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2963 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 6138 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 34552 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 34552 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1723701 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1723701 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16658716 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 16658716 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8894179 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 8894179 # number of ReadSharedReq hits
> system.cpu.l2cache.InvalidateReq_hits::cpu.data 672751 # number of InvalidateReq hits
> system.cpu.l2cache.InvalidateReq_hits::total 672751 # number of InvalidateReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 1313351 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 329734 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 16658716 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 10617880 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 28919681 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 1313351 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 329734 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 16658716 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 10617880 # number of overall hits
> system.cpu.l2cache.overall_hits::total 28919681 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10281 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8711 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 18992 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 47777 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 47777 # number of UpgradeReq misses
1243,1265c1237,1259
< system.cpu.l2cache.ReadExReq_misses::cpu.data 407912 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 407912 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 84184 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 84184 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 253746 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 253746 # number of ReadSharedReq misses
< system.cpu.l2cache.InvalidateReq_misses::cpu.data 492598 # number of InvalidateReq misses
< system.cpu.l2cache.InvalidateReq_misses::total 492598 # number of InvalidateReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 3175 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 2963 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 84184 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 661658 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 751980 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 3175 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 2963 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 84184 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 661658 # number of overall misses
< system.cpu.l2cache.overall_misses::total 751980 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276956000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 265379500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 542335500 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 544075000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 544075000 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 1312732 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 1312732 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 98354 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 98354 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 420801 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 420801 # number of ReadSharedReq misses
> system.cpu.l2cache.InvalidateReq_misses::cpu.data 590547 # number of InvalidateReq misses
> system.cpu.l2cache.InvalidateReq_misses::total 590547 # number of InvalidateReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 10281 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 8711 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 98354 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 1733533 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 1850879 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 10281 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 8711 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 98354 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 1733533 # number of overall misses
> system.cpu.l2cache.overall_misses::total 1850879 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 914040000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 769017500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1683057500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 621639500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 621639500 # number of UpgradeReq miss cycles
1268,1292c1262,1286
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36032836500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 36032836500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7082572500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 7082572500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22536354000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 22536354000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 51203919000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.InvalidateReq_miss_latency::total 51203919000 # number of InvalidateReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276956000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 265379500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 7082572500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 58569190500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 66194098500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276956000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 265379500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 7082572500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 58569190500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 66194098500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 792123 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302761 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1094884 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 7549082 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 7549082 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 44007 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 44007 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 120138160000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 120138160000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8298337000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 8298337000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37547469500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 37547469500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62416970000 # number of InvalidateReq miss cycles
> system.cpu.l2cache.InvalidateReq_miss_latency::total 62416970000 # number of InvalidateReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 914040000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 769017500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 8298337000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 157685629500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 167667024000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 914040000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 769017500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 8298337000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 157685629500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 167667024000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1323632 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 338445 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1662077 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 10299062 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 10299062 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 60664 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 60664 # number of UpgradeReq accesses(hits+misses)
1295,1317c1289,1311
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1983984 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1983984 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15042618 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 15042618 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6550100 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 6550100 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1224968 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.InvalidateReq_accesses::total 1224968 # number of InvalidateReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 792123 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 302761 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 15042618 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 8534084 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 24671586 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 792123 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 302761 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 15042618 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 8534084 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 24671586 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004008 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009787 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.005606 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785148 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785148 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 3036433 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 3036433 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16757070 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 16757070 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9314980 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 9314980 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263298 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.InvalidateReq_accesses::total 1263298 # number of InvalidateReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1323632 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 338445 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 16757070 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 12351413 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 30770560 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1323632 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 338445 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 16757070 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 12351413 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 30770560 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007767 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.025738 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.011427 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787568 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.787568 # miss rate for UpgradeReq accesses
1320,1342c1314,1336
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205602 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.205602 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005596 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005596 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.038739 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.038739 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.402131 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_miss_rate::total 0.402131 # miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004008 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009787 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005596 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.077531 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.030480 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004008 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009787 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005596 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.077531 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.030480 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87230.236220 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89564.461694 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 88357.038123 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15746.555916 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15746.555916 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.432327 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.432327 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005869 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005869 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045175 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045175 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.467465 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_miss_rate::total 0.467465 # miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007767 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.025738 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005869 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.140351 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.060151 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007767 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.025738 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005869 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.140351 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.060151 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88905.748468 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88281.196189 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 88619.287068 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13011.271114 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13011.271114 # average UpgradeReq miss latency
1345,1362c1339,1356
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88334.828345 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88334.828345 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84132.050033 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84132.050033 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88814.617767 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88814.617767 # average ReadSharedReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 103946.664420 # average InvalidateReq miss latency
< system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 103946.664420 # average InvalidateReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 88026.408282 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87230.236220 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89564.461694 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84132.050033 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88518.827703 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 88026.408282 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91517.659355 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91517.659355 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84372.135348 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84372.135348 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89228.565284 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89228.565284 # average ReadSharedReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 105693.484177 # average InvalidateReq miss latency
> system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 105693.484177 # average InvalidateReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88905.748468 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88281.196189 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84372.135348 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90962.000435 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 90587.782346 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88905.748468 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88281.196189 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84372.135348 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90962.000435 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 90587.782346 # average overall miss latency
1371,1385c1365,1379
< system.cpu.l2cache.writebacks::writebacks 967181 # number of writebacks
< system.cpu.l2cache.writebacks::total 967181 # number of writebacks
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3175 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2963 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 6138 # number of ReadReq MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1073 # number of CleanEvict MSHR misses
< system.cpu.l2cache.CleanEvict_mshr_misses::total 1073 # number of CleanEvict MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34552 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 34552 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 2075008 # number of writebacks
> system.cpu.l2cache.writebacks::total 2075008 # number of writebacks
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10281 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8711 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 18992 # number of ReadReq MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses
> system.cpu.l2cache.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47777 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 47777 # number of UpgradeReq MSHR misses
1388,1405c1382,1399
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 407912 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 407912 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 84184 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 84184 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 253725 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 253725 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 492598 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.InvalidateReq_mshr_misses::total 492598 # number of InvalidateReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3175 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2963 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 84184 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 661637 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 751959 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3175 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2963 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 84184 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 661637 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 751959 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1312732 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 1312732 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 98354 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 98354 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 420779 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 420779 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590547 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.InvalidateReq_mshr_misses::total 590547 # number of InvalidateReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10281 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8711 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 98354 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 1733511 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 1850857 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10281 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8711 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 98354 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 1733511 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 1850857 # number of overall MSHR misses
1407,1410c1401,1404
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54973 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54987 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
1412,1418c1406,1412
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88669 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 245206000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 235749500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 480955500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 717374500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 717374500 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88690 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 811230000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 681907500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1493137500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 993052500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 993052500 # number of UpgradeReq MSHR miss cycles
1421,1438c1415,1432
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31953716500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31953716500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6240732500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6240732500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19997854000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19997854000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 46277939000 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 46277939000 # number of InvalidateReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 245206000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 235749500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6240732500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51951570500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 58673258500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 245206000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 235749500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6240732500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51951570500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 58673258500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107010840000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107010840000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7314797000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7314797000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33338388000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33338388000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 56511500000 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 56511500000 # number of InvalidateReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 811230000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 681907500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7314797000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140349228000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 149157162500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 811230000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 681907500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7314797000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140349228000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 149157162500 # number of overall MSHR miss cycles
1440,1443c1434,1437
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407344500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6735569000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5315951000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5315951000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5407939500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6736164000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5316157000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5316157000 # number of WriteReq MSHR uncacheable cycles
1445,1449c1439,1443
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10723295500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12051520000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005606 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10724096500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12052321000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011427 # mshr miss rate for ReadReq accesses
1452,1453c1446,1447
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785148 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785148 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787568 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787568 # mshr miss rate for UpgradeReq accesses
1456,1478c1450,1472
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205602 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205602 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005596 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038736 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038736 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.402131 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.402131 # mshr miss rate for InvalidateReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.030479 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004008 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009787 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005596 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077529 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.030479 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78357.038123 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20762.170063 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.170063 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.432327 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.432327 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005869 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045172 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045172 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.467465 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.467465 # mshr miss rate for InvalidateReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060150 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007767 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.025738 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005869 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140349 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.060150 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78619.287068 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20785.158130 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20785.158130 # average UpgradeReq mshr miss latency
1481,1498c1475,1492
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78334.828345 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78334.828345 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74132.050033 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74132.050033 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78817.042073 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78817.042073 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 93946.664420 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 93946.664420 # average InvalidateReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77230.236220 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79564.461694 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74132.050033 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78519.747989 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78027.204276 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81517.659355 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81517.659355 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74372.135348 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74372.135348 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79230.161201 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79230.161201 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 95693.484177 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 95693.484177 # average InvalidateReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78905.748468 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78281.196189 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74372.135348 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80962.409815 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80588.161322 # average overall mshr miss latency
1500,1503c1494,1497
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160560.143120 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122525.039565 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157762.078585 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157762.078585 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160511.085718 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122504.664739 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157735.424146 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157735.424146 # average WriteReq mshr uncacheable latency
1505,1506c1499,1500
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159160.737080 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135915.821764 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159123.028415 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 135892.671102 # average overall mshr uncacheable latency
1508,1514c1502,1508
< system.cpu.toL2Bus.trans_dist::ReadReq 1633565 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 23227278 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 8622904 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 17438576 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 44010 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution
1516,1536c1510,1530
< system.cpu.toL2Bus.trans_dist::UpgradeResp 44017 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1983984 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1983984 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 15042826 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 6558947 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateReq 1331632 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::InvalidateResp 1224968 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45167572 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29499463 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 732865 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1940611 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 77340511 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 963068272 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1029563294 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2422088 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6336984 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2001390638 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1864369 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 52693428 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.056141 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.230194 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 3104722 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram
1539,1540c1533,1534
< system.cpu.toL2Bus.snoop_fanout::1 49735173 94.39% 94.39% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 2958255 5.61% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram
1544,1545c1538,1539
< system.cpu.toL2Bus.snoop_fanout::total 52693428 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 33222815494 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks)
1547c1541
< system.cpu.toL2Bus.snoopLayer0.occupancy 1182000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks)
1549c1543
< system.cpu.toL2Bus.respLayer0.occupancy 22592032956 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks)
1551c1545
< system.cpu.toL2Bus.respLayer1.occupancy 13487423434 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks)
1553c1547
< system.cpu.toL2Bus.respLayer2.occupancy 430634727 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks)
1555c1549
< system.cpu.toL2Bus.respLayer3.occupancy 1148958035 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks)
1557,1558c1551,1552
< system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
1577,1578c1571,1572
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
1581c1575
< system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes)
1598,1599c1592,1593
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
1602c1596
< system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes)
1631c1625
< system.iobus.reqLayer27.occupancy 568813596 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks)
1637c1631
< system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks)
1641,1642c1635,1636
< system.iocache.tags.replacements 115455 # number of replacements
< system.iocache.tags.tagsinuse 10.423947 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115458 # number of replacements
> system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use
1644c1638
< system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks.
1646,1651c1640,1645
< system.iocache.tags.warmup_cycle 13095311635000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.544418 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.879529 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.429971 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.651497 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy
1655,1656c1649,1650
< system.iocache.tags.tag_accesses 1039623 # Number of tag accesses
< system.iocache.tags.data_accesses 1039623 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
> system.iocache.tags.data_accesses 1039650 # Number of data accesses
1658,1659c1652,1653
< system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
1665,1666c1659,1660
< system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8850 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
1668,1669c1662,1663
< system.iocache.overall_misses::realview.ide 8810 # number of overall misses
< system.iocache.overall_misses::total 8850 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8813 # number of overall misses
> system.iocache.overall_misses::total 8853 # number of overall misses
1671,1672c1665,1666
< system.iocache.ReadReq_miss_latency::realview.ide 1621911166 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1626980166 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles
1675,1676c1669,1670
< system.iocache.WriteLineReq_miss_latency::realview.ide 12610487430 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12610487430 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles
1678,1679c1672,1673
< system.iocache.demand_miss_latency::realview.ide 1621911166 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1627331166 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles
1681,1682c1675,1676
< system.iocache.overall_miss_latency::realview.ide 1621911166 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1627331166 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles
1684,1685c1678,1679
< system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
1691,1692c1685,1686
< system.iocache.demand_accesses::realview.ide 8810 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8850 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
1694,1695c1688,1689
< system.iocache.overall_accesses::realview.ide 8810 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8850 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
1710,1711c1704,1705
< system.iocache.ReadReq_avg_miss_latency::realview.ide 184098.883768 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 183901.906409 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency
1714,1715c1708,1709
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.275313 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118226.275313 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency
1717,1718c1711,1712
< system.iocache.demand_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 183879.227797 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency
1720,1722c1714,1716
< system.iocache.overall_avg_miss_latency::realview.ide 184098.883768 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 183879.227797 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 31681 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked
1724c1718
< system.iocache.blocked::no_mshrs 3345 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked
1726c1720
< system.iocache.avg_blocked_cycles::no_mshrs 9.471151 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked
1733,1734c1727,1728
< system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses
1740,1741c1734,1735
< system.iocache.demand_mshr_misses::realview.ide 8810 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8850 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses
1743,1744c1737,1738
< system.iocache.overall_mshr_misses::realview.ide 8810 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8850 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses
1746,1747c1740,1741
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1181411166 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1184630166 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles
1750,1751c1744,1745
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277287430 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7277287430 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles
1753,1754c1747,1748
< system.iocache.demand_mshr_miss_latency::realview.ide 1181411166 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1184831166 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles
1756,1757c1750,1751
< system.iocache.overall_mshr_miss_latency::realview.ide 1181411166 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1184831166 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles
1772,1773c1766,1767
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134098.883768 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 133901.906409 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency
1776,1777c1770,1771
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.275313 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.275313 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency
1779,1780c1773,1774
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency
1782,1783c1776,1777
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 134098.883768 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 133879.227797 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency
1785,1791c1779,1785
< system.membus.trans_dist::ReadReq 54973 # Transaction distribution
< system.membus.trans_dist::ReadResp 407867 # Transaction distribution
< system.membus.trans_dist::WriteReq 33696 # Transaction distribution
< system.membus.trans_dist::WriteResp 33696 # Transaction distribution
< system.membus.trans_dist::Writeback 1073811 # Transaction distribution
< system.membus.trans_dist::CleanEvict 187846 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 35358 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 54987 # Transaction distribution
> system.membus.trans_dist::ReadResp 601962 # Transaction distribution
> system.membus.trans_dist::WriteReq 33703 # Transaction distribution
> system.membus.trans_dist::WriteResp 33703 # Transaction distribution
> system.membus.trans_dist::Writeback 2181638 # Transaction distribution
> system.membus.trans_dist::CleanEvict 277040 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution
1793,1796c1787,1790
< system.membus.trans_dist::UpgradeResp 35361 # Transaction distribution
< system.membus.trans_dist::ReadExReq 899707 # Transaction distribution
< system.membus.trans_dist::ReadExResp 899707 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 352894 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution
> system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution
> system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution
1801,1806c1795,1800
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3753956 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3883578 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341714 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 341714 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 4225292 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes)
1809,1816c1803,1810
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 141818700 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 141988686 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7244096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7244096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 149232782 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 2955 # Total snoops (count)
< system.membus.snoop_fanout::samples 2747442 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 2989 # Total snoops (count)
> system.membus.snoop_fanout::samples 5154600 # Request fanout histogram
1821c1815
< system.membus.snoop_fanout::1 2747442 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram
1826,1827c1820,1821
< system.membus.snoop_fanout::total 2747442 # Request fanout histogram
< system.membus.reqLayer0.occupancy 104159500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 5154600 # Request fanout histogram
> system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks)
1831c1825
< system.membus.reqLayer2.occupancy 5443500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks)
1833c1827
< system.membus.reqLayer5.occupancy 7279924206 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks)
1835c1829
< system.membus.respLayer2.occupancy 6776038462 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks)
1837c1831
< system.membus.respLayer3.occupancy 228860056 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks)
1848c1842
< system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
---
> system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
1852c1846
< system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
---
> system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
1880a1875
> system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
1887d1881
< system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
1892c1886
< system.cpu.kern.inst.quiesce 16150 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed