3,5c3,5
< sim_seconds 51.320647 # Number of seconds simulated
< sim_ticks 51320647066500 # Number of ticks simulated
< final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 51.320469 # Number of seconds simulated
> sim_ticks 51320468905000 # Number of ticks simulated
> final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 114690 # Simulator instruction rate (inst/s)
< host_op_rate 134762 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6864170011 # Simulator tick rate (ticks/s)
< host_mem_usage 721888 # Number of bytes of host memory used
< host_seconds 7476.60 # Real time elapsed on the host
< sim_insts 857487967 # Number of instructions simulated
< sim_ops 1007562352 # Number of ops (including micro ops) simulated
---
> host_inst_rate 114377 # Simulator instruction rate (inst/s)
> host_op_rate 134391 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6861255780 # Simulator tick rate (ticks/s)
> host_mem_usage 720736 # Number of bytes of host memory used
> host_seconds 7479.75 # Real time elapsed on the host
> sim_insts 855512158 # Number of instructions simulated
> sim_ops 1005211605 # Number of ops (including micro ops) simulated
16,24c16,24
< system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory
< system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory
> system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory
26,33c26,33
< system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory
35,44c35,44
< system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s)
46,97c46,97
< system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 791544 # Number of read requests accepted
< system.physmem.writeReqs 1694292 # Number of write requests accepted
< system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue
< system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 48315 # Per bank write bursts
< system.physmem.perBankRdBursts::1 50150 # Per bank write bursts
< system.physmem.perBankRdBursts::2 46175 # Per bank write bursts
< system.physmem.perBankRdBursts::3 46946 # Per bank write bursts
< system.physmem.perBankRdBursts::4 45323 # Per bank write bursts
< system.physmem.perBankRdBursts::5 52981 # Per bank write bursts
< system.physmem.perBankRdBursts::6 47646 # Per bank write bursts
< system.physmem.perBankRdBursts::7 48748 # Per bank write bursts
< system.physmem.perBankRdBursts::8 44337 # Per bank write bursts
< system.physmem.perBankRdBursts::9 72322 # Per bank write bursts
< system.physmem.perBankRdBursts::10 50834 # Per bank write bursts
< system.physmem.perBankRdBursts::11 50772 # Per bank write bursts
< system.physmem.perBankRdBursts::12 48451 # Per bank write bursts
< system.physmem.perBankRdBursts::13 47387 # Per bank write bursts
< system.physmem.perBankRdBursts::14 44232 # Per bank write bursts
< system.physmem.perBankRdBursts::15 46363 # Per bank write bursts
< system.physmem.perBankWrBursts::0 103979 # Per bank write bursts
< system.physmem.perBankWrBursts::1 105038 # Per bank write bursts
< system.physmem.perBankWrBursts::2 105754 # Per bank write bursts
< system.physmem.perBankWrBursts::3 105161 # Per bank write bursts
< system.physmem.perBankWrBursts::4 103562 # Per bank write bursts
< system.physmem.perBankWrBursts::5 108435 # Per bank write bursts
< system.physmem.perBankWrBursts::6 103867 # Per bank write bursts
< system.physmem.perBankWrBursts::7 105467 # Per bank write bursts
< system.physmem.perBankWrBursts::8 102645 # Per bank write bursts
< system.physmem.perBankWrBursts::9 108407 # Per bank write bursts
< system.physmem.perBankWrBursts::10 108582 # Per bank write bursts
< system.physmem.perBankWrBursts::11 107982 # Per bank write bursts
< system.physmem.perBankWrBursts::12 105330 # Per bank write bursts
< system.physmem.perBankWrBursts::13 105345 # Per bank write bursts
< system.physmem.perBankWrBursts::14 103911 # Per bank write bursts
< system.physmem.perBankWrBursts::15 104029 # Per bank write bursts
---
> system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 784654 # Number of read requests accepted
> system.physmem.writeReqs 1688539 # Number of write requests accepted
> system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue
> system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 46664 # Per bank write bursts
> system.physmem.perBankRdBursts::1 51485 # Per bank write bursts
> system.physmem.perBankRdBursts::2 48018 # Per bank write bursts
> system.physmem.perBankRdBursts::3 46409 # Per bank write bursts
> system.physmem.perBankRdBursts::4 44064 # Per bank write bursts
> system.physmem.perBankRdBursts::5 51949 # Per bank write bursts
> system.physmem.perBankRdBursts::6 45895 # Per bank write bursts
> system.physmem.perBankRdBursts::7 48923 # Per bank write bursts
> system.physmem.perBankRdBursts::8 45299 # Per bank write bursts
> system.physmem.perBankRdBursts::9 70789 # Per bank write bursts
> system.physmem.perBankRdBursts::10 48156 # Per bank write bursts
> system.physmem.perBankRdBursts::11 46739 # Per bank write bursts
> system.physmem.perBankRdBursts::12 48771 # Per bank write bursts
> system.physmem.perBankRdBursts::13 48997 # Per bank write bursts
> system.physmem.perBankRdBursts::14 45133 # Per bank write bursts
> system.physmem.perBankRdBursts::15 46835 # Per bank write bursts
> system.physmem.perBankWrBursts::0 99610 # Per bank write bursts
> system.physmem.perBankWrBursts::1 104326 # Per bank write bursts
> system.physmem.perBankWrBursts::2 103481 # Per bank write bursts
> system.physmem.perBankWrBursts::3 102430 # Per bank write bursts
> system.physmem.perBankWrBursts::4 101747 # Per bank write bursts
> system.physmem.perBankWrBursts::5 104971 # Per bank write bursts
> system.physmem.perBankWrBursts::6 100056 # Per bank write bursts
> system.physmem.perBankWrBursts::7 103888 # Per bank write bursts
> system.physmem.perBankWrBursts::8 99840 # Per bank write bursts
> system.physmem.perBankWrBursts::9 106110 # Per bank write bursts
> system.physmem.perBankWrBursts::10 102643 # Per bank write bursts
> system.physmem.perBankWrBursts::11 100858 # Per bank write bursts
> system.physmem.perBankWrBursts::12 103355 # Per bank write bursts
> system.physmem.perBankWrBursts::13 103593 # Per bank write bursts
> system.physmem.perBankWrBursts::14 100350 # Per bank write bursts
> system.physmem.perBankWrBursts::15 101960 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 30 # Number of times write queue was full causing retry
< system.physmem.totGap 51320645833500 # Total gap between requests
---
> system.physmem.numWrRetry 560 # Number of times write queue was full causing retry
> system.physmem.totGap 51320467654000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 770259 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 763369 # Read request sizes (log2)
114,135c114,135
< system.physmem.writePktSize::6 1691719 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1685966 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
137,138c137,138
< system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
162,229c162,229
< system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes
232,273c232,270
< system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads
< system.physmem.totQLat 15484448260 # Total ticks spent queuing
< system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads
> system.physmem.totQLat 15388206863 # Total ticks spent queuing
> system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst
275,279c272,276
< system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s
284,302c281,299
< system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing
< system.physmem.readRowHits 603455 # Number of row buffer hits during reads
< system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes
< system.physmem.avgGap 20645225.93 # Average gap between requests
< system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.473889 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states
---
> system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing
> system.physmem.readRowHits 598254 # Number of row buffer hits during reads
> system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes
> system.physmem.avgGap 20750692.59 # Average gap between requests
> system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.470318 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states
304c301
< system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states
306,316c303,313
< system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.480369 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states
---
> system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.479291 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states
318c315
< system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states
342,346c339,343
< system.cpu.branchPred.lookups 226505876 # Number of BP lookups
< system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits
---
> system.cpu.branchPred.lookups 226088242 # Number of BP lookups
> system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits
348,350c345,347
< system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions.
381,434c378,430
< system.cpu.dtb.walker.walks 931379 # Table walker walks requested
< system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors
< system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walks 945525 # Table walker walks requested
> system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors
> system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst
436,437c432,433
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst
439,440c435,436
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst
443,446c439,442
< system.cpu.dtb.read_hits 171278986 # DTB read hits
< system.cpu.dtb.read_misses 671795 # DTB read misses
< system.cpu.dtb.write_hits 149102166 # DTB write hits
< system.cpu.dtb.write_misses 259584 # DTB write misses
---
> system.cpu.dtb.read_hits 170900022 # DTB read hits
> system.cpu.dtb.read_misses 675244 # DTB read misses
> system.cpu.dtb.write_hits 148749524 # DTB write hits
> system.cpu.dtb.write_misses 270281 # DTB write misses
449,453c445,449
< system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID
< system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
< system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dtb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID
> system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch
455,457c451,453
< system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 171950781 # DTB read accesses
< system.cpu.dtb.write_accesses 149361750 # DTB write accesses
---
> system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 171575266 # DTB read accesses
> system.cpu.dtb.write_accesses 149019805 # DTB write accesses
459,461c455,457
< system.cpu.dtb.hits 320381152 # DTB hits
< system.cpu.dtb.misses 931379 # DTB misses
< system.cpu.dtb.accesses 321312531 # DTB accesses
---
> system.cpu.dtb.hits 319649546 # DTB hits
> system.cpu.dtb.misses 945525 # DTB misses
> system.cpu.dtb.accesses 320595071 # DTB accesses
491,503c487,499
< system.cpu.itb.walker.walks 161841 # Table walker walks requested
< system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors
< system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency
---
> system.cpu.itb.walker.walks 161869 # Table walker walks requested
> system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors
> system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency
505,507c501,503
< system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
509,541c505,532
< system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated
543,544c534,535
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst
546,550c537,541
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 360168043 # ITB inst hits
< system.cpu.itb.inst_misses 161841 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 359459512 # ITB inst hits
> system.cpu.itb.inst_misses 161869 # ITB inst misses
557,559c548,550
< system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID
< system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
< system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID
> system.cpu.itb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID
> system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB
563c554
< system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions
566,570c557,561
< system.cpu.itb.inst_accesses 360329884 # ITB inst accesses
< system.cpu.itb.hits 360168043 # DTB hits
< system.cpu.itb.misses 161841 # DTB misses
< system.cpu.itb.accesses 360329884 # DTB accesses
< system.cpu.numCycles 1576983833 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 359621381 # ITB inst accesses
> system.cpu.itb.hits 359459512 # DTB hits
> system.cpu.itb.misses 161869 # DTB misses
> system.cpu.itb.accesses 359621381 # DTB accesses
> system.cpu.numCycles 1580751099 # number of cpu cycles simulated
573,589c564,580
< system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total)
591,594c582,585
< system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total)
598,645c589,636
< system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full
< system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full
> system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle
647,652c638,643
< system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle
659c650
< system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle
661,691c652,682
< system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available
694,698c685,689
< system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued
< system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued
---
> system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued
> system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued
720c711
< system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued
724,725c715,716
< system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued
728,740c719,731
< system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued
< system.cpu.iq.rate 0.670005 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued
> system.cpu.iq.rate 0.666896 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores
742,745c733,736
< system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed
748,749c739,740
< system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked
751,754c742,745
< system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ
756,767c747,758
< system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute
769,777c760,768
< system.cpu.iew.exec_nop 224348 # number of nop insts executed
< system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed
< system.cpu.iew.exec_branches 198404489 # Number of branches executed
< system.cpu.iew.exec_stores 149099070 # Number of stores executed
< system.cpu.iew.exec_rate 0.662897 # Inst execution rate
< system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 442335874 # num instructions producing a value
< system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 222943 # number of nop insts executed
> system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed
> system.cpu.iew.exec_branches 197926826 # Number of branches executed
> system.cpu.iew.exec_stores 148745526 # Number of stores executed
> system.cpu.iew.exec_rate 0.659804 # Inst execution rate
> system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 441278048 # num instructions producing a value
> system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value
779,780c770,771
< system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back
782,787c773,778
< system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle
789,797c780,788
< system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle
801,803c792,794
< system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 857487967 # Number of instructions committed
< system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 855512158 # Number of instructions committed
> system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed
805,811c796,802
< system.cpu.commit.refs 307720812 # Number of memory references committed
< system.cpu.commit.loads 161382253 # Number of loads committed
< system.cpu.commit.membars 7017472 # Number of memory barriers committed
< system.cpu.commit.branches 191417503 # Number of branches committed
< system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions.
< system.cpu.commit.int_insts 925548459 # Number of committed integer instructions.
< system.cpu.commit.function_calls 25509836 # Number of function calls committed.
---
> system.cpu.commit.refs 307009160 # Number of memory references committed
> system.cpu.commit.loads 161022390 # Number of loads committed
> system.cpu.commit.membars 6998413 # Number of memory barriers committed
> system.cpu.commit.branches 190975004 # Number of branches committed
> system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions.
> system.cpu.commit.int_insts 923410198 # Number of committed integer instructions.
> system.cpu.commit.function_calls 25456304 # Number of function calls committed.
813,815c804,806
< system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction
< system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction
838c829
< system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction
---
> system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction
842,843c833,834
< system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction
846,847c837,838
< system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction
< system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction
> system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached
849,876c840,867
< system.cpu.rob.rob_reads 2555751551 # The number of ROB reads
< system.cpu.rob.rob_writes 2129995502 # The number of ROB writes
< system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 857487967 # Number of Instructions Simulated
< system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads
< system.cpu.int_regfile_writes 738733043 # number of integer regfile writes
< system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads
< system.cpu.fp_regfile_writes 782548 # number of floating regfile writes
< system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads
< system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes
< system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads
< system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 9822587 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy
---
> system.cpu.rob.rob_reads 2555711925 # The number of ROB reads
> system.cpu.rob.rob_writes 2125474325 # The number of ROB writes
> system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 855512158 # Number of Instructions Simulated
> system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads
> system.cpu.int_regfile_writes 737118708 # number of integer regfile writes
> system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads
> system.cpu.fp_regfile_writes 784484 # number of floating regfile writes
> system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads
> system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes
> system.cpu.misc_regfile_reads 5246257758 # number of misc regfile reads
> system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 9794555 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
878,880c869,871
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
882,976c873,967
< system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits
< system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits
< system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits
< system.cpu.dcache.overall_hits::total 278710234 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses
< system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses
< system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses
< system.cpu.dcache.overall_misses::total 22162626 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles
< system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles
< system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits
> system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits
> system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits
> system.cpu.dcache.overall_hits::total 278057664 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses
> system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses
> system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 22142972 # number of overall misses
> system.cpu.dcache.overall_misses::total 22142972 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 145395860730 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 336812014094 # number of WriteReq miss cycles
> system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35299806246 # number of WriteInvalidateReq miss cycles
> system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35299806246 # number of WriteInvalidateReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked
978c969
< system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked
980c971
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked
984,1067c975,1058
< system.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks
< system.cpu.dcache.writebacks::total 7597183 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7148 # number of WriteInvalidateReq MSHR hits
< system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7148 # number of WriteInvalidateReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220034 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 220034 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 13745551 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 13745551 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 13745551 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 13745551 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5177976 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 5177976 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041958 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2041958 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190352 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 1190352 # number of SoftPFReq MSHR misses
< system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226180 # number of WriteInvalidateReq MSHR misses
< system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226180 # number of WriteInvalidateReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230589 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 230589 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency
< system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks
> system.cpu.dcache.writebacks::total 7577660 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits
> system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses
> system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses
> system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency
> system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
1075,1083c1066,1074
< system.cpu.icache.tags.replacements 15084162 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 15070815 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
1085,1087c1076,1078
< system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
1089,1127c1080,1118
< system.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 374842526 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 343955623 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 343955623 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 343955623 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 343955623 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 343955623 # number of overall hits
< system.cpu.icache.overall_hits::total 343955623 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 15802123 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 15802123 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 15802123 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 15802123 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 15802123 # number of overall misses
< system.cpu.icache.overall_misses::total 15802123 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 208192919846 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 208192919846 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 208192919846 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 208192919846 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 208192919846 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 359757746 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 359757746 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 359757746 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 359757746 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 359757746 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 359757746 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043924 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.043924 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.043924 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.043924 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.043924 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.043924 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13174.996793 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13174.996793 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 11061 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 374120916 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 374120916 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 343233622 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 343233622 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 343233622 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 343233622 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 343233622 # number of overall hits
> system.cpu.icache.overall_hits::total 343233622 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 15815747 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 15815747 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 15815747 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 15815747 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 15815747 # number of overall misses
> system.cpu.icache.overall_misses::total 15815747 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 208885866517 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 208885866517 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 208885866517 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 208885866517 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 208885866517 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 359049369 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 359049369 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked
1129c1120
< system.cpu.icache.blocked::no_mshrs 978 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked
1131c1122
< system.cpu.icache.avg_blocked_cycles::no_mshrs 11.309816 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked
1135,1168c1126,1159
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 717343 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 717343 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 717343 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 717343 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 717343 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 717343 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15084780 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 15084780 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 15084780 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 15084780 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 15084780 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 15084780 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171798629050 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 171798629050 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171798629050 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 171798629050 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171798629050 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 171798629050 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1412899000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1412899000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1412899000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 1412899000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041930 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.041930 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.041930 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
1174,1214c1165,1204
< system.cpu.l2cache.tags.replacements 1166252 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65308.801684 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 29080427 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1229042 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 23.661052 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2430267000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 37210.550558 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 324.848912 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 496.111863 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 7620.063188 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.567788 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004957 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007570 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116273 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.299945 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996533 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 62489 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 300 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2670 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5157 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953506 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 273259305 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 273259305 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 799874 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299425 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 15000245 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 6339023 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 22438567 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 7597183 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 7597183 # number of Writeback hits
< system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730326 # number of WriteInvalidateReq hits
< system.cpu.l2cache.WriteInvalidateReq_hits::total 730326 # number of WriteInvalidateReq hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 9466 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 9466 # number of UpgradeReq hits
---
> system.cpu.l2cache.tags.replacements 1159288 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits
> system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits
> system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 9499 # number of UpgradeReq hits
1217,1345c1207,1335
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1583904 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1583904 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 799874 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 299425 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 15000245 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 7922927 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 24022471 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 799874 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 299425 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 15000245 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 7922927 # number of overall hits
< system.cpu.l2cache.overall_hits::total 24022471 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3543 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3208 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 84445 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 256196 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 347392 # number of ReadReq misses
< system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495854 # number of WriteInvalidateReq misses
< system.cpu.l2cache.WriteInvalidateReq_misses::total 495854 # number of WriteInvalidateReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 34479 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 34479 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 417812 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 417812 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 3543 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 3208 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 84445 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 674008 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 765204 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 3543 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 3208 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 84445 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 674008 # number of overall misses
< system.cpu.l2cache.overall_misses::total 765204 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 284358999 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 261200750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6500329478 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21309046436 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28354935663 # number of ReadReq miss cycles
< system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 3493350 # number of WriteInvalidateReq miss cycles
< system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 3493350 # number of WriteInvalidateReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 414507203 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 414507203 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 72000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 72000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34565495113 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 34565495113 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 284358999 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 261200750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 6500329478 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 55874541549 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 62920430776 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 284358999 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 261200750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 6500329478 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 55874541549 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 62920430776 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 803417 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302633 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 15084690 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 6595219 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 22785959 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 7597183 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 7597183 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226180 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226180 # number of WriteInvalidateReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43945 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 43945 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2001716 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2001716 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 803417 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 302633 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 15084690 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 8596935 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 24787675 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 803417 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 302633 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 15084690 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 8596935 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 24787675 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004410 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010600 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005598 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038846 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015246 # miss rate for ReadReq accesses
< system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404389 # miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404389 # miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784594 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784594 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.208727 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.208727 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004410 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010600 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005598 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.078401 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.030870 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004410 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010600 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005598 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.078401 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.030870 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 80259.384420 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81421.680175 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76977.079496 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83174.781948 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 81622.304667 # average ReadReq miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 7.045118 # average WriteInvalidateReq miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 7.045118 # average WriteInvalidateReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12022.019287 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12022.019287 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 36000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 36000 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82729.780650 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82729.780650 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82227.001918 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82227.001918 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1579833 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1579833 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 805883 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 304376 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 14986718 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 7901540 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 23998517 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 805883 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 304376 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 14986718 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 7901540 # number of overall hits
> system.cpu.l2cache.overall_hits::total 23998517 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3166 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3020 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 84629 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 253686 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 344501 # number of ReadReq misses
> system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495562 # number of WriteInvalidateReq misses
> system.cpu.l2cache.WriteInvalidateReq_misses::total 495562 # number of WriteInvalidateReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 34430 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 34430 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 413693 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 413693 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 3166 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 3020 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 84629 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 667379 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 758194 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 3166 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 3020 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 84629 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 667379 # number of overall misses
> system.cpu.l2cache.overall_misses::total 758194 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276962259 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 263518500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7145038838 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22760355464 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 30445875061 # number of ReadReq miss cycles
> system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4785347 # number of WriteInvalidateReq miss cycles
> system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4785347 # number of WriteInvalidateReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553374801 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 553374801 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36882340129 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 36882340129 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276962259 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 263518500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 7145038838 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 59642695593 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 67328215190 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276962259 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 263518500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 7145038838 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 59642695593 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 67328215190 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 809049 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 307396 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 15071347 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 6575393 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 22763185 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 7577660 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 7577660 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226164 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226164 # number of WriteInvalidateReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43929 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 43929 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1993526 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1993526 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 809049 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 307396 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 15071347 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 8568919 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 24756711 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 809049 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 307396 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 15071347 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 8568919 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 24756711 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.003913 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009824 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005615 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038581 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015134 # miss rate for ReadReq accesses
> system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404156 # miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404156 # miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783765 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783765 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207518 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.207518 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.003913 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009824 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005615 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.077884 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.030626 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.003913 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009824 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005615 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.077884 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.030626 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87480.182881 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87257.781457 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 84427.782888 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287 # average ReadReq miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.656404 # average WriteInvalidateReq miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.656404 # average WriteInvalidateReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89153.889790 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 88800.775514 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 88800.775514 # average overall miss latency
1354,1355c1344,1345
< system.cpu.l2cache.writebacks::writebacks 982720 # number of writebacks
< system.cpu.l2cache.writebacks::total 982720 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 977263 # number of writebacks
> system.cpu.l2cache.writebacks::total 977263 # number of writebacks
1362,1461c1352,1451
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3543 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3208 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84445 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256175 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 347371 # number of ReadReq MSHR misses
< system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495854 # number of WriteInvalidateReq MSHR misses
< system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495854 # number of WriteInvalidateReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34479 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 34479 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 417812 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 417812 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3543 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3208 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 84445 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 673987 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 765183 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3543 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3208 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 84445 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 673987 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 765183 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 240086499 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 221074750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5441255518 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18116835264 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24019252031 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 19575424791 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 19575424791 # number of WriteInvalidateReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345346475 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345346475 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70001 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29394156879 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29394156879 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 240086499 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 221074750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5441255518 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47510992143 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 53413408910 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 240086499 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 221074750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5441255518 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47510992143 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 53413408910 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103864500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289749251 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393613751 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176073500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176073500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103864500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465822751 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569687251 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038843 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015245 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404389 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404389 # mshr miss rate for WriteInvalidateReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784594 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784594 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208727 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208727 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.030869 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.030869 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249 # average ReadReq mshr miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840 # average WriteInvalidateReq mshr miss latency
< system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840 # average WriteInvalidateReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses
> system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses
> system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 413693 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 413693 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3166 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3020 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency
> system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
1471,1496c1461,1486
< system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 606880 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.003347 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram
1501,1504c1491,1492
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 34397489 99.67% 99.67% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 115519 0.33% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram
1506,1509c1494,1497
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
1511c1499
< system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
1513c1501
< system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks)
1515c1503
< system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks)
1517c1505
< system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks)
1519c1507
< system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks)
1521,1524c1509,1512
< system.iobus.trans_dist::ReadReq 40381 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40381 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136733 # Transaction distribution
< system.iobus.trans_dist::WriteResp 30069 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 40283 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40283 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136558 # Transaction distribution
> system.iobus.trans_dist::WriteResp 29894 # Transaction distribution
1526c1514
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1536c1524
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes)
1541,1543c1529,1531
< system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes)
1546,1547c1534,1535
< system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1557c1545
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes)
1562,1564c1550,1552
< system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes)
1567,1568c1555,1556
< system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
1588c1576
< system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks)
1596c1584
< system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks)
1600c1588
< system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks)
1602c1590
< system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks)
1604c1592
< system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
---
> system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
1606,1607c1594,1595
< system.iocache.tags.replacements 115461 # number of replacements
< system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115456 # number of replacements
> system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use
1609c1597
< system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks.
1611,1616c1599,1604
< system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy
1620,1621c1608,1609
< system.iocache.tags.tag_accesses 1039668 # Number of tag accesses
< system.iocache.tags.data_accesses 1039668 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1039632 # Number of tag accesses
> system.iocache.tags.data_accesses 1039632 # Number of data accesses
1623,1624c1611,1612
< system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses
1630,1631c1618,1619
< system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8855 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8851 # number of demand (read+write) misses
1633,1647c1621,1635
< system.iocache.overall_misses::realview.ide 8815 # number of overall misses
< system.iocache.overall_misses::total 8855 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles
---
> system.iocache.overall_misses::realview.ide 8811 # number of overall misses
> system.iocache.overall_misses::total 8851 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles
1649,1650c1637,1638
< system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses)
1656,1657c1644,1645
< system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses
1659,1660c1647,1648
< system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses
1674,1687c1662,1675
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked
1689c1677
< system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked
1691c1679
< system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked
1695,1696c1683,1684
< system.iocache.writebacks::writebacks 106631 # number of writebacks
< system.iocache.writebacks::total 106631 # number of writebacks
---
> system.iocache.writebacks::writebacks 106630 # number of writebacks
> system.iocache.writebacks::total 106630 # number of writebacks
1698,1699c1686,1687
< system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses
1705,1706c1693,1694
< system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses
1708,1722c1696,1710
< system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles
1736,1748c1724,1736
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency
1750,1762c1738,1750
< system.membus.trans_dist::ReadReq 411277 # Transaction distribution
< system.membus.trans_dist::ReadResp 411277 # Transaction distribution
< system.membus.trans_dist::WriteReq 33858 # Transaction distribution
< system.membus.trans_dist::WriteResp 33858 # Transaction distribution
< system.membus.trans_dist::Writeback 1089351 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution
< system.membus.trans_dist::ReadExReq 417183 # Transaction distribution
< system.membus.trans_dist::ReadExResp 417183 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 408284 # Transaction distribution
> system.membus.trans_dist::ReadResp 408284 # Transaction distribution
> system.membus.trans_dist::WriteReq 33682 # Transaction distribution
> system.membus.trans_dist::WriteResp 33682 # Transaction distribution
> system.membus.trans_dist::Writeback 1083893 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution
> system.membus.trans_dist::ReadExReq 413056 # Transaction distribution
> system.membus.trans_dist::ReadExResp 413056 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes)
1764,1770c1752,1758
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes)
1772,1779c1760,1767
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 3154 # Total snoops (count)
< system.membus.snoop_fanout::samples 2500418 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 3023 # Total snoops (count)
> system.membus.snoop_fanout::samples 2488136 # Request fanout histogram
1784c1772
< system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram
1789,1790c1777,1778
< system.membus.snoop_fanout::total 2500418 # Request fanout histogram
< system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2488136 # Request fanout histogram
> system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
1792c1780
< system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
1794c1782
< system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks)
1796c1784
< system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks)
1798c1786
< system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks)
1800c1788
< system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks)
1845c1833
< system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed