1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.327143 # Number of seconds simulated
4sim_ticks 51327142820000 # Number of ticks simulated
5final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 161850 # Simulator instruction rate (inst/s)
8host_op_rate 190176 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9793667461 # Simulator tick rate (ticks/s)
10host_mem_usage 681320 # Number of bytes of host memory used
11host_seconds 5240.85 # Real time elapsed on the host
12sim_insts 848230502 # Number of instructions simulated
13sim_ops 996685945 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory
21system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory
22system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory
26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
27system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory
28system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory
32system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory
35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.readReqs 769104 # Number of read requests accepted
56system.physmem.writeReqs 1072027 # Number of write requests accepted
57system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue
58system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue
59system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM
60system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue
61system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM
62system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side
63system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side
64system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue
65system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67system.physmem.perBankRdBursts::0 44564 # Per bank write bursts
68system.physmem.perBankRdBursts::1 52315 # Per bank write bursts
69system.physmem.perBankRdBursts::2 47721 # Per bank write bursts
70system.physmem.perBankRdBursts::3 44538 # Per bank write bursts
71system.physmem.perBankRdBursts::4 44659 # Per bank write bursts
72system.physmem.perBankRdBursts::5 50872 # Per bank write bursts
73system.physmem.perBankRdBursts::6 46439 # Per bank write bursts
74system.physmem.perBankRdBursts::7 47959 # Per bank write bursts
75system.physmem.perBankRdBursts::8 44018 # Per bank write bursts
76system.physmem.perBankRdBursts::9 71274 # Per bank write bursts
77system.physmem.perBankRdBursts::10 43972 # Per bank write bursts
78system.physmem.perBankRdBursts::11 51692 # Per bank write bursts
79system.physmem.perBankRdBursts::12 45026 # Per bank write bursts
80system.physmem.perBankRdBursts::13 46672 # Per bank write bursts
81system.physmem.perBankRdBursts::14 42515 # Per bank write bursts
82system.physmem.perBankRdBursts::15 44140 # Per bank write bursts
83system.physmem.perBankWrBursts::0 64758 # Per bank write bursts
84system.physmem.perBankWrBursts::1 69412 # Per bank write bursts
85system.physmem.perBankWrBursts::2 67623 # Per bank write bursts
86system.physmem.perBankWrBursts::3 66442 # Per bank write bursts
87system.physmem.perBankWrBursts::4 66817 # Per bank write bursts
88system.physmem.perBankWrBursts::5 69740 # Per bank write bursts
89system.physmem.perBankWrBursts::6 65132 # Per bank write bursts
90system.physmem.perBankWrBursts::7 69008 # Per bank write bursts
91system.physmem.perBankWrBursts::8 65482 # Per bank write bursts
92system.physmem.perBankWrBursts::9 70623 # Per bank write bursts
93system.physmem.perBankWrBursts::10 64235 # Per bank write bursts
94system.physmem.perBankWrBursts::11 70444 # Per bank write bursts
95system.physmem.perBankWrBursts::12 64965 # Per bank write bursts
96system.physmem.perBankWrBursts::13 66804 # Per bank write bursts
97system.physmem.perBankWrBursts::14 64273 # Per bank write bursts
98system.physmem.perBankWrBursts::15 63998 # Per bank write bursts
99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
100system.physmem.numWrRetry 34 # Number of times write queue was full causing retry
101system.physmem.totGap 51327141408500 # Total gap between requests
102system.physmem.readPktSize::0 0 # Read request sizes (log2)
103system.physmem.readPktSize::1 0 # Read request sizes (log2)
104system.physmem.readPktSize::2 0 # Read request sizes (log2)
105system.physmem.readPktSize::3 13 # Read request sizes (log2)
106system.physmem.readPktSize::4 21272 # Read request sizes (log2)
107system.physmem.readPktSize::5 0 # Read request sizes (log2)
108system.physmem.readPktSize::6 747819 # Read request sizes (log2)
109system.physmem.writePktSize::0 0 # Write request sizes (log2)
110system.physmem.writePktSize::1 0 # Write request sizes (log2)
111system.physmem.writePktSize::2 1 # Write request sizes (log2)
112system.physmem.writePktSize::3 2572 # Write request sizes (log2)
113system.physmem.writePktSize::4 0 # Write request sizes (log2)
114system.physmem.writePktSize::5 0 # Write request sizes (log2)
115system.physmem.writePktSize::6 1069454 # Write request sizes (log2)
116system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see
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120system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see
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129system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see
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131system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see
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135system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
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155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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163system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see
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175system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see
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190system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see
212system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation
216system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation
226system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
233system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
234system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes
235system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads
277system.physmem.totQLat 15209667379 # Total ticks spent queuing
278system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM
279system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers
280system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst
281system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
282system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst
283system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s
284system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s
285system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s
286system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s
287system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
288system.physmem.busUtil 0.02 # Data bus utilization in percentage
289system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
290system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
291system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
292system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing
293system.physmem.readRowHits 580662 # Number of row buffer hits during reads
294system.physmem.writeRowHits 785598 # Number of row buffer hits during writes
295system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads
296system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes
297system.physmem.avgGap 27878049.64 # Average gap between requests
298system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined
299system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ)
300system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ)
301system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ)
302system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ)
303system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
304system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ)
305system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ)
306system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ)
307system.physmem_0.averagePower 668.451533 # Core power per rank (mW)
308system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states
309system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states
310system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states
312system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
313system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ)
314system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ)
315system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ)
316system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ)
317system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
318system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ)
319system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ)
320system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ)
321system.physmem_1.averagePower 668.449411 # Core power per rank (mW)
322system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states
323system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states
324system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
325system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states
326system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
327system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
328system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
329system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
330system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
331system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
332system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
333system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
334system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
335system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
336system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
337system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
338system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
339system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
340system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
341system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
342system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
343system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
344system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
345system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
346system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
350system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
351system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
352system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
353system.cpu.branchPred.lookups 225047911 # Number of BP lookups
354system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted
355system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect
356system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups
357system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits
358system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
359system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage
360system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target.
361system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions.
362system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups.
363system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits.
364system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses.
365system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
368system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

389system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
390system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
391system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
392system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
393system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
394system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
395system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
396system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
397system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
398system.cpu.dtb.walker.walks 948773 # Table walker walks requested
399system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors
400system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate
401system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate
402system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting
403system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency
404system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency
405system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency
406system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency
407system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency
408system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency
409system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency
410system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency
411system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency
412system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency
413system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency
414system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
415system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
416system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency
417system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency
418system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency
419system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency
420system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency
421system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency
422system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency
423system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency
424system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency
425system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency
426system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency
427system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency
428system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
429system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
430system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
431system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
432system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency
433system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution
434system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution
435system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution
436system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution
437system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution
438system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution
439system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution
440system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution
441system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution
442system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution
443system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution
444system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution
445system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution
446system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated
447system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated
448system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated
449system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst
450system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
451system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst
452system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst
453system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
454system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst
455system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst
456system.cpu.dtb.inst_hits 0 # ITB inst hits
457system.cpu.dtb.inst_misses 0 # ITB inst misses
458system.cpu.dtb.read_hits 169411407 # DTB read hits
459system.cpu.dtb.read_misses 675369 # DTB read misses
460system.cpu.dtb.write_hits 147344334 # DTB write hits
461system.cpu.dtb.write_misses 273404 # DTB write misses
462system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
463system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
464system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID
465system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID
466system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB
467system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions
468system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch
469system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
470system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions
471system.cpu.dtb.read_accesses 170086776 # DTB read accesses
472system.cpu.dtb.write_accesses 147617738 # DTB write accesses
473system.cpu.dtb.inst_accesses 0 # ITB inst accesses
474system.cpu.dtb.hits 316755741 # DTB hits
475system.cpu.dtb.misses 948773 # DTB misses
476system.cpu.dtb.accesses 317704514 # DTB accesses
477system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
478system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
479system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
481system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
482system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
485system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

499system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
500system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
501system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
502system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
503system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
504system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
505system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
506system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
507system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
508system.cpu.itb.walker.walks 162181 # Table walker walks requested
509system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors
510system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate
511system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate
512system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting
513system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency
514system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency
515system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency
516system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency
517system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency
518system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency
519system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency
520system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency
521system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency
522system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency
523system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
524system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
525system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
526system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
527system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
528system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
529system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency
530system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency
531system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency
532system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency
533system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency
534system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency
535system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency
536system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency
537system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency
538system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency
539system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency
540system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency
541system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
542system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
543system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
544system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
545system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency
546system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution
547system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution
548system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution
549system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution
550system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution
551system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution
552system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution
553system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution
554system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution
555system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated
556system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated
557system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated
558system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
559system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst
560system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst
561system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
562system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst
563system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst
564system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst
565system.cpu.itb.inst_hits 357038073 # ITB inst hits
566system.cpu.itb.inst_misses 162181 # ITB inst misses
567system.cpu.itb.read_hits 0 # DTB read hits
568system.cpu.itb.read_misses 0 # DTB read misses
569system.cpu.itb.write_hits 0 # DTB write hits
570system.cpu.itb.write_misses 0 # DTB write misses
571system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
572system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
573system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID
574system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID
575system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB
576system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
577system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
578system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
579system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions
580system.cpu.itb.read_accesses 0 # DTB read accesses
581system.cpu.itb.write_accesses 0 # DTB write accesses
582system.cpu.itb.inst_accesses 357200254 # ITB inst accesses
583system.cpu.itb.hits 357038073 # DTB hits
584system.cpu.itb.misses 162181 # DTB misses
585system.cpu.itb.accesses 357200254 # DTB accesses
586system.cpu.numPwrStateTransitions 32228 # Number of power state transitions
587system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state
588system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state
589system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state
590system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state
591system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state
592system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
593system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
594system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
595system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
596system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
597system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
598system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
599system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
600system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
601system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
602system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
603system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state
604system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states
605system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states
606system.cpu.numCycles 1631385344 # number of cpu cycles simulated
607system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
608system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
609system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss
610system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed
611system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered
612system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken
613system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked
614system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing
615system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb
616system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
617system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps
618system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions
619system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR
620system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched
621system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed
622system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed
623system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total)
624system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total)
625system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total)
626system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
627system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total)
628system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total)
629system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total)
630system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total)
631system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
632system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
633system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
634system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total)
635system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle
636system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle
637system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle
638system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked
639system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running
640system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking
641system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing
642system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch
643system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction
644system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode
645system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode
646system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing
647system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle
648system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking
649system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst
650system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running
651system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking
652system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename
653system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename
654system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full
655system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full
656system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full
657system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full
658system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers
659system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed
660system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made
661system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups
662system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups
663system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed
664system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing
665system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed
666system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed
667system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer
668system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit.
669system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit.
670system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads.
671system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores.
672system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec)
673system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ
674system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued
675system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued
676system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling
677system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph
678system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed
679system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle
680system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle
681system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle
682system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
683system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle
684system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle
685system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle
686system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle
687system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle
688system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle
689system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
690system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
691system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
692system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
693system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
694system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
695system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle
696system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
697system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available
698system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available
699system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available
700system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available
701system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available
702system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available
703system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available
704system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available
705system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
706system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available
707system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available
708system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available
709system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available
710system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available
711system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available
712system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available
713system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available
714system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available
715system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available
716system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available
717system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available
718system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available
719system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available
720system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available
721system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available
722system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available
723system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available
724system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available
725system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
726system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available
727system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available
728system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
729system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
730system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
731system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued
732system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued
733system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued
734system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued
735system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued
736system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued
737system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued
738system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued
739system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued
740system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued
741system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued
742system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued
743system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued
744system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued
745system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued
746system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued
747system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued
748system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued
749system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued
750system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued
751system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued
752system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued
753system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued
754system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued
755system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued
756system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued
757system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
758system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
759system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
760system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued
761system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued
762system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
763system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
764system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued
765system.cpu.iq.rate 0.641055 # Inst issue rate
766system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested
767system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst)
768system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads
769system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes
770system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses
771system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads
772system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes
773system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses
774system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses
775system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses
776system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores
777system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
778system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed
779system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed
780system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations
781system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed
782system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
783system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
784system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled
785system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked
786system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
787system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing
788system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking
789system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking
790system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ
791system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
792system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions
793system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions
794system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions
795system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall
796system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall
797system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations
798system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly
799system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly
800system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute
801system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions
802system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed
803system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute
804system.cpu.iew.exec_swp 0 # number of swp insts executed
805system.cpu.iew.exec_nop 234792 # number of nop insts executed
806system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed
807system.cpu.iew.exec_branches 196198672 # Number of branches executed
808system.cpu.iew.exec_stores 147339596 # Number of stores executed
809system.cpu.iew.exec_rate 0.633999 # Inst execution rate
810system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit
811system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back
812system.cpu.iew.wb_producers 437853372 # num instructions producing a value
813system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value
814system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle
815system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back
816system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit
817system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards
818system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted
819system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle
820system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle
821system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle
822system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
823system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle
824system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle
825system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle
826system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle
827system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle
828system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle
829system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle
830system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle
831system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle
832system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
833system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
834system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
835system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle
836system.cpu.commit.committedInsts 848230502 # Number of instructions committed
837system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed
838system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
839system.cpu.commit.refs 304433343 # Number of memory references committed
840system.cpu.commit.loads 159663418 # Number of loads committed
841system.cpu.commit.membars 6927415 # Number of memory barriers committed
842system.cpu.commit.branches 189324067 # Number of branches committed
843system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions.
844system.cpu.commit.int_insts 915721971 # Number of committed integer instructions.
845system.cpu.commit.function_calls 25285288 # Number of function calls committed.
846system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
847system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction
848system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction
849system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction
850system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
851system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction
852system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction
853system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction
854system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction
855system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction
856system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction
857system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction
858system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction
859system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction
860system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction
861system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction
862system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction
863system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction
864system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction
865system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction
866system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction
867system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction
868system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction
869system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction
870system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction
871system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction
872system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction
873system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
874system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
875system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
876system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction
877system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction
878system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
879system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
880system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction
881system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached
882system.cpu.rob.rob_reads 2589097882 # The number of ROB reads
883system.cpu.rob.rob_writes 2109106528 # The number of ROB writes
884system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself
885system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling
886system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
887system.cpu.committedInsts 848230502 # Number of Instructions Simulated
888system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated
889system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction
890system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads
891system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle
892system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads
893system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads
894system.cpu.int_regfile_writes 731394790 # number of integer regfile writes
895system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads
896system.cpu.fp_regfile_writes 780644 # number of floating regfile writes
897system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads
898system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes
899system.cpu.misc_regfile_reads 2570368432 # number of misc regfile reads
900system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes
901system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
902system.cpu.dcache.tags.replacements 9701158 # number of replacements
903system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
904system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks.
905system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks.
906system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks.
907system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
908system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor
909system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
910system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
911system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
912system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
913system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id
914system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
915system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
916system.cpu.dcache.tags.tag_accesses 1237018765 # Number of tag accesses
917system.cpu.dcache.tags.data_accesses 1237018765 # Number of data accesses
918system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
919system.cpu.dcache.ReadReq_hits::cpu.data 147199934 # number of ReadReq hits
920system.cpu.dcache.ReadReq_hits::total 147199934 # number of ReadReq hits
921system.cpu.dcache.WriteReq_hits::cpu.data 128255410 # number of WriteReq hits
922system.cpu.dcache.WriteReq_hits::total 128255410 # number of WriteReq hits
923system.cpu.dcache.SoftPFReq_hits::cpu.data 377663 # number of SoftPFReq hits
924system.cpu.dcache.SoftPFReq_hits::total 377663 # number of SoftPFReq hits
925system.cpu.dcache.WriteLineReq_hits::cpu.data 323814 # number of WriteLineReq hits
926system.cpu.dcache.WriteLineReq_hits::total 323814 # number of WriteLineReq hits
927system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295431 # number of LoadLockedReq hits
928system.cpu.dcache.LoadLockedReq_hits::total 3295431 # number of LoadLockedReq hits
929system.cpu.dcache.StoreCondReq_hits::cpu.data 3691256 # number of StoreCondReq hits
930system.cpu.dcache.StoreCondReq_hits::total 3691256 # number of StoreCondReq hits
931system.cpu.dcache.demand_hits::cpu.data 275779158 # number of demand (read+write) hits
932system.cpu.dcache.demand_hits::total 275779158 # number of demand (read+write) hits
933system.cpu.dcache.overall_hits::cpu.data 276156821 # number of overall hits
934system.cpu.dcache.overall_hits::total 276156821 # number of overall hits
935system.cpu.dcache.ReadReq_misses::cpu.data 9580915 # number of ReadReq misses
936system.cpu.dcache.ReadReq_misses::total 9580915 # number of ReadReq misses
937system.cpu.dcache.WriteReq_misses::cpu.data 11254027 # number of WriteReq misses
938system.cpu.dcache.WriteReq_misses::total 11254027 # number of WriteReq misses
939system.cpu.dcache.SoftPFReq_misses::cpu.data 1170464 # number of SoftPFReq misses
940system.cpu.dcache.SoftPFReq_misses::total 1170464 # number of SoftPFReq misses
941system.cpu.dcache.WriteLineReq_misses::cpu.data 1233639 # number of WriteLineReq misses
942system.cpu.dcache.WriteLineReq_misses::total 1233639 # number of WriteLineReq misses
943system.cpu.dcache.LoadLockedReq_misses::cpu.data 446709 # number of LoadLockedReq misses
944system.cpu.dcache.LoadLockedReq_misses::total 446709 # number of LoadLockedReq misses
945system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses
946system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
947system.cpu.dcache.demand_misses::cpu.data 22068581 # number of demand (read+write) misses
948system.cpu.dcache.demand_misses::total 22068581 # number of demand (read+write) misses
949system.cpu.dcache.overall_misses::cpu.data 23239045 # number of overall misses
950system.cpu.dcache.overall_misses::total 23239045 # number of overall misses
951system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000 # number of ReadReq miss cycles
952system.cpu.dcache.ReadReq_miss_latency::total 168767240000 # number of ReadReq miss cycles
953system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810 # number of WriteReq miss cycles
954system.cpu.dcache.WriteReq_miss_latency::total 444298934810 # number of WriteReq miss cycles
955system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52375248289 # number of WriteLineReq miss cycles
956system.cpu.dcache.WriteLineReq_miss_latency::total 52375248289 # number of WriteLineReq miss cycles
957system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6883962000 # number of LoadLockedReq miss cycles
958system.cpu.dcache.LoadLockedReq_miss_latency::total 6883962000 # number of LoadLockedReq miss cycles
959system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 380500 # number of StoreCondReq miss cycles
960system.cpu.dcache.StoreCondReq_miss_latency::total 380500 # number of StoreCondReq miss cycles
961system.cpu.dcache.demand_miss_latency::cpu.data 665441423099 # number of demand (read+write) miss cycles
962system.cpu.dcache.demand_miss_latency::total 665441423099 # number of demand (read+write) miss cycles
963system.cpu.dcache.overall_miss_latency::cpu.data 665441423099 # number of overall miss cycles
964system.cpu.dcache.overall_miss_latency::total 665441423099 # number of overall miss cycles
965system.cpu.dcache.ReadReq_accesses::cpu.data 156780849 # number of ReadReq accesses(hits+misses)
966system.cpu.dcache.ReadReq_accesses::total 156780849 # number of ReadReq accesses(hits+misses)
967system.cpu.dcache.WriteReq_accesses::cpu.data 139509437 # number of WriteReq accesses(hits+misses)
968system.cpu.dcache.WriteReq_accesses::total 139509437 # number of WriteReq accesses(hits+misses)
969system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548127 # number of SoftPFReq accesses(hits+misses)
970system.cpu.dcache.SoftPFReq_accesses::total 1548127 # number of SoftPFReq accesses(hits+misses)
971system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557453 # number of WriteLineReq accesses(hits+misses)
972system.cpu.dcache.WriteLineReq_accesses::total 1557453 # number of WriteLineReq accesses(hits+misses)
973system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3742140 # number of LoadLockedReq accesses(hits+misses)
974system.cpu.dcache.LoadLockedReq_accesses::total 3742140 # number of LoadLockedReq accesses(hits+misses)
975system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691264 # number of StoreCondReq accesses(hits+misses)
976system.cpu.dcache.StoreCondReq_accesses::total 3691264 # number of StoreCondReq accesses(hits+misses)
977system.cpu.dcache.demand_accesses::cpu.data 297847739 # number of demand (read+write) accesses
978system.cpu.dcache.demand_accesses::total 297847739 # number of demand (read+write) accesses
979system.cpu.dcache.overall_accesses::cpu.data 299395866 # number of overall (read+write) accesses
980system.cpu.dcache.overall_accesses::total 299395866 # number of overall (read+write) accesses
981system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061110 # miss rate for ReadReq accesses
982system.cpu.dcache.ReadReq_miss_rate::total 0.061110 # miss rate for ReadReq accesses
983system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080669 # miss rate for WriteReq accesses
984system.cpu.dcache.WriteReq_miss_rate::total 0.080669 # miss rate for WriteReq accesses
985system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756052 # miss rate for SoftPFReq accesses
986system.cpu.dcache.SoftPFReq_miss_rate::total 0.756052 # miss rate for SoftPFReq accesses
987system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792087 # miss rate for WriteLineReq accesses
988system.cpu.dcache.WriteLineReq_miss_rate::total 0.792087 # miss rate for WriteLineReq accesses
989system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119373 # miss rate for LoadLockedReq accesses
990system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119373 # miss rate for LoadLockedReq accesses
991system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
992system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
993system.cpu.dcache.demand_miss_rate::cpu.data 0.074093 # miss rate for demand accesses
994system.cpu.dcache.demand_miss_rate::total 0.074093 # miss rate for demand accesses
995system.cpu.dcache.overall_miss_rate::cpu.data 0.077620 # miss rate for overall accesses
996system.cpu.dcache.overall_miss_rate::total 0.077620 # miss rate for overall accesses
997system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700 # average ReadReq miss latency
998system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700 # average ReadReq miss latency
999system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884 # average WriteReq miss latency
1000system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884 # average WriteReq miss latency
1001system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354 # average WriteLineReq miss latency
1002system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354 # average WriteLineReq miss latency
1003system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686 # average LoadLockedReq miss latency
1004system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686 # average LoadLockedReq miss latency
1005system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000 # average StoreCondReq miss latency
1006system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000 # average StoreCondReq miss latency
1007system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859 # average overall miss latency
1008system.cpu.dcache.demand_avg_miss_latency::total 30153.339859 # average overall miss latency
1009system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622 # average overall miss latency
1010system.cpu.dcache.overall_avg_miss_latency::total 28634.628622 # average overall miss latency
1011system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked
1012system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1013system.cpu.dcache.blocked::no_mshrs 1601607 # number of cycles access was blocked
1014system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1015system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.120048 # average number of cycles each access was blocked
1016system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1017system.cpu.dcache.writebacks::writebacks 7504086 # number of writebacks
1018system.cpu.dcache.writebacks::total 7504086 # number of writebacks
1019system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4456599 # number of ReadReq MSHR hits
1020system.cpu.dcache.ReadReq_mshr_hits::total 4456599 # number of ReadReq MSHR hits
1021system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9250788 # number of WriteReq MSHR hits
1022system.cpu.dcache.WriteReq_mshr_hits::total 9250788 # number of WriteReq MSHR hits
1023system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7056 # number of WriteLineReq MSHR hits
1024system.cpu.dcache.WriteLineReq_mshr_hits::total 7056 # number of WriteLineReq MSHR hits
1025system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219268 # number of LoadLockedReq MSHR hits
1026system.cpu.dcache.LoadLockedReq_mshr_hits::total 219268 # number of LoadLockedReq MSHR hits
1027system.cpu.dcache.demand_mshr_hits::cpu.data 13714443 # number of demand (read+write) MSHR hits
1028system.cpu.dcache.demand_mshr_hits::total 13714443 # number of demand (read+write) MSHR hits
1029system.cpu.dcache.overall_mshr_hits::cpu.data 13714443 # number of overall MSHR hits
1030system.cpu.dcache.overall_mshr_hits::total 13714443 # number of overall MSHR hits
1031system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5124316 # number of ReadReq MSHR misses
1032system.cpu.dcache.ReadReq_mshr_misses::total 5124316 # number of ReadReq MSHR misses
1033system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003239 # number of WriteReq MSHR misses
1034system.cpu.dcache.WriteReq_mshr_misses::total 2003239 # number of WriteReq MSHR misses
1035system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163648 # number of SoftPFReq MSHR misses
1036system.cpu.dcache.SoftPFReq_mshr_misses::total 1163648 # number of SoftPFReq MSHR misses
1037system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226583 # number of WriteLineReq MSHR misses
1038system.cpu.dcache.WriteLineReq_mshr_misses::total 1226583 # number of WriteLineReq MSHR misses
1039system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227441 # number of LoadLockedReq MSHR misses
1040system.cpu.dcache.LoadLockedReq_mshr_misses::total 227441 # number of LoadLockedReq MSHR misses
1041system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses
1042system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
1043system.cpu.dcache.demand_mshr_misses::cpu.data 8354138 # number of demand (read+write) MSHR misses
1044system.cpu.dcache.demand_mshr_misses::total 8354138 # number of demand (read+write) MSHR misses
1045system.cpu.dcache.overall_mshr_misses::cpu.data 9517786 # number of overall MSHR misses
1046system.cpu.dcache.overall_mshr_misses::total 9517786 # number of overall MSHR misses
1047system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
1048system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
1049system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
1050system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
1051system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
1052system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
1053system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84959954500 # number of ReadReq MSHR miss cycles
1054system.cpu.dcache.ReadReq_mshr_miss_latency::total 84959954500 # number of ReadReq MSHR miss cycles
1055system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77558080846 # number of WriteReq MSHR miss cycles
1056system.cpu.dcache.WriteReq_mshr_miss_latency::total 77558080846 # number of WriteReq MSHR miss cycles
1057system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles
1058system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles
1059system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles
1060system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles
1061system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles
1062system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles
1063system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles
1064system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles
1065system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles
1066system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles
1067system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles
1068system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles
1069system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles
1070system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles
1071system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles
1072system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles
1073system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses
1074system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses
1075system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses
1076system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses
1077system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses
1078system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses
1079system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses
1080system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses
1081system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses
1082system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses
1083system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
1084system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
1085system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses
1086system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses
1087system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses
1088system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses
1089system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency
1090system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency
1091system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency
1092system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency
1093system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency
1094system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency
1095system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency
1096system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency
1097system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency
1098system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency
1099system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency
1100system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency
1101system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency
1102system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency
1103system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency
1104system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency
1105system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency
1106system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency
1107system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency
1108system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency
1109system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1110system.cpu.icache.tags.replacements 15134592 # number of replacements
1111system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use
1112system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks.
1113system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks.
1114system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks.
1115system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit.
1116system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor
1117system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy
1118system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy
1119system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1120system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
1121system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
1122system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
1123system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1124system.cpu.icache.tags.tag_accesses 371779021 # Number of tag accesses
1125system.cpu.icache.tags.data_accesses 371779021 # Number of data accesses
1126system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1127system.cpu.icache.ReadReq_hits::cpu.inst 340756209 # number of ReadReq hits
1128system.cpu.icache.ReadReq_hits::total 340756209 # number of ReadReq hits
1129system.cpu.icache.demand_hits::cpu.inst 340756209 # number of demand (read+write) hits
1130system.cpu.icache.demand_hits::total 340756209 # number of demand (read+write) hits
1131system.cpu.icache.overall_hits::cpu.inst 340756209 # number of overall hits
1132system.cpu.icache.overall_hits::total 340756209 # number of overall hits
1133system.cpu.icache.ReadReq_misses::cpu.inst 15887482 # number of ReadReq misses
1134system.cpu.icache.ReadReq_misses::total 15887482 # number of ReadReq misses
1135system.cpu.icache.demand_misses::cpu.inst 15887482 # number of demand (read+write) misses
1136system.cpu.icache.demand_misses::total 15887482 # number of demand (read+write) misses
1137system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses
1138system.cpu.icache.overall_misses::total 15887482 # number of overall misses
1139system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles
1140system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles
1141system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles
1142system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles
1143system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles
1144system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles
1145system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses)
1146system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses)
1147system.cpu.icache.demand_accesses::cpu.inst 356643691 # number of demand (read+write) accesses
1148system.cpu.icache.demand_accesses::total 356643691 # number of demand (read+write) accesses
1149system.cpu.icache.overall_accesses::cpu.inst 356643691 # number of overall (read+write) accesses
1150system.cpu.icache.overall_accesses::total 356643691 # number of overall (read+write) accesses
1151system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044547 # miss rate for ReadReq accesses
1152system.cpu.icache.ReadReq_miss_rate::total 0.044547 # miss rate for ReadReq accesses
1153system.cpu.icache.demand_miss_rate::cpu.inst 0.044547 # miss rate for demand accesses
1154system.cpu.icache.demand_miss_rate::total 0.044547 # miss rate for demand accesses
1155system.cpu.icache.overall_miss_rate::cpu.inst 0.044547 # miss rate for overall accesses
1156system.cpu.icache.overall_miss_rate::total 0.044547 # miss rate for overall accesses
1157system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897 # average ReadReq miss latency
1158system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897 # average ReadReq miss latency
1159system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency
1160system.cpu.icache.demand_avg_miss_latency::total 13527.519897 # average overall miss latency
1161system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency
1162system.cpu.icache.overall_avg_miss_latency::total 13527.519897 # average overall miss latency
1163system.cpu.icache.blocked_cycles::no_mshrs 24649 # number of cycles access was blocked
1164system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1165system.cpu.icache.blocked::no_mshrs 1517 # number of cycles access was blocked
1166system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1167system.cpu.icache.avg_blocked_cycles::no_mshrs 16.248517 # average number of cycles each access was blocked
1168system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1169system.cpu.icache.writebacks::writebacks 15134592 # number of writebacks
1170system.cpu.icache.writebacks::total 15134592 # number of writebacks
1171system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752151 # number of ReadReq MSHR hits
1172system.cpu.icache.ReadReq_mshr_hits::total 752151 # number of ReadReq MSHR hits
1173system.cpu.icache.demand_mshr_hits::cpu.inst 752151 # number of demand (read+write) MSHR hits
1174system.cpu.icache.demand_mshr_hits::total 752151 # number of demand (read+write) MSHR hits
1175system.cpu.icache.overall_mshr_hits::cpu.inst 752151 # number of overall MSHR hits
1176system.cpu.icache.overall_mshr_hits::total 752151 # number of overall MSHR hits
1177system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15135331 # number of ReadReq MSHR misses
1178system.cpu.icache.ReadReq_mshr_misses::total 15135331 # number of ReadReq MSHR misses
1179system.cpu.icache.demand_mshr_misses::cpu.inst 15135331 # number of demand (read+write) MSHR misses
1180system.cpu.icache.demand_mshr_misses::total 15135331 # number of demand (read+write) MSHR misses
1181system.cpu.icache.overall_mshr_misses::cpu.inst 15135331 # number of overall MSHR misses
1182system.cpu.icache.overall_mshr_misses::total 15135331 # number of overall MSHR misses
1183system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
1184system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
1185system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
1186system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
1187system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192625378387 # number of ReadReq MSHR miss cycles
1188system.cpu.icache.ReadReq_mshr_miss_latency::total 192625378387 # number of ReadReq MSHR miss cycles
1189system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192625378387 # number of demand (read+write) MSHR miss cycles
1190system.cpu.icache.demand_mshr_miss_latency::total 192625378387 # number of demand (read+write) MSHR miss cycles
1191system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387 # number of overall MSHR miss cycles
1192system.cpu.icache.overall_mshr_miss_latency::total 192625378387 # number of overall MSHR miss cycles
1193system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938500 # number of ReadReq MSHR uncacheable cycles
1194system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938500 # number of ReadReq MSHR uncacheable cycles
1195system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938500 # number of overall MSHR uncacheable cycles
1196system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938500 # number of overall MSHR uncacheable cycles
1197system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for ReadReq accesses
1198system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042438 # mshr miss rate for ReadReq accesses
1199system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for demand accesses
1200system.cpu.icache.demand_mshr_miss_rate::total 0.042438 # mshr miss rate for demand accesses
1201system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for overall accesses
1202system.cpu.icache.overall_mshr_miss_rate::total 0.042438 # mshr miss rate for overall accesses
1203system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12726.869230 # average ReadReq mshr miss latency
1204system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12726.869230 # average ReadReq mshr miss latency
1205system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12726.869230 # average overall mshr miss latency
1206system.cpu.icache.demand_avg_mshr_miss_latency::total 12726.869230 # average overall mshr miss latency
1207system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12726.869230 # average overall mshr miss latency
1208system.cpu.icache.overall_avg_mshr_miss_latency::total 12726.869230 # average overall mshr miss latency
1209system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency
1210system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
1211system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
1212system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
1213system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1214system.cpu.l2cache.tags.replacements 1148622 # number of replacements
1215system.cpu.l2cache.tags.tagsinuse 65301.900403 # Cycle average of tags in use
1216system.cpu.l2cache.tags.total_refs 46289210 # Total number of references to valid blocks.
1217system.cpu.l2cache.tags.sampled_refs 1211379 # Sample count of references to valid blocks.
1218system.cpu.l2cache.tags.avg_refs 38.211996 # Average number of references to valid blocks.
1219system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit.
1220system.cpu.l2cache.tags.occ_blocks::writebacks 37189.560843 # Average occupied blocks per requestor
1221system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 293.778433 # Average occupied blocks per requestor
1222system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 476.562000 # Average occupied blocks per requestor
1223system.cpu.l2cache.tags.occ_blocks::cpu.inst 7800.369043 # Average occupied blocks per requestor
1224system.cpu.l2cache.tags.occ_blocks::cpu.data 19541.630085 # Average occupied blocks per requestor
1225system.cpu.l2cache.tags.occ_percent::writebacks 0.567468 # Average percentage of cache occupancy
1226system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004483 # Average percentage of cache occupancy
1227system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007272 # Average percentage of cache occupancy
1228system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119024 # Average percentage of cache occupancy
1229system.cpu.l2cache.tags.occ_percent::cpu.data 0.298182 # Average percentage of cache occupancy
1230system.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy
1231system.cpu.l2cache.tags.occ_task_id_blocks::1023 234 # Occupied blocks per task id
1232system.cpu.l2cache.tags.occ_task_id_blocks::1024 62523 # Occupied blocks per task id
1233system.cpu.l2cache.tags.age_task_id_blocks_1023::4 234 # Occupied blocks per task id
1234system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
1235system.cpu.l2cache.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id
1236system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2712 # Occupied blocks per task id
1237system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5162 # Occupied blocks per task id
1238system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54018 # Occupied blocks per task id
1239system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003571 # Percentage of cache occupancy per task id
1240system.cpu.l2cache.tags.occ_task_id_percent::1024 0.954025 # Percentage of cache occupancy per task id
1241system.cpu.l2cache.tags.tag_accesses 410396361 # Number of tag accesses
1242system.cpu.l2cache.tags.data_accesses 410396361 # Number of data accesses
1243system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1244system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 787478 # number of ReadReq hits
1245system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297374 # number of ReadReq hits
1246system.cpu.l2cache.ReadReq_hits::total 1084852 # number of ReadReq hits
1247system.cpu.l2cache.WritebackDirty_hits::writebacks 7504086 # number of WritebackDirty hits
1248system.cpu.l2cache.WritebackDirty_hits::total 7504086 # number of WritebackDirty hits
1249system.cpu.l2cache.WritebackClean_hits::writebacks 15131991 # number of WritebackClean hits
1250system.cpu.l2cache.WritebackClean_hits::total 15131991 # number of WritebackClean hits
1251system.cpu.l2cache.UpgradeReq_hits::cpu.data 9360 # number of UpgradeReq hits
1252system.cpu.l2cache.UpgradeReq_hits::total 9360 # number of UpgradeReq hits
1253system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
1254system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
1255system.cpu.l2cache.ReadExReq_hits::cpu.data 1568311 # number of ReadExReq hits
1256system.cpu.l2cache.ReadExReq_hits::total 1568311 # number of ReadExReq hits
1257system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15051780 # number of ReadCleanReq hits
1258system.cpu.l2cache.ReadCleanReq_hits::total 15051780 # number of ReadCleanReq hits
1259system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6254855 # number of ReadSharedReq hits
1260system.cpu.l2cache.ReadSharedReq_hits::total 6254855 # number of ReadSharedReq hits
1261system.cpu.l2cache.InvalidateReq_hits::cpu.data 727039 # number of InvalidateReq hits
1262system.cpu.l2cache.InvalidateReq_hits::total 727039 # number of InvalidateReq hits
1263system.cpu.l2cache.demand_hits::cpu.dtb.walker 787478 # number of demand (read+write) hits
1264system.cpu.l2cache.demand_hits::cpu.itb.walker 297374 # number of demand (read+write) hits
1265system.cpu.l2cache.demand_hits::cpu.inst 15051780 # number of demand (read+write) hits
1266system.cpu.l2cache.demand_hits::cpu.data 7823166 # number of demand (read+write) hits
1267system.cpu.l2cache.demand_hits::total 23959798 # number of demand (read+write) hits
1268system.cpu.l2cache.overall_hits::cpu.dtb.walker 787478 # number of overall hits
1269system.cpu.l2cache.overall_hits::cpu.itb.walker 297374 # number of overall hits
1270system.cpu.l2cache.overall_hits::cpu.inst 15051780 # number of overall hits
1271system.cpu.l2cache.overall_hits::cpu.data 7823166 # number of overall hits
1272system.cpu.l2cache.overall_hits::total 23959798 # number of overall hits
1273system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3559 # number of ReadReq misses
1274system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3326 # number of ReadReq misses
1275system.cpu.l2cache.ReadReq_misses::total 6885 # number of ReadReq misses
1276system.cpu.l2cache.UpgradeReq_misses::cpu.data 34185 # number of UpgradeReq misses
1277system.cpu.l2cache.UpgradeReq_misses::total 34185 # number of UpgradeReq misses
1278system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
1279system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
1280system.cpu.l2cache.ReadExReq_misses::cpu.data 394921 # number of ReadExReq misses
1281system.cpu.l2cache.ReadExReq_misses::total 394921 # number of ReadExReq misses
1282system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83338 # number of ReadCleanReq misses
1283system.cpu.l2cache.ReadCleanReq_misses::total 83338 # number of ReadCleanReq misses
1284system.cpu.l2cache.ReadSharedReq_misses::cpu.data 257015 # number of ReadSharedReq misses
1285system.cpu.l2cache.ReadSharedReq_misses::total 257015 # number of ReadSharedReq misses
1286system.cpu.l2cache.InvalidateReq_misses::cpu.data 499544 # number of InvalidateReq misses
1287system.cpu.l2cache.InvalidateReq_misses::total 499544 # number of InvalidateReq misses
1288system.cpu.l2cache.demand_misses::cpu.dtb.walker 3559 # number of demand (read+write) misses
1289system.cpu.l2cache.demand_misses::cpu.itb.walker 3326 # number of demand (read+write) misses
1290system.cpu.l2cache.demand_misses::cpu.inst 83338 # number of demand (read+write) misses
1291system.cpu.l2cache.demand_misses::cpu.data 651936 # number of demand (read+write) misses
1292system.cpu.l2cache.demand_misses::total 742159 # number of demand (read+write) misses
1293system.cpu.l2cache.overall_misses::cpu.dtb.walker 3559 # number of overall misses
1294system.cpu.l2cache.overall_misses::cpu.itb.walker 3326 # number of overall misses
1295system.cpu.l2cache.overall_misses::cpu.inst 83338 # number of overall misses
1296system.cpu.l2cache.overall_misses::cpu.data 651936 # number of overall misses
1297system.cpu.l2cache.overall_misses::total 742159 # number of overall misses
1298system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 491952000 # number of ReadReq miss cycles
1299system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 462404000 # number of ReadReq miss cycles
1300system.cpu.l2cache.ReadReq_miss_latency::total 954356000 # number of ReadReq miss cycles
1301system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1389212000 # number of UpgradeReq miss cycles
1302system.cpu.l2cache.UpgradeReq_miss_latency::total 1389212000 # number of UpgradeReq miss cycles
1303system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 239000 # number of SCUpgradeReq miss cycles
1304system.cpu.l2cache.SCUpgradeReq_miss_latency::total 239000 # number of SCUpgradeReq miss cycles
1305system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55032106500 # number of ReadExReq miss cycles
1306system.cpu.l2cache.ReadExReq_miss_latency::total 55032106500 # number of ReadExReq miss cycles
1307system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11239521500 # number of ReadCleanReq miss cycles
1308system.cpu.l2cache.ReadCleanReq_miss_latency::total 11239521500 # number of ReadCleanReq miss cycles
1309system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35839167500 # number of ReadSharedReq miss cycles
1310system.cpu.l2cache.ReadSharedReq_miss_latency::total 35839167500 # number of ReadSharedReq miss cycles
1311system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 7495000 # number of InvalidateReq miss cycles
1312system.cpu.l2cache.InvalidateReq_miss_latency::total 7495000 # number of InvalidateReq miss cycles
1313system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 491952000 # number of demand (read+write) miss cycles
1314system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 462404000 # number of demand (read+write) miss cycles
1315system.cpu.l2cache.demand_miss_latency::cpu.inst 11239521500 # number of demand (read+write) miss cycles
1316system.cpu.l2cache.demand_miss_latency::cpu.data 90871274000 # number of demand (read+write) miss cycles
1317system.cpu.l2cache.demand_miss_latency::total 103065151500 # number of demand (read+write) miss cycles
1318system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 491952000 # number of overall miss cycles
1319system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 462404000 # number of overall miss cycles
1320system.cpu.l2cache.overall_miss_latency::cpu.inst 11239521500 # number of overall miss cycles
1321system.cpu.l2cache.overall_miss_latency::cpu.data 90871274000 # number of overall miss cycles
1322system.cpu.l2cache.overall_miss_latency::total 103065151500 # number of overall miss cycles
1323system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 791037 # number of ReadReq accesses(hits+misses)
1324system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 300700 # number of ReadReq accesses(hits+misses)
1325system.cpu.l2cache.ReadReq_accesses::total 1091737 # number of ReadReq accesses(hits+misses)
1326system.cpu.l2cache.WritebackDirty_accesses::writebacks 7504086 # number of WritebackDirty accesses(hits+misses)
1327system.cpu.l2cache.WritebackDirty_accesses::total 7504086 # number of WritebackDirty accesses(hits+misses)
1328system.cpu.l2cache.WritebackClean_accesses::writebacks 15131991 # number of WritebackClean accesses(hits+misses)
1329system.cpu.l2cache.WritebackClean_accesses::total 15131991 # number of WritebackClean accesses(hits+misses)
1330system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43545 # number of UpgradeReq accesses(hits+misses)
1331system.cpu.l2cache.UpgradeReq_accesses::total 43545 # number of UpgradeReq accesses(hits+misses)
1332system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses)
1333system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses)
1334system.cpu.l2cache.ReadExReq_accesses::cpu.data 1963232 # number of ReadExReq accesses(hits+misses)
1335system.cpu.l2cache.ReadExReq_accesses::total 1963232 # number of ReadExReq accesses(hits+misses)
1336system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15135118 # number of ReadCleanReq accesses(hits+misses)
1337system.cpu.l2cache.ReadCleanReq_accesses::total 15135118 # number of ReadCleanReq accesses(hits+misses)
1338system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6511870 # number of ReadSharedReq accesses(hits+misses)
1339system.cpu.l2cache.ReadSharedReq_accesses::total 6511870 # number of ReadSharedReq accesses(hits+misses)
1340system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226583 # number of InvalidateReq accesses(hits+misses)
1341system.cpu.l2cache.InvalidateReq_accesses::total 1226583 # number of InvalidateReq accesses(hits+misses)
1342system.cpu.l2cache.demand_accesses::cpu.dtb.walker 791037 # number of demand (read+write) accesses
1343system.cpu.l2cache.demand_accesses::cpu.itb.walker 300700 # number of demand (read+write) accesses
1344system.cpu.l2cache.demand_accesses::cpu.inst 15135118 # number of demand (read+write) accesses
1345system.cpu.l2cache.demand_accesses::cpu.data 8475102 # number of demand (read+write) accesses
1346system.cpu.l2cache.demand_accesses::total 24701957 # number of demand (read+write) accesses
1347system.cpu.l2cache.overall_accesses::cpu.dtb.walker 791037 # number of overall (read+write) accesses
1348system.cpu.l2cache.overall_accesses::cpu.itb.walker 300700 # number of overall (read+write) accesses
1349system.cpu.l2cache.overall_accesses::cpu.inst 15135118 # number of overall (read+write) accesses
1350system.cpu.l2cache.overall_accesses::cpu.data 8475102 # number of overall (read+write) accesses
1351system.cpu.l2cache.overall_accesses::total 24701957 # number of overall (read+write) accesses
1352system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004499 # miss rate for ReadReq accesses
1353system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.011061 # miss rate for ReadReq accesses
1354system.cpu.l2cache.ReadReq_miss_rate::total 0.006306 # miss rate for ReadReq accesses
1355system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785050 # miss rate for UpgradeReq accesses
1356system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785050 # miss rate for UpgradeReq accesses
1357system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
1358system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
1359system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.201159 # miss rate for ReadExReq accesses
1360system.cpu.l2cache.ReadExReq_miss_rate::total 0.201159 # miss rate for ReadExReq accesses
1361system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005506 # miss rate for ReadCleanReq accesses
1362system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005506 # miss rate for ReadCleanReq accesses
1363system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039469 # miss rate for ReadSharedReq accesses
1364system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039469 # miss rate for ReadSharedReq accesses
1365system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.407265 # miss rate for InvalidateReq accesses
1366system.cpu.l2cache.InvalidateReq_miss_rate::total 0.407265 # miss rate for InvalidateReq accesses
1367system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004499 # miss rate for demand accesses
1368system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.011061 # miss rate for demand accesses
1369system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005506 # miss rate for demand accesses
1370system.cpu.l2cache.demand_miss_rate::cpu.data 0.076924 # miss rate for demand accesses
1371system.cpu.l2cache.demand_miss_rate::total 0.030045 # miss rate for demand accesses
1372system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004499 # miss rate for overall accesses
1373system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.011061 # miss rate for overall accesses
1374system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005506 # miss rate for overall accesses
1375system.cpu.l2cache.overall_miss_rate::cpu.data 0.076924 # miss rate for overall accesses
1376system.cpu.l2cache.overall_miss_rate::total 0.030045 # miss rate for overall accesses
1377system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138227.592020 # average ReadReq miss latency
1378system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139027.059531 # average ReadReq miss latency
1379system.cpu.l2cache.ReadReq_avg_miss_latency::total 138613.798112 # average ReadReq miss latency
1380system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40638.057628 # average UpgradeReq miss latency
1381system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40638.057628 # average UpgradeReq miss latency
1382system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 59750 # average SCUpgradeReq miss latency
1383system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 59750 # average SCUpgradeReq miss latency
1384system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139349.658539 # average ReadExReq miss latency
1385system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139349.658539 # average ReadExReq miss latency
1386system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134866.705464 # average ReadCleanReq miss latency
1387system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134866.705464 # average ReadCleanReq miss latency
1388system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139443.874871 # average ReadSharedReq miss latency
1389system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139443.874871 # average ReadSharedReq miss latency
1390system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 15.003683 # average InvalidateReq miss latency
1391system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 15.003683 # average InvalidateReq miss latency
1392system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138227.592020 # average overall miss latency
1393system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139027.059531 # average overall miss latency
1394system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134866.705464 # average overall miss latency
1395system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139386.801772 # average overall miss latency
1396system.cpu.l2cache.demand_avg_miss_latency::total 138872.063129 # average overall miss latency
1397system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138227.592020 # average overall miss latency
1398system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139027.059531 # average overall miss latency
1399system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134866.705464 # average overall miss latency
1400system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139386.801772 # average overall miss latency
1401system.cpu.l2cache.overall_avg_miss_latency::total 138872.063129 # average overall miss latency
1402system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1403system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1404system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1405system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1406system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1407system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1408system.cpu.l2cache.writebacks::writebacks 962824 # number of writebacks
1409system.cpu.l2cache.writebacks::total 962824 # number of writebacks
1410system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
1411system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
1412system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
1413system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
1414system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
1415system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
1416system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
1417system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
1418system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
1419system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
1420system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3558 # number of ReadReq MSHR misses
1421system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3326 # number of ReadReq MSHR misses
1422system.cpu.l2cache.ReadReq_mshr_misses::total 6884 # number of ReadReq MSHR misses
1423system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
1424system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
1425system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34185 # number of UpgradeReq MSHR misses
1426system.cpu.l2cache.UpgradeReq_mshr_misses::total 34185 # number of UpgradeReq MSHR misses
1427system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
1428system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
1429system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 394921 # number of ReadExReq MSHR misses
1430system.cpu.l2cache.ReadExReq_mshr_misses::total 394921 # number of ReadExReq MSHR misses
1431system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 83338 # number of ReadCleanReq MSHR misses
1432system.cpu.l2cache.ReadCleanReq_mshr_misses::total 83338 # number of ReadCleanReq MSHR misses
1433system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256994 # number of ReadSharedReq MSHR misses
1434system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256994 # number of ReadSharedReq MSHR misses
1435system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 499544 # number of InvalidateReq MSHR misses
1436system.cpu.l2cache.InvalidateReq_mshr_misses::total 499544 # number of InvalidateReq MSHR misses
1437system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3558 # number of demand (read+write) MSHR misses
1438system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3326 # number of demand (read+write) MSHR misses
1439system.cpu.l2cache.demand_mshr_misses::cpu.inst 83338 # number of demand (read+write) MSHR misses
1440system.cpu.l2cache.demand_mshr_misses::cpu.data 651915 # number of demand (read+write) MSHR misses
1441system.cpu.l2cache.demand_mshr_misses::total 742137 # number of demand (read+write) MSHR misses
1442system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3558 # number of overall MSHR misses
1443system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3326 # number of overall MSHR misses
1444system.cpu.l2cache.overall_mshr_misses::cpu.inst 83338 # number of overall MSHR misses
1445system.cpu.l2cache.overall_mshr_misses::cpu.data 651915 # number of overall MSHR misses
1446system.cpu.l2cache.overall_mshr_misses::total 742137 # number of overall MSHR misses
1447system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
1448system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
1449system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54972 # number of ReadReq MSHR uncacheable
1450system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
1451system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
1452system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
1453system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
1454system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88668 # number of overall MSHR uncacheable misses
1455system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 456305510 # number of ReadReq MSHR miss cycles
1456system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 429144000 # number of ReadReq MSHR miss cycles
1457system.cpu.l2cache.ReadReq_mshr_miss_latency::total 885449510 # number of ReadReq MSHR miss cycles
1458system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2325232000 # number of UpgradeReq MSHR miss cycles
1459system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2325232000 # number of UpgradeReq MSHR miss cycles
1460system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 277500 # number of SCUpgradeReq MSHR miss cycles
1461system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 277500 # number of SCUpgradeReq MSHR miss cycles
1462system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 51081891916 # number of ReadExReq MSHR miss cycles
1463system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 51081891916 # number of ReadExReq MSHR miss cycles
1464system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10406063168 # number of ReadCleanReq MSHR miss cycles
1465system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10406063168 # number of ReadCleanReq MSHR miss cycles
1466system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33266030305 # number of ReadSharedReq MSHR miss cycles
1467system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33266030305 # number of ReadSharedReq MSHR miss cycles
1468system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 34915200500 # number of InvalidateReq MSHR miss cycles
1469system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 34915200500 # number of InvalidateReq MSHR miss cycles
1470system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 456305510 # number of demand (read+write) MSHR miss cycles
1471system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 429144000 # number of demand (read+write) MSHR miss cycles
1472system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10406063168 # number of demand (read+write) MSHR miss cycles
1473system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84347922221 # number of demand (read+write) MSHR miss cycles
1474system.cpu.l2cache.demand_mshr_miss_latency::total 95639434899 # number of demand (read+write) MSHR miss cycles
1475system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 456305510 # number of overall MSHR miss cycles
1476system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 429144000 # number of overall MSHR miss cycles
1477system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10406063168 # number of overall MSHR miss cycles
1478system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84347922221 # number of overall MSHR miss cycles
1479system.cpu.l2cache.overall_mshr_miss_latency::total 95639434899 # number of overall MSHR miss cycles
1480system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763500 # number of ReadReq MSHR uncacheable cycles
1481system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770936000 # number of ReadReq MSHR uncacheable cycles
1482system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189699500 # number of ReadReq MSHR uncacheable cycles
1483system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles
1484system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770936000 # number of overall MSHR uncacheable cycles
1485system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189699500 # number of overall MSHR uncacheable cycles
1486system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for ReadReq accesses
1487system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for ReadReq accesses
1488system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006306 # mshr miss rate for ReadReq accesses
1489system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1490system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1491system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785050 # mshr miss rate for UpgradeReq accesses
1492system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785050 # mshr miss rate for UpgradeReq accesses
1493system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
1494system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
1495system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201159 # mshr miss rate for ReadExReq accesses
1496system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201159 # mshr miss rate for ReadExReq accesses
1497system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for ReadCleanReq accesses
1498system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005506 # mshr miss rate for ReadCleanReq accesses
1499system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039465 # mshr miss rate for ReadSharedReq accesses
1500system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039465 # mshr miss rate for ReadSharedReq accesses
1501system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407265 # mshr miss rate for InvalidateReq accesses
1502system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407265 # mshr miss rate for InvalidateReq accesses
1503system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for demand accesses
1504system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for demand accesses
1505system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for demand accesses
1506system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for demand accesses
1507system.cpu.l2cache.demand_mshr_miss_rate::total 0.030044 # mshr miss rate for demand accesses
1508system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses
1509system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses
1510system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses
1511system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses
1512system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses
1513system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency
1514system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency
1515system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency
1516system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency
1517system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency
1518system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency
1519system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency
1520system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency
1521system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency
1522system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency
1523system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency
1524system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency
1525system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency
1526system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency
1527system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency
1528system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency
1529system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency
1530system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency
1531system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency
1532system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency
1533system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency
1534system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency
1535system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency
1536system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency
1537system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency
1538system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency
1539system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency
1540system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency
1541system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency
1542system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency
1543system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency
1544system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter.
1545system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1546system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1547system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter.
1548system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1549system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1550system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1551system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution
1552system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution
1553system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
1554system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
1555system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution
1556system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution
1557system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution
1558system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution
1559system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution
1560system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution
1561system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution
1562system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution
1563system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution
1564system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution
1565system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution
1566system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution
1567system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes)
1568system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes)
1569system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes)
1570system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes)
1571system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes)
1572system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes)
1573system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes)
1574system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes)
1575system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes)
1576system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes)
1577system.cpu.toL2Bus.snoops 1852603 # Total snoops (count)
1578system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes)
1579system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram
1580system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram
1581system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram
1582system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1583system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram
1584system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram
1585system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1586system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1587system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1588system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1589system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram
1590system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks)
1591system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1592system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks)
1593system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1594system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks)
1595system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1596system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks)
1597system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1598system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks)
1599system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1600system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks)
1601system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1602system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1603system.iobus.trans_dist::ReadReq 40293 # Transaction distribution
1604system.iobus.trans_dist::ReadResp 40293 # Transaction distribution
1605system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1606system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1607system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1608system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1609system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1610system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1611system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1612system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1613system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1614system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1615system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1616system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1617system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1618system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1619system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1620system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
1621system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes)
1622system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes)
1623system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1624system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1625system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes)
1626system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
1627system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1628system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
1629system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1630system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1631system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1632system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1633system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1634system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1635system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1636system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1637system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1638system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1639system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
1640system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes)
1641system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes)
1642system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1643system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1644system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes)
1645system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks)
1646system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1647system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
1648system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1649system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks)
1650system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1651system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
1652system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1653system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
1654system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1655system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
1656system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1657system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
1658system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1659system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
1660system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1661system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
1662system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1663system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
1664system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1665system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
1666system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1667system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks)
1668system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1669system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks)
1670system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1671system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks)
1672system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1673system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1674system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1675system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks)
1676system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1677system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1678system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1679system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1680system.iocache.tags.replacements 115453 # number of replacements
1681system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use
1682system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1683system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks.
1684system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1685system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit.
1686system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor
1687system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor
1688system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy
1689system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy
1690system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy
1691system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1692system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1693system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1694system.iocache.tags.tag_accesses 1039605 # Number of tag accesses
1695system.iocache.tags.data_accesses 1039605 # Number of data accesses
1696system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1697system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1698system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses
1699system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses
1700system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1701system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1702system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1703system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1704system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1705system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses
1706system.iocache.demand_misses::total 115512 # number of demand (read+write) misses
1707system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1708system.iocache.overall_misses::realview.ide 115472 # number of overall misses
1709system.iocache.overall_misses::total 115512 # number of overall misses
1710system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles
1711system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles
1712system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles
1713system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
1714system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
1715system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles
1716system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles
1717system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles
1718system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles
1719system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles
1720system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles
1721system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles
1722system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles
1723system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1724system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses)
1725system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses)
1726system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1727system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1728system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
1729system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
1730system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1731system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses
1732system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses
1733system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1734system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses
1735system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses
1736system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1737system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1738system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1739system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1740system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1741system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
1742system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1743system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1744system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1745system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1746system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1747system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1748system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1749system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency
1750system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency
1751system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency
1752system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
1753system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
1754system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency
1755system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency
1756system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency
1757system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency
1758system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency
1759system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency
1760system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency
1761system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency
1762system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked
1763system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1764system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked
1765system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1766system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked
1767system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1768system.iocache.writebacks::writebacks 106630 # number of writebacks
1769system.iocache.writebacks::total 106630 # number of writebacks
1770system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1771system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses
1772system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses
1773system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1774system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1775system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
1776system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
1777system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1778system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses
1779system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses
1780system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1781system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses
1782system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses
1783system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles
1784system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles
1785system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles
1786system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
1787system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
1788system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles
1789system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles
1790system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles
1791system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles
1792system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles
1793system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles
1794system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles
1795system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles
1796system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1797system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1798system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1799system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1800system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1801system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
1802system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1803system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1804system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1805system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1806system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1807system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1808system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1809system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency
1810system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency
1811system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency
1812system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
1813system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
1814system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency
1815system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency
1816system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency
1817system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency
1818system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency
1819system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency
1820system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency
1821system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency
1822system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1823system.membus.trans_dist::ReadReq 54972 # Transaction distribution
1824system.membus.trans_dist::ReadResp 411033 # Transaction distribution
1825system.membus.trans_dist::WriteReq 33696 # Transaction distribution
1826system.membus.trans_dist::WriteResp 33696 # Transaction distribution
1827system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution
1828system.membus.trans_dist::CleanEvict 193565 # Transaction distribution
1829system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution
1830system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
1831system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
1832system.membus.trans_dist::ReadExReq 394310 # Transaction distribution
1833system.membus.trans_dist::ReadExResp 394310 # Transaction distribution
1834system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution
1835system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution
1836system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
1837system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
1838system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
1839system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes)
1840system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes)
1841system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes)
1842system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes)
1843system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes)
1844system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
1845system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
1846system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
1847system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes)
1848system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes)
1849system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes)
1850system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes)
1851system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes)
1852system.membus.snoops 2560 # Total snoops (count)
1853system.membus.snoopTraffic 163328 # Total snoop traffic (bytes)
1854system.membus.snoop_fanout::samples 2743103 # Request fanout histogram
1855system.membus.snoop_fanout::mean 1 # Request fanout histogram
1856system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1857system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1858system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1859system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram
1860system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1861system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1862system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1863system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1864system.membus.snoop_fanout::total 2743103 # Request fanout histogram
1865system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks)
1866system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1867system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
1868system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1869system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks)
1870system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1871system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks)
1872system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1873system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks)
1874system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1875system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks)
1876system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1877system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1878system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1879system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1880system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1881system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1882system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1883system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1884system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1885system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1886system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1887system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1888system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1889system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1890system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1891system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1892system.realview.ethernet.txBytes 966 # Bytes Transmitted
1893system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1894system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1895system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1896system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1897system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1898system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1899system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1900system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1901system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
1902system.realview.ethernet.totPackets 3 # Total Packets
1903system.realview.ethernet.totBytes 966 # Total Bytes
1904system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
1905system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
1906system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
1907system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1908system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
1909system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1910system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1911system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
1912system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1913system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU

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1926system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1927system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1928system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1929system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1930system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1931system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1932system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1933system.realview.ethernet.droppedPackets 0 # number of packets dropped
1934system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1935system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1936system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1937system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1938system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1939system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1940system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1941system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1942system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1943system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1944system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1945system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1946system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1947system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1948system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1949system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1950system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1951system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1952system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1953system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1954system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1955system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1956system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states
1957system.cpu.kern.inst.arm 0 # number of arm instructions executed
1958system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed
1959
1960---------- End Simulation Statistics ----------