1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.557115 # Number of seconds simulated
4sim_ticks 51557114994500 # Number of ticks simulated
5final_tick 51557114994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 111994 # Simulator instruction rate (inst/s)
8host_op_rate 131638 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5181426993 # Simulator tick rate (ticks/s)
10host_mem_usage 668412 # Number of bytes of host memory used
11host_seconds 9950.37 # Real time elapsed on the host
12sim_insts 1114380469 # Number of instructions simulated
13sim_ops 1309844804 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
17system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
18system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
19system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
20system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
21system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
22system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
23system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
24system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
25system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
27system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
28system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
29system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
30system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
31system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bytes_read::realview.ide 437568 # Number of bytes read from this memory
33system.physmem.bytes_read::cpu.dtb.walker 1002304 # Number of bytes read from this memory
34system.physmem.bytes_read::cpu.itb.walker 1237760 # Number of bytes read from this memory
35system.physmem.bytes_read::cpu.inst 6145632 # Number of bytes read from this memory
36system.physmem.bytes_read::cpu.data 128560840 # Number of bytes read from this memory
37system.physmem.bytes_read::total 137384104 # Number of bytes read from this memory
38system.physmem.bytes_inst_read::cpu.inst 6145632 # Number of instructions bytes read from this memory
39system.physmem.bytes_inst_read::total 6145632 # Number of instructions bytes read from this memory
40system.physmem.bytes_written::writebacks 102180288 # Number of bytes written to this memory
41system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
42system.physmem.bytes_written::cpu.data 102783780 # Number of bytes written to this memory
43system.physmem.bytes_written::total 211790564 # Number of bytes written to this memory
44system.physmem.num_reads::realview.ide 6837 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu.dtb.walker 15661 # Number of read requests responded to by this memory
46system.physmem.num_reads::cpu.itb.walker 19340 # Number of read requests responded to by this memory
47system.physmem.num_reads::cpu.inst 111978 # Number of read requests responded to by this memory
48system.physmem.num_reads::cpu.data 2008776 # Number of read requests responded to by this memory
49system.physmem.num_reads::total 2162592 # Number of read requests responded to by this memory
50system.physmem.num_writes::writebacks 1596567 # Number of write requests responded to by this memory
51system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
52system.physmem.num_writes::cpu.data 1608248 # Number of write requests responded to by this memory
53system.physmem.num_writes::total 3311479 # Number of write requests responded to by this memory
54system.physmem.bw_read::realview.ide 8487 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu.dtb.walker 19441 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu.itb.walker 24008 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu.inst 119200 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu.data 2493562 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::total 2664697 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu.inst 119200 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::total 119200 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_write::writebacks 1981885 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::realview.ide 132406 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu.data 1993591 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::total 4107882 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_total::writebacks 1981885 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::realview.ide 140894 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu.dtb.walker 19441 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu.itb.walker 24008 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu.inst 119200 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu.data 4487152 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::total 6772580 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.readReqs 2162592 # Number of read requests accepted
74system.physmem.writeReqs 3311479 # Number of write requests accepted
75system.physmem.readBursts 2162592 # Number of DRAM read bursts, including those serviced by the write queue
76system.physmem.writeBursts 3311479 # Number of DRAM write bursts, including those merged in the write queue
77system.physmem.bytesReadDRAM 138204608 # Total number of bytes read from DRAM
78system.physmem.bytesReadWrQ 201280 # Total number of bytes read from write queue
79system.physmem.bytesWritten 207618304 # Total number of bytes written to DRAM
80system.physmem.bytesReadSys 137384104 # Total read bytes from the system interface side
81system.physmem.bytesWrittenSys 211790564 # Total written bytes from the system interface side
82system.physmem.servicedByWrQ 3145 # Number of DRAM read bursts serviced by the write queue
83system.physmem.mergedWrBursts 67428 # Number of DRAM write bursts merged with an existing one
84system.physmem.neitherReadNorWriteReqs 48470 # Number of requests that are neither read nor write
85system.physmem.perBankRdBursts::0 140382 # Per bank write bursts
86system.physmem.perBankRdBursts::1 139333 # Per bank write bursts
87system.physmem.perBankRdBursts::2 140658 # Per bank write bursts
88system.physmem.perBankRdBursts::3 133921 # Per bank write bursts
89system.physmem.perBankRdBursts::4 130324 # Per bank write bursts
90system.physmem.perBankRdBursts::5 134612 # Per bank write bursts
91system.physmem.perBankRdBursts::6 126217 # Per bank write bursts
92system.physmem.perBankRdBursts::7 133097 # Per bank write bursts
93system.physmem.perBankRdBursts::8 129592 # Per bank write bursts
94system.physmem.perBankRdBursts::9 157619 # Per bank write bursts
95system.physmem.perBankRdBursts::10 133394 # Per bank write bursts
96system.physmem.perBankRdBursts::11 133867 # Per bank write bursts
97system.physmem.perBankRdBursts::12 132326 # Per bank write bursts
98system.physmem.perBankRdBursts::13 132284 # Per bank write bursts
99system.physmem.perBankRdBursts::14 133117 # Per bank write bursts
100system.physmem.perBankRdBursts::15 128704 # Per bank write bursts
101system.physmem.perBankWrBursts::0 201659 # Per bank write bursts
102system.physmem.perBankWrBursts::1 203665 # Per bank write bursts
103system.physmem.perBankWrBursts::2 231223 # Per bank write bursts
104system.physmem.perBankWrBursts::3 188549 # Per bank write bursts
105system.physmem.perBankWrBursts::4 224931 # Per bank write bursts
106system.physmem.perBankWrBursts::5 188791 # Per bank write bursts
107system.physmem.perBankWrBursts::6 176287 # Per bank write bursts
108system.physmem.perBankWrBursts::7 226882 # Per bank write bursts
109system.physmem.perBankWrBursts::8 203233 # Per bank write bursts
110system.physmem.perBankWrBursts::9 233524 # Per bank write bursts
111system.physmem.perBankWrBursts::10 253232 # Per bank write bursts
112system.physmem.perBankWrBursts::11 198347 # Per bank write bursts
113system.physmem.perBankWrBursts::12 181957 # Per bank write bursts
114system.physmem.perBankWrBursts::13 175879 # Per bank write bursts
115system.physmem.perBankWrBursts::14 180282 # Per bank write bursts
116system.physmem.perBankWrBursts::15 175595 # Per bank write bursts
117system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
118system.physmem.numWrRetry 190 # Number of times write queue was full causing retry
119system.physmem.totGap 51557113761500 # Total gap between requests
120system.physmem.readPktSize::0 0 # Read request sizes (log2)
121system.physmem.readPktSize::1 0 # Read request sizes (log2)
122system.physmem.readPktSize::2 0 # Read request sizes (log2)
123system.physmem.readPktSize::3 13 # Read request sizes (log2)
124system.physmem.readPktSize::4 21272 # Read request sizes (log2)
125system.physmem.readPktSize::5 0 # Read request sizes (log2)
126system.physmem.readPktSize::6 2141307 # Read request sizes (log2)
127system.physmem.writePktSize::0 0 # Write request sizes (log2)
128system.physmem.writePktSize::1 0 # Write request sizes (log2)
129system.physmem.writePktSize::2 1 # Write request sizes (log2)
130system.physmem.writePktSize::3 2572 # Write request sizes (log2)
131system.physmem.writePktSize::4 0 # Write request sizes (log2)
132system.physmem.writePktSize::5 0 # Write request sizes (log2)
133system.physmem.writePktSize::6 3308906 # Write request sizes (log2)
134system.physmem.rdQLenPdf::0 1296550 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::1 764534 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::2 68768 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::3 25837 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::4 916 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::5 532 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::6 444 # What read queue length does an incoming req see
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142system.physmem.rdQLenPdf::8 233 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::9 165 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::12 129 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::13 131 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
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173system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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181system.physmem.wrQLenPdf::15 55343 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::16 88539 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::17 132669 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::18 172060 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::19 179259 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::20 199827 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::21 201826 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::22 215089 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::23 217686 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::24 234764 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::25 216813 # What write queue length does an incoming req see
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194system.physmem.wrQLenPdf::28 202440 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::29 157954 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::30 153989 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::31 157951 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::32 145311 # What write queue length does an incoming req see
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200system.physmem.wrQLenPdf::34 7805 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::35 6801 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::36 6277 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::37 6099 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::38 5695 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::39 5430 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::40 5062 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::41 4998 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::42 4548 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::43 4335 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::44 4121 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::45 4055 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::46 3702 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::47 3601 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::48 3413 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::49 3461 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::50 3051 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::51 2987 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::52 2852 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::53 2836 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::54 2345 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::55 2139 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::56 1813 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::57 1591 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::58 1247 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::59 993 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::60 739 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::61 476 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::62 356 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::63 474 # What write queue length does an incoming req see
230system.physmem.bytesPerActivate::samples 1034839 # Bytes accessed per row activation
231system.physmem.bytesPerActivate::mean 334.179783 # Bytes accessed per row activation
232system.physmem.bytesPerActivate::gmean 188.532509 # Bytes accessed per row activation
233system.physmem.bytesPerActivate::stdev 356.014667 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::0-127 392208 37.90% 37.90% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::128-255 234584 22.67% 60.57% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::256-383 87901 8.49% 69.06% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::384-511 49413 4.77% 73.84% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::512-639 38348 3.71% 77.54% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::640-767 26689 2.58% 80.12% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::768-895 21988 2.12% 82.25% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::896-1023 25501 2.46% 84.71% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::1024-1151 158207 15.29% 100.00% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::total 1034839 # Bytes accessed per row activation
244system.physmem.rdPerTurnAround::samples 135592 # Reads before turning the bus around for writes
245system.physmem.rdPerTurnAround::mean 15.925969 # Reads before turning the bus around for writes
246system.physmem.rdPerTurnAround::stdev 128.724301 # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::0-2047 135587 100.00% 100.00% # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::40960-43007 1 0.00% 100.00% # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::total 135592 # Reads before turning the bus around for writes
254system.physmem.wrPerTurnAround::samples 135592 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::mean 23.924981 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::gmean 20.930688 # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::stdev 17.164557 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::16-23 101303 74.71% 74.71% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::24-31 7599 5.60% 80.32% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::32-39 12845 9.47% 89.79% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::40-47 3908 2.88% 92.67% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::48-55 2324 1.71% 94.39% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::56-63 925 0.68% 95.07% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::64-71 2932 2.16% 97.23% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::72-79 1250 0.92% 98.15% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::80-87 889 0.66% 98.81% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::88-95 249 0.18% 98.99% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::96-103 327 0.24% 99.23% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::104-111 193 0.14% 99.37% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::112-119 473 0.35% 99.72% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::120-127 16 0.01% 99.74% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::128-135 22 0.02% 99.75% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::136-143 28 0.02% 99.77% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::144-151 17 0.01% 99.78% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::152-159 31 0.02% 99.81% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::160-167 89 0.07% 99.87% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::168-175 56 0.04% 99.91% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::176-183 42 0.03% 99.95% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::184-191 7 0.01% 99.95% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::192-199 15 0.01% 99.96% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::200-207 2 0.00% 99.96% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::208-215 15 0.01% 99.97% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::224-231 6 0.00% 99.98% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::232-239 3 0.00% 99.98% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::240-247 9 0.01% 99.99% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::248-255 5 0.00% 99.99% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::256-263 5 0.00% 100.00% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::264-271 3 0.00% 100.00% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::total 135592 # Writes before turning the bus around for reads
292system.physmem.totQLat 43990891280 # Total ticks spent queuing
293system.physmem.totMemAccLat 84480522530 # Total ticks spent from burst creation until serviced by the DRAM
294system.physmem.totBusLat 10797235000 # Total ticks spent in databus transfers
295system.physmem.avgQLat 20371.37 # Average queueing delay per DRAM burst
296system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
297system.physmem.avgMemAccLat 39121.37 # Average memory access latency per DRAM burst
298system.physmem.avgRdBW 2.68 # Average DRAM read bandwidth in MiByte/s
299system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s
300system.physmem.avgRdBWSys 2.66 # Average system read bandwidth in MiByte/s
301system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s
302system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
303system.physmem.busUtil 0.05 # Data bus utilization in percentage
304system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
305system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
306system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
307system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing
308system.physmem.readRowHits 1747291 # Number of row buffer hits during reads
309system.physmem.writeRowHits 2621349 # Number of row buffer hits during writes
310system.physmem.readRowHitRate 80.91 # Row buffer hit rate for reads
311system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
312system.physmem.avgGap 9418422.55 # Average gap between requests
313system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined
314system.physmem.memoryStateTime::IDLE 49290195125250 # Time in different power states
315system.physmem.memoryStateTime::REF 1721605340000 # Time in different power states
316system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
317system.physmem.memoryStateTime::ACT 545313634750 # Time in different power states
318system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
319system.physmem.actEnergy::0 3951453240 # Energy for activate commands per rank (pJ)
320system.physmem.actEnergy::1 3871929600 # Energy for activate commands per rank (pJ)
321system.physmem.preEnergy::0 2156050875 # Energy for precharge commands per rank (pJ)
322system.physmem.preEnergy::1 2112660000 # Energy for precharge commands per rank (pJ)
323system.physmem.readEnergy::0 8412588600 # Energy for read commands per rank (pJ)
324system.physmem.readEnergy::1 8431020000 # Energy for read commands per rank (pJ)
325system.physmem.writeEnergy::0 10640075760 # Energy for write commands per rank (pJ)
326system.physmem.writeEnergy::1 10381277520 # Energy for write commands per rank (pJ)
327system.physmem.refreshEnergy::0 3367460045040 # Energy for refresh commands per rank (pJ)
328system.physmem.refreshEnergy::1 3367460045040 # Energy for refresh commands per rank (pJ)
329system.physmem.actBackEnergy::0 1383947967870 # Energy for active background per rank (pJ)
330system.physmem.actBackEnergy::1 1368871606665 # Energy for active background per rank (pJ)
331system.physmem.preBackEnergy::0 29720278968750 # Energy for precharge background per rank (pJ)
332system.physmem.preBackEnergy::1 29733503847000 # Energy for precharge background per rank (pJ)
333system.physmem.totalEnergy::0 34496847150135 # Total energy per rank (pJ)
334system.physmem.totalEnergy::1 34494632385825 # Total energy per rank (pJ)
335system.physmem.averagePower::0 669.099654 # Core power per rank (mW)
336system.physmem.averagePower::1 669.056696 # Core power per rank (mW)
337system.membus.trans_dist::ReadReq 657217 # Transaction distribution
338system.membus.trans_dist::ReadResp 657217 # Transaction distribution
339system.membus.trans_dist::WriteReq 33865 # Transaction distribution
340system.membus.trans_dist::WriteResp 33865 # Transaction distribution
341system.membus.trans_dist::Writeback 1596567 # Transaction distribution
342system.membus.trans_dist::WriteInvalidateReq 1712339 # Transaction distribution
343system.membus.trans_dist::WriteInvalidateResp 1712339 # Transaction distribution
344system.membus.trans_dist::UpgradeReq 48473 # Transaction distribution
345system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
346system.membus.trans_dist::UpgradeResp 48476 # Transaction distribution
347system.membus.trans_dist::ReadExReq 1541174 # Transaction distribution
348system.membus.trans_dist::ReadExResp 1541174 # Transaction distribution
349system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
350system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
351system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
352system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9221519 # Packet count per connected master and slave (bytes)
353system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9351669 # Packet count per connected master and slave (bytes)
354system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229018 # Packet count per connected master and slave (bytes)
355system.membus.pkt_count_system.iocache.mem_side::total 229018 # Packet count per connected master and slave (bytes)
356system.membus.pkt_count::total 9580687 # Packet count per connected master and slave (bytes)
357system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
358system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
359system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
360system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341910604 # Cumulative packet size per connected master and slave (bytes)
361system.membus.pkt_size_system.cpu.l2cache.mem_side::total 342081160 # Cumulative packet size per connected master and slave (bytes)
362system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264064 # Cumulative packet size per connected master and slave (bytes)
363system.membus.pkt_size_system.iocache.mem_side::total 7264064 # Cumulative packet size per connected master and slave (bytes)
364system.membus.pkt_size::total 349345224 # Cumulative packet size per connected master and slave (bytes)
365system.membus.snoops 2022 # Total snoops (count)
366system.membus.snoop_fanout::samples 5500895 # Request fanout histogram
367system.membus.snoop_fanout::mean 1 # Request fanout histogram
368system.membus.snoop_fanout::stdev 0 # Request fanout histogram
369system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
370system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
371system.membus.snoop_fanout::1 5500895 100.00% 100.00% # Request fanout histogram
372system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
373system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
374system.membus.snoop_fanout::min_value 1 # Request fanout histogram
375system.membus.snoop_fanout::max_value 1 # Request fanout histogram
376system.membus.snoop_fanout::total 5500895 # Request fanout histogram
377system.membus.reqLayer0.occupancy 109641999 # Layer occupancy (ticks)
378system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
379system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
380system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
381system.membus.reqLayer2.occupancy 5450500 # Layer occupancy (ticks)
382system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
383system.membus.reqLayer5.occupancy 32462148974 # Layer occupancy (ticks)
384system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
385system.membus.respLayer2.occupancy 21571101815 # Layer occupancy (ticks)
386system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
387system.membus.respLayer3.occupancy 186532342 # Layer occupancy (ticks)
388system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
389system.realview.ethernet.txBytes 966 # Bytes Transmitted
390system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
391system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
392system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
393system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
394system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
395system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
396system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
397system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
398system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
399system.realview.ethernet.totPackets 3 # Total Packets
400system.realview.ethernet.totBytes 966 # Total Bytes
401system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
402system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
403system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
404system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
405system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
406system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
407system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
408system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
409system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
410system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
411system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
412system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
413system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
414system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
415system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
416system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
417system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
418system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
419system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
420system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
421system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
422system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
423system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
424system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
425system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
426system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
427system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
428system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
429system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
430system.realview.ethernet.droppedPackets 0 # number of packets dropped
431system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
432system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
433system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
434system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
435system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
436system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
437system.iobus.trans_dist::ReadReq 40379 # Transaction distribution
438system.iobus.trans_dist::ReadResp 40379 # Transaction distribution
439system.iobus.trans_dist::WriteReq 136716 # Transaction distribution
440system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
441system.iobus.trans_dist::WriteInvalidateReq 17 # Transaction distribution
442system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
443system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
444system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
445system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
446system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
447system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
448system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
449system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
450system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
451system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
452system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
453system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
454system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
455system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
456system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
457system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
458system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
459system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
460system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
461system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
462system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes)
463system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
464system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
465system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
466system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
467system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
468system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
469system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
470system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
471system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
472system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
473system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
474system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
475system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
476system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
477system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
478system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
479system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
480system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
481system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
482system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
483system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes)
484system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
485system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
486system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
487system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
488system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
489system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
490system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
491system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
492system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
493system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
494system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
495system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
496system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
497system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
498system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
499system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
500system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
501system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
502system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
503system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
504system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
505system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
506system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
507system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
508system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
509system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
510system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
511system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
512system.iobus.reqLayer27.occupancy 981079506 # Layer occupancy (ticks)
513system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
514system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
515system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
516system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
517system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
518system.iobus.respLayer3.occupancy 179002658 # Layer occupancy (ticks)
519system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
520system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
521system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
522system.cpu_clk_domain.clock 500 # Clock period in ticks
523system.cpu.branchPred.lookups 291488483 # Number of BP lookups
524system.cpu.branchPred.condPredicted 200150149 # Number of conditional branches predicted
525system.cpu.branchPred.condIncorrect 13608043 # Number of conditional branches incorrect
526system.cpu.branchPred.BTBLookups 209143322 # Number of BTB lookups
527system.cpu.branchPred.BTBHits 138326751 # Number of BTB hits
528system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
529system.cpu.branchPred.BTBHitPct 66.139693 # BTB Hit Percentage
530system.cpu.branchPred.usedRAS 37688944 # Number of times the RAS was used to get a target.
531system.cpu.branchPred.RASInCorrect 403819 # Number of incorrect RAS predictions.
532system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
533system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
534system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
535system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
536system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
537system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
538system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
539system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

547system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
548system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
549system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
550system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
551system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
552system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
553system.cpu.dtb.inst_hits 0 # ITB inst hits
554system.cpu.dtb.inst_misses 0 # ITB inst misses
555system.cpu.dtb.read_hits 220000246 # DTB read hits
556system.cpu.dtb.read_misses 1007031 # DTB read misses
557system.cpu.dtb.write_hits 193886106 # DTB write hits
558system.cpu.dtb.write_misses 416122 # DTB write misses
559system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
560system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
561system.cpu.dtb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID
562system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
563system.cpu.dtb.flush_entries 89690 # Number of entries that have been flushed from TLB
564system.cpu.dtb.align_faults 112 # Number of TLB faults due to alignment restrictions
565system.cpu.dtb.prefetch_faults 15179 # Number of TLB faults due to prefetch
566system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
567system.cpu.dtb.perms_faults 87251 # Number of TLB faults due to permissions restrictions
568system.cpu.dtb.read_accesses 221007277 # DTB read accesses
569system.cpu.dtb.write_accesses 194302228 # DTB write accesses
570system.cpu.dtb.inst_accesses 0 # ITB inst accesses
571system.cpu.dtb.hits 413886352 # DTB hits
572system.cpu.dtb.misses 1423153 # DTB misses
573system.cpu.dtb.accesses 415309505 # DTB accesses
574system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
575system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
576system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
577system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
578system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
579system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
580system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
581system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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587system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
588system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
589system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
590system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
591system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
592system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
593system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
594system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
595system.cpu.itb.inst_hits 465588468 # ITB inst hits
596system.cpu.itb.inst_misses 176797 # ITB inst misses
597system.cpu.itb.read_hits 0 # DTB read hits
598system.cpu.itb.read_misses 0 # DTB read misses
599system.cpu.itb.write_hits 0 # DTB write hits
600system.cpu.itb.write_misses 0 # DTB write misses
601system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
602system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
603system.cpu.itb.flush_tlb_mva_asid 63968 # Number of times TLB was flushed by MVA & ASID
604system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
605system.cpu.itb.flush_entries 63536 # Number of entries that have been flushed from TLB
606system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
607system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
608system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
609system.cpu.itb.perms_faults 462381 # Number of TLB faults due to permissions restrictions
610system.cpu.itb.read_accesses 0 # DTB read accesses
611system.cpu.itb.write_accesses 0 # DTB write accesses
612system.cpu.itb.inst_accesses 465765265 # ITB inst accesses
613system.cpu.itb.hits 465588468 # DTB hits
614system.cpu.itb.misses 176797 # DTB misses
615system.cpu.itb.accesses 465765265 # DTB accesses
616system.cpu.numCycles 2146849645 # number of cpu cycles simulated
617system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
618system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
619system.cpu.fetch.icacheStallCycles 791511347 # Number of cycles fetch is stalled on an Icache miss
620system.cpu.fetch.Insts 1301628389 # Number of instructions fetch has processed
621system.cpu.fetch.Branches 291488483 # Number of branches that fetch encountered
622system.cpu.fetch.predictedBranches 176015695 # Number of branches that fetch has predicted taken
623system.cpu.fetch.Cycles 1268750537 # Number of cycles fetch has run and was not squashing or blocked
624system.cpu.fetch.SquashCycles 29307286 # Number of cycles fetch has spent squashing
625system.cpu.fetch.TlbCycles 4254748 # Number of cycles fetch has spent waiting for tlb
626system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
627system.cpu.fetch.PendingTrapStallCycles 12217982 # Number of stall cycles due to pending traps
628system.cpu.fetch.PendingQuiesceStallCycles 1219824 # Number of stall cycles due to pending quiesce instructions
629system.cpu.fetch.IcacheWaitRetryStallCycles 381 # Number of stall cycles due to full MSHR
630system.cpu.fetch.CacheLines 465107423 # Number of cache lines fetched
631system.cpu.fetch.IcacheSquashes 6746831 # Number of outstanding Icache misses that were squashed
632system.cpu.fetch.ItlbSquashes 53918 # Number of outstanding ITLB misses that were squashed
633system.cpu.fetch.rateDist::samples 2092636388 # Number of instructions fetched each cycle (Total)
634system.cpu.fetch.rateDist::mean 0.729302 # Number of instructions fetched each cycle (Total)
635system.cpu.fetch.rateDist::stdev 1.142136 # Number of instructions fetched each cycle (Total)
636system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
637system.cpu.fetch.rateDist::0 1367675983 65.36% 65.36% # Number of instructions fetched each cycle (Total)
638system.cpu.fetch.rateDist::1 280886167 13.42% 78.78% # Number of instructions fetched each cycle (Total)
639system.cpu.fetch.rateDist::2 86945610 4.15% 82.93% # Number of instructions fetched each cycle (Total)
640system.cpu.fetch.rateDist::3 357128628 17.07% 100.00% # Number of instructions fetched each cycle (Total)
641system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
642system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
643system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
644system.cpu.fetch.rateDist::total 2092636388 # Number of instructions fetched each cycle (Total)
645system.cpu.fetch.branchRate 0.135775 # Number of branch fetches per cycle
646system.cpu.fetch.rate 0.606297 # Number of inst fetches per cycle
647system.cpu.decode.IdleCycles 614820490 # Number of cycles decode is idle
648system.cpu.decode.BlockedCycles 852644163 # Number of cycles decode is blocked
649system.cpu.decode.RunCycles 531180111 # Number of cycles decode is running
650system.cpu.decode.UnblockCycles 83391963 # Number of cycles decode is unblocking
651system.cpu.decode.SquashCycles 10599661 # Number of cycles decode is squashing
652system.cpu.decode.BranchResolved 41490545 # Number of times decode resolved a branch
653system.cpu.decode.BranchMispred 4112846 # Number of times decode detected a branch misprediction
654system.cpu.decode.DecodedInsts 1415541998 # Number of instructions handled by decode
655system.cpu.decode.SquashedInsts 32718079 # Number of squashed instructions handled by decode
656system.cpu.rename.SquashCycles 10599661 # Number of cycles rename is squashing
657system.cpu.rename.IdleCycles 678805488 # Number of cycles rename is idle
658system.cpu.rename.BlockCycles 83662136 # Number of cycles rename is blocking
659system.cpu.rename.serializeStallCycles 556428904 # count of cycles rename stalled for serializing inst
660system.cpu.rename.RunCycles 549849830 # Number of cycles rename is running
661system.cpu.rename.UnblockCycles 213290369 # Number of cycles rename is unblocking
662system.cpu.rename.RenamedInsts 1391734034 # Number of instructions processed by rename
663system.cpu.rename.SquashedInsts 7977079 # Number of squashed instructions processed by rename
664system.cpu.rename.ROBFullEvents 7435136 # Number of times rename has blocked due to ROB full
665system.cpu.rename.IQFullEvents 893230 # Number of times rename has blocked due to IQ full
666system.cpu.rename.LQFullEvents 1023922 # Number of times rename has blocked due to LQ full
667system.cpu.rename.SQFullEvents 127479585 # Number of times rename has blocked due to SQ full
668system.cpu.rename.FullRegisterEvents 25199 # Number of times there has been no free registers
669system.cpu.rename.RenamedOperands 1342075875 # Number of destination operands rename has renamed
670system.cpu.rename.RenameLookups 2217645602 # Number of register rename lookups that rename has made
671system.cpu.rename.int_rename_lookups 1652184740 # Number of integer rename lookups
672system.cpu.rename.fp_rename_lookups 1639045 # Number of floating rename lookups
673system.cpu.rename.CommittedMaps 1263873564 # Number of HB maps that are committed
674system.cpu.rename.UndoneMaps 78202308 # Number of HB maps that are undone due to squashing
675system.cpu.rename.serializingInsts 44203192 # count of serializing insts renamed
676system.cpu.rename.tempSerializingInsts 39719264 # count of temporary serializing insts renamed
677system.cpu.rename.skidInsts 172796539 # count of insts added to the skid buffer
678system.cpu.memDep0.insertedLoads 223511224 # Number of loads inserted to the mem dependence unit.
679system.cpu.memDep0.insertedStores 198396121 # Number of stores inserted to the mem dependence unit.
680system.cpu.memDep0.conflictingLoads 12647992 # Number of conflicting loads.
681system.cpu.memDep0.conflictingStores 11061331 # Number of conflicting stores.
682system.cpu.iq.iqInstsAdded 1338396177 # Number of instructions added to the IQ (excludes non-spec)
683system.cpu.iq.iqNonSpecInstsAdded 44508712 # Number of non-speculative instructions added to the IQ
684system.cpu.iq.iqInstsIssued 1370133902 # Number of instructions issued
685system.cpu.iq.iqSquashedInstsIssued 4153047 # Number of squashed instructions issued
686system.cpu.iq.iqSquashedInstsExamined 65240654 # Number of squashed instructions iterated over during squash; mainly for profiling
687system.cpu.iq.iqSquashedOperandsExamined 41320787 # Number of squashed operands that are examined and possibly removed from graph
688system.cpu.iq.iqSquashedNonSpecRemoved 373617 # Number of squashed non-spec instructions that were removed
689system.cpu.iq.issued_per_cycle::samples 2092636388 # Number of insts issued each cycle
690system.cpu.iq.issued_per_cycle::mean 0.654741 # Number of insts issued each cycle
691system.cpu.iq.issued_per_cycle::stdev 0.915536 # Number of insts issued each cycle
692system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
693system.cpu.iq.issued_per_cycle::0 1237717942 59.15% 59.15% # Number of insts issued each cycle
694system.cpu.iq.issued_per_cycle::1 455529583 21.77% 80.91% # Number of insts issued each cycle
695system.cpu.iq.issued_per_cycle::2 292996726 14.00% 94.92% # Number of insts issued each cycle
696system.cpu.iq.issued_per_cycle::3 96986296 4.63% 99.55% # Number of insts issued each cycle
697system.cpu.iq.issued_per_cycle::4 9377226 0.45% 100.00% # Number of insts issued each cycle
698system.cpu.iq.issued_per_cycle::5 28615 0.00% 100.00% # Number of insts issued each cycle
699system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
700system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
701system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
702system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
703system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
704system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
705system.cpu.iq.issued_per_cycle::total 2092636388 # Number of insts issued each cycle
706system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
707system.cpu.iq.fu_full::IntAlu 74528454 34.28% 34.28% # attempts to use FU when none available
708system.cpu.iq.fu_full::IntMult 90672 0.04% 34.33% # attempts to use FU when none available
709system.cpu.iq.fu_full::IntDiv 26772 0.01% 34.34% # attempts to use FU when none available
710system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.34% # attempts to use FU when none available
711system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.34% # attempts to use FU when none available
712system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.34% # attempts to use FU when none available
713system.cpu.iq.fu_full::FloatMult 0 0.00% 34.34% # attempts to use FU when none available
714system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.34% # attempts to use FU when none available
715system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.34% # attempts to use FU when none available
716system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.34% # attempts to use FU when none available
717system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.34% # attempts to use FU when none available
718system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.34% # attempts to use FU when none available
719system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.34% # attempts to use FU when none available
720system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.34% # attempts to use FU when none available
721system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.34% # attempts to use FU when none available
722system.cpu.iq.fu_full::SimdMult 0 0.00% 34.34% # attempts to use FU when none available
723system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.34% # attempts to use FU when none available
724system.cpu.iq.fu_full::SimdShift 0 0.00% 34.34% # attempts to use FU when none available
725system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.34% # attempts to use FU when none available
726system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.34% # attempts to use FU when none available
727system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.34% # attempts to use FU when none available
728system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.34% # attempts to use FU when none available
729system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.34% # attempts to use FU when none available
730system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.34% # attempts to use FU when none available
731system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.34% # attempts to use FU when none available
732system.cpu.iq.fu_full::SimdFloatMisc 287 0.00% 34.34% # attempts to use FU when none available
733system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.34% # attempts to use FU when none available
734system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.34% # attempts to use FU when none available
735system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.34% # attempts to use FU when none available
736system.cpu.iq.fu_full::MemRead 58830485 27.06% 61.40% # attempts to use FU when none available
737system.cpu.iq.fu_full::MemWrite 83911289 38.60% 100.00% # attempts to use FU when none available
738system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
739system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
740system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
741system.cpu.iq.FU_type_0::IntAlu 945793660 69.03% 69.03% # Type of FU issued
742system.cpu.iq.FU_type_0::IntMult 2946266 0.22% 69.24% # Type of FU issued
743system.cpu.iq.FU_type_0::IntDiv 129775 0.01% 69.25% # Type of FU issued
744system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 69.25% # Type of FU issued
745system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.25% # Type of FU issued
746system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.25% # Type of FU issued
747system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.25% # Type of FU issued
748system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.25% # Type of FU issued
749system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.25% # Type of FU issued
750system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.25% # Type of FU issued
751system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.25% # Type of FU issued
752system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.25% # Type of FU issued
753system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.25% # Type of FU issued
754system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.25% # Type of FU issued
755system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.25% # Type of FU issued
756system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.25% # Type of FU issued
757system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.25% # Type of FU issued
758system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.25% # Type of FU issued
759system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.25% # Type of FU issued
760system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.25% # Type of FU issued
761system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.25% # Type of FU issued
762system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.25% # Type of FU issued
763system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.25% # Type of FU issued
764system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.25% # Type of FU issued
765system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.25% # Type of FU issued
766system.cpu.iq.FU_type_0::SimdFloatMisc 114397 0.01% 69.26% # Type of FU issued
767system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.26% # Type of FU issued
768system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.26% # Type of FU issued
769system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.26% # Type of FU issued
770system.cpu.iq.FU_type_0::MemRead 224851656 16.41% 85.67% # Type of FU issued
771system.cpu.iq.FU_type_0::MemWrite 196298100 14.33% 100.00% # Type of FU issued
772system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
773system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
774system.cpu.iq.FU_type_0::total 1370133902 # Type of FU issued
775system.cpu.iq.rate 0.638207 # Inst issue rate
776system.cpu.iq.fu_busy_cnt 217387959 # FU busy when requested
777system.cpu.iq.fu_busy_rate 0.158662 # FU busy rate (busy events/executed inst)
778system.cpu.iq.int_inst_queue_reads 5052021388 # Number of integer instruction queue reads
779system.cpu.iq.int_inst_queue_writes 1447405501 # Number of integer instruction queue writes
780system.cpu.iq.int_inst_queue_wakeup_accesses 1347303683 # Number of integer instruction queue wakeup accesses
781system.cpu.iq.fp_inst_queue_reads 2423809 # Number of floating instruction queue reads
782system.cpu.iq.fp_inst_queue_writes 923681 # Number of floating instruction queue writes
783system.cpu.iq.fp_inst_queue_wakeup_accesses 885699 # Number of floating instruction queue wakeup accesses
784system.cpu.iq.int_alu_accesses 1585997449 # Number of integer alu accesses
785system.cpu.iq.fp_alu_accesses 1524411 # Number of floating point alu accesses
786system.cpu.iew.lsq.thread0.forwLoads 5766333 # Number of loads that had data forwarded from stores
787system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
788system.cpu.iew.lsq.thread0.squashedLoads 16996131 # Number of loads squashed
789system.cpu.iew.lsq.thread0.ignoredResponses 24128 # Number of memory responses ignored because the instruction is squashed
790system.cpu.iew.lsq.thread0.memOrderViolation 185382 # Number of memory ordering violations
791system.cpu.iew.lsq.thread0.squashedStores 8259714 # Number of stores squashed
792system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
793system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
794system.cpu.iew.lsq.thread0.rescheduledLoads 3623609 # Number of loads that were rescheduled
795system.cpu.iew.lsq.thread0.cacheBlocked 3385962 # Number of times an access to memory failed due to the cache being blocked
796system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
797system.cpu.iew.iewSquashCycles 10599661 # Number of cycles IEW is squashing
798system.cpu.iew.iewBlockCycles 11961718 # Number of cycles IEW is blocking
799system.cpu.iew.iewUnblockCycles 7304667 # Number of cycles IEW is unblocking
800system.cpu.iew.iewDispatchedInsts 1383179145 # Number of instructions dispatched to IQ
801system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
802system.cpu.iew.iewDispLoadInsts 223511224 # Number of dispatched load instructions
803system.cpu.iew.iewDispStoreInsts 198396121 # Number of dispatched store instructions
804system.cpu.iew.iewDispNonSpecInsts 39177517 # Number of dispatched non-speculative instructions
805system.cpu.iew.iewIQFullEvents 185228 # Number of times the IQ has become full, causing a stall
806system.cpu.iew.iewLSQFullEvents 6936317 # Number of times the LSQ has become full, causing a stall
807system.cpu.iew.memOrderViolationEvents 185382 # Number of memory order violations
808system.cpu.iew.predictedTakenIncorrect 4274350 # Number of branches that were predicted taken incorrectly
809system.cpu.iew.predictedNotTakenIncorrect 5730421 # Number of branches that were predicted not taken incorrectly
810system.cpu.iew.branchMispredicts 10004771 # Number of branch mispredicts detected at execute
811system.cpu.iew.iewExecutedInsts 1356817685 # Number of executed instructions
812system.cpu.iew.iewExecLoadInsts 220004444 # Number of load instructions executed
813system.cpu.iew.iewExecSquashedInsts 11924579 # Number of squashed instructions skipped in execute
814system.cpu.iew.exec_swp 0 # number of swp insts executed
815system.cpu.iew.exec_nop 274256 # number of nop insts executed
816system.cpu.iew.exec_refs 413901554 # number of memory reference insts executed
817system.cpu.iew.exec_branches 257473473 # Number of branches executed
818system.cpu.iew.exec_stores 193897110 # Number of stores executed
819system.cpu.iew.exec_rate 0.632004 # Inst execution rate
820system.cpu.iew.wb_sent 1349182874 # cumulative count of insts sent to commit
821system.cpu.iew.wb_count 1348189382 # cumulative count of insts written-back
822system.cpu.iew.wb_producers 579023420 # num instructions producing a value
823system.cpu.iew.wb_consumers 949767765 # num instructions consuming a value
824system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
825system.cpu.iew.wb_rate 0.627985 # insts written-back per cycle
826system.cpu.iew.wb_fanout 0.609647 # average fanout of values written-back
827system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
828system.cpu.commit.commitSquashedInsts 62443917 # The number of squashed insts skipped by commit
829system.cpu.commit.commitNonSpecStalls 44135095 # The number of times commit has been forced to stall to communicate backwards
830system.cpu.commit.branchMispredicts 9554061 # The number of times a branch was mispredicted
831system.cpu.commit.committed_per_cycle::samples 2078483160 # Number of insts commited each cycle
832system.cpu.commit.committed_per_cycle::mean 0.630193 # Number of insts commited each cycle
833system.cpu.commit.committed_per_cycle::stdev 1.269789 # Number of insts commited each cycle
834system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
835system.cpu.commit.committed_per_cycle::0 1396354428 67.18% 67.18% # Number of insts commited each cycle
836system.cpu.commit.committed_per_cycle::1 397736022 19.14% 86.32% # Number of insts commited each cycle
837system.cpu.commit.committed_per_cycle::2 152396085 7.33% 93.65% # Number of insts commited each cycle
838system.cpu.commit.committed_per_cycle::3 44287772 2.13% 95.78% # Number of insts commited each cycle
839system.cpu.commit.committed_per_cycle::4 35996912 1.73% 97.51% # Number of insts commited each cycle
840system.cpu.commit.committed_per_cycle::5 18656723 0.90% 98.41% # Number of insts commited each cycle
841system.cpu.commit.committed_per_cycle::6 10905184 0.52% 98.93% # Number of insts commited each cycle
842system.cpu.commit.committed_per_cycle::7 5449343 0.26% 99.20% # Number of insts commited each cycle
843system.cpu.commit.committed_per_cycle::8 16700691 0.80% 100.00% # Number of insts commited each cycle
844system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
845system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
846system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
847system.cpu.commit.committed_per_cycle::total 2078483160 # Number of insts commited each cycle
848system.cpu.commit.committedInsts 1114380469 # Number of instructions committed
849system.cpu.commit.committedOps 1309844804 # Number of ops (including micro ops) committed
850system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
851system.cpu.commit.refs 396651499 # Number of memory references committed
852system.cpu.commit.loads 206515092 # Number of loads committed
853system.cpu.commit.membars 9189565 # Number of memory barriers committed
854system.cpu.commit.branches 249089949 # Number of branches committed
855system.cpu.commit.fp_insts 873640 # Number of committed floating point instructions.
856system.cpu.commit.int_insts 1196978104 # Number of committed integer instructions.
857system.cpu.commit.function_calls 31078874 # Number of function calls committed.
858system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
859system.cpu.commit.op_class_0::IntAlu 910428363 69.51% 69.51% # Class of committed instruction
860system.cpu.commit.op_class_0::IntMult 2554988 0.20% 69.70% # Class of committed instruction
861system.cpu.commit.op_class_0::IntDiv 104143 0.01% 69.71% # Class of committed instruction
862system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.71% # Class of committed instruction
863system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.71% # Class of committed instruction
864system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.71% # Class of committed instruction
865system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.71% # Class of committed instruction
866system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.71% # Class of committed instruction
867system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction
868system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction
869system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction
870system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction
871system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction
872system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction
873system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction
874system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction
875system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction
876system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction
877system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction
878system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction
879system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.71% # Class of committed instruction
880system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction
881system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.71% # Class of committed instruction
882system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.71% # Class of committed instruction
883system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction
884system.cpu.commit.op_class_0::SimdFloatMisc 105769 0.01% 69.72% # Class of committed instruction
885system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.72% # Class of committed instruction
886system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.72% # Class of committed instruction
887system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.72% # Class of committed instruction
888system.cpu.commit.op_class_0::MemRead 206515092 15.77% 85.48% # Class of committed instruction
889system.cpu.commit.op_class_0::MemWrite 190136407 14.52% 100.00% # Class of committed instruction
890system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
891system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
892system.cpu.commit.op_class_0::total 1309844804 # Class of committed instruction
893system.cpu.commit.bw_lim_events 16700691 # number cycles where commit BW limit reached
894system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
895system.cpu.rob.rob_reads 3424556806 # The number of ROB reads
896system.cpu.rob.rob_writes 2758622493 # The number of ROB writes
897system.cpu.timesIdled 9031521 # Number of times that the entire CPU went into an idle state and unscheduled itself
898system.cpu.idleCycles 54213257 # Total number of cycles that the CPU has spent unscheduled due to idling
899system.cpu.quiesceCycles 100967380384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
900system.cpu.committedInsts 1114380469 # Number of Instructions Simulated
901system.cpu.committedOps 1309844804 # Number of Ops (including micro ops) Simulated
902system.cpu.cpi 1.926496 # CPI: Cycles Per Instruction
903system.cpu.cpi_total 1.926496 # CPI: Total CPI of All Threads
904system.cpu.ipc 0.519077 # IPC: Instructions Per Cycle
905system.cpu.ipc_total 0.519077 # IPC: Total IPC of All Threads
906system.cpu.int_regfile_reads 1611998606 # number of integer regfile reads
907system.cpu.int_regfile_writes 948639021 # number of integer regfile writes
908system.cpu.fp_regfile_reads 1420015 # number of floating regfile reads
909system.cpu.fp_regfile_writes 765124 # number of floating regfile writes
910system.cpu.cc_regfile_reads 315259155 # number of cc regfile reads
911system.cpu.cc_regfile_writes 316098925 # number of cc regfile writes
912system.cpu.misc_regfile_reads 6952427793 # number of misc regfile reads
913system.cpu.misc_regfile_writes 45059384 # number of misc regfile writes
914system.cpu.toL2Bus.trans_dist::ReadReq 28539920 # Transaction distribution
915system.cpu.toL2Bus.trans_dist::ReadResp 28531649 # Transaction distribution
916system.cpu.toL2Bus.trans_dist::WriteReq 33865 # Transaction distribution
917system.cpu.toL2Bus.trans_dist::WriteResp 33865 # Transaction distribution
918system.cpu.toL2Bus.trans_dist::Writeback 9369509 # Transaction distribution
919system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1712344 # Transaction distribution
920system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1605675 # Transaction distribution
921system.cpu.toL2Bus.trans_dist::UpgradeReq 61529 # Transaction distribution
922system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
923system.cpu.toL2Bus.trans_dist::UpgradeResp 61535 # Transaction distribution
924system.cpu.toL2Bus.trans_dist::ReadExReq 3074731 # Transaction distribution
925system.cpu.toL2Bus.trans_dist::ReadExResp 3074731 # Transaction distribution
926system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33703094 # Packet count per connected master and slave (bytes)
927system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37825776 # Packet count per connected master and slave (bytes)
928system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 810571 # Packet count per connected master and slave (bytes)
929system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3115869 # Packet count per connected master and slave (bytes)
930system.cpu.toL2Bus.pkt_count::total 75455310 # Packet count per connected master and slave (bytes)
931system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1077469744 # Cumulative packet size per connected master and slave (bytes)
932system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1502191576 # Cumulative packet size per connected master and slave (bytes)
933system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2724416 # Cumulative packet size per connected master and slave (bytes)
934system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10868120 # Cumulative packet size per connected master and slave (bytes)
935system.cpu.toL2Bus.pkt_size::total 2593253856 # Cumulative packet size per connected master and slave (bytes)
936system.cpu.toL2Bus.snoops 644632 # Total snoops (count)
937system.cpu.toL2Bus.snoop_fanout::samples 42703026 # Request fanout histogram
938system.cpu.toL2Bus.snoop_fanout::mean 5.002705 # Request fanout histogram
939system.cpu.toL2Bus.snoop_fanout::stdev 0.051942 # Request fanout histogram
940system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
941system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
942system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
943system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
944system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
945system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
946system.cpu.toL2Bus.snoop_fanout::5 42587504 99.73% 99.73% # Request fanout histogram
947system.cpu.toL2Bus.snoop_fanout::6 115522 0.27% 100.00% # Request fanout histogram
948system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
949system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
950system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
951system.cpu.toL2Bus.snoop_fanout::total 42703026 # Request fanout histogram
952system.cpu.toL2Bus.reqLayer0.occupancy 32333793873 # Layer occupancy (ticks)
953system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
954system.cpu.toL2Bus.snoopLayer0.occupancy 871500 # Layer occupancy (ticks)
955system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
956system.cpu.toL2Bus.respLayer0.occupancy 25296093441 # Layer occupancy (ticks)
957system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
958system.cpu.toL2Bus.respLayer1.occupancy 19876823538 # Layer occupancy (ticks)
959system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
960system.cpu.toL2Bus.respLayer2.occupancy 472614279 # Layer occupancy (ticks)
961system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
962system.cpu.toL2Bus.respLayer3.occupancy 1760067316 # Layer occupancy (ticks)
963system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
964system.cpu.icache.tags.replacements 16829629 # number of replacements
965system.cpu.icache.tags.tagsinuse 511.959617 # Cycle average of tags in use
966system.cpu.icache.tags.total_refs 447510611 # Total number of references to valid blocks.
967system.cpu.icache.tags.sampled_refs 16830141 # Sample count of references to valid blocks.
968system.cpu.icache.tags.avg_refs 26.589831 # Average number of references to valid blocks.
969system.cpu.icache.tags.warmup_cycle 12236526000 # Cycle when the warmup percentage was hit.
970system.cpu.icache.tags.occ_blocks::cpu.inst 511.959617 # Average occupied blocks per requestor
971system.cpu.icache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy
972system.cpu.icache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy
973system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
974system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
975system.cpu.icache.tags.age_task_id_blocks_1024::1 291 # Occupied blocks per task id
976system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id
977system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
978system.cpu.icache.tags.tag_accesses 481916487 # Number of tag accesses
979system.cpu.icache.tags.data_accesses 481916487 # Number of data accesses
980system.cpu.icache.ReadReq_hits::cpu.inst 447510611 # number of ReadReq hits
981system.cpu.icache.ReadReq_hits::total 447510611 # number of ReadReq hits
982system.cpu.icache.demand_hits::cpu.inst 447510611 # number of demand (read+write) hits
983system.cpu.icache.demand_hits::total 447510611 # number of demand (read+write) hits
984system.cpu.icache.overall_hits::cpu.inst 447510611 # number of overall hits
985system.cpu.icache.overall_hits::total 447510611 # number of overall hits
986system.cpu.icache.ReadReq_misses::cpu.inst 17575514 # number of ReadReq misses
987system.cpu.icache.ReadReq_misses::total 17575514 # number of ReadReq misses
988system.cpu.icache.demand_misses::cpu.inst 17575514 # number of demand (read+write) misses
989system.cpu.icache.demand_misses::total 17575514 # number of demand (read+write) misses
990system.cpu.icache.overall_misses::cpu.inst 17575514 # number of overall misses
991system.cpu.icache.overall_misses::total 17575514 # number of overall misses
992system.cpu.icache.ReadReq_miss_latency::cpu.inst 231527181766 # number of ReadReq miss cycles
993system.cpu.icache.ReadReq_miss_latency::total 231527181766 # number of ReadReq miss cycles
994system.cpu.icache.demand_miss_latency::cpu.inst 231527181766 # number of demand (read+write) miss cycles
995system.cpu.icache.demand_miss_latency::total 231527181766 # number of demand (read+write) miss cycles
996system.cpu.icache.overall_miss_latency::cpu.inst 231527181766 # number of overall miss cycles
997system.cpu.icache.overall_miss_latency::total 231527181766 # number of overall miss cycles
998system.cpu.icache.ReadReq_accesses::cpu.inst 465086125 # number of ReadReq accesses(hits+misses)
999system.cpu.icache.ReadReq_accesses::total 465086125 # number of ReadReq accesses(hits+misses)
1000system.cpu.icache.demand_accesses::cpu.inst 465086125 # number of demand (read+write) accesses
1001system.cpu.icache.demand_accesses::total 465086125 # number of demand (read+write) accesses
1002system.cpu.icache.overall_accesses::cpu.inst 465086125 # number of overall (read+write) accesses
1003system.cpu.icache.overall_accesses::total 465086125 # number of overall (read+write) accesses
1004system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.037790 # miss rate for ReadReq accesses
1005system.cpu.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses
1006system.cpu.icache.demand_miss_rate::cpu.inst 0.037790 # miss rate for demand accesses
1007system.cpu.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses
1008system.cpu.icache.overall_miss_rate::cpu.inst 0.037790 # miss rate for overall accesses
1009system.cpu.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses
1010system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13173.280836 # average ReadReq miss latency
1011system.cpu.icache.ReadReq_avg_miss_latency::total 13173.280836 # average ReadReq miss latency
1012system.cpu.icache.demand_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency
1013system.cpu.icache.demand_avg_miss_latency::total 13173.280836 # average overall miss latency
1014system.cpu.icache.overall_avg_miss_latency::cpu.inst 13173.280836 # average overall miss latency
1015system.cpu.icache.overall_avg_miss_latency::total 13173.280836 # average overall miss latency
1016system.cpu.icache.blocked_cycles::no_mshrs 11084 # number of cycles access was blocked
1017system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1018system.cpu.icache.blocked::no_mshrs 920 # number of cycles access was blocked
1019system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1020system.cpu.icache.avg_blocked_cycles::no_mshrs 12.047826 # average number of cycles each access was blocked
1021system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1022system.cpu.icache.fast_writes 0 # number of fast writes performed
1023system.cpu.icache.cache_copies 0 # number of cache copies performed
1024system.cpu.icache.ReadReq_mshr_hits::cpu.inst 745151 # number of ReadReq MSHR hits
1025system.cpu.icache.ReadReq_mshr_hits::total 745151 # number of ReadReq MSHR hits
1026system.cpu.icache.demand_mshr_hits::cpu.inst 745151 # number of demand (read+write) MSHR hits
1027system.cpu.icache.demand_mshr_hits::total 745151 # number of demand (read+write) MSHR hits
1028system.cpu.icache.overall_mshr_hits::cpu.inst 745151 # number of overall MSHR hits
1029system.cpu.icache.overall_mshr_hits::total 745151 # number of overall MSHR hits
1030system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16830363 # number of ReadReq MSHR misses
1031system.cpu.icache.ReadReq_mshr_misses::total 16830363 # number of ReadReq MSHR misses
1032system.cpu.icache.demand_mshr_misses::cpu.inst 16830363 # number of demand (read+write) MSHR misses
1033system.cpu.icache.demand_mshr_misses::total 16830363 # number of demand (read+write) MSHR misses
1034system.cpu.icache.overall_mshr_misses::cpu.inst 16830363 # number of overall MSHR misses
1035system.cpu.icache.overall_mshr_misses::total 16830363 # number of overall MSHR misses
1036system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191394786019 # number of ReadReq MSHR miss cycles
1037system.cpu.icache.ReadReq_mshr_miss_latency::total 191394786019 # number of ReadReq MSHR miss cycles
1038system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191394786019 # number of demand (read+write) MSHR miss cycles
1039system.cpu.icache.demand_mshr_miss_latency::total 191394786019 # number of demand (read+write) MSHR miss cycles
1040system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191394786019 # number of overall MSHR miss cycles
1041system.cpu.icache.overall_mshr_miss_latency::total 191394786019 # number of overall MSHR miss cycles
1042system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1413030250 # number of ReadReq MSHR uncacheable cycles
1043system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1413030250 # number of ReadReq MSHR uncacheable cycles
1044system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1413030250 # number of overall MSHR uncacheable cycles
1045system.cpu.icache.overall_mshr_uncacheable_latency::total 1413030250 # number of overall MSHR uncacheable cycles
1046system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for ReadReq accesses
1047system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036188 # mshr miss rate for ReadReq accesses
1048system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for demand accesses
1049system.cpu.icache.demand_mshr_miss_rate::total 0.036188 # mshr miss rate for demand accesses
1050system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036188 # mshr miss rate for overall accesses
1051system.cpu.icache.overall_mshr_miss_rate::total 0.036188 # mshr miss rate for overall accesses
1052system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.993939 # average ReadReq mshr miss latency
1053system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.993939 # average ReadReq mshr miss latency
1054system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency
1055system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency
1056system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.993939 # average overall mshr miss latency
1057system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.993939 # average overall mshr miss latency
1058system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1059system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1060system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1061system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1062system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1063system.cpu.l2cache.tags.replacements 1866229 # number of replacements
1064system.cpu.l2cache.tags.tagsinuse 64521.528187 # Cycle average of tags in use
1065system.cpu.l2cache.tags.total_refs 35312731 # Total number of references to valid blocks.
1066system.cpu.l2cache.tags.sampled_refs 1928499 # Sample count of references to valid blocks.
1067system.cpu.l2cache.tags.avg_refs 18.310993 # Average number of references to valid blocks.
1068system.cpu.l2cache.tags.warmup_cycle 13813873928000 # Cycle when the warmup percentage was hit.
1069system.cpu.l2cache.tags.occ_blocks::writebacks 34323.724648 # Average occupied blocks per requestor
1070system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 307.320059 # Average occupied blocks per requestor
1071system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.834309 # Average occupied blocks per requestor
1072system.cpu.l2cache.tags.occ_blocks::cpu.inst 7078.453286 # Average occupied blocks per requestor
1073system.cpu.l2cache.tags.occ_blocks::cpu.data 22362.195885 # Average occupied blocks per requestor
1074system.cpu.l2cache.tags.occ_percent::writebacks 0.523738 # Average percentage of cache occupancy
1075system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004689 # Average percentage of cache occupancy
1076system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy
1077system.cpu.l2cache.tags.occ_percent::cpu.inst 0.108009 # Average percentage of cache occupancy
1078system.cpu.l2cache.tags.occ_percent::cpu.data 0.341220 # Average percentage of cache occupancy
1079system.cpu.l2cache.tags.occ_percent::total 0.984520 # Average percentage of cache occupancy
1080system.cpu.l2cache.tags.occ_task_id_blocks::1023 496 # Occupied blocks per task id
1081system.cpu.l2cache.tags.occ_task_id_blocks::1024 61774 # Occupied blocks per task id
1082system.cpu.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
1083system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
1084system.cpu.l2cache.tags.age_task_id_blocks_1023::4 485 # Occupied blocks per task id
1085system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
1086system.cpu.l2cache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
1087system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2102 # Occupied blocks per task id
1088system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5030 # Occupied blocks per task id
1089system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54369 # Occupied blocks per task id
1090system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007568 # Percentage of cache occupancy per task id
1091system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942596 # Percentage of cache occupancy per task id
1092system.cpu.l2cache.tags.tag_accesses 341864435 # Number of tag accesses
1093system.cpu.l2cache.tags.data_accesses 341864435 # Number of data accesses
1094system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1342854 # number of ReadReq hits
1095system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 321211 # number of ReadReq hits
1096system.cpu.l2cache.ReadReq_hits::cpu.inst 16739434 # number of ReadReq hits
1097system.cpu.l2cache.ReadReq_hits::cpu.data 8950656 # number of ReadReq hits
1098system.cpu.l2cache.ReadReq_hits::total 27354155 # number of ReadReq hits
1099system.cpu.l2cache.Writeback_hits::writebacks 9369509 # number of Writeback hits
1100system.cpu.l2cache.Writeback_hits::total 9369509 # number of Writeback hits
1101system.cpu.l2cache.UpgradeReq_hits::cpu.data 13684 # number of UpgradeReq hits
1102system.cpu.l2cache.UpgradeReq_hits::total 13684 # number of UpgradeReq hits
1103system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
1104system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
1105system.cpu.l2cache.ReadExReq_hits::cpu.data 1532929 # number of ReadExReq hits
1106system.cpu.l2cache.ReadExReq_hits::total 1532929 # number of ReadExReq hits
1107system.cpu.l2cache.demand_hits::cpu.dtb.walker 1342854 # number of demand (read+write) hits
1108system.cpu.l2cache.demand_hits::cpu.itb.walker 321211 # number of demand (read+write) hits
1109system.cpu.l2cache.demand_hits::cpu.inst 16739434 # number of demand (read+write) hits
1110system.cpu.l2cache.demand_hits::cpu.data 10483585 # number of demand (read+write) hits
1111system.cpu.l2cache.demand_hits::total 28887084 # number of demand (read+write) hits
1112system.cpu.l2cache.overall_hits::cpu.dtb.walker 1342854 # number of overall hits
1113system.cpu.l2cache.overall_hits::cpu.itb.walker 321211 # number of overall hits
1114system.cpu.l2cache.overall_hits::cpu.inst 16739434 # number of overall hits
1115system.cpu.l2cache.overall_hits::cpu.data 10483585 # number of overall hits
1116system.cpu.l2cache.overall_hits::total 28887084 # number of overall hits
1117system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15661 # number of ReadReq misses
1118system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 19341 # number of ReadReq misses
1119system.cpu.l2cache.ReadReq_misses::cpu.inst 90708 # number of ReadReq misses
1120system.cpu.l2cache.ReadReq_misses::cpu.data 467610 # number of ReadReq misses
1121system.cpu.l2cache.ReadReq_misses::total 593320 # number of ReadReq misses
1122system.cpu.l2cache.UpgradeReq_misses::cpu.data 47842 # number of UpgradeReq misses
1123system.cpu.l2cache.UpgradeReq_misses::total 47842 # number of UpgradeReq misses
1124system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
1125system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
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1296system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.056790 # mshr miss rate for ReadReq accesses
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1300system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.777590 # mshr miss rate for UpgradeReq accesses
1301system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.777590 # mshr miss rate for UpgradeReq accesses
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1311system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011528 # mshr miss rate for overall accesses
1312system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.056790 # mshr miss rate for overall accesses
1313system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005390 # mshr miss rate for overall accesses
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1321system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
1322system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1323system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10006.580745 # average UpgradeReq mshr miss latency
1324system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10006.580745 # average UpgradeReq mshr miss latency
1325system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
1326system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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1328system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71012.621808 # average ReadExReq mshr miss latency
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1331system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64286.978734 # average overall mshr miss latency
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1335system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66214.178335 # average overall mshr miss latency
1336system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64286.978734 # average overall mshr miss latency
1337system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70545.291099 # average overall mshr miss latency
1338system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70213.494723 # average overall mshr miss latency
1339system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1340system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1341system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1342system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1343system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1344system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1345system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1346system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1347system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1348system.cpu.dcache.tags.replacements 13756884 # number of replacements
1349system.cpu.dcache.tags.tagsinuse 511.985330 # Cycle average of tags in use
1350system.cpu.dcache.tags.total_refs 363427258 # Total number of references to valid blocks.
1351system.cpu.dcache.tags.sampled_refs 13757396 # Sample count of references to valid blocks.
1352system.cpu.dcache.tags.avg_refs 26.416864 # Average number of references to valid blocks.
1353system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit.
1354system.cpu.dcache.tags.occ_blocks::cpu.data 511.985330 # Average occupied blocks per requestor
1355system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy
1356system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy
1357system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1358system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
1359system.cpu.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id
1360system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
1361system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1362system.cpu.dcache.tags.tag_accesses 1609448196 # Number of tag accesses
1363system.cpu.dcache.tags.data_accesses 1609448196 # Number of data accesses
1364system.cpu.dcache.ReadReq_hits::cpu.data 188132338 # number of ReadReq hits
1365system.cpu.dcache.ReadReq_hits::total 188132338 # number of ReadReq hits
1366system.cpu.dcache.WriteReq_hits::cpu.data 164232223 # number of WriteReq hits
1367system.cpu.dcache.WriteReq_hits::total 164232223 # number of WriteReq hits
1368system.cpu.dcache.SoftPFReq_hits::cpu.data 465761 # number of SoftPFReq hits
1369system.cpu.dcache.SoftPFReq_hits::total 465761 # number of SoftPFReq hits
1370system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1605675 # number of WriteInvalidateReq hits
1371system.cpu.dcache.WriteInvalidateReq_hits::total 1605675 # number of WriteInvalidateReq hits
1372system.cpu.dcache.LoadLockedReq_hits::cpu.data 4847947 # number of LoadLockedReq hits
1373system.cpu.dcache.LoadLockedReq_hits::total 4847947 # number of LoadLockedReq hits
1374system.cpu.dcache.StoreCondReq_hits::cpu.data 5335203 # number of StoreCondReq hits
1375system.cpu.dcache.StoreCondReq_hits::total 5335203 # number of StoreCondReq hits
1376system.cpu.dcache.demand_hits::cpu.data 352364561 # number of demand (read+write) hits
1377system.cpu.dcache.demand_hits::total 352364561 # number of demand (read+write) hits
1378system.cpu.dcache.overall_hits::cpu.data 352830322 # number of overall hits
1379system.cpu.dcache.overall_hits::total 352830322 # number of overall hits
1380system.cpu.dcache.ReadReq_misses::cpu.data 12712279 # number of ReadReq misses
1381system.cpu.dcache.ReadReq_misses::total 12712279 # number of ReadReq misses
1382system.cpu.dcache.WriteReq_misses::cpu.data 18968725 # number of WriteReq misses
1383system.cpu.dcache.WriteReq_misses::total 18968725 # number of WriteReq misses
1384system.cpu.dcache.SoftPFReq_misses::cpu.data 2072118 # number of SoftPFReq misses
1385system.cpu.dcache.SoftPFReq_misses::total 2072118 # number of SoftPFReq misses
1386system.cpu.dcache.LoadLockedReq_misses::cpu.data 550419 # number of LoadLockedReq misses
1387system.cpu.dcache.LoadLockedReq_misses::total 550419 # number of LoadLockedReq misses
1388system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses
1389system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
1390system.cpu.dcache.demand_misses::cpu.data 31681004 # number of demand (read+write) misses
1391system.cpu.dcache.demand_misses::total 31681004 # number of demand (read+write) misses
1392system.cpu.dcache.overall_misses::cpu.data 33753122 # number of overall misses
1393system.cpu.dcache.overall_misses::total 33753122 # number of overall misses
1394system.cpu.dcache.ReadReq_miss_latency::cpu.data 203403538452 # number of ReadReq miss cycles
1395system.cpu.dcache.ReadReq_miss_latency::total 203403538452 # number of ReadReq miss cycles
1396system.cpu.dcache.WriteReq_miss_latency::cpu.data 1021678237791 # number of WriteReq miss cycles
1397system.cpu.dcache.WriteReq_miss_latency::total 1021678237791 # number of WriteReq miss cycles
1398system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8626183252 # number of LoadLockedReq miss cycles
1399system.cpu.dcache.LoadLockedReq_miss_latency::total 8626183252 # number of LoadLockedReq miss cycles
1400system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 117003 # number of StoreCondReq miss cycles
1401system.cpu.dcache.StoreCondReq_miss_latency::total 117003 # number of StoreCondReq miss cycles
1402system.cpu.dcache.demand_miss_latency::cpu.data 1225081776243 # number of demand (read+write) miss cycles
1403system.cpu.dcache.demand_miss_latency::total 1225081776243 # number of demand (read+write) miss cycles
1404system.cpu.dcache.overall_miss_latency::cpu.data 1225081776243 # number of overall miss cycles
1405system.cpu.dcache.overall_miss_latency::total 1225081776243 # number of overall miss cycles
1406system.cpu.dcache.ReadReq_accesses::cpu.data 200844617 # number of ReadReq accesses(hits+misses)
1407system.cpu.dcache.ReadReq_accesses::total 200844617 # number of ReadReq accesses(hits+misses)
1408system.cpu.dcache.WriteReq_accesses::cpu.data 183200948 # number of WriteReq accesses(hits+misses)
1409system.cpu.dcache.WriteReq_accesses::total 183200948 # number of WriteReq accesses(hits+misses)
1410system.cpu.dcache.SoftPFReq_accesses::cpu.data 2537879 # number of SoftPFReq accesses(hits+misses)
1411system.cpu.dcache.SoftPFReq_accesses::total 2537879 # number of SoftPFReq accesses(hits+misses)
1412system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1605675 # number of WriteInvalidateReq accesses(hits+misses)
1413system.cpu.dcache.WriteInvalidateReq_accesses::total 1605675 # number of WriteInvalidateReq accesses(hits+misses)
1414system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5398366 # number of LoadLockedReq accesses(hits+misses)
1415system.cpu.dcache.LoadLockedReq_accesses::total 5398366 # number of LoadLockedReq accesses(hits+misses)
1416system.cpu.dcache.StoreCondReq_accesses::cpu.data 5335209 # number of StoreCondReq accesses(hits+misses)
1417system.cpu.dcache.StoreCondReq_accesses::total 5335209 # number of StoreCondReq accesses(hits+misses)
1418system.cpu.dcache.demand_accesses::cpu.data 384045565 # number of demand (read+write) accesses
1419system.cpu.dcache.demand_accesses::total 384045565 # number of demand (read+write) accesses
1420system.cpu.dcache.overall_accesses::cpu.data 386583444 # number of overall (read+write) accesses
1421system.cpu.dcache.overall_accesses::total 386583444 # number of overall (read+write) accesses
1422system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063294 # miss rate for ReadReq accesses
1423system.cpu.dcache.ReadReq_miss_rate::total 0.063294 # miss rate for ReadReq accesses
1424system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103541 # miss rate for WriteReq accesses
1425system.cpu.dcache.WriteReq_miss_rate::total 0.103541 # miss rate for WriteReq accesses
1426system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816476 # miss rate for SoftPFReq accesses
1427system.cpu.dcache.SoftPFReq_miss_rate::total 0.816476 # miss rate for SoftPFReq accesses
1428system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.101960 # miss rate for LoadLockedReq accesses
1429system.cpu.dcache.LoadLockedReq_miss_rate::total 0.101960 # miss rate for LoadLockedReq accesses
1430system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
1431system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
1432system.cpu.dcache.demand_miss_rate::cpu.data 0.082493 # miss rate for demand accesses
1433system.cpu.dcache.demand_miss_rate::total 0.082493 # miss rate for demand accesses
1434system.cpu.dcache.overall_miss_rate::cpu.data 0.087311 # miss rate for overall accesses
1435system.cpu.dcache.overall_miss_rate::total 0.087311 # miss rate for overall accesses
1436system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16000.556505 # average ReadReq miss latency
1437system.cpu.dcache.ReadReq_avg_miss_latency::total 16000.556505 # average ReadReq miss latency
1438system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53861.197196 # average WriteReq miss latency
1439system.cpu.dcache.WriteReq_avg_miss_latency::total 53861.197196 # average WriteReq miss latency
1440system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15672.030311 # average LoadLockedReq miss latency
1441system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15672.030311 # average LoadLockedReq miss latency
1442system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency
1443system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency
1444system.cpu.dcache.demand_avg_miss_latency::cpu.data 38669.285110 # average overall miss latency
1445system.cpu.dcache.demand_avg_miss_latency::total 38669.285110 # average overall miss latency
1446system.cpu.dcache.overall_avg_miss_latency::cpu.data 36295.361841 # average overall miss latency
1447system.cpu.dcache.overall_avg_miss_latency::total 36295.361841 # average overall miss latency
1448system.cpu.dcache.blocked_cycles::no_mshrs 38319499 # number of cycles access was blocked
1449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1450system.cpu.dcache.blocked::no_mshrs 2284719 # number of cycles access was blocked
1451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1452system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.772084 # average number of cycles each access was blocked
1453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1454system.cpu.dcache.fast_writes 1605675 # number of fast writes performed
1455system.cpu.dcache.cache_copies 0 # number of cache copies performed
1456system.cpu.dcache.writebacks::writebacks 9369509 # number of writebacks
1457system.cpu.dcache.writebacks::total 9369509 # number of writebacks
1458system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628309 # number of ReadReq MSHR hits
1459system.cpu.dcache.ReadReq_mshr_hits::total 5628309 # number of ReadReq MSHR hits
1460system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15829986 # number of WriteReq MSHR hits
1461system.cpu.dcache.WriteReq_mshr_hits::total 15829986 # number of WriteReq MSHR hits
1462system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265840 # number of LoadLockedReq MSHR hits
1463system.cpu.dcache.LoadLockedReq_mshr_hits::total 265840 # number of LoadLockedReq MSHR hits
1464system.cpu.dcache.demand_mshr_hits::cpu.data 21458295 # number of demand (read+write) MSHR hits
1465system.cpu.dcache.demand_mshr_hits::total 21458295 # number of demand (read+write) MSHR hits
1466system.cpu.dcache.overall_mshr_hits::cpu.data 21458295 # number of overall MSHR hits
1467system.cpu.dcache.overall_mshr_hits::total 21458295 # number of overall MSHR hits
1468system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7083970 # number of ReadReq MSHR misses
1469system.cpu.dcache.ReadReq_mshr_misses::total 7083970 # number of ReadReq MSHR misses
1470system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3120649 # number of WriteReq MSHR misses
1471system.cpu.dcache.WriteReq_mshr_misses::total 3120649 # number of WriteReq MSHR misses
1472system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2065320 # number of SoftPFReq MSHR misses
1473system.cpu.dcache.SoftPFReq_mshr_misses::total 2065320 # number of SoftPFReq MSHR misses
1474system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284579 # number of LoadLockedReq MSHR misses
1475system.cpu.dcache.LoadLockedReq_mshr_misses::total 284579 # number of LoadLockedReq MSHR misses
1476system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses
1477system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
1478system.cpu.dcache.demand_mshr_misses::cpu.data 10204619 # number of demand (read+write) MSHR misses
1479system.cpu.dcache.demand_mshr_misses::total 10204619 # number of demand (read+write) MSHR misses
1480system.cpu.dcache.overall_mshr_misses::cpu.data 12269939 # number of overall MSHR misses
1481system.cpu.dcache.overall_mshr_misses::total 12269939 # number of overall MSHR misses
1482system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102477717871 # number of ReadReq MSHR miss cycles
1483system.cpu.dcache.ReadReq_mshr_miss_latency::total 102477717871 # number of ReadReq MSHR miss cycles
1484system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 148263766896 # number of WriteReq MSHR miss cycles
1485system.cpu.dcache.WriteReq_mshr_miss_latency::total 148263766896 # number of WriteReq MSHR miss cycles
1486system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 31611668497 # number of SoftPFReq MSHR miss cycles
1487system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 31611668497 # number of SoftPFReq MSHR miss cycles
1488system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 59007365277 # number of WriteInvalidateReq MSHR miss cycles
1489system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 59007365277 # number of WriteInvalidateReq MSHR miss cycles
1490system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3751055249 # number of LoadLockedReq MSHR miss cycles
1491system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3751055249 # number of LoadLockedReq MSHR miss cycles
1492system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 104997 # number of StoreCondReq MSHR miss cycles
1493system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 104997 # number of StoreCondReq MSHR miss cycles
1494system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250741484767 # number of demand (read+write) MSHR miss cycles
1495system.cpu.dcache.demand_mshr_miss_latency::total 250741484767 # number of demand (read+write) MSHR miss cycles
1496system.cpu.dcache.overall_mshr_miss_latency::cpu.data 282353153264 # number of overall MSHR miss cycles
1497system.cpu.dcache.overall_mshr_miss_latency::total 282353153264 # number of overall MSHR miss cycles
1498system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729434750 # number of ReadReq MSHR uncacheable cycles
1499system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729434750 # number of ReadReq MSHR uncacheable cycles
1500system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587276983 # number of WriteReq MSHR uncacheable cycles
1501system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587276983 # number of WriteReq MSHR uncacheable cycles
1502system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316711733 # number of overall MSHR uncacheable cycles
1503system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316711733 # number of overall MSHR uncacheable cycles
1504system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035271 # mshr miss rate for ReadReq accesses
1505system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035271 # mshr miss rate for ReadReq accesses
1506system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.017034 # mshr miss rate for WriteReq accesses
1507system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.017034 # mshr miss rate for WriteReq accesses
1508system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813798 # mshr miss rate for SoftPFReq accesses
1509system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813798 # mshr miss rate for SoftPFReq accesses
1510system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052716 # mshr miss rate for LoadLockedReq accesses
1511system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052716 # mshr miss rate for LoadLockedReq accesses
1512system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
1513system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
1514system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026571 # mshr miss rate for demand accesses
1515system.cpu.dcache.demand_mshr_miss_rate::total 0.026571 # mshr miss rate for demand accesses
1516system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031739 # mshr miss rate for overall accesses
1517system.cpu.dcache.overall_mshr_miss_rate::total 0.031739 # mshr miss rate for overall accesses
1518system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.142272 # average ReadReq mshr miss latency
1519system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.142272 # average ReadReq mshr miss latency
1520system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47510.555303 # average WriteReq mshr miss latency
1521system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47510.555303 # average WriteReq mshr miss latency
1522system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15305.942177 # average SoftPFReq mshr miss latency
1523system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15305.942177 # average SoftPFReq mshr miss latency
1524system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
1525system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1526system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13181.068347 # average LoadLockedReq mshr miss latency
1527system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13181.068347 # average LoadLockedReq mshr miss latency
1528system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency
1529system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency
1530system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24571.371530 # average overall mshr miss latency
1531system.cpu.dcache.demand_avg_mshr_miss_latency::total 24571.371530 # average overall mshr miss latency
1532system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23011.781335 # average overall mshr miss latency
1533system.cpu.dcache.overall_avg_mshr_miss_latency::total 23011.781335 # average overall mshr miss latency
1534system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1535system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1536system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1537system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1538system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1539system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1541system.iocache.tags.replacements 115458 # number of replacements
1542system.iocache.tags.tagsinuse 10.450727 # Cycle average of tags in use
1543system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1544system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks.
1545system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1546system.iocache.tags.warmup_cycle 13090278324000 # Cycle when the warmup percentage was hit.
1547system.iocache.tags.occ_blocks::realview.ethernet 3.528058 # Average occupied blocks per requestor
1548system.iocache.tags.occ_blocks::realview.ide 6.922669 # Average occupied blocks per requestor
1549system.iocache.tags.occ_percent::realview.ethernet 0.220504 # Average percentage of cache occupancy
1550system.iocache.tags.occ_percent::realview.ide 0.432667 # Average percentage of cache occupancy
1551system.iocache.tags.occ_percent::total 0.653170 # Average percentage of cache occupancy
1552system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1553system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1554system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1555system.iocache.tags.tag_accesses 1039786 # Number of tag accesses
1556system.iocache.tags.data_accesses 1039786 # Number of data accesses
1557system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
1558system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
1559system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1560system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
1561system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
1562system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1563system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1564system.iocache.WriteInvalidateReq_misses::realview.ide 17 # number of WriteInvalidateReq misses
1565system.iocache.WriteInvalidateReq_misses::total 17 # number of WriteInvalidateReq misses
1566system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1567system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
1568system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
1569system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1570system.iocache.overall_misses::realview.ide 8813 # number of overall misses
1571system.iocache.overall_misses::total 8853 # number of overall misses
1572system.iocache.ReadReq_miss_latency::realview.ethernet 5547000 # number of ReadReq miss cycles
1573system.iocache.ReadReq_miss_latency::realview.ide 1929395843 # number of ReadReq miss cycles
1574system.iocache.ReadReq_miss_latency::total 1934942843 # number of ReadReq miss cycles
1575system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
1576system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
1577system.iocache.demand_miss_latency::realview.ethernet 5886000 # number of demand (read+write) miss cycles
1578system.iocache.demand_miss_latency::realview.ide 1929395843 # number of demand (read+write) miss cycles
1579system.iocache.demand_miss_latency::total 1935281843 # number of demand (read+write) miss cycles
1580system.iocache.overall_miss_latency::realview.ethernet 5886000 # number of overall miss cycles
1581system.iocache.overall_miss_latency::realview.ide 1929395843 # number of overall miss cycles
1582system.iocache.overall_miss_latency::total 1935281843 # number of overall miss cycles
1583system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1584system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
1585system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
1586system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1587system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1588system.iocache.WriteInvalidateReq_accesses::realview.ide 106681 # number of WriteInvalidateReq accesses(hits+misses)
1589system.iocache.WriteInvalidateReq_accesses::total 106681 # number of WriteInvalidateReq accesses(hits+misses)
1590system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1591system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
1592system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
1593system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1594system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
1595system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
1596system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1597system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1598system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1599system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1600system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1601system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000159 # miss rate for WriteInvalidateReq accesses
1602system.iocache.WriteInvalidateReq_miss_rate::total 0.000159 # miss rate for WriteInvalidateReq accesses
1603system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1604system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1605system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1606system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1607system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1608system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1609system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149918.918919 # average ReadReq miss latency
1610system.iocache.ReadReq_avg_miss_latency::realview.ide 218926.114036 # average ReadReq miss latency
1611system.iocache.ReadReq_avg_miss_latency::total 218637.609379 # average ReadReq miss latency
1612system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
1613system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
1614system.iocache.demand_avg_miss_latency::realview.ethernet 147150 # average overall miss latency
1615system.iocache.demand_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency
1616system.iocache.demand_avg_miss_latency::total 218601.812154 # average overall miss latency
1617system.iocache.overall_avg_miss_latency::realview.ethernet 147150 # average overall miss latency
1618system.iocache.overall_avg_miss_latency::realview.ide 218926.114036 # average overall miss latency
1619system.iocache.overall_avg_miss_latency::total 218601.812154 # average overall miss latency
1620system.iocache.blocked_cycles::no_mshrs 53350 # number of cycles access was blocked
1621system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1622system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
1623system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1624system.iocache.avg_blocked_cycles::no_mshrs 9.717668 # average number of cycles each access was blocked
1625system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1626system.iocache.fast_writes 106664 # number of fast writes performed
1627system.iocache.cache_copies 0 # number of cache copies performed
1628system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1629system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses
1630system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses
1631system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1632system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1633system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1634system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses
1635system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses
1636system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1637system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses
1638system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses
1639system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3623000 # number of ReadReq MSHR miss cycles
1640system.iocache.ReadReq_mshr_miss_latency::realview.ide 1470987863 # number of ReadReq MSHR miss cycles
1641system.iocache.ReadReq_mshr_miss_latency::total 1474610863 # number of ReadReq MSHR miss cycles
1642system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
1643system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
1644system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6546677301 # number of WriteInvalidateReq MSHR miss cycles
1645system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6546677301 # number of WriteInvalidateReq MSHR miss cycles
1646system.iocache.demand_mshr_miss_latency::realview.ethernet 3806000 # number of demand (read+write) MSHR miss cycles
1647system.iocache.demand_mshr_miss_latency::realview.ide 1470987863 # number of demand (read+write) MSHR miss cycles
1648system.iocache.demand_mshr_miss_latency::total 1474793863 # number of demand (read+write) MSHR miss cycles
1649system.iocache.overall_mshr_miss_latency::realview.ethernet 3806000 # number of overall MSHR miss cycles
1650system.iocache.overall_mshr_miss_latency::realview.ide 1470987863 # number of overall MSHR miss cycles
1651system.iocache.overall_mshr_miss_latency::total 1474793863 # number of overall MSHR miss cycles
1652system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1653system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1654system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1655system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1656system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1657system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1658system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1659system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1660system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1661system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1662system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1663system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97918.918919 # average ReadReq mshr miss latency
1664system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166911.138432 # average ReadReq mshr miss latency
1665system.iocache.ReadReq_avg_mshr_miss_latency::total 166622.696384 # average ReadReq mshr miss latency
1666system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
1667system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
1668system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
1669system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1670system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency
1671system.iocache.demand_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency
1672system.iocache.demand_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency
1673system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 95150 # average overall mshr miss latency
1674system.iocache.overall_avg_mshr_miss_latency::realview.ide 166911.138432 # average overall mshr miss latency
1675system.iocache.overall_avg_mshr_miss_latency::total 166586.904213 # average overall mshr miss latency
1676system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1677system.cpu.kern.inst.arm 0 # number of arm instructions executed
1678system.cpu.kern.inst.quiesce 17164 # number of quiesce instructions executed
1679
1680---------- End Simulation Statistics ----------