1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.327140 # Number of seconds simulated
4sim_ticks 51327139864000 # Number of ticks simulated
5final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 184861 # Simulator instruction rate (inst/s)
8host_op_rate 217215 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 11186950873 # Simulator tick rate (ticks/s)
10host_mem_usage 729056 # Number of bytes of host memory used
11host_seconds 4588.13 # Real time elapsed on the host
12sim_insts 848164321 # Number of instructions simulated
13sim_ops 996610207 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory
21system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory
22system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory
--- 294 unchanged lines hidden (view full) ---
319system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ)
320system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ)
321system.physmem_1.averagePower 668.450284 # Core power per rank (mW)
322system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states
323system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states
324system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
325system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states
326system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
327system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
328system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
329system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
330system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
331system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
332system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
333system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
334system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
335system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
336system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
337system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
338system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
339system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
340system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
341system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
342system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
343system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
344system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
345system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
346system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
350system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
351system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
352system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
353system.cpu.branchPred.lookups 225024609 # Number of BP lookups
354system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted
--- 4 unchanged lines hidden (view full) ---
359system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage
360system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target.
361system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions.
362system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups.
363system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits.
364system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses.
365system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
368system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
389system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
390system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
391system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
392system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
393system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
394system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
395system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
396system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
397system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
398system.cpu.dtb.walker.walks 947007 # Table walker walks requested
399system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors
400system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate
401system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate
402system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting
403system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency
404system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency
405system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency
--- 65 unchanged lines hidden (view full) ---
471system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
472system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions
473system.cpu.dtb.read_accesses 170073675 # DTB read accesses
474system.cpu.dtb.write_accesses 147605121 # DTB write accesses
475system.cpu.dtb.inst_accesses 0 # ITB inst accesses
476system.cpu.dtb.hits 316731789 # DTB hits
477system.cpu.dtb.misses 947007 # DTB misses
478system.cpu.dtb.accesses 317678796 # DTB accesses
479system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
480system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
481system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
482system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
483system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
484system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
485system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
487system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
501system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
502system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
503system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
504system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
505system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
506system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
507system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
508system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
509system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
510system.cpu.itb.walker.walks 162102 # Table walker walks requested
511system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors
512system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate
513system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate
514system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting
515system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency
516system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency
517system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency
--- 62 unchanged lines hidden (view full) ---
580system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
581system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions
582system.cpu.itb.read_accesses 0 # DTB read accesses
583system.cpu.itb.write_accesses 0 # DTB write accesses
584system.cpu.itb.inst_accesses 357169890 # ITB inst accesses
585system.cpu.itb.hits 357007788 # DTB hits
586system.cpu.itb.misses 162102 # DTB misses
587system.cpu.itb.accesses 357169890 # DTB accesses
588system.cpu.numPwrStateTransitions 32228 # Number of power state transitions
589system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state
590system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state
591system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state
592system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state
593system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state
594system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
595system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
596system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
597system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
598system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
599system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
600system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
601system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
602system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
603system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
604system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
605system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state
606system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states
607system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states
608system.cpu.numCycles 1631144067 # number of cpu cycles simulated
609system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
610system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
611system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss
612system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed
613system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered
614system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken
615system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked
--- 279 unchanged lines hidden (view full) ---
895system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads
896system.cpu.int_regfile_writes 731349757 # number of integer regfile writes
897system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads
898system.cpu.fp_regfile_writes 780384 # number of floating regfile writes
899system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads
900system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
901system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
902system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
903system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
904system.cpu.dcache.tags.replacements 9706309 # number of replacements
905system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
906system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks.
907system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks.
908system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks.
909system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
910system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor
911system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
912system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
913system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
914system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
915system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
916system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
917system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
918system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses
919system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses
920system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
921system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits
922system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits
923system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits
924system.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits
925system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits
926system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits
927system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits
928system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits
--- 174 unchanged lines hidden (view full) ---
1103system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency
1104system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency
1105system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency
1106system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency
1107system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency
1108system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
1109system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
1110system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
1111system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1112system.cpu.icache.tags.replacements 15141033 # number of replacements
1113system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
1114system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
1115system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks.
1116system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks.
1117system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit.
1118system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor
1119system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy
1120system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy
1121system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1122system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
1123system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
1124system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
1125system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1126system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses
1127system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses
1128system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1129system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits
1130system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits
1131system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits
1132system.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits
1133system.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits
1134system.cpu.icache.overall_hits::total 340718799 # number of overall hits
1135system.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses
1136system.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses
--- 70 unchanged lines hidden (view full) ---
1207system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency
1208system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency
1209system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency
1210system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency
1211system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency
1212system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
1213system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
1214system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
1215system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1216system.cpu.l2cache.tags.replacements 1146896 # number of replacements
1217system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use
1218system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks.
1219system.cpu.l2cache.tags.sampled_refs 1209243 # Sample count of references to valid blocks.
1220system.cpu.l2cache.tags.avg_refs 38.281145 # Average number of references to valid blocks.
1221system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit.
1222system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589 # Average occupied blocks per requestor
1223system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 299.826567 # Average occupied blocks per requestor
--- 14 unchanged lines hidden (view full) ---
1238system.cpu.l2cache.tags.age_task_id_blocks_1024::1 573 # Occupied blocks per task id
1239system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2710 # Occupied blocks per task id
1240system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5168 # Occupied blocks per task id
1241system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53538 # Occupied blocks per task id
1242system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id
1243system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id
1244system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses
1245system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses
1246system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1247system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits
1248system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits
1249system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits
1250system.cpu.l2cache.WritebackDirty_hits::writebacks 7511281 # number of WritebackDirty hits
1251system.cpu.l2cache.WritebackDirty_hits::total 7511281 # number of WritebackDirty hits
1252system.cpu.l2cache.WritebackClean_hits::writebacks 15138290 # number of WritebackClean hits
1253system.cpu.l2cache.WritebackClean_hits::total 15138290 # number of WritebackClean hits
1254system.cpu.l2cache.UpgradeReq_hits::cpu.data 9403 # number of UpgradeReq hits
--- 290 unchanged lines hidden (view full) ---
1545system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency
1546system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency
1547system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter.
1548system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1549system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1550system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter.
1551system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1552system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1553system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1554system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution
1555system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution
1556system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
1557system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
1558system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution
1559system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution
1560system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution
1561system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution
--- 34 unchanged lines hidden (view full) ---
1596system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks)
1597system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1598system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks)
1599system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1600system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks)
1601system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1602system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks)
1603system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1604system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1605system.iobus.trans_dist::ReadReq 40299 # Transaction distribution
1606system.iobus.trans_dist::ReadResp 40299 # Transaction distribution
1607system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1608system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1609system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1610system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1611system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1612system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
--- 60 unchanged lines hidden (view full) ---
1673system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks)
1674system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1675system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1676system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1677system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks)
1678system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1679system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1680system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1681system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1682system.iocache.tags.replacements 115459 # number of replacements
1683system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use
1684system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1685system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
1686system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1687system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit.
1688system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor
1689system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor
1690system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy
1691system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy
1692system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy
1693system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1694system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1695system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1696system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
1697system.iocache.tags.data_accesses 1039659 # Number of data accesses
1698system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1699system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1700system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
1701system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
1702system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1703system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1704system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1705system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1706system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
--- 109 unchanged lines hidden (view full) ---
1816system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency
1817system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency
1818system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
1819system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
1820system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1821system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
1822system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
1823system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1824system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1825system.membus.trans_dist::ReadReq 54972 # Transaction distribution
1826system.membus.trans_dist::ReadResp 410008 # Transaction distribution
1827system.membus.trans_dist::WriteReq 33696 # Transaction distribution
1828system.membus.trans_dist::WriteResp 33696 # Transaction distribution
1829system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution
1830system.membus.trans_dist::CleanEvict 192763 # Transaction distribution
1831system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution
1832system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
--- 37 unchanged lines hidden (view full) ---
1870system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks)
1871system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1872system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks)
1873system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1874system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks)
1875system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1876system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks)
1877system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1878system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1879system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1880system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1881system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1882system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1883system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1884system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1885system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1886system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1887system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1888system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1889system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1890system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1891system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1892system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1893system.realview.ethernet.txBytes 966 # Bytes Transmitted
1894system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1895system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1896system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1897system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1898system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1899system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1900system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
--- 26 unchanged lines hidden (view full) ---
1927system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1928system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1929system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1930system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1931system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1932system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1933system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1934system.realview.ethernet.droppedPackets 0 # number of packets dropped
1935system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1936system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1937system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1938system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1939system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1940system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1941system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1942system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1943system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1944system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1945system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1946system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1947system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1948system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1949system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1950system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1951system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1952system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1953system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1954system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1955system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1956system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1957system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1958system.cpu.kern.inst.arm 0 # number of arm instructions executed
1959system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed
1960
1961---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.327140 # Number of seconds simulated
4sim_ticks 51327139864000 # Number of ticks simulated
5final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 184861 # Simulator instruction rate (inst/s)
8host_op_rate 217215 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 11186950873 # Simulator tick rate (ticks/s)
10host_mem_usage 729056 # Number of bytes of host memory used
11host_seconds 4588.13 # Real time elapsed on the host
12sim_insts 848164321 # Number of instructions simulated
13sim_ops 996610207 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory
21system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory
22system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory
--- 294 unchanged lines hidden (view full) ---
319system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ)
320system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ)
321system.physmem_1.averagePower 668.450284 # Core power per rank (mW)
322system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states
323system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states
324system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
325system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states
326system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
327system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
328system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
329system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
330system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
331system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
332system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
333system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
334system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
335system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
336system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
337system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
338system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
339system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
340system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
341system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
342system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
343system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
344system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
345system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
346system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
350system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
351system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
352system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
353system.cpu.branchPred.lookups 225024609 # Number of BP lookups
354system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted
--- 4 unchanged lines hidden (view full) ---
359system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage
360system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target.
361system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions.
362system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups.
363system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits.
364system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses.
365system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
368system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
389system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
390system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
391system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
392system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
393system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
394system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
395system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
396system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
397system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
398system.cpu.dtb.walker.walks 947007 # Table walker walks requested
399system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors
400system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate
401system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate
402system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting
403system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency
404system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency
405system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency
--- 65 unchanged lines hidden (view full) ---
471system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
472system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions
473system.cpu.dtb.read_accesses 170073675 # DTB read accesses
474system.cpu.dtb.write_accesses 147605121 # DTB write accesses
475system.cpu.dtb.inst_accesses 0 # ITB inst accesses
476system.cpu.dtb.hits 316731789 # DTB hits
477system.cpu.dtb.misses 947007 # DTB misses
478system.cpu.dtb.accesses 317678796 # DTB accesses
479system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
480system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
481system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
482system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
483system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
484system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
485system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
487system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
501system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
502system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
503system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
504system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
505system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
506system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
507system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
508system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
509system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
510system.cpu.itb.walker.walks 162102 # Table walker walks requested
511system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors
512system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate
513system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate
514system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting
515system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency
516system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency
517system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency
--- 62 unchanged lines hidden (view full) ---
580system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
581system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions
582system.cpu.itb.read_accesses 0 # DTB read accesses
583system.cpu.itb.write_accesses 0 # DTB write accesses
584system.cpu.itb.inst_accesses 357169890 # ITB inst accesses
585system.cpu.itb.hits 357007788 # DTB hits
586system.cpu.itb.misses 162102 # DTB misses
587system.cpu.itb.accesses 357169890 # DTB accesses
588system.cpu.numPwrStateTransitions 32228 # Number of power state transitions
589system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state
590system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state
591system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state
592system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state
593system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state
594system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
595system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state
596system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
597system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
598system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
599system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
600system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
601system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
602system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
603system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
604system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
605system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state
606system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states
607system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states
608system.cpu.numCycles 1631144067 # number of cpu cycles simulated
609system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
610system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
611system.cpu.fetch.icacheStallCycles 646909150 # Number of cycles fetch is stalled on an Icache miss
612system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed
613system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered
614system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken
615system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked
--- 279 unchanged lines hidden (view full) ---
895system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads
896system.cpu.int_regfile_writes 731349757 # number of integer regfile writes
897system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads
898system.cpu.fp_regfile_writes 780384 # number of floating regfile writes
899system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads
900system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
901system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads
902system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
903system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
904system.cpu.dcache.tags.replacements 9706309 # number of replacements
905system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
906system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks.
907system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks.
908system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks.
909system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
910system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor
911system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
912system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
913system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
914system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
915system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
916system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
917system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
918system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses
919system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses
920system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
921system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits
922system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits
923system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits
924system.cpu.dcache.WriteReq_hits::total 128244124 # number of WriteReq hits
925system.cpu.dcache.SoftPFReq_hits::cpu.data 377753 # number of SoftPFReq hits
926system.cpu.dcache.SoftPFReq_hits::total 377753 # number of SoftPFReq hits
927system.cpu.dcache.WriteLineReq_hits::cpu.data 323466 # number of WriteLineReq hits
928system.cpu.dcache.WriteLineReq_hits::total 323466 # number of WriteLineReq hits
--- 174 unchanged lines hidden (view full) ---
1103system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25504.994582 # average overall mshr miss latency
1104system.cpu.dcache.demand_avg_mshr_miss_latency::total 25504.994582 # average overall mshr miss latency
1105system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24874.769579 # average overall mshr miss latency
1106system.cpu.dcache.overall_avg_mshr_miss_latency::total 24874.769579 # average overall mshr miss latency
1107system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 # average ReadReq mshr uncacheable latency
1108system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
1109system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency
1110system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency
1111system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1112system.cpu.icache.tags.replacements 15141033 # number of replacements
1113system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
1114system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
1115system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks.
1116system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks.
1117system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit.
1118system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor
1119system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy
1120system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy
1121system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1122system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
1123system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
1124system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
1125system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1126system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses
1127system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses
1128system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1129system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits
1130system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits
1131system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits
1132system.cpu.icache.demand_hits::total 340718799 # number of demand (read+write) hits
1133system.cpu.icache.overall_hits::cpu.inst 340718799 # number of overall hits
1134system.cpu.icache.overall_hits::total 340718799 # number of overall hits
1135system.cpu.icache.ReadReq_misses::cpu.inst 15894345 # number of ReadReq misses
1136system.cpu.icache.ReadReq_misses::total 15894345 # number of ReadReq misses
--- 70 unchanged lines hidden (view full) ---
1207system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency
1208system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency
1209system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.209653 # average overall mshr miss latency
1210system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.209653 # average overall mshr miss latency
1211system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency
1212system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency
1213system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency
1214system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency
1215system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1216system.cpu.l2cache.tags.replacements 1146896 # number of replacements
1217system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use
1218system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks.
1219system.cpu.l2cache.tags.sampled_refs 1209243 # Sample count of references to valid blocks.
1220system.cpu.l2cache.tags.avg_refs 38.281145 # Average number of references to valid blocks.
1221system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit.
1222system.cpu.l2cache.tags.occ_blocks::writebacks 37206.816589 # Average occupied blocks per requestor
1223system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 299.826567 # Average occupied blocks per requestor
--- 14 unchanged lines hidden (view full) ---
1238system.cpu.l2cache.tags.age_task_id_blocks_1024::1 573 # Occupied blocks per task id
1239system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2710 # Occupied blocks per task id
1240system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5168 # Occupied blocks per task id
1241system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53538 # Occupied blocks per task id
1242system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id
1243system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id
1244system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses
1245system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses
1246system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1247system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits
1248system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits
1249system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits
1250system.cpu.l2cache.WritebackDirty_hits::writebacks 7511281 # number of WritebackDirty hits
1251system.cpu.l2cache.WritebackDirty_hits::total 7511281 # number of WritebackDirty hits
1252system.cpu.l2cache.WritebackClean_hits::writebacks 15138290 # number of WritebackClean hits
1253system.cpu.l2cache.WritebackClean_hits::total 15138290 # number of WritebackClean hits
1254system.cpu.l2cache.UpgradeReq_hits::cpu.data 9403 # number of UpgradeReq hits
--- 290 unchanged lines hidden (view full) ---
1545system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85654.636804 # average overall mshr uncacheable latency
1546system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.186268 # average overall mshr uncacheable latency
1547system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter.
1548system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1549system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1550system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter.
1551system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1552system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1553system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1554system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution
1555system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution
1556system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
1557system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
1558system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution
1559system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution
1560system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution
1561system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution
--- 34 unchanged lines hidden (view full) ---
1596system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks)
1597system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1598system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks)
1599system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1600system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks)
1601system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1602system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks)
1603system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1604system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1605system.iobus.trans_dist::ReadReq 40299 # Transaction distribution
1606system.iobus.trans_dist::ReadResp 40299 # Transaction distribution
1607system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
1608system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
1609system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
1610system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1611system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1612system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
--- 60 unchanged lines hidden (view full) ---
1673system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks)
1674system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1675system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
1676system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1677system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks)
1678system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1679system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
1680system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1681system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1682system.iocache.tags.replacements 115459 # number of replacements
1683system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use
1684system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1685system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
1686system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1687system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit.
1688system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor
1689system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor
1690system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy
1691system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy
1692system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy
1693system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1694system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1695system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1696system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
1697system.iocache.tags.data_accesses 1039659 # Number of data accesses
1698system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1699system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1700system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
1701system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
1702system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1703system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1704system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
1705system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
1706system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
--- 109 unchanged lines hidden (view full) ---
1816system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency
1817system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency
1818system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
1819system.iocache.demand_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
1820system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1821system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
1822system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency
1823system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency
1824system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1825system.membus.trans_dist::ReadReq 54972 # Transaction distribution
1826system.membus.trans_dist::ReadResp 410008 # Transaction distribution
1827system.membus.trans_dist::WriteReq 33696 # Transaction distribution
1828system.membus.trans_dist::WriteResp 33696 # Transaction distribution
1829system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution
1830system.membus.trans_dist::CleanEvict 192763 # Transaction distribution
1831system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution
1832system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
--- 37 unchanged lines hidden (view full) ---
1870system.membus.reqLayer2.occupancy 5571500 # Layer occupancy (ticks)
1871system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1872system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks)
1873system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1874system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks)
1875system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1876system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks)
1877system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1878system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1879system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1880system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1881system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1882system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1883system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1884system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1885system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1886system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1887system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1888system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1889system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1890system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1891system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1892system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1893system.realview.ethernet.txBytes 966 # Bytes Transmitted
1894system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1895system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1896system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1897system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1898system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1899system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1900system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
--- 26 unchanged lines hidden (view full) ---
1927system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1928system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1929system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1930system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1931system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1932system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1933system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1934system.realview.ethernet.droppedPackets 0 # number of packets dropped
1935system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1936system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1937system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1938system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1939system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1940system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1941system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1942system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1943system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1944system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1945system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1946system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1947system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1948system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1949system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1950system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1951system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1952system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1953system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1954system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1955system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1956system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1957system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states
1958system.cpu.kern.inst.arm 0 # number of arm instructions executed
1959system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed
1960
1961---------- End Simulation Statistics ----------