1
2---------- Begin Simulation Statistics ----------
3sim_seconds 51.320621 # Number of seconds simulated
4sim_ticks 51320620981500 # Number of ticks simulated
5final_tick 51320620981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 107709 # Simulator instruction rate (inst/s)
8host_op_rate 126560 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6449160479 # Simulator tick rate (ticks/s)
10host_mem_usage 667684 # Number of bytes of host memory used
11host_seconds 7957.72 # Real time elapsed on the host
12sim_insts 857117694 # Number of instructions simulated
13sim_ops 1007133124 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.dtb.walker 227264 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.itb.walker 206272 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.inst 5756576 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.data 43073416 # Number of bytes read from this memory
20system.physmem.bytes_read::realview.ide 400256 # Number of bytes read from this memory
21system.physmem.bytes_read::total 49663784 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 5756576 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 5756576 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 69780544 # Number of bytes written to this memory
25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
26system.physmem.bytes_written::total 69801124 # Number of bytes written to this memory
27system.physmem.num_reads::cpu.dtb.walker 3551 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 3223 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 105899 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 673035 # Number of read requests responded to by this memory
31system.physmem.num_reads::realview.ide 6254 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 791962 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 1090321 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 1092894 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.itb.walker 4019 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.inst 112169 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.data 839300 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::realview.ide 7799 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 967716 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 112169 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 112169 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1359698 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 1360099 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1359698 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.itb.walker 4019 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.inst 112169 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.data 839701 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::realview.ide 7799 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 2327815 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 791962 # Number of read requests accepted
55system.physmem.writeReqs 1696531 # Number of write requests accepted
56system.physmem.readBursts 791962 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 1696531 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 50649920 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 35648 # Total number of bytes read from write queue
60system.physmem.bytesWritten 108090368 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 49663784 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 108433892 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 557 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 7601 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 35291 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 50546 # Per bank write bursts
67system.physmem.perBankRdBursts::1 51810 # Per bank write bursts
68system.physmem.perBankRdBursts::2 46789 # Per bank write bursts
69system.physmem.perBankRdBursts::3 46242 # Per bank write bursts
70system.physmem.perBankRdBursts::4 46096 # Per bank write bursts
71system.physmem.perBankRdBursts::5 52242 # Per bank write bursts
72system.physmem.perBankRdBursts::6 46925 # Per bank write bursts
73system.physmem.perBankRdBursts::7 49452 # Per bank write bursts
74system.physmem.perBankRdBursts::8 44750 # Per bank write bursts
75system.physmem.perBankRdBursts::9 73148 # Per bank write bursts
76system.physmem.perBankRdBursts::10 48402 # Per bank write bursts
77system.physmem.perBankRdBursts::11 51457 # Per bank write bursts
78system.physmem.perBankRdBursts::12 45806 # Per bank write bursts
79system.physmem.perBankRdBursts::13 48601 # Per bank write bursts
80system.physmem.perBankRdBursts::14 42635 # Per bank write bursts
81system.physmem.perBankRdBursts::15 46504 # Per bank write bursts
82system.physmem.perBankWrBursts::0 106325 # Per bank write bursts
83system.physmem.perBankWrBursts::1 106592 # Per bank write bursts
84system.physmem.perBankWrBursts::2 106293 # Per bank write bursts
85system.physmem.perBankWrBursts::3 105191 # Per bank write bursts
86system.physmem.perBankWrBursts::4 106687 # Per bank write bursts
87system.physmem.perBankWrBursts::5 109171 # Per bank write bursts
88system.physmem.perBankWrBursts::6 103226 # Per bank write bursts
89system.physmem.perBankWrBursts::7 105745 # Per bank write bursts
90system.physmem.perBankWrBursts::8 103090 # Per bank write bursts
91system.physmem.perBankWrBursts::9 109771 # Per bank write bursts
92system.physmem.perBankWrBursts::10 107182 # Per bank write bursts
93system.physmem.perBankWrBursts::11 108709 # Per bank write bursts
94system.physmem.perBankWrBursts::12 102154 # Per bank write bursts
95system.physmem.perBankWrBursts::13 106063 # Per bank write bursts
96system.physmem.perBankWrBursts::14 100653 # Per bank write bursts
97system.physmem.perBankWrBursts::15 102060 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 63 # Number of times write queue was full causing retry
100system.physmem.totGap 51320619748500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 0 # Read request sizes (log2)
104system.physmem.readPktSize::3 13 # Read request sizes (log2)
105system.physmem.readPktSize::4 21272 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 770677 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 1 # Write request sizes (log2)
111system.physmem.writePktSize::3 2572 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 1693958 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 524690 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 218670 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 33629 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 11094 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 426 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 389 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 320 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 222 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 146 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 143 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 129 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see

--- 9 unchanged lines hidden (view full) ---

154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 35109 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 66510 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 80685 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 95220 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 95674 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 107871 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 105650 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 115186 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 109604 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 123316 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 110089 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 98131 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 89808 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 90193 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 76388 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 75197 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 74826 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 71320 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 5232 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 4640 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 4117 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 3862 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 3608 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 3366 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 3244 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 3200 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 3037 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 2834 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 2761 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 2689 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 2623 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 2429 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 2386 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 2389 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 2289 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 2041 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 1971 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 1782 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 1608 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 1297 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 1152 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 990 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 767 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 434 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 324 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 202 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 140 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 151 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 519847 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 305.358892 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 172.693203 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 342.458813 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 210597 40.51% 40.51% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 125304 24.10% 64.62% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 44434 8.55% 73.16% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 23828 4.58% 77.75% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 16026 3.08% 80.83% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 10297 1.98% 82.81% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 8038 1.55% 84.36% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 7736 1.49% 85.84% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 73587 14.16% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 519847 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 65806 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 12.026092 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 69.420005 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-511 65801 99.99% 99.99% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::total 65806 # Reads before turning the bus around for writes
233system.physmem.wrPerTurnAround::samples 65806 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::mean 25.665015 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::gmean 22.295407 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::stdev 18.784846 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::16-23 44130 67.06% 67.06% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-31 6726 10.22% 77.28% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-39 8110 12.32% 89.61% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::40-47 2086 3.17% 92.78% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::48-55 1158 1.76% 94.54% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::56-63 536 0.81% 95.35% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::64-71 588 0.89% 96.24% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::72-79 530 0.81% 97.05% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::80-87 479 0.73% 97.78% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::88-95 220 0.33% 98.11% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::96-103 383 0.58% 98.69% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::104-111 149 0.23% 98.92% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::112-119 276 0.42% 99.34% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::120-127 79 0.12% 99.46% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::128-135 128 0.19% 99.65% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::136-143 41 0.06% 99.72% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::144-151 35 0.05% 99.77% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::152-159 20 0.03% 99.80% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::160-167 44 0.07% 99.87% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::168-175 20 0.03% 99.90% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::176-183 23 0.03% 99.93% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::184-191 10 0.02% 99.95% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::192-199 5 0.01% 99.95% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::200-207 3 0.00% 99.96% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::208-215 10 0.02% 99.97% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::216-223 3 0.00% 99.98% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::232-239 1 0.00% 99.99% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::248-255 1 0.00% 99.99% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::256-263 5 0.01% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::total 65806 # Writes before turning the bus around for reads
270system.physmem.totQLat 15790981009 # Total ticks spent queuing
271system.physmem.totMemAccLat 30629824759 # Total ticks spent from burst creation until serviced by the DRAM
272system.physmem.totBusLat 3957025000 # Total ticks spent in databus transfers
273system.physmem.avgQLat 19953.10 # Average queueing delay per DRAM burst
274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
275system.physmem.avgMemAccLat 38703.10 # Average memory access latency per DRAM burst
276system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s
277system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s
278system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s
279system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s
280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
281system.physmem.busUtil 0.02 # Data bus utilization in percentage
282system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
284system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
285system.physmem.avgWrQLen 25.05 # Average write queue length when enqueuing
286system.physmem.readRowHits 603831 # Number of row buffer hits during reads
287system.physmem.writeRowHits 1356638 # Number of row buffer hits during writes
288system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads
289system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes
290system.physmem.avgGap 20623172.24 # Average gap between requests
291system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined
292system.physmem.memoryStateTime::IDLE 49368372569000 # Time in different power states
293system.physmem.memoryStateTime::REF 1713708100000 # Time in different power states
294system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
295system.physmem.memoryStateTime::ACT 238539960500 # Time in different power states
296system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
297system.physmem.actEnergy::0 1984348800 # Energy for activate commands per rank (pJ)
298system.physmem.actEnergy::1 1945694520 # Energy for activate commands per rank (pJ)
299system.physmem.preEnergy::0 1082730000 # Energy for precharge commands per rank (pJ)
300system.physmem.preEnergy::1 1061638875 # Energy for precharge commands per rank (pJ)
301system.physmem.readEnergy::0 3042748800 # Energy for read commands per rank (pJ)
302system.physmem.readEnergy::1 3130163400 # Energy for read commands per rank (pJ)
303system.physmem.writeEnergy::0 5503010400 # Energy for write commands per rank (pJ)
304system.physmem.writeEnergy::1 5441139360 # Energy for write commands per rank (pJ)
305system.physmem.refreshEnergy::0 3352013043600 # Energy for refresh commands per rank (pJ)
306system.physmem.refreshEnergy::1 3352013043600 # Energy for refresh commands per rank (pJ)
307system.physmem.actBackEnergy::0 1228384903950 # Energy for active background per rank (pJ)
308system.physmem.actBackEnergy::1 1226638074825 # Energy for active background per rank (pJ)
309system.physmem.preBackEnergy::0 29714838054000 # Energy for precharge background per rank (pJ)
310system.physmem.preBackEnergy::1 29716370360250 # Energy for precharge background per rank (pJ)
311system.physmem.totalEnergy::0 34306848839550 # Total energy per rank (pJ)
312system.physmem.totalEnergy::1 34306600114830 # Total energy per rank (pJ)
313system.physmem.averagePower::0 668.480867 # Core power per rank (mW)
314system.physmem.averagePower::1 668.476020 # Core power per rank (mW)
315system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
316system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
317system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
318system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
319system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
320system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
321system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
322system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
323system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
324system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
325system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
326system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
327system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
328system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
329system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
330system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
331system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
332system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
333system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
334system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
335system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
336system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
337system.cpu.branchPred.lookups 226428976 # Number of BP lookups
338system.cpu.branchPred.condPredicted 151471445 # Number of conditional branches predicted
339system.cpu.branchPred.condIncorrect 12246087 # Number of conditional branches incorrect
340system.cpu.branchPred.BTBLookups 159886473 # Number of BTB lookups
341system.cpu.branchPred.BTBHits 104578062 # Number of BTB hits
342system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
343system.cpu.branchPred.BTBHitPct 65.407698 # BTB Hit Percentage
344system.cpu.branchPred.usedRAS 31061917 # Number of times the RAS was used to get a target.
345system.cpu.branchPred.RASInCorrect 345275 # Number of incorrect RAS predictions.
346system.cpu_clk_domain.clock 500 # Clock period in ticks
347system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
348system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
349system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
350system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
351system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
352system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
353system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
354system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

362system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
363system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
364system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
365system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
366system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
367system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
368system.cpu.dtb.inst_hits 0 # ITB inst hits
369system.cpu.dtb.inst_misses 0 # ITB inst misses
370system.cpu.dtb.read_hits 171196432 # DTB read hits
371system.cpu.dtb.read_misses 671544 # DTB read misses
372system.cpu.dtb.write_hits 149025904 # DTB write hits
373system.cpu.dtb.write_misses 258759 # DTB write misses
374system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
375system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
376system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID
377system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
378system.cpu.dtb.flush_entries 72979 # Number of entries that have been flushed from TLB
379system.cpu.dtb.align_faults 104 # Number of TLB faults due to alignment restrictions
380system.cpu.dtb.prefetch_faults 10362 # Number of TLB faults due to prefetch
381system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
382system.cpu.dtb.perms_faults 68614 # Number of TLB faults due to permissions restrictions
383system.cpu.dtb.read_accesses 171867976 # DTB read accesses
384system.cpu.dtb.write_accesses 149284663 # DTB write accesses
385system.cpu.dtb.inst_accesses 0 # ITB inst accesses
386system.cpu.dtb.hits 320222336 # DTB hits
387system.cpu.dtb.misses 930303 # DTB misses
388system.cpu.dtb.accesses 321152639 # DTB accesses
389system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
390system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
391system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
392system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
393system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
394system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
395system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
396system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

402system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
403system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
404system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
405system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
406system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
407system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
408system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
409system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
410system.cpu.itb.inst_hits 360051885 # ITB inst hits
411system.cpu.itb.inst_misses 161655 # ITB inst misses
412system.cpu.itb.read_hits 0 # DTB read hits
413system.cpu.itb.read_misses 0 # DTB read misses
414system.cpu.itb.write_hits 0 # DTB write hits
415system.cpu.itb.write_misses 0 # DTB write misses
416system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
417system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
418system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID
419system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
420system.cpu.itb.flush_entries 53701 # Number of entries that have been flushed from TLB
421system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
422system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
423system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
424system.cpu.itb.perms_faults 372863 # Number of TLB faults due to permissions restrictions
425system.cpu.itb.read_accesses 0 # DTB read accesses
426system.cpu.itb.write_accesses 0 # DTB write accesses
427system.cpu.itb.inst_accesses 360213540 # ITB inst accesses
428system.cpu.itb.hits 360051885 # DTB hits
429system.cpu.itb.misses 161655 # DTB misses
430system.cpu.itb.accesses 360213540 # DTB accesses
431system.cpu.numCycles 1576874693 # number of cpu cycles simulated
432system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
433system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
434system.cpu.fetch.icacheStallCycles 648679854 # Number of cycles fetch is stalled on an Icache miss
435system.cpu.fetch.Insts 1010290403 # Number of instructions fetch has processed
436system.cpu.fetch.Branches 226428976 # Number of branches that fetch encountered
437system.cpu.fetch.predictedBranches 135639979 # Number of branches that fetch has predicted taken
438system.cpu.fetch.Cycles 852655064 # Number of cycles fetch has run and was not squashing or blocked
439system.cpu.fetch.SquashCycles 26160452 # Number of cycles fetch has spent squashing
440system.cpu.fetch.TlbCycles 3389644 # Number of cycles fetch has spent waiting for tlb
441system.cpu.fetch.MiscStallCycles 26807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
442system.cpu.fetch.PendingTrapStallCycles 9240220 # Number of stall cycles due to pending traps
443system.cpu.fetch.PendingQuiesceStallCycles 1021673 # Number of stall cycles due to pending quiesce instructions
444system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR
445system.cpu.fetch.CacheLines 359662567 # Number of cache lines fetched
446system.cpu.fetch.IcacheSquashes 6136086 # Number of outstanding Icache misses that were squashed
447system.cpu.fetch.ItlbSquashes 47510 # Number of outstanding ITLB misses that were squashed
448system.cpu.fetch.rateDist::samples 1528093850 # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::mean 0.774691 # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::stdev 1.161324 # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::0 965958627 63.21% 63.21% # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::1 215893777 14.13% 77.34% # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::2 70817340 4.63% 81.98% # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::3 275424106 18.02% 100.00% # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
458system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
459system.cpu.fetch.rateDist::total 1528093850 # Number of instructions fetched each cycle (Total)
460system.cpu.fetch.branchRate 0.143594 # Number of branch fetches per cycle
461system.cpu.fetch.rate 0.640692 # Number of inst fetches per cycle
462system.cpu.decode.IdleCycles 527180052 # Number of cycles decode is idle
463system.cpu.decode.BlockedCycles 504302107 # Number of cycles decode is blocked
464system.cpu.decode.RunCycles 436284853 # Number of cycles decode is running
465system.cpu.decode.UnblockCycles 51059674 # Number of cycles decode is unblocking
466system.cpu.decode.SquashCycles 9267164 # Number of cycles decode is squashing
467system.cpu.decode.BranchResolved 33905862 # Number of times decode resolved a branch
468system.cpu.decode.BranchMispred 3872221 # Number of times decode detected a branch misprediction
469system.cpu.decode.DecodedInsts 1095429909 # Number of instructions handled by decode
470system.cpu.decode.SquashedInsts 29099398 # Number of squashed instructions handled by decode
471system.cpu.rename.SquashCycles 9267164 # Number of cycles rename is squashing
472system.cpu.rename.IdleCycles 572442291 # Number of cycles rename is idle
473system.cpu.rename.BlockCycles 46180186 # Number of cycles rename is blocking
474system.cpu.rename.serializeStallCycles 363186865 # count of cycles rename stalled for serializing inst
475system.cpu.rename.RunCycles 441948285 # Number of cycles rename is running
476system.cpu.rename.UnblockCycles 95069059 # Number of cycles rename is unblocking
477system.cpu.rename.RenamedInsts 1075584704 # Number of instructions processed by rename
478system.cpu.rename.SquashedInsts 6788495 # Number of squashed instructions processed by rename
479system.cpu.rename.ROBFullEvents 4945824 # Number of times rename has blocked due to ROB full
480system.cpu.rename.IQFullEvents 318864 # Number of times rename has blocked due to IQ full
481system.cpu.rename.LQFullEvents 589123 # Number of times rename has blocked due to LQ full
482system.cpu.rename.SQFullEvents 42956715 # Number of times rename has blocked due to SQ full
483system.cpu.rename.FullRegisterEvents 21763 # Number of times there has been no free registers
484system.cpu.rename.RenamedOperands 1023437611 # Number of destination operands rename has renamed
485system.cpu.rename.RenameLookups 1659121727 # Number of register rename lookups that rename has made
486system.cpu.rename.int_rename_lookups 1272319582 # Number of integer rename lookups
487system.cpu.rename.fp_rename_lookups 1685396 # Number of floating rename lookups
488system.cpu.rename.CommittedMaps 957674620 # Number of HB maps that are committed
489system.cpu.rename.UndoneMaps 65762988 # Number of HB maps that are undone due to squashing
490system.cpu.rename.serializingInsts 27435128 # count of serializing insts renamed
491system.cpu.rename.tempSerializingInsts 23745394 # count of temporary serializing insts renamed
492system.cpu.rename.skidInsts 104747763 # count of insts added to the skid buffer
493system.cpu.memDep0.insertedLoads 175168030 # Number of loads inserted to the mem dependence unit.
494system.cpu.memDep0.insertedStores 152601618 # Number of stores inserted to the mem dependence unit.
495system.cpu.memDep0.conflictingLoads 9963388 # Number of conflicting loads.
496system.cpu.memDep0.conflictingStores 9061948 # Number of conflicting stores.
497system.cpu.iq.iqInstsAdded 1040022976 # Number of instructions added to the IQ (excludes non-spec)
498system.cpu.iq.iqNonSpecInstsAdded 27737741 # Number of non-speculative instructions added to the IQ
499system.cpu.iq.iqInstsIssued 1056135120 # Number of instructions issued
500system.cpu.iq.iqSquashedInstsIssued 3300763 # Number of squashed instructions issued
501system.cpu.iq.iqSquashedInstsExamined 53598061 # Number of squashed instructions iterated over during squash; mainly for profiling
502system.cpu.iq.iqSquashedOperandsExamined 33623556 # Number of squashed operands that are examined and possibly removed from graph
503system.cpu.iq.iqSquashedNonSpecRemoved 314928 # Number of squashed non-spec instructions that were removed
504system.cpu.iq.issued_per_cycle::samples 1528093850 # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::mean 0.691145 # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::stdev 0.927830 # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::0 873977548 57.19% 57.19% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::1 338098484 22.13% 79.32% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::2 236626258 15.49% 94.80% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::3 72801252 4.76% 99.57% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::4 6571176 0.43% 100.00% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::5 19132 0.00% 100.00% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
517system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
518system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
519system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
520system.cpu.iq.issued_per_cycle::total 1528093850 # Number of insts issued each cycle
521system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
522system.cpu.iq.fu_full::IntAlu 58371154 35.14% 35.14% # attempts to use FU when none available
523system.cpu.iq.fu_full::IntMult 100885 0.06% 35.20% # attempts to use FU when none available
524system.cpu.iq.fu_full::IntDiv 26756 0.02% 35.21% # attempts to use FU when none available
525system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available
528system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available
529system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available
530system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available
547system.cpu.iq.fu_full::SimdFloatMisc 767 0.00% 35.22% # attempts to use FU when none available
548system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.22% # attempts to use FU when none available
549system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.22% # attempts to use FU when none available
550system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.22% # attempts to use FU when none available
551system.cpu.iq.fu_full::MemRead 44544414 26.81% 62.03% # attempts to use FU when none available
552system.cpu.iq.fu_full::MemWrite 63075062 37.97% 100.00% # attempts to use FU when none available
553system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
554system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
555system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued
556system.cpu.iq.FU_type_0::IntAlu 727332382 68.87% 68.87% # Type of FU issued
557system.cpu.iq.FU_type_0::IntMult 2546997 0.24% 69.11% # Type of FU issued
558system.cpu.iq.FU_type_0::IntDiv 123061 0.01% 69.12% # Type of FU issued
559system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 69.12% # Type of FU issued
560system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
561system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
562system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
563system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
564system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
565system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
566system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
567system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
568system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
579system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
580system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
581system.cpu.iq.FU_type_0::SimdFloatMisc 120668 0.01% 69.13% # Type of FU issued
582system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
583system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
584system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
585system.cpu.iq.FU_type_0::MemRead 175096796 16.58% 85.71% # Type of FU issued
586system.cpu.iq.FU_type_0::MemWrite 150915164 14.29% 100.00% # Type of FU issued
587system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
588system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
589system.cpu.iq.FU_type_0::total 1056135120 # Type of FU issued
590system.cpu.iq.rate 0.669765 # Inst issue rate
591system.cpu.iq.fu_busy_cnt 166119038 # FU busy when requested
592system.cpu.iq.fu_busy_rate 0.157290 # FU busy rate (busy events/executed inst)
593system.cpu.iq.int_inst_queue_reads 3807304115 # Number of integer instruction queue reads
594system.cpu.iq.int_inst_queue_writes 1120557954 # Number of integer instruction queue writes
595system.cpu.iq.int_inst_queue_wakeup_accesses 1038099529 # Number of integer instruction queue wakeup accesses
596system.cpu.iq.fp_inst_queue_reads 2479775 # Number of floating instruction queue reads
597system.cpu.iq.fp_inst_queue_writes 941816 # Number of floating instruction queue writes
598system.cpu.iq.fp_inst_queue_wakeup_accesses 907592 # Number of floating instruction queue wakeup accesses
599system.cpu.iq.int_alu_accesses 1220693938 # Number of integer alu accesses
600system.cpu.iq.fp_alu_accesses 1560218 # Number of floating point alu accesses
601system.cpu.iew.lsq.thread0.forwLoads 4348848 # Number of loads that had data forwarded from stores
602system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
603system.cpu.iew.lsq.thread0.squashedLoads 13855252 # Number of loads squashed
604system.cpu.iew.lsq.thread0.ignoredResponses 14404 # Number of memory responses ignored because the instruction is squashed
605system.cpu.iew.lsq.thread0.memOrderViolation 142361 # Number of memory ordering violations
606system.cpu.iew.lsq.thread0.squashedStores 6337064 # Number of stores squashed
607system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
608system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
609system.cpu.iew.lsq.thread0.rescheduledLoads 2552747 # Number of loads that were rescheduled
610system.cpu.iew.lsq.thread0.cacheBlocked 1859122 # Number of times an access to memory failed due to the cache being blocked
611system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
612system.cpu.iew.iewSquashCycles 9267164 # Number of cycles IEW is squashing
613system.cpu.iew.iewBlockCycles 6379535 # Number of cycles IEW is blocking
614system.cpu.iew.iewUnblockCycles 3965873 # Number of cycles IEW is unblocking
615system.cpu.iew.iewDispatchedInsts 1067985048 # Number of instructions dispatched to IQ
616system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
617system.cpu.iew.iewDispLoadInsts 175168030 # Number of dispatched load instructions
618system.cpu.iew.iewDispStoreInsts 152601618 # Number of dispatched store instructions
619system.cpu.iew.iewDispNonSpecInsts 23314125 # Number of dispatched non-speculative instructions
620system.cpu.iew.iewIQFullEvents 62024 # Number of times the IQ has become full, causing a stall
621system.cpu.iew.iewLSQFullEvents 3832996 # Number of times the LSQ has become full, causing a stall
622system.cpu.iew.memOrderViolationEvents 142361 # Number of memory order violations
623system.cpu.iew.predictedTakenIncorrect 3691152 # Number of branches that were predicted taken incorrectly
624system.cpu.iew.predictedNotTakenIncorrect 5135953 # Number of branches that were predicted not taken incorrectly
625system.cpu.iew.branchMispredicts 8827105 # Number of branch mispredicts detected at execute
626system.cpu.iew.iewExecutedInsts 1044930592 # Number of executed instructions
627system.cpu.iew.iewExecLoadInsts 171186057 # Number of load instructions executed
628system.cpu.iew.iewExecSquashedInsts 10287379 # Number of squashed instructions skipped in execute
629system.cpu.iew.exec_swp 0 # number of swp insts executed
630system.cpu.iew.exec_nop 224331 # number of nop insts executed
631system.cpu.iew.exec_refs 320208959 # number of memory reference insts executed
632system.cpu.iew.exec_branches 198322451 # Number of branches executed
633system.cpu.iew.exec_stores 149022902 # Number of stores executed
634system.cpu.iew.exec_rate 0.662659 # Inst execution rate
635system.cpu.iew.wb_sent 1039793819 # cumulative count of insts sent to commit
636system.cpu.iew.wb_count 1039007121 # cumulative count of insts written-back
637system.cpu.iew.wb_producers 442154878 # num instructions producing a value
638system.cpu.iew.wb_consumers 715627882 # num instructions consuming a value
639system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
640system.cpu.iew.wb_rate 0.658903 # insts written-back per cycle
641system.cpu.iew.wb_fanout 0.617856 # average fanout of values written-back
642system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
643system.cpu.commit.commitSquashedInsts 51471265 # The number of squashed insts skipped by commit
644system.cpu.commit.commitNonSpecStalls 27422813 # The number of times commit has been forced to stall to communicate backwards
645system.cpu.commit.branchMispredicts 8433025 # The number of times a branch was mispredicted
646system.cpu.commit.committed_per_cycle::samples 1516084212 # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::mean 0.664299 # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::stdev 1.291990 # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::0 998537580 65.86% 65.86% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::1 291350566 19.22% 85.08% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::2 121957393 8.04% 93.12% # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::3 36696853 2.42% 95.54% # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::4 28610485 1.89% 97.43% # Number of insts commited each cycle
655system.cpu.commit.committed_per_cycle::5 14255849 0.94% 98.37% # Number of insts commited each cycle
656system.cpu.commit.committed_per_cycle::6 8557612 0.56% 98.94% # Number of insts commited each cycle
657system.cpu.commit.committed_per_cycle::7 4232636 0.28% 99.22% # Number of insts commited each cycle
658system.cpu.commit.committed_per_cycle::8 11885238 0.78% 100.00% # Number of insts commited each cycle
659system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
660system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
661system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
662system.cpu.commit.committed_per_cycle::total 1516084212 # Number of insts commited each cycle
663system.cpu.commit.committedInsts 857117694 # Number of instructions committed
664system.cpu.commit.committedOps 1007133124 # Number of ops (including micro ops) committed
665system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
666system.cpu.commit.refs 307577331 # Number of memory references committed
667system.cpu.commit.loads 161312777 # Number of loads committed
668system.cpu.commit.membars 7014752 # Number of memory barriers committed
669system.cpu.commit.branches 191334741 # Number of branches committed
670system.cpu.commit.fp_insts 896026 # Number of committed floating point instructions.
671system.cpu.commit.int_insts 925144388 # Number of committed integer instructions.
672system.cpu.commit.function_calls 25493443 # Number of function calls committed.
673system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
674system.cpu.commit.op_class_0::IntAlu 697181314 69.22% 69.22% # Class of committed instruction
675system.cpu.commit.op_class_0::IntMult 2164633 0.21% 69.44% # Class of committed instruction
676system.cpu.commit.op_class_0::IntDiv 98281 0.01% 69.45% # Class of committed instruction
677system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
678system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
679system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
680system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
681system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
682system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
683system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
684system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
685system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
686system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
687system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
688system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
689system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
690system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
691system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
692system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
693system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
694system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
695system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
696system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
697system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
698system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
699system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction
700system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
701system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
702system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
703system.cpu.commit.op_class_0::MemRead 161312777 16.02% 85.48% # Class of committed instruction
704system.cpu.commit.op_class_0::MemWrite 146264554 14.52% 100.00% # Class of committed instruction
705system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
706system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
707system.cpu.commit.op_class_0::total 1007133124 # Class of committed instruction
708system.cpu.commit.bw_lim_events 11885238 # number cycles where commit BW limit reached
709system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
710system.cpu.rob.rob_reads 2555181565 # The number of ROB reads
711system.cpu.rob.rob_writes 2129123637 # The number of ROB writes
712system.cpu.timesIdled 8137810 # Number of times that the entire CPU went into an idle state and unscheduled itself
713system.cpu.idleCycles 48780843 # Total number of cycles that the CPU has spent unscheduled due to idling
714system.cpu.quiesceCycles 101064367400 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
715system.cpu.committedInsts 857117694 # Number of Instructions Simulated
716system.cpu.committedOps 1007133124 # Number of Ops (including micro ops) Simulated
717system.cpu.cpi 1.839741 # CPI: Cycles Per Instruction
718system.cpu.cpi_total 1.839741 # CPI: Total CPI of All Threads
719system.cpu.ipc 0.543555 # IPC: Instructions Per Cycle
720system.cpu.ipc_total 0.543555 # IPC: Total IPC of All Threads
721system.cpu.int_regfile_reads 1237020079 # number of integer regfile reads
722system.cpu.int_regfile_writes 738429626 # number of integer regfile writes
723system.cpu.fp_regfile_reads 1457787 # number of floating regfile reads
724system.cpu.fp_regfile_writes 782552 # number of floating regfile writes
725system.cpu.cc_regfile_reads 228125574 # number of cc regfile reads
726system.cpu.cc_regfile_writes 228731881 # number of cc regfile writes
727system.cpu.misc_regfile_reads 5247037954 # number of misc regfile reads
728system.cpu.misc_regfile_writes 27486572 # number of misc regfile writes
729system.cpu.dcache.tags.replacements 9822538 # number of replacements
730system.cpu.dcache.tags.tagsinuse 511.985265 # Cycle average of tags in use
731system.cpu.dcache.tags.total_refs 286045243 # Total number of references to valid blocks.
732system.cpu.dcache.tags.sampled_refs 9823050 # Sample count of references to valid blocks.
733system.cpu.dcache.tags.avg_refs 29.119799 # Average number of references to valid blocks.
734system.cpu.dcache.tags.warmup_cycle 1485814250 # Cycle when the warmup percentage was hit.
735system.cpu.dcache.tags.occ_blocks::cpu.data 511.985265 # Average occupied blocks per requestor
736system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy
737system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy
738system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
739system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
740system.cpu.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
741system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id
742system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
743system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
744system.cpu.dcache.tags.tag_accesses 1249214859 # Number of tag accesses
745system.cpu.dcache.tags.data_accesses 1249214859 # Number of data accesses
746system.cpu.dcache.ReadReq_hits::cpu.data 148712432 # number of ReadReq hits
747system.cpu.dcache.ReadReq_hits::total 148712432 # number of ReadReq hits
748system.cpu.dcache.WriteReq_hits::cpu.data 129479125 # number of WriteReq hits
749system.cpu.dcache.WriteReq_hits::total 129479125 # number of WriteReq hits
750system.cpu.dcache.SoftPFReq_hits::cpu.data 381594 # number of SoftPFReq hits
751system.cpu.dcache.SoftPFReq_hits::total 381594 # number of SoftPFReq hits
752system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324870 # number of WriteInvalidateReq hits
753system.cpu.dcache.WriteInvalidateReq_hits::total 324870 # number of WriteInvalidateReq hits
754system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352883 # number of LoadLockedReq hits
755system.cpu.dcache.LoadLockedReq_hits::total 3352883 # number of LoadLockedReq hits
756system.cpu.dcache.StoreCondReq_hits::cpu.data 3750315 # number of StoreCondReq hits
757system.cpu.dcache.StoreCondReq_hits::total 3750315 # number of StoreCondReq hits
758system.cpu.dcache.demand_hits::cpu.data 278191557 # number of demand (read+write) hits
759system.cpu.dcache.demand_hits::total 278191557 # number of demand (read+write) hits
760system.cpu.dcache.overall_hits::cpu.data 278573151 # number of overall hits
761system.cpu.dcache.overall_hits::total 278573151 # number of overall hits
762system.cpu.dcache.ReadReq_misses::cpu.data 9502058 # number of ReadReq misses
763system.cpu.dcache.ReadReq_misses::total 9502058 # number of ReadReq misses
764system.cpu.dcache.WriteReq_misses::cpu.data 11465174 # number of WriteReq misses
765system.cpu.dcache.WriteReq_misses::total 11465174 # number of WriteReq misses
766system.cpu.dcache.SoftPFReq_misses::cpu.data 1197022 # number of SoftPFReq misses
767system.cpu.dcache.SoftPFReq_misses::total 1197022 # number of SoftPFReq misses
768system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233022 # number of WriteInvalidateReq misses
769system.cpu.dcache.WriteInvalidateReq_misses::total 1233022 # number of WriteInvalidateReq misses
770system.cpu.dcache.LoadLockedReq_misses::cpu.data 449448 # number of LoadLockedReq misses
771system.cpu.dcache.LoadLockedReq_misses::total 449448 # number of LoadLockedReq misses
772system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
773system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
774system.cpu.dcache.demand_misses::cpu.data 20967232 # number of demand (read+write) misses
775system.cpu.dcache.demand_misses::total 20967232 # number of demand (read+write) misses
776system.cpu.dcache.overall_misses::cpu.data 22164254 # number of overall misses
777system.cpu.dcache.overall_misses::total 22164254 # number of overall misses
778system.cpu.dcache.ReadReq_miss_latency::cpu.data 140935225401 # number of ReadReq miss cycles
779system.cpu.dcache.ReadReq_miss_latency::total 140935225401 # number of ReadReq miss cycles
780system.cpu.dcache.WriteReq_miss_latency::cpu.data 322991667568 # number of WriteReq miss cycles
781system.cpu.dcache.WriteReq_miss_latency::total 322991667568 # number of WriteReq miss cycles
782system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38675981880 # number of WriteInvalidateReq miss cycles
783system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38675981880 # number of WriteInvalidateReq miss cycles
784system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6315194753 # number of LoadLockedReq miss cycles
785system.cpu.dcache.LoadLockedReq_miss_latency::total 6315194753 # number of LoadLockedReq miss cycles
786system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles
787system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles
788system.cpu.dcache.demand_miss_latency::cpu.data 463926892969 # number of demand (read+write) miss cycles
789system.cpu.dcache.demand_miss_latency::total 463926892969 # number of demand (read+write) miss cycles
790system.cpu.dcache.overall_miss_latency::cpu.data 463926892969 # number of overall miss cycles
791system.cpu.dcache.overall_miss_latency::total 463926892969 # number of overall miss cycles
792system.cpu.dcache.ReadReq_accesses::cpu.data 158214490 # number of ReadReq accesses(hits+misses)
793system.cpu.dcache.ReadReq_accesses::total 158214490 # number of ReadReq accesses(hits+misses)
794system.cpu.dcache.WriteReq_accesses::cpu.data 140944299 # number of WriteReq accesses(hits+misses)
795system.cpu.dcache.WriteReq_accesses::total 140944299 # number of WriteReq accesses(hits+misses)
796system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578616 # number of SoftPFReq accesses(hits+misses)
797system.cpu.dcache.SoftPFReq_accesses::total 1578616 # number of SoftPFReq accesses(hits+misses)
798system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557892 # number of WriteInvalidateReq accesses(hits+misses)
799system.cpu.dcache.WriteInvalidateReq_accesses::total 1557892 # number of WriteInvalidateReq accesses(hits+misses)
800system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3802331 # number of LoadLockedReq accesses(hits+misses)
801system.cpu.dcache.LoadLockedReq_accesses::total 3802331 # number of LoadLockedReq accesses(hits+misses)
802system.cpu.dcache.StoreCondReq_accesses::cpu.data 3750320 # number of StoreCondReq accesses(hits+misses)
803system.cpu.dcache.StoreCondReq_accesses::total 3750320 # number of StoreCondReq accesses(hits+misses)
804system.cpu.dcache.demand_accesses::cpu.data 299158789 # number of demand (read+write) accesses
805system.cpu.dcache.demand_accesses::total 299158789 # number of demand (read+write) accesses
806system.cpu.dcache.overall_accesses::cpu.data 300737405 # number of overall (read+write) accesses
807system.cpu.dcache.overall_accesses::total 300737405 # number of overall (read+write) accesses
808system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060058 # miss rate for ReadReq accesses
809system.cpu.dcache.ReadReq_miss_rate::total 0.060058 # miss rate for ReadReq accesses
810system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081345 # miss rate for WriteReq accesses
811system.cpu.dcache.WriteReq_miss_rate::total 0.081345 # miss rate for WriteReq accesses
812system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758273 # miss rate for SoftPFReq accesses
813system.cpu.dcache.SoftPFReq_miss_rate::total 0.758273 # miss rate for SoftPFReq accesses
814system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791468 # miss rate for WriteInvalidateReq accesses
815system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791468 # miss rate for WriteInvalidateReq accesses
816system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118203 # miss rate for LoadLockedReq accesses
817system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118203 # miss rate for LoadLockedReq accesses
818system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
819system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
820system.cpu.dcache.demand_miss_rate::cpu.data 0.070087 # miss rate for demand accesses
821system.cpu.dcache.demand_miss_rate::total 0.070087 # miss rate for demand accesses
822system.cpu.dcache.overall_miss_rate::cpu.data 0.073700 # miss rate for overall accesses
823system.cpu.dcache.overall_miss_rate::total 0.073700 # miss rate for overall accesses
824system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14832.073789 # average ReadReq miss latency
825system.cpu.dcache.ReadReq_avg_miss_latency::total 14832.073789 # average ReadReq miss latency
826system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28171.545200 # average WriteReq miss latency
827system.cpu.dcache.WriteReq_avg_miss_latency::total 28171.545200 # average WriteReq miss latency
828system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31366.822230 # average WriteInvalidateReq miss latency
829system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31366.822230 # average WriteInvalidateReq miss latency
830system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14051.002014 # average LoadLockedReq miss latency
831system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14051.002014 # average LoadLockedReq miss latency
832system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency
833system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency
834system.cpu.dcache.demand_avg_miss_latency::cpu.data 22126.282237 # average overall miss latency
835system.cpu.dcache.demand_avg_miss_latency::total 22126.282237 # average overall miss latency
836system.cpu.dcache.overall_avg_miss_latency::cpu.data 20931.310973 # average overall miss latency
837system.cpu.dcache.overall_avg_miss_latency::total 20931.310973 # average overall miss latency
838system.cpu.dcache.blocked_cycles::no_mshrs 21466802 # number of cycles access was blocked
839system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
840system.cpu.dcache.blocked::no_mshrs 1401851 # number of cycles access was blocked
841system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
842system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.313184 # average number of cycles each access was blocked
843system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
844system.cpu.dcache.fast_writes 0 # number of fast writes performed
845system.cpu.dcache.cache_copies 0 # number of cache copies performed
846system.cpu.dcache.writebacks::writebacks 7593763 # number of writebacks
847system.cpu.dcache.writebacks::total 7593763 # number of writebacks
848system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4321399 # number of ReadReq MSHR hits
849system.cpu.dcache.ReadReq_mshr_hits::total 4321399 # number of ReadReq MSHR hits
850system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9425025 # number of WriteReq MSHR hits
851system.cpu.dcache.WriteReq_mshr_hits::total 9425025 # number of WriteReq MSHR hits
852system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7055 # number of WriteInvalidateReq MSHR hits
853system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7055 # number of WriteInvalidateReq MSHR hits
854system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219414 # number of LoadLockedReq MSHR hits
855system.cpu.dcache.LoadLockedReq_mshr_hits::total 219414 # number of LoadLockedReq MSHR hits
856system.cpu.dcache.demand_mshr_hits::cpu.data 13746424 # number of demand (read+write) MSHR hits
857system.cpu.dcache.demand_mshr_hits::total 13746424 # number of demand (read+write) MSHR hits
858system.cpu.dcache.overall_mshr_hits::cpu.data 13746424 # number of overall MSHR hits
859system.cpu.dcache.overall_mshr_hits::total 13746424 # number of overall MSHR hits
860system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5180659 # number of ReadReq MSHR misses
861system.cpu.dcache.ReadReq_mshr_misses::total 5180659 # number of ReadReq MSHR misses
862system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2040149 # number of WriteReq MSHR misses
863system.cpu.dcache.WriteReq_mshr_misses::total 2040149 # number of WriteReq MSHR misses
864system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190231 # number of SoftPFReq MSHR misses
865system.cpu.dcache.SoftPFReq_mshr_misses::total 1190231 # number of SoftPFReq MSHR misses
866system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1225967 # number of WriteInvalidateReq MSHR misses
867system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1225967 # number of WriteInvalidateReq MSHR misses
868system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230034 # number of LoadLockedReq MSHR misses
869system.cpu.dcache.LoadLockedReq_mshr_misses::total 230034 # number of LoadLockedReq MSHR misses
870system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
871system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
872system.cpu.dcache.demand_mshr_misses::cpu.data 7220808 # number of demand (read+write) MSHR misses
873system.cpu.dcache.demand_mshr_misses::total 7220808 # number of demand (read+write) MSHR misses
874system.cpu.dcache.overall_mshr_misses::cpu.data 8411039 # number of overall MSHR misses
875system.cpu.dcache.overall_mshr_misses::total 8411039 # number of overall MSHR misses
876system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70208074682 # number of ReadReq MSHR miss cycles
877system.cpu.dcache.ReadReq_mshr_miss_latency::total 70208074682 # number of ReadReq MSHR miss cycles
878system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53752252884 # number of WriteReq MSHR miss cycles
879system.cpu.dcache.WriteReq_mshr_miss_latency::total 53752252884 # number of WriteReq MSHR miss cycles
880system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18853760746 # number of SoftPFReq MSHR miss cycles
881system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18853760746 # number of SoftPFReq MSHR miss cycles
882system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35977742828 # number of WriteInvalidateReq MSHR miss cycles
883system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35977742828 # number of WriteInvalidateReq MSHR miss cycles
884system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2809792248 # number of LoadLockedReq MSHR miss cycles
885system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2809792248 # number of LoadLockedReq MSHR miss cycles
886system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles
887system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles
888system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123960327566 # number of demand (read+write) MSHR miss cycles
889system.cpu.dcache.demand_mshr_miss_latency::total 123960327566 # number of demand (read+write) MSHR miss cycles
890system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142814088312 # number of overall MSHR miss cycles
891system.cpu.dcache.overall_mshr_miss_latency::total 142814088312 # number of overall MSHR miss cycles
892system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729213249 # number of ReadReq MSHR uncacheable cycles
893system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729213249 # number of ReadReq MSHR uncacheable cycles
894system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587099983 # number of WriteReq MSHR uncacheable cycles
895system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587099983 # number of WriteReq MSHR uncacheable cycles
896system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316313232 # number of overall MSHR uncacheable cycles
897system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316313232 # number of overall MSHR uncacheable cycles
898system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032745 # mshr miss rate for ReadReq accesses
899system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032745 # mshr miss rate for ReadReq accesses
900system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014475 # mshr miss rate for WriteReq accesses
901system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014475 # mshr miss rate for WriteReq accesses
902system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753971 # mshr miss rate for SoftPFReq accesses
903system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753971 # mshr miss rate for SoftPFReq accesses
904system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786940 # mshr miss rate for WriteInvalidateReq accesses
905system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786940 # mshr miss rate for WriteInvalidateReq accesses
906system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060498 # mshr miss rate for LoadLockedReq accesses
907system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060498 # mshr miss rate for LoadLockedReq accesses
908system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
909system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
910system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024137 # mshr miss rate for demand accesses
911system.cpu.dcache.demand_mshr_miss_rate::total 0.024137 # mshr miss rate for demand accesses
912system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027968 # mshr miss rate for overall accesses
913system.cpu.dcache.overall_mshr_miss_rate::total 0.027968 # mshr miss rate for overall accesses
914system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13551.958290 # average ReadReq mshr miss latency
915system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13551.958290 # average ReadReq mshr miss latency
916system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26347.219190 # average WriteReq mshr miss latency
917system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26347.219190 # average WriteReq mshr miss latency
918system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15840.421520 # average SoftPFReq mshr miss latency
919system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15840.421520 # average SoftPFReq mshr miss latency
920system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29346.420277 # average WriteInvalidateReq mshr miss latency
921system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29346.420277 # average WriteInvalidateReq mshr miss latency
922system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12214.682386 # average LoadLockedReq mshr miss latency
923system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12214.682386 # average LoadLockedReq mshr miss latency
924system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency
925system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency
926system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17167.099245 # average overall mshr miss latency
927system.cpu.dcache.demand_avg_mshr_miss_latency::total 17167.099245 # average overall mshr miss latency
928system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16979.363467 # average overall mshr miss latency
929system.cpu.dcache.overall_avg_mshr_miss_latency::total 16979.363467 # average overall mshr miss latency
930system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
931system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
932system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
933system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
934system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
935system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
936system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
937system.cpu.icache.tags.replacements 15082585 # number of replacements
938system.cpu.icache.tags.tagsinuse 511.954216 # Cycle average of tags in use
939system.cpu.icache.tags.total_refs 343840613 # Total number of references to valid blocks.
940system.cpu.icache.tags.sampled_refs 15083097 # Sample count of references to valid blocks.
941system.cpu.icache.tags.avg_refs 22.796420 # Average number of references to valid blocks.
942system.cpu.icache.tags.warmup_cycle 14175734000 # Cycle when the warmup percentage was hit.
943system.cpu.icache.tags.occ_blocks::cpu.inst 511.954216 # Average occupied blocks per requestor
944system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy
945system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy
946system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
947system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
948system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
949system.cpu.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id
950system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
951system.cpu.icache.tags.tag_accesses 374724467 # Number of tag accesses
952system.cpu.icache.tags.data_accesses 374724467 # Number of data accesses
953system.cpu.icache.ReadReq_hits::cpu.inst 343840613 # number of ReadReq hits
954system.cpu.icache.ReadReq_hits::total 343840613 # number of ReadReq hits
955system.cpu.icache.demand_hits::cpu.inst 343840613 # number of demand (read+write) hits
956system.cpu.icache.demand_hits::total 343840613 # number of demand (read+write) hits
957system.cpu.icache.overall_hits::cpu.inst 343840613 # number of overall hits
958system.cpu.icache.overall_hits::total 343840613 # number of overall hits
959system.cpu.icache.ReadReq_misses::cpu.inst 15800655 # number of ReadReq misses
960system.cpu.icache.ReadReq_misses::total 15800655 # number of ReadReq misses
961system.cpu.icache.demand_misses::cpu.inst 15800655 # number of demand (read+write) misses
962system.cpu.icache.demand_misses::total 15800655 # number of demand (read+write) misses
963system.cpu.icache.overall_misses::cpu.inst 15800655 # number of overall misses
964system.cpu.icache.overall_misses::total 15800655 # number of overall misses
965system.cpu.icache.ReadReq_miss_latency::cpu.inst 208208668907 # number of ReadReq miss cycles
966system.cpu.icache.ReadReq_miss_latency::total 208208668907 # number of ReadReq miss cycles
967system.cpu.icache.demand_miss_latency::cpu.inst 208208668907 # number of demand (read+write) miss cycles
968system.cpu.icache.demand_miss_latency::total 208208668907 # number of demand (read+write) miss cycles
969system.cpu.icache.overall_miss_latency::cpu.inst 208208668907 # number of overall miss cycles
970system.cpu.icache.overall_miss_latency::total 208208668907 # number of overall miss cycles
971system.cpu.icache.ReadReq_accesses::cpu.inst 359641268 # number of ReadReq accesses(hits+misses)
972system.cpu.icache.ReadReq_accesses::total 359641268 # number of ReadReq accesses(hits+misses)
973system.cpu.icache.demand_accesses::cpu.inst 359641268 # number of demand (read+write) accesses
974system.cpu.icache.demand_accesses::total 359641268 # number of demand (read+write) accesses
975system.cpu.icache.overall_accesses::cpu.inst 359641268 # number of overall (read+write) accesses
976system.cpu.icache.overall_accesses::total 359641268 # number of overall (read+write) accesses
977system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043934 # miss rate for ReadReq accesses
978system.cpu.icache.ReadReq_miss_rate::total 0.043934 # miss rate for ReadReq accesses
979system.cpu.icache.demand_miss_rate::cpu.inst 0.043934 # miss rate for demand accesses
980system.cpu.icache.demand_miss_rate::total 0.043934 # miss rate for demand accesses
981system.cpu.icache.overall_miss_rate::cpu.inst 0.043934 # miss rate for overall accesses
982system.cpu.icache.overall_miss_rate::total 0.043934 # miss rate for overall accesses
983system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13177.217584 # average ReadReq miss latency
984system.cpu.icache.ReadReq_avg_miss_latency::total 13177.217584 # average ReadReq miss latency
985system.cpu.icache.demand_avg_miss_latency::cpu.inst 13177.217584 # average overall miss latency
986system.cpu.icache.demand_avg_miss_latency::total 13177.217584 # average overall miss latency
987system.cpu.icache.overall_avg_miss_latency::cpu.inst 13177.217584 # average overall miss latency
988system.cpu.icache.overall_avg_miss_latency::total 13177.217584 # average overall miss latency
989system.cpu.icache.blocked_cycles::no_mshrs 10839 # number of cycles access was blocked
990system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
991system.cpu.icache.blocked::no_mshrs 972 # number of cycles access was blocked
992system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
993system.cpu.icache.avg_blocked_cycles::no_mshrs 11.151235 # average number of cycles each access was blocked
994system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
995system.cpu.icache.fast_writes 0 # number of fast writes performed
996system.cpu.icache.cache_copies 0 # number of cache copies performed
997system.cpu.icache.ReadReq_mshr_hits::cpu.inst 717456 # number of ReadReq MSHR hits
998system.cpu.icache.ReadReq_mshr_hits::total 717456 # number of ReadReq MSHR hits
999system.cpu.icache.demand_mshr_hits::cpu.inst 717456 # number of demand (read+write) MSHR hits
1000system.cpu.icache.demand_mshr_hits::total 717456 # number of demand (read+write) MSHR hits
1001system.cpu.icache.overall_mshr_hits::cpu.inst 717456 # number of overall MSHR hits
1002system.cpu.icache.overall_mshr_hits::total 717456 # number of overall MSHR hits
1003system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15083199 # number of ReadReq MSHR misses
1004system.cpu.icache.ReadReq_mshr_misses::total 15083199 # number of ReadReq MSHR misses
1005system.cpu.icache.demand_mshr_misses::cpu.inst 15083199 # number of demand (read+write) MSHR misses
1006system.cpu.icache.demand_mshr_misses::total 15083199 # number of demand (read+write) MSHR misses
1007system.cpu.icache.overall_mshr_misses::cpu.inst 15083199 # number of overall MSHR misses
1008system.cpu.icache.overall_mshr_misses::total 15083199 # number of overall MSHR misses
1009system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171815580989 # number of ReadReq MSHR miss cycles
1010system.cpu.icache.ReadReq_mshr_miss_latency::total 171815580989 # number of ReadReq MSHR miss cycles
1011system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171815580989 # number of demand (read+write) MSHR miss cycles
1012system.cpu.icache.demand_mshr_miss_latency::total 171815580989 # number of demand (read+write) MSHR miss cycles
1013system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171815580989 # number of overall MSHR miss cycles
1014system.cpu.icache.overall_mshr_miss_latency::total 171815580989 # number of overall MSHR miss cycles
1015system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1413030250 # number of ReadReq MSHR uncacheable cycles
1016system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1413030250 # number of ReadReq MSHR uncacheable cycles
1017system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1413030250 # number of overall MSHR uncacheable cycles
1018system.cpu.icache.overall_mshr_uncacheable_latency::total 1413030250 # number of overall MSHR uncacheable cycles
1019system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041940 # mshr miss rate for ReadReq accesses
1020system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041940 # mshr miss rate for ReadReq accesses
1021system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041940 # mshr miss rate for demand accesses
1022system.cpu.icache.demand_mshr_miss_rate::total 0.041940 # mshr miss rate for demand accesses
1023system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041940 # mshr miss rate for overall accesses
1024system.cpu.icache.overall_mshr_miss_rate::total 0.041940 # mshr miss rate for overall accesses
1025system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11391.189693 # average ReadReq mshr miss latency
1026system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11391.189693 # average ReadReq mshr miss latency
1027system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11391.189693 # average overall mshr miss latency
1028system.cpu.icache.demand_avg_mshr_miss_latency::total 11391.189693 # average overall mshr miss latency
1029system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11391.189693 # average overall mshr miss latency
1030system.cpu.icache.overall_avg_mshr_miss_latency::total 11391.189693 # average overall mshr miss latency
1031system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1032system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1033system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1034system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1035system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1036system.cpu.l2cache.tags.replacements 1167362 # number of replacements
1037system.cpu.l2cache.tags.tagsinuse 65297.852107 # Cycle average of tags in use
1038system.cpu.l2cache.tags.total_refs 29065274 # Total number of references to valid blocks.
1039system.cpu.l2cache.tags.sampled_refs 1230222 # Sample count of references to valid blocks.
1040system.cpu.l2cache.tags.avg_refs 23.626040 # Average number of references to valid blocks.
1041system.cpu.l2cache.tags.warmup_cycle 2430272000 # Cycle when the warmup percentage was hit.
1042system.cpu.l2cache.tags.occ_blocks::writebacks 37323.559826 # Average occupied blocks per requestor
1043system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 320.853018 # Average occupied blocks per requestor
1044system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 490.286692 # Average occupied blocks per requestor
1045system.cpu.l2cache.tags.occ_blocks::cpu.inst 7518.567341 # Average occupied blocks per requestor
1046system.cpu.l2cache.tags.occ_blocks::cpu.data 19644.585230 # Average occupied blocks per requestor
1047system.cpu.l2cache.tags.occ_percent::writebacks 0.569512 # Average percentage of cache occupancy
1048system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004896 # Average percentage of cache occupancy
1049system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007481 # Average percentage of cache occupancy
1050system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114724 # Average percentage of cache occupancy
1051system.cpu.l2cache.tags.occ_percent::cpu.data 0.299753 # Average percentage of cache occupancy
1052system.cpu.l2cache.tags.occ_percent::total 0.996366 # Average percentage of cache occupancy
1053system.cpu.l2cache.tags.occ_task_id_blocks::1023 285 # Occupied blocks per task id
1054system.cpu.l2cache.tags.occ_task_id_blocks::1024 62575 # Occupied blocks per task id
1055system.cpu.l2cache.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id
1056system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
1057system.cpu.l2cache.tags.age_task_id_blocks_1024::1 565 # Occupied blocks per task id
1058system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2655 # Occupied blocks per task id
1059system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5044 # Occupied blocks per task id
1060system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54243 # Occupied blocks per task id
1061system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004349 # Percentage of cache occupancy per task id
1062system.cpu.l2cache.tags.occ_task_id_percent::1024 0.954819 # Percentage of cache occupancy per task id
1063system.cpu.l2cache.tags.tag_accesses 273181992 # Number of tag accesses
1064system.cpu.l2cache.tags.data_accesses 273181992 # Number of data accesses
1065system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 797530 # number of ReadReq hits
1066system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297299 # number of ReadReq hits
1067system.cpu.l2cache.ReadReq_hits::cpu.inst 14998467 # number of ReadReq hits
1068system.cpu.l2cache.ReadReq_hits::cpu.data 6339712 # number of ReadReq hits
1069system.cpu.l2cache.ReadReq_hits::total 22433008 # number of ReadReq hits
1070system.cpu.l2cache.Writeback_hits::writebacks 7593763 # number of Writeback hits
1071system.cpu.l2cache.Writeback_hits::total 7593763 # number of Writeback hits
1072system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 728839 # number of WriteInvalidateReq hits
1073system.cpu.l2cache.WriteInvalidateReq_hits::total 728839 # number of WriteInvalidateReq hits
1074system.cpu.l2cache.UpgradeReq_hits::cpu.data 9472 # number of UpgradeReq hits
1075system.cpu.l2cache.UpgradeReq_hits::total 9472 # number of UpgradeReq hits
1076system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
1077system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
1078system.cpu.l2cache.ReadExReq_hits::cpu.data 1583067 # number of ReadExReq hits
1079system.cpu.l2cache.ReadExReq_hits::total 1583067 # number of ReadExReq hits
1080system.cpu.l2cache.demand_hits::cpu.dtb.walker 797530 # number of demand (read+write) hits
1081system.cpu.l2cache.demand_hits::cpu.itb.walker 297299 # number of demand (read+write) hits
1082system.cpu.l2cache.demand_hits::cpu.inst 14998467 # number of demand (read+write) hits
1083system.cpu.l2cache.demand_hits::cpu.data 7922779 # number of demand (read+write) hits
1084system.cpu.l2cache.demand_hits::total 24016075 # number of demand (read+write) hits
1085system.cpu.l2cache.overall_hits::cpu.dtb.walker 797530 # number of overall hits
1086system.cpu.l2cache.overall_hits::cpu.itb.walker 297299 # number of overall hits
1087system.cpu.l2cache.overall_hits::cpu.inst 14998467 # number of overall hits
1088system.cpu.l2cache.overall_hits::cpu.data 7922779 # number of overall hits
1089system.cpu.l2cache.overall_hits::total 24016075 # number of overall hits
1090system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3551 # number of ReadReq misses
1091system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3223 # number of ReadReq misses
1092system.cpu.l2cache.ReadReq_misses::cpu.inst 84643 # number of ReadReq misses
1093system.cpu.l2cache.ReadReq_misses::cpu.data 257522 # number of ReadReq misses
1094system.cpu.l2cache.ReadReq_misses::total 348939 # number of ReadReq misses
1095system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 497128 # number of WriteInvalidateReq misses
1096system.cpu.l2cache.WriteInvalidateReq_misses::total 497128 # number of WriteInvalidateReq misses
1097system.cpu.l2cache.UpgradeReq_misses::cpu.data 34502 # number of UpgradeReq misses
1098system.cpu.l2cache.UpgradeReq_misses::total 34502 # number of UpgradeReq misses
1099system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
1100system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
1101system.cpu.l2cache.ReadExReq_misses::cpu.data 416799 # number of ReadExReq misses
1102system.cpu.l2cache.ReadExReq_misses::total 416799 # number of ReadExReq misses
1103system.cpu.l2cache.demand_misses::cpu.dtb.walker 3551 # number of demand (read+write) misses
1104system.cpu.l2cache.demand_misses::cpu.itb.walker 3223 # number of demand (read+write) misses
1105system.cpu.l2cache.demand_misses::cpu.inst 84643 # number of demand (read+write) misses
1106system.cpu.l2cache.demand_misses::cpu.data 674321 # number of demand (read+write) misses
1107system.cpu.l2cache.demand_misses::total 765738 # number of demand (read+write) misses
1108system.cpu.l2cache.overall_misses::cpu.dtb.walker 3551 # number of overall misses
1109system.cpu.l2cache.overall_misses::cpu.itb.walker 3223 # number of overall misses
1110system.cpu.l2cache.overall_misses::cpu.inst 84643 # number of overall misses
1111system.cpu.l2cache.overall_misses::cpu.data 674321 # number of overall misses
1112system.cpu.l2cache.overall_misses::total 765738 # number of overall misses
1113system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 283709749 # number of ReadReq miss cycles
1114system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260562999 # number of ReadReq miss cycles
1115system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6536550232 # number of ReadReq miss cycles
1116system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21467939178 # number of ReadReq miss cycles
1117system.cpu.l2cache.ReadReq_miss_latency::total 28548762158 # number of ReadReq miss cycles
1118system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 3612846 # number of WriteInvalidateReq miss cycles
1119system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 3612846 # number of WriteInvalidateReq miss cycles
1120system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 412251300 # number of UpgradeReq miss cycles
1121system.cpu.l2cache.UpgradeReq_miss_latency::total 412251300 # number of UpgradeReq miss cycles
1122system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 72000 # number of SCUpgradeReq miss cycles
1123system.cpu.l2cache.SCUpgradeReq_miss_latency::total 72000 # number of SCUpgradeReq miss cycles
1124system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34736796105 # number of ReadExReq miss cycles
1125system.cpu.l2cache.ReadExReq_miss_latency::total 34736796105 # number of ReadExReq miss cycles
1126system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 283709749 # number of demand (read+write) miss cycles
1127system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260562999 # number of demand (read+write) miss cycles
1128system.cpu.l2cache.demand_miss_latency::cpu.inst 6536550232 # number of demand (read+write) miss cycles
1129system.cpu.l2cache.demand_miss_latency::cpu.data 56204735283 # number of demand (read+write) miss cycles
1130system.cpu.l2cache.demand_miss_latency::total 63285558263 # number of demand (read+write) miss cycles
1131system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 283709749 # number of overall miss cycles
1132system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260562999 # number of overall miss cycles
1133system.cpu.l2cache.overall_miss_latency::cpu.inst 6536550232 # number of overall miss cycles
1134system.cpu.l2cache.overall_miss_latency::cpu.data 56204735283 # number of overall miss cycles
1135system.cpu.l2cache.overall_miss_latency::total 63285558263 # number of overall miss cycles
1136system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 801081 # number of ReadReq accesses(hits+misses)
1137system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 300522 # number of ReadReq accesses(hits+misses)
1138system.cpu.l2cache.ReadReq_accesses::cpu.inst 15083110 # number of ReadReq accesses(hits+misses)
1139system.cpu.l2cache.ReadReq_accesses::cpu.data 6597234 # number of ReadReq accesses(hits+misses)
1140system.cpu.l2cache.ReadReq_accesses::total 22781947 # number of ReadReq accesses(hits+misses)
1141system.cpu.l2cache.Writeback_accesses::writebacks 7593763 # number of Writeback accesses(hits+misses)
1142system.cpu.l2cache.Writeback_accesses::total 7593763 # number of Writeback accesses(hits+misses)
1143system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1225967 # number of WriteInvalidateReq accesses(hits+misses)
1144system.cpu.l2cache.WriteInvalidateReq_accesses::total 1225967 # number of WriteInvalidateReq accesses(hits+misses)
1145system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43974 # number of UpgradeReq accesses(hits+misses)
1146system.cpu.l2cache.UpgradeReq_accesses::total 43974 # number of UpgradeReq accesses(hits+misses)
1147system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
1148system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
1149system.cpu.l2cache.ReadExReq_accesses::cpu.data 1999866 # number of ReadExReq accesses(hits+misses)
1150system.cpu.l2cache.ReadExReq_accesses::total 1999866 # number of ReadExReq accesses(hits+misses)
1151system.cpu.l2cache.demand_accesses::cpu.dtb.walker 801081 # number of demand (read+write) accesses
1152system.cpu.l2cache.demand_accesses::cpu.itb.walker 300522 # number of demand (read+write) accesses
1153system.cpu.l2cache.demand_accesses::cpu.inst 15083110 # number of demand (read+write) accesses
1154system.cpu.l2cache.demand_accesses::cpu.data 8597100 # number of demand (read+write) accesses
1155system.cpu.l2cache.demand_accesses::total 24781813 # number of demand (read+write) accesses
1156system.cpu.l2cache.overall_accesses::cpu.dtb.walker 801081 # number of overall (read+write) accesses
1157system.cpu.l2cache.overall_accesses::cpu.itb.walker 300522 # number of overall (read+write) accesses
1158system.cpu.l2cache.overall_accesses::cpu.inst 15083110 # number of overall (read+write) accesses
1159system.cpu.l2cache.overall_accesses::cpu.data 8597100 # number of overall (read+write) accesses
1160system.cpu.l2cache.overall_accesses::total 24781813 # number of overall (read+write) accesses
1161system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004433 # miss rate for ReadReq accesses
1162system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010725 # miss rate for ReadReq accesses
1163system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005612 # miss rate for ReadReq accesses
1164system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.039035 # miss rate for ReadReq accesses
1165system.cpu.l2cache.ReadReq_miss_rate::total 0.015316 # miss rate for ReadReq accesses
1166system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.405499 # miss rate for WriteInvalidateReq accesses
1167system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.405499 # miss rate for WriteInvalidateReq accesses
1168system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784600 # miss rate for UpgradeReq accesses
1169system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784600 # miss rate for UpgradeReq accesses
1170system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
1171system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
1172system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.208413 # miss rate for ReadExReq accesses
1173system.cpu.l2cache.ReadExReq_miss_rate::total 0.208413 # miss rate for ReadExReq accesses
1174system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004433 # miss rate for demand accesses
1175system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010725 # miss rate for demand accesses
1176system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005612 # miss rate for demand accesses
1177system.cpu.l2cache.demand_miss_rate::cpu.data 0.078436 # miss rate for demand accesses
1178system.cpu.l2cache.demand_miss_rate::total 0.030899 # miss rate for demand accesses
1179system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004433 # miss rate for overall accesses
1180system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010725 # miss rate for overall accesses
1181system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005612 # miss rate for overall accesses
1182system.cpu.l2cache.overall_miss_rate::cpu.data 0.078436 # miss rate for overall accesses
1183system.cpu.l2cache.overall_miss_rate::total 0.030899 # miss rate for overall accesses
1184system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79895.733315 # average ReadReq miss latency
1185system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80844.864722 # average ReadReq miss latency
1186system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77224.935695 # average ReadReq miss latency
1187system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83363.515265 # average ReadReq miss latency
1188system.cpu.l2cache.ReadReq_avg_miss_latency::total 81815.910970 # average ReadReq miss latency
1189system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 7.267436 # average WriteInvalidateReq miss latency
1190system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 7.267436 # average WriteInvalidateReq miss latency
1191system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11948.620370 # average UpgradeReq miss latency
1192system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11948.620370 # average UpgradeReq miss latency
1193system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 36000 # average SCUpgradeReq miss latency
1194system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 36000 # average SCUpgradeReq miss latency
1195system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83341.841283 # average ReadExReq miss latency
1196system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83341.841283 # average ReadExReq miss latency
1197system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79895.733315 # average overall miss latency
1198system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80844.864722 # average overall miss latency
1199system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77224.935695 # average overall miss latency
1200system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83350.118539 # average overall miss latency
1201system.cpu.l2cache.demand_avg_miss_latency::total 82646.490396 # average overall miss latency
1202system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79895.733315 # average overall miss latency
1203system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80844.864722 # average overall miss latency
1204system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77224.935695 # average overall miss latency
1205system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83350.118539 # average overall miss latency
1206system.cpu.l2cache.overall_avg_miss_latency::total 82646.490396 # average overall miss latency
1207system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1208system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1209system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1210system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1211system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1212system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1213system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1214system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1215system.cpu.l2cache.writebacks::writebacks 983690 # number of writebacks
1216system.cpu.l2cache.writebacks::total 983690 # number of writebacks
1217system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
1218system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits
1219system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
1220system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
1221system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
1222system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
1223system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3551 # number of ReadReq MSHR misses
1224system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3223 # number of ReadReq MSHR misses
1225system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84643 # number of ReadReq MSHR misses
1226system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 257501 # number of ReadReq MSHR misses
1227system.cpu.l2cache.ReadReq_mshr_misses::total 348918 # number of ReadReq MSHR misses
1228system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 497128 # number of WriteInvalidateReq MSHR misses
1229system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 497128 # number of WriteInvalidateReq MSHR misses
1230system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34502 # number of UpgradeReq MSHR misses
1231system.cpu.l2cache.UpgradeReq_mshr_misses::total 34502 # number of UpgradeReq MSHR misses
1232system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1233system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1234system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 416799 # number of ReadExReq MSHR misses
1235system.cpu.l2cache.ReadExReq_mshr_misses::total 416799 # number of ReadExReq MSHR misses
1236system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3551 # number of demand (read+write) MSHR misses
1237system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3223 # number of demand (read+write) MSHR misses
1238system.cpu.l2cache.demand_mshr_misses::cpu.inst 84643 # number of demand (read+write) MSHR misses
1239system.cpu.l2cache.demand_mshr_misses::cpu.data 674300 # number of demand (read+write) MSHR misses
1240system.cpu.l2cache.demand_mshr_misses::total 765717 # number of demand (read+write) MSHR misses
1241system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3551 # number of overall MSHR misses
1242system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3223 # number of overall MSHR misses
1243system.cpu.l2cache.overall_mshr_misses::cpu.inst 84643 # number of overall MSHR misses
1244system.cpu.l2cache.overall_mshr_misses::cpu.data 674300 # number of overall MSHR misses
1245system.cpu.l2cache.overall_mshr_misses::total 765717 # number of overall MSHR misses
1246system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 239359749 # number of ReadReq MSHR miss cycles
1247system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 220243499 # number of ReadReq MSHR miss cycles
1248system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5475082762 # number of ReadReq MSHR miss cycles
1249system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18259324004 # number of ReadReq MSHR miss cycles
1250system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24194010014 # number of ReadReq MSHR miss cycles
1251system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 19601424690 # number of WriteInvalidateReq MSHR miss cycles
1252system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 19601424690 # number of WriteInvalidateReq MSHR miss cycles
1253system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345545498 # number of UpgradeReq MSHR miss cycles
1254system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345545498 # number of UpgradeReq MSHR miss cycles
1255system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70001 # number of SCUpgradeReq MSHR miss cycles
1256system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles
1257system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29577738885 # number of ReadExReq MSHR miss cycles
1258system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29577738885 # number of ReadExReq MSHR miss cycles
1259system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 239359749 # number of demand (read+write) MSHR miss cycles
1260system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 220243499 # number of demand (read+write) MSHR miss cycles
1261system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5475082762 # number of demand (read+write) MSHR miss cycles
1262system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47837062889 # number of demand (read+write) MSHR miss cycles
1263system.cpu.l2cache.demand_mshr_miss_latency::total 53771748899 # number of demand (read+write) MSHR miss cycles
1264system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 239359749 # number of overall MSHR miss cycles
1265system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 220243499 # number of overall MSHR miss cycles
1266system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5475082762 # number of overall MSHR miss cycles
1267system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47837062889 # number of overall MSHR miss cycles
1268system.cpu.l2cache.overall_mshr_miss_latency::total 53771748899 # number of overall MSHR miss cycles
1269system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103982250 # number of ReadReq MSHR uncacheable cycles
1270system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289733251 # number of ReadReq MSHR uncacheable cycles
1271system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393715501 # number of ReadReq MSHR uncacheable cycles
1272system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176071500 # number of WriteReq MSHR uncacheable cycles
1273system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176071500 # number of WriteReq MSHR uncacheable cycles
1274system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103982250 # number of overall MSHR uncacheable cycles
1275system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465804751 # number of overall MSHR uncacheable cycles
1276system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569787001 # number of overall MSHR uncacheable cycles
1277system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for ReadReq accesses
1278system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for ReadReq accesses
1279system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for ReadReq accesses
1280system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.039032 # mshr miss rate for ReadReq accesses
1281system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015316 # mshr miss rate for ReadReq accesses
1282system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.405499 # mshr miss rate for WriteInvalidateReq accesses
1283system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.405499 # mshr miss rate for WriteInvalidateReq accesses
1284system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784600 # mshr miss rate for UpgradeReq accesses
1285system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784600 # mshr miss rate for UpgradeReq accesses
1286system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
1287system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
1288system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208413 # mshr miss rate for ReadExReq accesses
1289system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208413 # mshr miss rate for ReadExReq accesses
1290system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for demand accesses
1291system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for demand accesses
1292system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for demand accesses
1293system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078433 # mshr miss rate for demand accesses
1294system.cpu.l2cache.demand_mshr_miss_rate::total 0.030898 # mshr miss rate for demand accesses
1295system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004433 # mshr miss rate for overall accesses
1296system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010725 # mshr miss rate for overall accesses
1297system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005612 # mshr miss rate for overall accesses
1298system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078433 # mshr miss rate for overall accesses
1299system.cpu.l2cache.overall_mshr_miss_rate::total 0.030898 # mshr miss rate for overall accesses
1300system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average ReadReq mshr miss latency
1301system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average ReadReq mshr miss latency
1302system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64684.412911 # average ReadReq mshr miss latency
1303system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70909.720754 # average ReadReq mshr miss latency
1304system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69340.102872 # average ReadReq mshr miss latency
1305system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39429.331460 # average WriteInvalidateReq mshr miss latency
1306system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39429.331460 # average WriteInvalidateReq mshr miss latency
1307system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10015.230943 # average UpgradeReq mshr miss latency
1308system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10015.230943 # average UpgradeReq mshr miss latency
1309system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency
1310system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency
1311system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70964.035146 # average ReadExReq mshr miss latency
1312system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70964.035146 # average ReadExReq mshr miss latency
1313system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency
1314system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency
1315system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency
1316system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency
1317system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency
1318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67406.293720 # average overall mshr miss latency
1319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68334.936084 # average overall mshr miss latency
1320system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.412911 # average overall mshr miss latency
1321system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70943.293622 # average overall mshr miss latency
1322system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70224.050007 # average overall mshr miss latency
1323system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1324system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1325system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1326system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1327system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1328system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1329system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1330system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1331system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1332system.cpu.toL2Bus.trans_dist::ReadReq 23341232 # Transaction distribution
1333system.cpu.toL2Bus.trans_dist::ReadResp 23333163 # Transaction distribution
1334system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution
1335system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution
1336system.cpu.toL2Bus.trans_dist::Writeback 7593763 # Transaction distribution
1337system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332631 # Transaction distribution
1338system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1225967 # Transaction distribution
1339system.cpu.toL2Bus.trans_dist::UpgradeReq 43977 # Transaction distribution
1340system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
1341system.cpu.toL2Bus.trans_dist::UpgradeResp 43982 # Transaction distribution
1342system.cpu.toL2Bus.trans_dist::ReadExReq 1999866 # Transaction distribution
1343system.cpu.toL2Bus.trans_dist::ReadExResp 1999866 # Transaction distribution
1344system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30208899 # Packet count per connected master and slave (bytes)
1345system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27463876 # Packet count per connected master and slave (bytes)
1346system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 731462 # Packet count per connected master and slave (bytes)
1347system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1967033 # Packet count per connected master and slave (bytes)
1348system.cpu.toL2Bus.pkt_count::total 60371270 # Packet count per connected master and slave (bytes)
1349system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965659760 # Cumulative packet size per connected master and slave (bytes)
1350system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1114918084 # Cumulative packet size per connected master and slave (bytes)
1351system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2404176 # Cumulative packet size per connected master and slave (bytes)
1352system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6408648 # Cumulative packet size per connected master and slave (bytes)
1353system.cpu.toL2Bus.pkt_size::total 2089390668 # Cumulative packet size per connected master and slave (bytes)
1354system.cpu.toL2Bus.snoops 611685 # Total snoops (count)
1355system.cpu.toL2Bus.snoop_fanout::samples 34508223 # Request fanout histogram
1356system.cpu.toL2Bus.snoop_fanout::mean 5.003348 # Request fanout histogram
1357system.cpu.toL2Bus.snoop_fanout::stdev 0.057762 # Request fanout histogram
1358system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1359system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1360system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1361system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1362system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1363system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1364system.cpu.toL2Bus.snoop_fanout::5 34392703 99.67% 99.67% # Request fanout histogram
1365system.cpu.toL2Bus.snoop_fanout::6 115520 0.33% 100.00% # Request fanout histogram
1366system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1367system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1368system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1369system.cpu.toL2Bus.snoop_fanout::total 34508223 # Request fanout histogram
1370system.cpu.toL2Bus.reqLayer0.occupancy 26206492236 # Layer occupancy (ticks)
1371system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1372system.cpu.toL2Bus.snoopLayer0.occupancy 1177500 # Layer occupancy (ticks)
1373system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1374system.cpu.toL2Bus.respLayer0.occupancy 22671590732 # Layer occupancy (ticks)
1375system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1376system.cpu.toL2Bus.respLayer1.occupancy 13674088224 # Layer occupancy (ticks)
1377system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1378system.cpu.toL2Bus.respLayer2.occupancy 431886005 # Layer occupancy (ticks)
1379system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1380system.cpu.toL2Bus.respLayer3.occupancy 1166711358 # Layer occupancy (ticks)
1381system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1382system.iobus.trans_dist::ReadReq 40382 # Transaction distribution
1383system.iobus.trans_dist::ReadResp 40382 # Transaction distribution
1384system.iobus.trans_dist::WriteReq 136733 # Transaction distribution
1385system.iobus.trans_dist::WriteResp 30069 # Transaction distribution
1386system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
1387system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
1388system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1389system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1390system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1391system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1392system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1393system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1394system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1395system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1396system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1397system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1398system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1399system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1400system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1401system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1402system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
1403system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes)
1404system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes)
1405system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1406system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1407system.iobus.pkt_count::total 354230 # Packet count per connected master and slave (bytes)
1408system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
1409system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1410system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1411system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1412system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1413system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1414system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1415system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1416system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1417system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1418system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1419system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1420system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1421system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1422system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1423system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
1424system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes)
1425system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes)
1426system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1427system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1428system.iobus.pkt_size::total 7492678 # Cumulative packet size per connected master and slave (bytes)
1429system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
1430system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1431system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1432system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1433system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1434system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1435system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1436system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1437system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1438system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1439system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1440system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1441system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1442system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1443system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1444system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1445system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1446system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1447system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1448system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1449system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1450system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1451system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1452system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1453system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1454system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1455system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1456system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1457system.iobus.reqLayer27.occupancy 1042360658 # Layer occupancy (ticks)
1458system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1459system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1460system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1461system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
1462system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1463system.iobus.respLayer3.occupancy 179004169 # Layer occupancy (ticks)
1464system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1465system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
1466system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1467system.iocache.tags.replacements 115462 # number of replacements
1468system.iocache.tags.tagsinuse 10.424613 # Cycle average of tags in use
1469system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1470system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks.
1471system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1472system.iocache.tags.warmup_cycle 13092189065000 # Cycle when the warmup percentage was hit.
1473system.iocache.tags.occ_blocks::realview.ethernet 3.544618 # Average occupied blocks per requestor
1474system.iocache.tags.occ_blocks::realview.ide 6.879995 # Average occupied blocks per requestor
1475system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy
1476system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy
1477system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy
1478system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1479system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1480system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1481system.iocache.tags.tag_accesses 1039677 # Number of tag accesses
1482system.iocache.tags.data_accesses 1039677 # Number of data accesses
1483system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
1484system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses
1485system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses
1486system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
1487system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
1488system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
1489system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
1490system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
1491system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses
1492system.iocache.demand_misses::total 8856 # number of demand (read+write) misses
1493system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
1494system.iocache.overall_misses::realview.ide 8816 # number of overall misses
1495system.iocache.overall_misses::total 8856 # number of overall misses
1496system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles
1497system.iocache.ReadReq_miss_latency::realview.ide 1927411613 # number of ReadReq miss cycles
1498system.iocache.ReadReq_miss_latency::total 1932938613 # number of ReadReq miss cycles
1499system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
1500system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
1501system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28910124876 # number of WriteInvalidateReq miss cycles
1502system.iocache.WriteInvalidateReq_miss_latency::total 28910124876 # number of WriteInvalidateReq miss cycles
1503system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles
1504system.iocache.demand_miss_latency::realview.ide 1927411613 # number of demand (read+write) miss cycles
1505system.iocache.demand_miss_latency::total 1933277613 # number of demand (read+write) miss cycles
1506system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles
1507system.iocache.overall_miss_latency::realview.ide 1927411613 # number of overall miss cycles
1508system.iocache.overall_miss_latency::total 1933277613 # number of overall miss cycles
1509system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
1510system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses)
1511system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses)
1512system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
1513system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
1514system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
1515system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
1516system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
1517system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses
1518system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses
1519system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
1520system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses
1521system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses
1522system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
1523system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
1524system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1525system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
1526system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
1527system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
1528system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1529system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
1530system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
1531system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1532system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
1533system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
1534system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1535system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency
1536system.iocache.ReadReq_avg_miss_latency::realview.ide 218626.544124 # average ReadReq miss latency
1537system.iocache.ReadReq_avg_miss_latency::total 218337.130125 # average ReadReq miss latency
1538system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
1539system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
1540system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271039.196692 # average WriteInvalidateReq miss latency
1541system.iocache.WriteInvalidateReq_avg_miss_latency::total 271039.196692 # average WriteInvalidateReq miss latency
1542system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency
1543system.iocache.demand_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency
1544system.iocache.demand_avg_miss_latency::total 218301.446816 # average overall miss latency
1545system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency
1546system.iocache.overall_avg_miss_latency::realview.ide 218626.544124 # average overall miss latency
1547system.iocache.overall_avg_miss_latency::total 218301.446816 # average overall miss latency
1548system.iocache.blocked_cycles::no_mshrs 226675 # number of cycles access was blocked
1549system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1550system.iocache.blocked::no_mshrs 27646 # number of cycles access was blocked
1551system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1552system.iocache.avg_blocked_cycles::no_mshrs 8.199197 # average number of cycles each access was blocked
1553system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1554system.iocache.fast_writes 0 # number of fast writes performed
1555system.iocache.cache_copies 0 # number of cache copies performed
1556system.iocache.writebacks::writebacks 106631 # number of writebacks
1557system.iocache.writebacks::total 106631 # number of writebacks
1558system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
1559system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses
1560system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses
1561system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
1562system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
1563system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
1564system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
1565system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
1566system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses
1567system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses
1568system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
1569system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses
1570system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses
1571system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles
1572system.iocache.ReadReq_mshr_miss_latency::realview.ide 1468863623 # number of ReadReq MSHR miss cycles
1573system.iocache.ReadReq_mshr_miss_latency::total 1472466623 # number of ReadReq MSHR miss cycles
1574system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
1575system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
1576system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23363269204 # number of WriteInvalidateReq MSHR miss cycles
1577system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23363269204 # number of WriteInvalidateReq MSHR miss cycles
1578system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles
1579system.iocache.demand_mshr_miss_latency::realview.ide 1468863623 # number of demand (read+write) MSHR miss cycles
1580system.iocache.demand_mshr_miss_latency::total 1472649623 # number of demand (read+write) MSHR miss cycles
1581system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles
1582system.iocache.overall_mshr_miss_latency::realview.ide 1468863623 # number of overall MSHR miss cycles
1583system.iocache.overall_mshr_miss_latency::total 1472649623 # number of overall MSHR miss cycles
1584system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
1585system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
1586system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1587system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
1588system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
1589system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1590system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1591system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
1592system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
1593system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1594system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
1595system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
1596system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1597system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency
1598system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166613.387364 # average ReadReq mshr miss latency
1599system.iocache.ReadReq_avg_mshr_miss_latency::total 166324.028352 # average ReadReq mshr miss latency
1600system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
1601system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
1602system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219036.124691 # average WriteInvalidateReq mshr miss latency
1603system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219036.124691 # average WriteInvalidateReq mshr miss latency
1604system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency
1605system.iocache.demand_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency
1606system.iocache.demand_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency
1607system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency
1608system.iocache.overall_avg_mshr_miss_latency::realview.ide 166613.387364 # average overall mshr miss latency
1609system.iocache.overall_avg_mshr_miss_latency::total 166288.349481 # average overall mshr miss latency
1610system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1611system.membus.trans_dist::ReadReq 412825 # Transaction distribution
1612system.membus.trans_dist::ReadResp 412825 # Transaction distribution
1613system.membus.trans_dist::WriteReq 33858 # Transaction distribution
1614system.membus.trans_dist::WriteResp 33858 # Transaction distribution
1615system.membus.trans_dist::Writeback 1090321 # Transaction distribution
1616system.membus.trans_dist::WriteInvalidateReq 603637 # Transaction distribution
1617system.membus.trans_dist::WriteInvalidateResp 603637 # Transaction distribution
1618system.membus.trans_dist::UpgradeReq 35296 # Transaction distribution
1619system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
1620system.membus.trans_dist::UpgradeResp 35298 # Transaction distribution
1621system.membus.trans_dist::ReadExReq 416163 # Transaction distribution
1622system.membus.trans_dist::ReadExResp 416163 # Transaction distribution
1623system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
1624system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
1625system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
1626system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3625442 # Packet count per connected master and slave (bytes)
1627system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3755550 # Packet count per connected master and slave (bytes)
1628system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
1629system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
1630system.membus.pkt_count::total 4090619 # Packet count per connected master and slave (bytes)
1631system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
1632system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
1633system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
1634system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144046540 # Cumulative packet size per connected master and slave (bytes)
1635system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144217012 # Cumulative packet size per connected master and slave (bytes)
1636system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14051136 # Cumulative packet size per connected master and slave (bytes)
1637system.membus.pkt_size_system.iocache.mem_side::total 14051136 # Cumulative packet size per connected master and slave (bytes)
1638system.membus.pkt_size::total 158268148 # Cumulative packet size per connected master and slave (bytes)
1639system.membus.snoops 3264 # Total snoops (count)
1640system.membus.snoop_fanout::samples 2503253 # Request fanout histogram
1641system.membus.snoop_fanout::mean 1 # Request fanout histogram
1642system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1643system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1644system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1645system.membus.snoop_fanout::1 2503253 100.00% 100.00% # Request fanout histogram
1646system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1647system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1648system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1649system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1650system.membus.snoop_fanout::total 2503253 # Request fanout histogram
1651system.membus.reqLayer0.occupancy 109702500 # Layer occupancy (ticks)
1652system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1653system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks)
1654system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
1655system.membus.reqLayer2.occupancy 5437999 # Layer occupancy (ticks)
1656system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
1657system.membus.reqLayer5.occupancy 16337638979 # Layer occupancy (ticks)
1658system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
1659system.membus.respLayer2.occupancy 7836649146 # Layer occupancy (ticks)
1660system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1661system.membus.respLayer3.occupancy 186565831 # Layer occupancy (ticks)
1662system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
1663system.realview.ethernet.txBytes 966 # Bytes Transmitted
1664system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
1665system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
1666system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
1667system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
1668system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1669system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1670system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1671system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1672system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
1673system.realview.ethernet.totPackets 3 # Total Packets
1674system.realview.ethernet.totBytes 966 # Total Bytes
1675system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
1676system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
1677system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
1678system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1679system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
1680system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1681system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1682system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
1683system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1684system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1685system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
1686system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1687system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1688system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
1689system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1690system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1691system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
1692system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1693system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1694system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
1695system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1696system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1697system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
1698system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1699system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1700system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
1701system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1702system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
1703system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
1704system.realview.ethernet.droppedPackets 0 # number of packets dropped
1705system.cpu.kern.inst.arm 0 # number of arm instructions executed
1706system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed
1707
1708---------- End Simulation Statistics ----------