| config.ini (10798:74e3c7359393) | config.ini (10900:ac6617bf9967) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 14atags_addr=134217728 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 14atags_addr=134217728 |
| 15boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 | 15boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 |
| 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 | 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 |
| 17boot_release_addr=65528 | |
| 18cache_line_size=64 19clk_domain=system.clk_domain | 17cache_line_size=64 18clk_domain=system.clk_domain |
| 20dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb | 19dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb |
| 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24flags_addr=469827632 25gic_cpu_addr=738205696 | 20early_kernel_symbols=false 21enable_context_switch_stats_dump=false 22eventq_index=0 23flags_addr=469827632 24gic_cpu_addr=738205696 |
| 26have_generic_timer=false | |
| 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 | 25have_large_asid_64=false 26have_lpae=false 27have_security=false 28have_virtualization=false 29highest_el_is_64=false 30init_param=0 |
| 33kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 | 31kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 |
| 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43num_work_ids=16 44panic_on_oops=true 45panic_on_panic=true 46phys_addr_range_64=40 | 32kernel_addr_check=true 33load_addr_mask=268435455 34load_offset=2147483648 35machine_type=VExpress_EMM64 36mem_mode=timing 37mem_ranges=2147483648:2415919103 38memories=system.physmem system.realview.nvmem system.realview.vram 39mmap_using_noreserve=false 40multi_proc=true 41num_work_ids=16 42panic_on_oops=true 43panic_on_panic=true 44phys_addr_range_64=40 |
| 47readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh | 45readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh |
| 48reset_addr_64=0 49symbolfile= 50work_begin_ckpt_count=0 51work_begin_cpu_id_exit=-1 52work_begin_exit_count=0 53work_cpus_ckpt_count=0 54work_end_ckpt_count=0 55work_end_exit_count=0 --- 26 unchanged lines hidden (view full) --- 82eventq_index=0 83image_file= 84read_only=false 85table_size=65536 86 87[system.cf0.image.child] 88type=RawDiskImage 89eventq_index=0 | 46reset_addr_64=0 47symbolfile= 48work_begin_ckpt_count=0 49work_begin_cpu_id_exit=-1 50work_begin_exit_count=0 51work_cpus_ckpt_count=0 52work_end_ckpt_count=0 53work_end_exit_count=0 --- 26 unchanged lines hidden (view full) --- 80eventq_index=0 81image_file= 82read_only=false 83table_size=65536 84 85[system.cf0.image.child] 86type=RawDiskImage 87eventq_index=0 |
| 90image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img | 88image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img |
| 91read_only=true 92 93[system.clk_domain] 94type=SrcClockDomain 95clock=1000 96domain_id=-1 97eventq_index=0 98init_perf_level=0 --- 108 unchanged lines hidden (view full) --- 207children=tags 208addr_ranges=0:18446744073709551615 209assoc=4 210clk_domain=system.cpu_clk_domain 211demand_mshr_reserve=1 212eventq_index=0 213forward_snoops=true 214hit_latency=2 | 89read_only=true 90 91[system.clk_domain] 92type=SrcClockDomain 93clock=1000 94domain_id=-1 95eventq_index=0 96init_perf_level=0 --- 108 unchanged lines hidden (view full) --- 205children=tags 206addr_ranges=0:18446744073709551615 207assoc=4 208clk_domain=system.cpu_clk_domain 209demand_mshr_reserve=1 210eventq_index=0 211forward_snoops=true 212hit_latency=2 |
| 215is_top_level=true | 213is_read_only=false |
| 216max_miss_count=0 217mshrs=4 218prefetch_on_access=false 219prefetcher=Null 220response_latency=2 221sequential_access=false 222size=32768 223system=system 224tags=system.cpu.dcache.tags 225tgts_per_mshr=20 | 214max_miss_count=0 215mshrs=4 216prefetch_on_access=false 217prefetcher=Null 218response_latency=2 219sequential_access=false 220size=32768 221system=system 222tags=system.cpu.dcache.tags 223tgts_per_mshr=20 |
| 226two_queue=false | |
| 227write_buffers=8 228cpu_side=system.cpu.dcache_port 229mem_side=system.cpu.toL2Bus.slave[1] 230 231[system.cpu.dcache.tags] 232type=LRU 233assoc=4 234block_size=64 --- 55 unchanged lines hidden (view full) --- 290children=opList 291count=2 292eventq_index=0 293opList=system.cpu.fuPool.FUList0.opList 294 295[system.cpu.fuPool.FUList0.opList] 296type=OpDesc 297eventq_index=0 | 224write_buffers=8 225cpu_side=system.cpu.dcache_port 226mem_side=system.cpu.toL2Bus.slave[1] 227 228[system.cpu.dcache.tags] 229type=LRU 230assoc=4 231block_size=64 --- 55 unchanged lines hidden (view full) --- 287children=opList 288count=2 289eventq_index=0 290opList=system.cpu.fuPool.FUList0.opList 291 292[system.cpu.fuPool.FUList0.opList] 293type=OpDesc 294eventq_index=0 |
| 298issueLat=1 | |
| 299opClass=IntAlu 300opLat=1 | 295opClass=IntAlu 296opLat=1 |
| 297pipelined=true |
|
| 301 302[system.cpu.fuPool.FUList1] 303type=FUDesc 304children=opList0 opList1 opList2 305count=1 306eventq_index=0 307opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 308 309[system.cpu.fuPool.FUList1.opList0] 310type=OpDesc 311eventq_index=0 | 298 299[system.cpu.fuPool.FUList1] 300type=FUDesc 301children=opList0 opList1 opList2 302count=1 303eventq_index=0 304opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 305 306[system.cpu.fuPool.FUList1.opList0] 307type=OpDesc 308eventq_index=0 |
| 312issueLat=1 | |
| 313opClass=IntMult 314opLat=3 | 309opClass=IntMult 310opLat=3 |
| 311pipelined=true |
|
| 315 316[system.cpu.fuPool.FUList1.opList1] 317type=OpDesc 318eventq_index=0 | 312 313[system.cpu.fuPool.FUList1.opList1] 314type=OpDesc 315eventq_index=0 |
| 319issueLat=12 | |
| 320opClass=IntDiv 321opLat=12 | 316opClass=IntDiv 317opLat=12 |
| 318pipelined=false |
|
| 322 323[system.cpu.fuPool.FUList1.opList2] 324type=OpDesc 325eventq_index=0 | 319 320[system.cpu.fuPool.FUList1.opList2] 321type=OpDesc 322eventq_index=0 |
| 326issueLat=1 | |
| 327opClass=IprAccess 328opLat=3 | 323opClass=IprAccess 324opLat=3 |
| 325pipelined=true |
|
| 329 330[system.cpu.fuPool.FUList2] 331type=FUDesc 332children=opList 333count=1 334eventq_index=0 335opList=system.cpu.fuPool.FUList2.opList 336 337[system.cpu.fuPool.FUList2.opList] 338type=OpDesc 339eventq_index=0 | 326 327[system.cpu.fuPool.FUList2] 328type=FUDesc 329children=opList 330count=1 331eventq_index=0 332opList=system.cpu.fuPool.FUList2.opList 333 334[system.cpu.fuPool.FUList2.opList] 335type=OpDesc 336eventq_index=0 |
| 340issueLat=1 | |
| 341opClass=MemRead 342opLat=2 | 337opClass=MemRead 338opLat=2 |
| 339pipelined=true |
|
| 343 344[system.cpu.fuPool.FUList3] 345type=FUDesc 346children=opList 347count=1 348eventq_index=0 349opList=system.cpu.fuPool.FUList3.opList 350 351[system.cpu.fuPool.FUList3.opList] 352type=OpDesc 353eventq_index=0 | 340 341[system.cpu.fuPool.FUList3] 342type=FUDesc 343children=opList 344count=1 345eventq_index=0 346opList=system.cpu.fuPool.FUList3.opList 347 348[system.cpu.fuPool.FUList3.opList] 349type=OpDesc 350eventq_index=0 |
| 354issueLat=1 | |
| 355opClass=MemWrite 356opLat=2 | 351opClass=MemWrite 352opLat=2 |
| 353pipelined=true |
|
| 357 358[system.cpu.fuPool.FUList4] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 361count=2 362eventq_index=0 363opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 364 365[system.cpu.fuPool.FUList4.opList00] 366type=OpDesc 367eventq_index=0 | 354 355[system.cpu.fuPool.FUList4] 356type=FUDesc 357children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 358count=2 359eventq_index=0 360opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 361 362[system.cpu.fuPool.FUList4.opList00] 363type=OpDesc 364eventq_index=0 |
| 368issueLat=1 | |
| 369opClass=SimdAdd 370opLat=4 | 365opClass=SimdAdd 366opLat=4 |
| 367pipelined=true |
|
| 371 372[system.cpu.fuPool.FUList4.opList01] 373type=OpDesc 374eventq_index=0 | 368 369[system.cpu.fuPool.FUList4.opList01] 370type=OpDesc 371eventq_index=0 |
| 375issueLat=1 | |
| 376opClass=SimdAddAcc 377opLat=4 | 372opClass=SimdAddAcc 373opLat=4 |
| 374pipelined=true |
|
| 378 379[system.cpu.fuPool.FUList4.opList02] 380type=OpDesc 381eventq_index=0 | 375 376[system.cpu.fuPool.FUList4.opList02] 377type=OpDesc 378eventq_index=0 |
| 382issueLat=1 | |
| 383opClass=SimdAlu 384opLat=4 | 379opClass=SimdAlu 380opLat=4 |
| 381pipelined=true |
|
| 385 386[system.cpu.fuPool.FUList4.opList03] 387type=OpDesc 388eventq_index=0 | 382 383[system.cpu.fuPool.FUList4.opList03] 384type=OpDesc 385eventq_index=0 |
| 389issueLat=1 | |
| 390opClass=SimdCmp 391opLat=4 | 386opClass=SimdCmp 387opLat=4 |
| 388pipelined=true |
|
| 392 393[system.cpu.fuPool.FUList4.opList04] 394type=OpDesc 395eventq_index=0 | 389 390[system.cpu.fuPool.FUList4.opList04] 391type=OpDesc 392eventq_index=0 |
| 396issueLat=1 | |
| 397opClass=SimdCvt 398opLat=3 | 393opClass=SimdCvt 394opLat=3 |
| 395pipelined=true |
|
| 399 400[system.cpu.fuPool.FUList4.opList05] 401type=OpDesc 402eventq_index=0 | 396 397[system.cpu.fuPool.FUList4.opList05] 398type=OpDesc 399eventq_index=0 |
| 403issueLat=1 | |
| 404opClass=SimdMisc 405opLat=3 | 400opClass=SimdMisc 401opLat=3 |
| 402pipelined=true |
|
| 406 407[system.cpu.fuPool.FUList4.opList06] 408type=OpDesc 409eventq_index=0 | 403 404[system.cpu.fuPool.FUList4.opList06] 405type=OpDesc 406eventq_index=0 |
| 410issueLat=1 | |
| 411opClass=SimdMult 412opLat=5 | 407opClass=SimdMult 408opLat=5 |
| 409pipelined=true |
|
| 413 414[system.cpu.fuPool.FUList4.opList07] 415type=OpDesc 416eventq_index=0 | 410 411[system.cpu.fuPool.FUList4.opList07] 412type=OpDesc 413eventq_index=0 |
| 417issueLat=1 | |
| 418opClass=SimdMultAcc 419opLat=5 | 414opClass=SimdMultAcc 415opLat=5 |
| 416pipelined=true |
|
| 420 421[system.cpu.fuPool.FUList4.opList08] 422type=OpDesc 423eventq_index=0 | 417 418[system.cpu.fuPool.FUList4.opList08] 419type=OpDesc 420eventq_index=0 |
| 424issueLat=1 | |
| 425opClass=SimdShift 426opLat=3 | 421opClass=SimdShift 422opLat=3 |
| 423pipelined=true |
|
| 427 428[system.cpu.fuPool.FUList4.opList09] 429type=OpDesc 430eventq_index=0 | 424 425[system.cpu.fuPool.FUList4.opList09] 426type=OpDesc 427eventq_index=0 |
| 431issueLat=1 | |
| 432opClass=SimdShiftAcc 433opLat=3 | 428opClass=SimdShiftAcc 429opLat=3 |
| 430pipelined=true |
|
| 434 435[system.cpu.fuPool.FUList4.opList10] 436type=OpDesc 437eventq_index=0 | 431 432[system.cpu.fuPool.FUList4.opList10] 433type=OpDesc 434eventq_index=0 |
| 438issueLat=1 | |
| 439opClass=SimdSqrt 440opLat=9 | 435opClass=SimdSqrt 436opLat=9 |
| 437pipelined=true |
|
| 441 442[system.cpu.fuPool.FUList4.opList11] 443type=OpDesc 444eventq_index=0 | 438 439[system.cpu.fuPool.FUList4.opList11] 440type=OpDesc 441eventq_index=0 |
| 445issueLat=1 | |
| 446opClass=SimdFloatAdd 447opLat=5 | 442opClass=SimdFloatAdd 443opLat=5 |
| 444pipelined=true |
|
| 448 449[system.cpu.fuPool.FUList4.opList12] 450type=OpDesc 451eventq_index=0 | 445 446[system.cpu.fuPool.FUList4.opList12] 447type=OpDesc 448eventq_index=0 |
| 452issueLat=1 | |
| 453opClass=SimdFloatAlu 454opLat=5 | 449opClass=SimdFloatAlu 450opLat=5 |
| 451pipelined=true |
|
| 455 456[system.cpu.fuPool.FUList4.opList13] 457type=OpDesc 458eventq_index=0 | 452 453[system.cpu.fuPool.FUList4.opList13] 454type=OpDesc 455eventq_index=0 |
| 459issueLat=1 | |
| 460opClass=SimdFloatCmp 461opLat=3 | 456opClass=SimdFloatCmp 457opLat=3 |
| 458pipelined=true |
|
| 462 463[system.cpu.fuPool.FUList4.opList14] 464type=OpDesc 465eventq_index=0 | 459 460[system.cpu.fuPool.FUList4.opList14] 461type=OpDesc 462eventq_index=0 |
| 466issueLat=1 | |
| 467opClass=SimdFloatCvt 468opLat=3 | 463opClass=SimdFloatCvt 464opLat=3 |
| 465pipelined=true |
|
| 469 470[system.cpu.fuPool.FUList4.opList15] 471type=OpDesc 472eventq_index=0 | 466 467[system.cpu.fuPool.FUList4.opList15] 468type=OpDesc 469eventq_index=0 |
| 473issueLat=1 | |
| 474opClass=SimdFloatDiv 475opLat=3 | 470opClass=SimdFloatDiv 471opLat=3 |
| 472pipelined=true |
|
| 476 477[system.cpu.fuPool.FUList4.opList16] 478type=OpDesc 479eventq_index=0 | 473 474[system.cpu.fuPool.FUList4.opList16] 475type=OpDesc 476eventq_index=0 |
| 480issueLat=1 | |
| 481opClass=SimdFloatMisc 482opLat=3 | 477opClass=SimdFloatMisc 478opLat=3 |
| 479pipelined=true |
|
| 483 484[system.cpu.fuPool.FUList4.opList17] 485type=OpDesc 486eventq_index=0 | 480 481[system.cpu.fuPool.FUList4.opList17] 482type=OpDesc 483eventq_index=0 |
| 487issueLat=1 | |
| 488opClass=SimdFloatMult 489opLat=3 | 484opClass=SimdFloatMult 485opLat=3 |
| 486pipelined=true |
|
| 490 491[system.cpu.fuPool.FUList4.opList18] 492type=OpDesc 493eventq_index=0 | 487 488[system.cpu.fuPool.FUList4.opList18] 489type=OpDesc 490eventq_index=0 |
| 494issueLat=1 | |
| 495opClass=SimdFloatMultAcc 496opLat=1 | 491opClass=SimdFloatMultAcc 492opLat=1 |
| 493pipelined=true |
|
| 497 498[system.cpu.fuPool.FUList4.opList19] 499type=OpDesc 500eventq_index=0 | 494 495[system.cpu.fuPool.FUList4.opList19] 496type=OpDesc 497eventq_index=0 |
| 501issueLat=1 | |
| 502opClass=SimdFloatSqrt 503opLat=9 | 498opClass=SimdFloatSqrt 499opLat=9 |
| 500pipelined=true |
|
| 504 505[system.cpu.fuPool.FUList4.opList20] 506type=OpDesc 507eventq_index=0 | 501 502[system.cpu.fuPool.FUList4.opList20] 503type=OpDesc 504eventq_index=0 |
| 508issueLat=1 | |
| 509opClass=FloatAdd 510opLat=5 | 505opClass=FloatAdd 506opLat=5 |
| 507pipelined=true |
|
| 511 512[system.cpu.fuPool.FUList4.opList21] 513type=OpDesc 514eventq_index=0 | 508 509[system.cpu.fuPool.FUList4.opList21] 510type=OpDesc 511eventq_index=0 |
| 515issueLat=1 | |
| 516opClass=FloatCmp 517opLat=5 | 512opClass=FloatCmp 513opLat=5 |
| 514pipelined=true |
|
| 518 519[system.cpu.fuPool.FUList4.opList22] 520type=OpDesc 521eventq_index=0 | 515 516[system.cpu.fuPool.FUList4.opList22] 517type=OpDesc 518eventq_index=0 |
| 522issueLat=1 | |
| 523opClass=FloatCvt 524opLat=5 | 519opClass=FloatCvt 520opLat=5 |
| 521pipelined=true |
|
| 525 526[system.cpu.fuPool.FUList4.opList23] 527type=OpDesc 528eventq_index=0 | 522 523[system.cpu.fuPool.FUList4.opList23] 524type=OpDesc 525eventq_index=0 |
| 529issueLat=9 | |
| 530opClass=FloatDiv 531opLat=9 | 526opClass=FloatDiv 527opLat=9 |
| 528pipelined=false |
|
| 532 533[system.cpu.fuPool.FUList4.opList24] 534type=OpDesc 535eventq_index=0 | 529 530[system.cpu.fuPool.FUList4.opList24] 531type=OpDesc 532eventq_index=0 |
| 536issueLat=33 | |
| 537opClass=FloatSqrt 538opLat=33 | 533opClass=FloatSqrt 534opLat=33 |
| 535pipelined=false |
|
| 539 540[system.cpu.fuPool.FUList4.opList25] 541type=OpDesc 542eventq_index=0 | 536 537[system.cpu.fuPool.FUList4.opList25] 538type=OpDesc 539eventq_index=0 |
| 543issueLat=1 | |
| 544opClass=FloatMult 545opLat=4 | 540opClass=FloatMult 541opLat=4 |
| 542pipelined=true |
|
| 546 547[system.cpu.icache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=1 552clk_domain=system.cpu_clk_domain 553demand_mshr_reserve=1 554eventq_index=0 555forward_snoops=true 556hit_latency=2 | 543 544[system.cpu.icache] 545type=BaseCache 546children=tags 547addr_ranges=0:18446744073709551615 548assoc=1 549clk_domain=system.cpu_clk_domain 550demand_mshr_reserve=1 551eventq_index=0 552forward_snoops=true 553hit_latency=2 |
| 557is_top_level=true | 554is_read_only=true |
| 558max_miss_count=0 559mshrs=4 560prefetch_on_access=false 561prefetcher=Null 562response_latency=2 563sequential_access=false 564size=32768 565system=system 566tags=system.cpu.icache.tags 567tgts_per_mshr=20 | 555max_miss_count=0 556mshrs=4 557prefetch_on_access=false 558prefetcher=Null 559response_latency=2 560sequential_access=false 561size=32768 562system=system 563tags=system.cpu.icache.tags 564tgts_per_mshr=20 |
| 568two_queue=false | |
| 569write_buffers=8 570cpu_side=system.cpu.icache_port 571mem_side=system.cpu.toL2Bus.slave[0] 572 573[system.cpu.icache.tags] 574type=LRU 575assoc=1 576block_size=64 --- 83 unchanged lines hidden (view full) --- 660children=tags 661addr_ranges=0:18446744073709551615 662assoc=8 663clk_domain=system.cpu_clk_domain 664demand_mshr_reserve=1 665eventq_index=0 666forward_snoops=true 667hit_latency=20 | 565write_buffers=8 566cpu_side=system.cpu.icache_port 567mem_side=system.cpu.toL2Bus.slave[0] 568 569[system.cpu.icache.tags] 570type=LRU 571assoc=1 572block_size=64 --- 83 unchanged lines hidden (view full) --- 656children=tags 657addr_ranges=0:18446744073709551615 658assoc=8 659clk_domain=system.cpu_clk_domain 660demand_mshr_reserve=1 661eventq_index=0 662forward_snoops=true 663hit_latency=20 |
| 668is_top_level=false | 664is_read_only=false |
| 669max_miss_count=0 670mshrs=20 671prefetch_on_access=false 672prefetcher=Null 673response_latency=20 674sequential_access=false 675size=4194304 676system=system 677tags=system.cpu.l2cache.tags 678tgts_per_mshr=12 | 665max_miss_count=0 666mshrs=20 667prefetch_on_access=false 668prefetcher=Null 669response_latency=20 670sequential_access=false 671size=4194304 672system=system 673tags=system.cpu.l2cache.tags 674tgts_per_mshr=12 |
| 679two_queue=false | |
| 680write_buffers=8 681cpu_side=system.cpu.toL2Bus.master[0] 682mem_side=system.membus.slave[2] 683 684[system.cpu.l2cache.tags] 685type=LRU 686assoc=8 687block_size=64 --- 61 unchanged lines hidden (view full) --- 749children=tags 750addr_ranges=2147483648:2415919103 751assoc=8 752clk_domain=system.clk_domain 753demand_mshr_reserve=1 754eventq_index=0 755forward_snoops=false 756hit_latency=50 | 675write_buffers=8 676cpu_side=system.cpu.toL2Bus.master[0] 677mem_side=system.membus.slave[2] 678 679[system.cpu.l2cache.tags] 680type=LRU 681assoc=8 682block_size=64 --- 61 unchanged lines hidden (view full) --- 744children=tags 745addr_ranges=2147483648:2415919103 746assoc=8 747clk_domain=system.clk_domain 748demand_mshr_reserve=1 749eventq_index=0 750forward_snoops=false 751hit_latency=50 |
| 757is_top_level=true | 752is_read_only=false |
| 758max_miss_count=0 759mshrs=20 760prefetch_on_access=false 761prefetcher=Null 762response_latency=50 763sequential_access=false 764size=1024 765system=system 766tags=system.iocache.tags 767tgts_per_mshr=12 | 753max_miss_count=0 754mshrs=20 755prefetch_on_access=false 756prefetcher=Null 757response_latency=50 758sequential_access=false 759size=1024 760system=system 761tags=system.iocache.tags 762tgts_per_mshr=12 |
| 768two_queue=false | |
| 769write_buffers=8 770cpu_side=system.iobus.master[27] 771mem_side=system.membus.slave[3] 772 773[system.iocache.tags] 774type=LRU 775assoc=8 776block_size=64 --- 351 unchanged lines hidden (view full) --- 1128config=system.iobus.master[26] 1129dma=system.iobus.slave[4] 1130pio=system.iobus.master[25] 1131 1132[system.realview.generic_timer] 1133type=GenericTimer 1134eventq_index=0 1135gic=system.realview.gic | 763write_buffers=8 764cpu_side=system.iobus.master[27] 765mem_side=system.membus.slave[3] 766 767[system.iocache.tags] 768type=LRU 769assoc=8 770block_size=64 --- 351 unchanged lines hidden (view full) --- 1122config=system.iobus.master[26] 1123dma=system.iobus.slave[4] 1124pio=system.iobus.master[25] 1125 1126[system.realview.generic_timer] 1127type=GenericTimer 1128eventq_index=0 1129gic=system.realview.gic |
| 1136int_num=29 | 1130int_phys=29 1131int_virt=27 |
| 1137system=system 1138 1139[system.realview.gic] 1140type=Pl390 1141clk_domain=system.clk_domain 1142cpu_addr=738205696 1143cpu_pio_delay=10000 1144dist_addr=738201600 --- 13 unchanged lines hidden (view full) --- 1158eventq_index=0 1159gic=system.realview.gic 1160int_num=117 1161pio_addr=721420288 1162pio_latency=10000 1163pixel_clock=7299 1164system=system 1165vnc=system.vncserver | 1132system=system 1133 1134[system.realview.gic] 1135type=Pl390 1136clk_domain=system.clk_domain 1137cpu_addr=738205696 1138cpu_pio_delay=10000 1139dist_addr=738201600 --- 13 unchanged lines hidden (view full) --- 1153eventq_index=0 1154gic=system.realview.gic 1155int_num=117 1156pio_addr=721420288 1157pio_latency=10000 1158pixel_clock=7299 1159system=system 1160vnc=system.vncserver |
| 1161workaround_swap_rb=true |
|
| 1166dma=system.membus.slave[0] 1167pio=system.iobus.master[5] 1168 1169[system.realview.ide] 1170type=IdeController 1171BAR0=1 1172BAR0LegacyIO=false 1173BAR0Size=8 --- 389 unchanged lines hidden --- | 1162dma=system.membus.slave[0] 1163pio=system.iobus.master[5] 1164 1165[system.realview.ide] 1166type=IdeController 1167BAR0=1 1168BAR0LegacyIO=false 1169BAR0Size=8 --- 389 unchanged lines hidden --- |