| config.ini (10515:bd7c2aa12122) | config.ini (10798:74e3c7359393) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 14atags_addr=134217728 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxArmSystem 13children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain 14atags_addr=134217728 |
| 15boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 | 15boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 |
| 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain | 16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 17boot_release_addr=65528 18cache_line_size=64 19clk_domain=system.clk_domain |
| 20dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb | 20dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb |
| 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24flags_addr=469827632 25gic_cpu_addr=738205696 26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 | 21early_kernel_symbols=false 22enable_context_switch_stats_dump=false 23eventq_index=0 24flags_addr=469827632 25gic_cpu_addr=738205696 26have_generic_timer=false 27have_large_asid_64=false 28have_lpae=false 29have_security=false 30have_virtualization=false 31highest_el_is_64=false 32init_param=0 |
| 33kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 | 33kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 |
| 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing 39mem_ranges=2147483648:2415919103 | 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing 39mem_ranges=2147483648:2415919103 |
| 40memories=system.realview.nvmem system.physmem system.realview.vram | 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false |
| 41multi_proc=true 42num_work_ids=16 43panic_on_oops=true 44panic_on_panic=true 45phys_addr_range_64=40 | 42multi_proc=true 43num_work_ids=16 44panic_on_oops=true 45panic_on_panic=true 46phys_addr_range_64=40 |
| 46readfile=/work/gem5.latest/tests/halt.sh | 47readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh |
| 47reset_addr_64=0 48symbolfile= 49work_begin_ckpt_count=0 50work_begin_cpu_id_exit=-1 51work_begin_exit_count=0 52work_cpus_ckpt_count=0 53work_end_ckpt_count=0 54work_end_exit_count=0 --- 26 unchanged lines hidden (view full) --- 81eventq_index=0 82image_file= 83read_only=false 84table_size=65536 85 86[system.cf0.image.child] 87type=RawDiskImage 88eventq_index=0 | 48reset_addr_64=0 49symbolfile= 50work_begin_ckpt_count=0 51work_begin_cpu_id_exit=-1 52work_begin_exit_count=0 53work_cpus_ckpt_count=0 54work_end_ckpt_count=0 55work_end_exit_count=0 --- 26 unchanged lines hidden (view full) --- 82eventq_index=0 83image_file= 84read_only=false 85table_size=65536 86 87[system.cf0.image.child] 88type=RawDiskImage 89eventq_index=0 |
| 89image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img | 90image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img |
| 90read_only=true 91 92[system.clk_domain] 93type=SrcClockDomain 94clock=1000 95domain_id=-1 96eventq_index=0 97init_perf_level=0 --- 86 unchanged lines hidden (view full) --- 184tracer=system.cpu.tracer 185trapLatency=13 186wbWidth=8 187workload= 188dcache_port=system.cpu.dcache.cpu_side 189icache_port=system.cpu.icache.cpu_side 190 191[system.cpu.branchPred] | 91read_only=true 92 93[system.clk_domain] 94type=SrcClockDomain 95clock=1000 96domain_id=-1 97eventq_index=0 98init_perf_level=0 --- 86 unchanged lines hidden (view full) --- 185tracer=system.cpu.tracer 186trapLatency=13 187wbWidth=8 188workload= 189dcache_port=system.cpu.dcache.cpu_side 190icache_port=system.cpu.icache.cpu_side 191 192[system.cpu.branchPred] |
| 192type=BranchPredictor | 193type=BiModeBP |
| 193BTBEntries=2048 194BTBTagSize=18 195RASSize=16 196choiceCtrBits=2 197choicePredictorSize=8192 198eventq_index=0 199globalCtrBits=2 200globalPredictorSize=8192 201instShiftAmt=2 | 194BTBEntries=2048 195BTBTagSize=18 196RASSize=16 197choiceCtrBits=2 198choicePredictorSize=8192 199eventq_index=0 200globalCtrBits=2 201globalPredictorSize=8192 202instShiftAmt=2 |
| 202localCtrBits=2 203localHistoryTableSize=2048 204localPredictorSize=2048 | |
| 205numThreads=1 | 203numThreads=1 |
| 206predType=bi-mode | |
| 207 208[system.cpu.dcache] 209type=BaseCache 210children=tags 211addr_ranges=0:18446744073709551615 212assoc=4 213clk_domain=system.cpu_clk_domain | 204 205[system.cpu.dcache] 206type=BaseCache 207children=tags 208addr_ranges=0:18446744073709551615 209assoc=4 210clk_domain=system.cpu_clk_domain |
| 211demand_mshr_reserve=1 |
|
| 214eventq_index=0 215forward_snoops=true 216hit_latency=2 217is_top_level=true 218max_miss_count=0 219mshrs=4 220prefetch_on_access=false 221prefetcher=Null --- 18 unchanged lines hidden (view full) --- 240sequential_access=false 241size=32768 242 243[system.cpu.dstage2_mmu] 244type=ArmStage2MMU 245children=stage2_tlb 246eventq_index=0 247stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 212eventq_index=0 213forward_snoops=true 214hit_latency=2 215is_top_level=true 216max_miss_count=0 217mshrs=4 218prefetch_on_access=false 219prefetcher=Null --- 18 unchanged lines hidden (view full) --- 238sequential_access=false 239size=32768 240 241[system.cpu.dstage2_mmu] 242type=ArmStage2MMU 243children=stage2_tlb 244eventq_index=0 245stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 246sys=system |
|
| 248tlb=system.cpu.dtb 249 250[system.cpu.dstage2_mmu.stage2_tlb] 251type=ArmTLB 252children=walker 253eventq_index=0 254is_stage2=true 255size=32 256walker=system.cpu.dstage2_mmu.stage2_tlb.walker 257 258[system.cpu.dstage2_mmu.stage2_tlb.walker] 259type=ArmTableWalker 260clk_domain=system.cpu_clk_domain 261eventq_index=0 262is_stage2=true 263num_squash_per_cycle=2 264sys=system | 247tlb=system.cpu.dtb 248 249[system.cpu.dstage2_mmu.stage2_tlb] 250type=ArmTLB 251children=walker 252eventq_index=0 253is_stage2=true 254size=32 255walker=system.cpu.dstage2_mmu.stage2_tlb.walker 256 257[system.cpu.dstage2_mmu.stage2_tlb.walker] 258type=ArmTableWalker 259clk_domain=system.cpu_clk_domain 260eventq_index=0 261is_stage2=true 262num_squash_per_cycle=2 263sys=system |
| 265port=system.cpu.toL2Bus.slave[5] | |
| 266 267[system.cpu.dtb] 268type=ArmTLB 269children=walker 270eventq_index=0 271is_stage2=false 272size=64 273walker=system.cpu.dtb.walker --- 273 unchanged lines hidden (view full) --- 547opLat=4 548 549[system.cpu.icache] 550type=BaseCache 551children=tags 552addr_ranges=0:18446744073709551615 553assoc=1 554clk_domain=system.cpu_clk_domain | 264 265[system.cpu.dtb] 266type=ArmTLB 267children=walker 268eventq_index=0 269is_stage2=false 270size=64 271walker=system.cpu.dtb.walker --- 273 unchanged lines hidden (view full) --- 545opLat=4 546 547[system.cpu.icache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=1 552clk_domain=system.cpu_clk_domain |
| 553demand_mshr_reserve=1 |
|
| 555eventq_index=0 556forward_snoops=true 557hit_latency=2 558is_top_level=true 559max_miss_count=0 560mshrs=4 561prefetch_on_access=false 562prefetcher=Null --- 52 unchanged lines hidden (view full) --- 615pmu=Null 616system=system 617 618[system.cpu.istage2_mmu] 619type=ArmStage2MMU 620children=stage2_tlb 621eventq_index=0 622stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 554eventq_index=0 555forward_snoops=true 556hit_latency=2 557is_top_level=true 558max_miss_count=0 559mshrs=4 560prefetch_on_access=false 561prefetcher=Null --- 52 unchanged lines hidden (view full) --- 614pmu=Null 615system=system 616 617[system.cpu.istage2_mmu] 618type=ArmStage2MMU 619children=stage2_tlb 620eventq_index=0 621stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 622sys=system |
|
| 623tlb=system.cpu.itb 624 625[system.cpu.istage2_mmu.stage2_tlb] 626type=ArmTLB 627children=walker 628eventq_index=0 629is_stage2=true 630size=32 631walker=system.cpu.istage2_mmu.stage2_tlb.walker 632 633[system.cpu.istage2_mmu.stage2_tlb.walker] 634type=ArmTableWalker 635clk_domain=system.cpu_clk_domain 636eventq_index=0 637is_stage2=true 638num_squash_per_cycle=2 639sys=system | 623tlb=system.cpu.itb 624 625[system.cpu.istage2_mmu.stage2_tlb] 626type=ArmTLB 627children=walker 628eventq_index=0 629is_stage2=true 630size=32 631walker=system.cpu.istage2_mmu.stage2_tlb.walker 632 633[system.cpu.istage2_mmu.stage2_tlb.walker] 634type=ArmTableWalker 635clk_domain=system.cpu_clk_domain 636eventq_index=0 637is_stage2=true 638num_squash_per_cycle=2 639sys=system |
| 640port=system.cpu.toL2Bus.slave[4] | |
| 641 642[system.cpu.itb] 643type=ArmTLB 644children=walker 645eventq_index=0 646is_stage2=false 647size=64 648walker=system.cpu.itb.walker --- 8 unchanged lines hidden (view full) --- 657port=system.cpu.toL2Bus.slave[2] 658 659[system.cpu.l2cache] 660type=BaseCache 661children=tags 662addr_ranges=0:18446744073709551615 663assoc=8 664clk_domain=system.cpu_clk_domain | 640 641[system.cpu.itb] 642type=ArmTLB 643children=walker 644eventq_index=0 645is_stage2=false 646size=64 647walker=system.cpu.itb.walker --- 8 unchanged lines hidden (view full) --- 656port=system.cpu.toL2Bus.slave[2] 657 658[system.cpu.l2cache] 659type=BaseCache 660children=tags 661addr_ranges=0:18446744073709551615 662assoc=8 663clk_domain=system.cpu_clk_domain |
| 664demand_mshr_reserve=1 |
|
| 665eventq_index=0 666forward_snoops=true 667hit_latency=20 668is_top_level=false 669max_miss_count=0 670mshrs=20 671prefetch_on_access=false 672prefetcher=Null --- 17 unchanged lines hidden (view full) --- 690hit_latency=20 691sequential_access=false 692size=4194304 693 694[system.cpu.toL2Bus] 695type=CoherentXBar 696clk_domain=system.cpu_clk_domain 697eventq_index=0 | 665eventq_index=0 666forward_snoops=true 667hit_latency=20 668is_top_level=false 669max_miss_count=0 670mshrs=20 671prefetch_on_access=false 672prefetcher=Null --- 17 unchanged lines hidden (view full) --- 690hit_latency=20 691sequential_access=false 692size=4194304 693 694[system.cpu.toL2Bus] 695type=CoherentXBar 696clk_domain=system.cpu_clk_domain 697eventq_index=0 |
| 698header_cycles=1 | 698forward_latency=0 699frontend_latency=1 700response_latency=1 |
| 699snoop_filter=Null | 701snoop_filter=Null |
| 702snoop_response_latency=1 |
|
| 700system=system 701use_default_range=false 702width=32 703master=system.cpu.l2cache.cpu_side | 703system=system 704use_default_range=false 705width=32 706master=system.cpu.l2cache.cpu_side |
| 704slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port | 707slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 705 706[system.cpu.tracer] 707type=ExeTracer 708eventq_index=0 709 710[system.cpu_clk_domain] 711type=SrcClockDomain 712clock=500 --- 14 unchanged lines hidden (view full) --- 727type=IntrControl 728eventq_index=0 729sys=system 730 731[system.iobus] 732type=NoncoherentXBar 733clk_domain=system.clk_domain 734eventq_index=0 | 708 709[system.cpu.tracer] 710type=ExeTracer 711eventq_index=0 712 713[system.cpu_clk_domain] 714type=SrcClockDomain 715clock=500 --- 14 unchanged lines hidden (view full) --- 730type=IntrControl 731eventq_index=0 732sys=system 733 734[system.iobus] 735type=NoncoherentXBar 736clk_domain=system.clk_domain 737eventq_index=0 |
| 735header_cycles=1 | 738forward_latency=1 739frontend_latency=2 740response_latency=2 |
| 736use_default_range=true | 741use_default_range=true |
| 737width=8 | 742width=16 |
| 738default=system.realview.pciconfig.pio 739master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 740slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 741 742[system.iocache] 743type=BaseCache 744children=tags 745addr_ranges=2147483648:2415919103 746assoc=8 747clk_domain=system.clk_domain | 743default=system.realview.pciconfig.pio 744master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 745slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 746 747[system.iocache] 748type=BaseCache 749children=tags 750addr_ranges=2147483648:2415919103 751assoc=8 752clk_domain=system.clk_domain |
| 753demand_mshr_reserve=1 |
|
| 748eventq_index=0 749forward_snoops=false 750hit_latency=50 751is_top_level=true 752max_miss_count=0 753mshrs=20 754prefetch_on_access=false 755prefetcher=Null --- 18 unchanged lines hidden (view full) --- 774sequential_access=false 775size=1024 776 777[system.membus] 778type=CoherentXBar 779children=badaddr_responder 780clk_domain=system.clk_domain 781eventq_index=0 | 754eventq_index=0 755forward_snoops=false 756hit_latency=50 757is_top_level=true 758max_miss_count=0 759mshrs=20 760prefetch_on_access=false 761prefetcher=Null --- 18 unchanged lines hidden (view full) --- 780sequential_access=false 781size=1024 782 783[system.membus] 784type=CoherentXBar 785children=badaddr_responder 786clk_domain=system.clk_domain 787eventq_index=0 |
| 782header_cycles=1 | 788forward_latency=4 789frontend_latency=3 790response_latency=2 |
| 783snoop_filter=Null | 791snoop_filter=Null |
| 792snoop_response_latency=4 |
|
| 784system=system 785use_default_range=false | 793system=system 794use_default_range=false |
| 786width=8 | 795width=16 |
| 787default=system.membus.badaddr_responder.pio | 796default=system.membus.badaddr_responder.pio |
| 788master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port | 797master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port |
| 789slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 790 791[system.membus.badaddr_responder] 792type=IsaFake 793clk_domain=system.clk_domain 794eventq_index=0 795fake_mem=false 796pio_addr=0 --- 31 unchanged lines hidden (view full) --- 828IDD4W2=0.000000 829IDD5=0.220000 830IDD52=0.000000 831IDD6=0.000000 832IDD62=0.000000 833VDD=1.500000 834VDD2=0.000000 835activation_limit=4 | 798slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 799 800[system.membus.badaddr_responder] 801type=IsaFake 802clk_domain=system.clk_domain 803eventq_index=0 804fake_mem=false 805pio_addr=0 --- 31 unchanged lines hidden (view full) --- 837IDD4W2=0.000000 838IDD5=0.220000 839IDD52=0.000000 840IDD6=0.000000 841IDD62=0.000000 842VDD=1.500000 843VDD2=0.000000 844activation_limit=4 |
| 836addr_mapping=RoRaBaChCo | 845addr_mapping=RoRaBaCoCh |
| 837bank_groups_per_rank=0 838banks_per_rank=8 839burst_length=8 840channels=1 841clk_domain=system.clk_domain 842conf_table_reported=true 843device_bus_width=8 844device_rowbuffer_size=1024 --- 287 unchanged lines hidden (view full) --- 1132clk_domain=system.clk_domain 1133cpu_addr=738205696 1134cpu_pio_delay=10000 1135dist_addr=738201600 1136dist_pio_delay=10000 1137eventq_index=0 1138int_latency=10000 1139it_lines=128 | 846bank_groups_per_rank=0 847banks_per_rank=8 848burst_length=8 849channels=1 850clk_domain=system.clk_domain 851conf_table_reported=true 852device_bus_width=8 853device_rowbuffer_size=1024 --- 287 unchanged lines hidden (view full) --- 1141clk_domain=system.clk_domain 1142cpu_addr=738205696 1143cpu_pio_delay=10000 1144dist_addr=738201600 1145dist_pio_delay=10000 1146eventq_index=0 1147int_latency=10000 1148it_lines=128 |
| 1140msix_addr=0 | |
| 1141platform=system.realview 1142system=system 1143pio=system.membus.master[2] 1144 1145[system.realview.hdlcd] 1146type=HDLcd 1147amba_id=1314816 1148clk_domain=system.clk_domain --- 170 unchanged lines hidden (view full) --- 1319clk_domain=system.clk_domain 1320eventq_index=0 1321gic=system.realview.gic 1322int_num_timer=29 1323int_num_watchdog=30 1324pio_addr=738721792 1325pio_latency=100000 1326system=system | 1149platform=system.realview 1150system=system 1151pio=system.membus.master[2] 1152 1153[system.realview.hdlcd] 1154type=HDLcd 1155amba_id=1314816 1156clk_domain=system.clk_domain --- 170 unchanged lines hidden (view full) --- 1327clk_domain=system.clk_domain 1328eventq_index=0 1329gic=system.realview.gic 1330int_num_timer=29 1331int_num_watchdog=30 1332pio_addr=738721792 1333pio_latency=100000 1334system=system |
| 1327pio=system.membus.master[3] | 1335pio=system.membus.master[4] |
| 1328 1329[system.realview.mmc_fake] 1330type=AmbaFake 1331amba_id=0 1332clk_domain=system.clk_domain 1333eventq_index=0 1334ignore_access=false 1335pio_addr=470089728 --- 165 unchanged lines hidden (view full) --- 1501eventq_index=0 1502gic=system.realview.gic 1503hv_addr=738213888 1504pio_delay=10000 1505platform=system.realview 1506ppint=25 1507system=system 1508vcpu_addr=738222080 | 1336 1337[system.realview.mmc_fake] 1338type=AmbaFake 1339amba_id=0 1340clk_domain=system.clk_domain 1341eventq_index=0 1342ignore_access=false 1343pio_addr=470089728 --- 165 unchanged lines hidden (view full) --- 1509eventq_index=0 1510gic=system.realview.gic 1511hv_addr=738213888 1512pio_delay=10000 1513platform=system.realview 1514ppint=25 1515system=system 1516vcpu_addr=738222080 |
| 1509pio=system.membus.master[4] | 1517pio=system.membus.master[3] |
| 1510 1511[system.realview.vram] 1512type=SimpleMemory 1513bandwidth=73.000000 1514clk_domain=system.clk_domain 1515conf_table_reported=false 1516eventq_index=0 1517in_addr_map=true --- 37 unchanged lines hidden --- | 1518 1519[system.realview.vram] 1520type=SimpleMemory 1521bandwidth=73.000000 1522clk_domain=system.clk_domain 1523conf_table_reported=false 1524eventq_index=0 1525in_addr_map=true --- 37 unchanged lines hidden --- |