1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 22 unchanged lines hidden (view full) ---
31highest_el_is_64=false
32init_param=0
33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM64
38mem_mode=timing
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43multi_thread=false
44num_work_ids=16
45p_state_clk_gate_bins=20
46p_state_clk_gate_max=1000000000000
47p_state_clk_gate_min=1000
--- 20 unchanged lines hidden (view full) ---
68clk_domain=system.clk_domain
69default_p_state=UNDEFINED
70delay=50000
71eventq_index=0
72p_state_clk_gate_bins=20
73p_state_clk_gate_max=1000000000000
74p_state_clk_gate_min=1000
75power_model=Null
76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
77req_size=16
78resp_size=16
79master=system.iobus.slave[0]
80slave=system.membus.master[0]
81
82[system.cf0]
83type=IdeDisk
84children=image
--- 139 unchanged lines hidden (view full) ---
224indirectWays=2
225instShiftAmt=2
226numThreads=1
227useIndirect=true
228
229[system.cpu.dcache]
230type=Cache
231children=tags
232addr_ranges=0:18446744073709551615
233assoc=4
234clk_domain=system.cpu_clk_domain
235clusivity=mostly_incl
236default_p_state=UNDEFINED
237demand_mshr_reserve=1
238eventq_index=0
239hit_latency=2
240is_read_only=false
--- 345 unchanged lines hidden (view full) ---
586eventq_index=0
587opClass=FloatMult
588opLat=4
589pipelined=true
590
591[system.cpu.icache]
592type=Cache
593children=tags
594addr_ranges=0:18446744073709551615
595assoc=1
596clk_domain=system.cpu_clk_domain
597clusivity=mostly_incl
598default_p_state=UNDEFINED
599demand_mshr_reserve=1
600eventq_index=0
601hit_latency=2
602is_read_only=true
--- 115 unchanged lines hidden (view full) ---
718p_state_clk_gate_min=1000
719power_model=Null
720sys=system
721port=system.cpu.toL2Bus.slave[2]
722
723[system.cpu.l2cache]
724type=Cache
725children=tags
726addr_ranges=0:18446744073709551615
727assoc=8
728clk_domain=system.cpu_clk_domain
729clusivity=mostly_incl
730default_p_state=UNDEFINED
731demand_mshr_reserve=1
732eventq_index=0
733hit_latency=20
734is_read_only=false
--- 100 unchanged lines hidden (view full) ---
835use_default_range=false
836width=16
837master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
838slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
839
840[system.iocache]
841type=Cache
842children=tags
843addr_ranges=2147483648:2415919103
844assoc=8
845clk_domain=system.clk_domain
846clusivity=mostly_incl
847default_p_state=UNDEFINED
848demand_mshr_reserve=1
849eventq_index=0
850hit_latency=50
851is_read_only=false
--- 28 unchanged lines hidden (view full) ---
880p_state_clk_gate_max=1000000000000
881p_state_clk_gate_min=1000
882power_model=Null
883sequential_access=false
884size=1024
885
886[system.membus]
887type=CoherentXBar
888children=badaddr_responder
889clk_domain=system.clk_domain
890default_p_state=UNDEFINED
891eventq_index=0
892forward_latency=4
893frontend_latency=3
894p_state_clk_gate_bins=20
895p_state_clk_gate_max=1000000000000
896p_state_clk_gate_min=1000
897point_of_coherency=true
898power_model=Null
899response_latency=2
900snoop_filter=Null
901snoop_response_latency=4
902system=system
903use_default_range=false
904width=16
905default=system.membus.badaddr_responder.pio
906master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
907slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
908
--- 15 unchanged lines hidden (view full) ---
924ret_data32=4294967295
925ret_data64=18446744073709551615
926ret_data8=255
927system=system
928update_data=false
929warn_access=warn
930pio=system.membus.default
931
932[system.physmem]
933type=DRAMCtrl
934IDD0=0.075000
935IDD02=0.000000
936IDD2N=0.050000
937IDD2N2=0.000000
938IDD2P0=0.000000
939IDD2P02=0.000000
940IDD2P1=0.000000
941IDD2P12=0.000000
942IDD3N=0.057000
943IDD3N2=0.000000
944IDD3P0=0.000000
945IDD3P02=0.000000
946IDD3P1=0.000000
947IDD3P12=0.000000
948IDD4R=0.187000
949IDD4R2=0.000000
950IDD4W=0.165000
951IDD4W2=0.000000
952IDD5=0.220000
953IDD52=0.000000
954IDD6=0.000000
955IDD62=0.000000
956VDD=1.500000
957VDD2=0.000000
958activation_limit=4
959addr_mapping=RoRaBaCoCh
960bank_groups_per_rank=0
961banks_per_rank=8
962burst_length=8
963channels=1
964clk_domain=system.clk_domain
965conf_table_reported=true
966default_p_state=UNDEFINED
967device_bus_width=8
968device_rowbuffer_size=1024
969device_size=536870912
970devices_per_rank=8
971dll=true
972eventq_index=0
973in_addr_map=true
974max_accesses_per_row=16
975mem_sched_policy=frfcfs
976min_writes_per_switch=16
977null=false
978p_state_clk_gate_bins=20
979p_state_clk_gate_max=1000000000000
980p_state_clk_gate_min=1000
981page_policy=open_adaptive
982power_model=Null
983range=2147483648:2415919103
984ranks_per_channel=2
985read_buffer_size=32
986static_backend_latency=10000
987static_frontend_latency=10000
988tBURST=5000
989tCCD_L=0
990tCK=1250
991tCL=13750
--- 5 unchanged lines hidden (view full) ---
997tRP=13750
998tRRD=6000
999tRRD_L=0
1000tRTP=7500
1001tRTW=2500
1002tWR=15000
1003tWTR=7500
1004tXAW=30000
1005tXP=0
1006tXPDLL=0
1007tXS=0
1008tXSDLL=0
1009write_buffer_size=64
1010write_high_thresh_perc=85
1011write_low_thresh_perc=50
1012port=system.membus.master[5]
1013
1014[system.realview]
1015type=RealView
--- 336 unchanged lines hidden (view full) ---
1352type=Pl390
1353clk_domain=system.clk_domain
1354cpu_addr=738205696
1355cpu_pio_delay=10000
1356default_p_state=UNDEFINED
1357dist_addr=738201600
1358dist_pio_delay=10000
1359eventq_index=0
1360gem5_extensions=true
1361int_latency=10000
1362it_lines=128
1363p_state_clk_gate_bins=20
1364p_state_clk_gate_max=1000000000000
1365p_state_clk_gate_min=1000
1366platform=system.realview
1367power_model=Null
1368system=system
--- 296 unchanged lines hidden (view full) ---
1665power_model=Null
1666system=system
1667pio=system.iobus.master[21]
1668
1669[system.realview.nvmem]
1670type=SimpleMemory
1671bandwidth=73.000000
1672clk_domain=system.clk_domain
1673conf_table_reported=true
1674default_p_state=UNDEFINED
1675eventq_index=0
1676in_addr_map=true
1677latency=30000
1678latency_var=0
1679null=false
1680p_state_clk_gate_bins=20
1681p_state_clk_gate_max=1000000000000
1682p_state_clk_gate_min=1000
1683power_model=Null
1684range=0:67108863
1685port=system.membus.master[1]
1686
1687[system.realview.pci_host]
1688type=GenericPciHost
1689clk_domain=system.clk_domain
1690conf_base=805306368
1691conf_device_bits=12
1692conf_size=268435456
--- 214 unchanged lines hidden (view full) ---
1907[system.realview.vram]
1908type=SimpleMemory
1909bandwidth=73.000000
1910clk_domain=system.clk_domain
1911conf_table_reported=false
1912default_p_state=UNDEFINED
1913eventq_index=0
1914in_addr_map=true
1915latency=30000
1916latency_var=0
1917null=false
1918p_state_clk_gate_bins=20
1919p_state_clk_gate_max=1000000000000
1920p_state_clk_gate_min=1000
1921power_model=Null
1922range=402653184:436207615
1923port=system.iobus.master[11]
1924
1925[system.realview.watchdog_fake]
1926type=AmbaFake
1927amba_id=0
1928clk_domain=system.clk_domain
1929default_p_state=UNDEFINED
1930eventq_index=0
--- 30 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 22 unchanged lines hidden (view full) ---
31highest_el_is_64=false
32init_param=0
33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM64
38mem_mode=timing
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43multi_thread=false
44num_work_ids=16
45p_state_clk_gate_bins=20
46p_state_clk_gate_max=1000000000000
47p_state_clk_gate_min=1000
--- 20 unchanged lines hidden (view full) ---
68clk_domain=system.clk_domain
69default_p_state=UNDEFINED
70delay=50000
71eventq_index=0
72p_state_clk_gate_bins=20
73p_state_clk_gate_max=1000000000000
74p_state_clk_gate_min=1000
75power_model=Null
76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
77req_size=16
78resp_size=16
79master=system.iobus.slave[0]
80slave=system.membus.master[0]
81
82[system.cf0]
83type=IdeDisk
84children=image
--- 139 unchanged lines hidden (view full) ---
224indirectWays=2
225instShiftAmt=2
226numThreads=1
227useIndirect=true
228
229[system.cpu.dcache]
230type=Cache
231children=tags
232addr_ranges=0:18446744073709551615
233assoc=4
234clk_domain=system.cpu_clk_domain
235clusivity=mostly_incl
236default_p_state=UNDEFINED
237demand_mshr_reserve=1
238eventq_index=0
239hit_latency=2
240is_read_only=false
--- 345 unchanged lines hidden (view full) ---
586eventq_index=0
587opClass=FloatMult
588opLat=4
589pipelined=true
590
591[system.cpu.icache]
592type=Cache
593children=tags
594addr_ranges=0:18446744073709551615
595assoc=1
596clk_domain=system.cpu_clk_domain
597clusivity=mostly_incl
598default_p_state=UNDEFINED
599demand_mshr_reserve=1
600eventq_index=0
601hit_latency=2
602is_read_only=true
--- 115 unchanged lines hidden (view full) ---
718p_state_clk_gate_min=1000
719power_model=Null
720sys=system
721port=system.cpu.toL2Bus.slave[2]
722
723[system.cpu.l2cache]
724type=Cache
725children=tags
726addr_ranges=0:18446744073709551615
727assoc=8
728clk_domain=system.cpu_clk_domain
729clusivity=mostly_incl
730default_p_state=UNDEFINED
731demand_mshr_reserve=1
732eventq_index=0
733hit_latency=20
734is_read_only=false
--- 100 unchanged lines hidden (view full) ---
835use_default_range=false
836width=16
837master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
838slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
839
840[system.iocache]
841type=Cache
842children=tags
843addr_ranges=2147483648:2415919103
844assoc=8
845clk_domain=system.clk_domain
846clusivity=mostly_incl
847default_p_state=UNDEFINED
848demand_mshr_reserve=1
849eventq_index=0
850hit_latency=50
851is_read_only=false
--- 28 unchanged lines hidden (view full) ---
880p_state_clk_gate_max=1000000000000
881p_state_clk_gate_min=1000
882power_model=Null
883sequential_access=false
884size=1024
885
886[system.membus]
887type=CoherentXBar
888children=badaddr_responder
889clk_domain=system.clk_domain
890default_p_state=UNDEFINED
891eventq_index=0
892forward_latency=4
893frontend_latency=3
894p_state_clk_gate_bins=20
895p_state_clk_gate_max=1000000000000
896p_state_clk_gate_min=1000
897point_of_coherency=true
898power_model=Null
899response_latency=2
900snoop_filter=Null
901snoop_response_latency=4
902system=system
903use_default_range=false
904width=16
905default=system.membus.badaddr_responder.pio
906master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
907slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
908
--- 15 unchanged lines hidden (view full) ---
924ret_data32=4294967295
925ret_data64=18446744073709551615
926ret_data8=255
927system=system
928update_data=false
929warn_access=warn
930pio=system.membus.default
931
932[system.physmem]
933type=DRAMCtrl
934IDD0=0.075000
935IDD02=0.000000
936IDD2N=0.050000
937IDD2N2=0.000000
938IDD2P0=0.000000
939IDD2P02=0.000000
940IDD2P1=0.000000
941IDD2P12=0.000000
942IDD3N=0.057000
943IDD3N2=0.000000
944IDD3P0=0.000000
945IDD3P02=0.000000
946IDD3P1=0.000000
947IDD3P12=0.000000
948IDD4R=0.187000
949IDD4R2=0.000000
950IDD4W=0.165000
951IDD4W2=0.000000
952IDD5=0.220000
953IDD52=0.000000
954IDD6=0.000000
955IDD62=0.000000
956VDD=1.500000
957VDD2=0.000000
958activation_limit=4
959addr_mapping=RoRaBaCoCh
960bank_groups_per_rank=0
961banks_per_rank=8
962burst_length=8
963channels=1
964clk_domain=system.clk_domain
965conf_table_reported=true
966default_p_state=UNDEFINED
967device_bus_width=8
968device_rowbuffer_size=1024
969device_size=536870912
970devices_per_rank=8
971dll=true
972eventq_index=0
973in_addr_map=true
974max_accesses_per_row=16
975mem_sched_policy=frfcfs
976min_writes_per_switch=16
977null=false
978p_state_clk_gate_bins=20
979p_state_clk_gate_max=1000000000000
980p_state_clk_gate_min=1000
981page_policy=open_adaptive
982power_model=Null
983range=2147483648:2415919103
984ranks_per_channel=2
985read_buffer_size=32
986static_backend_latency=10000
987static_frontend_latency=10000
988tBURST=5000
989tCCD_L=0
990tCK=1250
991tCL=13750
--- 5 unchanged lines hidden (view full) ---
997tRP=13750
998tRRD=6000
999tRRD_L=0
1000tRTP=7500
1001tRTW=2500
1002tWR=15000
1003tWTR=7500
1004tXAW=30000
1005tXP=0
1006tXPDLL=0
1007tXS=0
1008tXSDLL=0
1009write_buffer_size=64
1010write_high_thresh_perc=85
1011write_low_thresh_perc=50
1012port=system.membus.master[5]
1013
1014[system.realview]
1015type=RealView
--- 336 unchanged lines hidden (view full) ---
1352type=Pl390
1353clk_domain=system.clk_domain
1354cpu_addr=738205696
1355cpu_pio_delay=10000
1356default_p_state=UNDEFINED
1357dist_addr=738201600
1358dist_pio_delay=10000
1359eventq_index=0
1360gem5_extensions=true
1361int_latency=10000
1362it_lines=128
1363p_state_clk_gate_bins=20
1364p_state_clk_gate_max=1000000000000
1365p_state_clk_gate_min=1000
1366platform=system.realview
1367power_model=Null
1368system=system
--- 296 unchanged lines hidden (view full) ---
1665power_model=Null
1666system=system
1667pio=system.iobus.master[21]
1668
1669[system.realview.nvmem]
1670type=SimpleMemory
1671bandwidth=73.000000
1672clk_domain=system.clk_domain
1673conf_table_reported=true
1674default_p_state=UNDEFINED
1675eventq_index=0
1676in_addr_map=true
1677latency=30000
1678latency_var=0
1679null=false
1680p_state_clk_gate_bins=20
1681p_state_clk_gate_max=1000000000000
1682p_state_clk_gate_min=1000
1683power_model=Null
1684range=0:67108863
1685port=system.membus.master[1]
1686
1687[system.realview.pci_host]
1688type=GenericPciHost
1689clk_domain=system.clk_domain
1690conf_base=805306368
1691conf_device_bits=12
1692conf_size=268435456
--- 214 unchanged lines hidden (view full) ---
1907[system.realview.vram]
1908type=SimpleMemory
1909bandwidth=73.000000
1910clk_domain=system.clk_domain
1911conf_table_reported=false
1912default_p_state=UNDEFINED
1913eventq_index=0
1914in_addr_map=true
1915latency=30000
1916latency_var=0
1917null=false
1918p_state_clk_gate_bins=20
1919p_state_clk_gate_max=1000000000000
1920p_state_clk_gate_min=1000
1921power_model=Null
1922range=402653184:436207615
1923port=system.iobus.master[11]
1924
1925[system.realview.watchdog_fake]
1926type=AmbaFake
1927amba_id=0
1928clk_domain=system.clk_domain
1929default_p_state=UNDEFINED
1930eventq_index=0
--- 30 unchanged lines hidden ---