1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17cache_line_size=64
18clk_domain=system.clk_domain
19dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
20early_kernel_symbols=false
21enable_context_switch_stats_dump=false
22eventq_index=0
23flags_addr=469827632
24gic_cpu_addr=738205696
25have_large_asid_64=false
26have_lpae=false
27have_security=false
28have_virtualization=false
29highest_el_is_64=false
30init_param=0
31kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
32kernel_addr_check=true
33load_addr_mask=268435455
34load_offset=2147483648
35machine_type=VExpress_EMM64
36mem_mode=timing
37mem_ranges=2147483648:2415919103
38memories=system.physmem system.realview.nvmem system.realview.vram
39mmap_using_noreserve=false
40multi_proc=true
41num_work_ids=16
42panic_on_oops=true
43panic_on_panic=true
44phys_addr_range_64=40
45readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
46reset_addr_64=0
47symbolfile=
48work_begin_ckpt_count=0
49work_begin_cpu_id_exit=-1
50work_begin_exit_count=0
51work_cpus_ckpt_count=0
52work_end_ckpt_count=0
53work_end_exit_count=0

--- 26 unchanged lines hidden (view full) ---

80eventq_index=0
81image_file=
82read_only=false
83table_size=65536
84
85[system.cf0.image.child]
86type=RawDiskImage
87eventq_index=0
88image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
89read_only=true
90
91[system.clk_domain]
92type=SrcClockDomain
93clock=1000
94domain_id=-1
95eventq_index=0
96init_perf_level=0

--- 108 unchanged lines hidden (view full) ---

205children=tags
206addr_ranges=0:18446744073709551615
207assoc=4
208clk_domain=system.cpu_clk_domain
209demand_mshr_reserve=1
210eventq_index=0
211forward_snoops=true
212hit_latency=2
213is_read_only=false
214max_miss_count=0
215mshrs=4
216prefetch_on_access=false
217prefetcher=Null
218response_latency=2
219sequential_access=false
220size=32768
221system=system
222tags=system.cpu.dcache.tags
223tgts_per_mshr=20
224write_buffers=8
225cpu_side=system.cpu.dcache_port
226mem_side=system.cpu.toL2Bus.slave[1]
227
228[system.cpu.dcache.tags]
229type=LRU
230assoc=4
231block_size=64

--- 55 unchanged lines hidden (view full) ---

287children=opList
288count=2
289eventq_index=0
290opList=system.cpu.fuPool.FUList0.opList
291
292[system.cpu.fuPool.FUList0.opList]
293type=OpDesc
294eventq_index=0
295opClass=IntAlu
296opLat=1
297pipelined=true
298
299[system.cpu.fuPool.FUList1]
300type=FUDesc
301children=opList0 opList1 opList2
302count=1
303eventq_index=0
304opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
305
306[system.cpu.fuPool.FUList1.opList0]
307type=OpDesc
308eventq_index=0
309opClass=IntMult
310opLat=3
311pipelined=true
312
313[system.cpu.fuPool.FUList1.opList1]
314type=OpDesc
315eventq_index=0
316opClass=IntDiv
317opLat=12
318pipelined=false
319
320[system.cpu.fuPool.FUList1.opList2]
321type=OpDesc
322eventq_index=0
323opClass=IprAccess
324opLat=3
325pipelined=true
326
327[system.cpu.fuPool.FUList2]
328type=FUDesc
329children=opList
330count=1
331eventq_index=0
332opList=system.cpu.fuPool.FUList2.opList
333
334[system.cpu.fuPool.FUList2.opList]
335type=OpDesc
336eventq_index=0
337opClass=MemRead
338opLat=2
339pipelined=true
340
341[system.cpu.fuPool.FUList3]
342type=FUDesc
343children=opList
344count=1
345eventq_index=0
346opList=system.cpu.fuPool.FUList3.opList
347
348[system.cpu.fuPool.FUList3.opList]
349type=OpDesc
350eventq_index=0
351opClass=MemWrite
352opLat=2
353pipelined=true
354
355[system.cpu.fuPool.FUList4]
356type=FUDesc
357children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
358count=2
359eventq_index=0
360opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
361
362[system.cpu.fuPool.FUList4.opList00]
363type=OpDesc
364eventq_index=0
365opClass=SimdAdd
366opLat=4
367pipelined=true
368
369[system.cpu.fuPool.FUList4.opList01]
370type=OpDesc
371eventq_index=0
372opClass=SimdAddAcc
373opLat=4
374pipelined=true
375
376[system.cpu.fuPool.FUList4.opList02]
377type=OpDesc
378eventq_index=0
379opClass=SimdAlu
380opLat=4
381pipelined=true
382
383[system.cpu.fuPool.FUList4.opList03]
384type=OpDesc
385eventq_index=0
386opClass=SimdCmp
387opLat=4
388pipelined=true
389
390[system.cpu.fuPool.FUList4.opList04]
391type=OpDesc
392eventq_index=0
393opClass=SimdCvt
394opLat=3
395pipelined=true
396
397[system.cpu.fuPool.FUList4.opList05]
398type=OpDesc
399eventq_index=0
400opClass=SimdMisc
401opLat=3
402pipelined=true
403
404[system.cpu.fuPool.FUList4.opList06]
405type=OpDesc
406eventq_index=0
407opClass=SimdMult
408opLat=5
409pipelined=true
410
411[system.cpu.fuPool.FUList4.opList07]
412type=OpDesc
413eventq_index=0
414opClass=SimdMultAcc
415opLat=5
416pipelined=true
417
418[system.cpu.fuPool.FUList4.opList08]
419type=OpDesc
420eventq_index=0
421opClass=SimdShift
422opLat=3
423pipelined=true
424
425[system.cpu.fuPool.FUList4.opList09]
426type=OpDesc
427eventq_index=0
428opClass=SimdShiftAcc
429opLat=3
430pipelined=true
431
432[system.cpu.fuPool.FUList4.opList10]
433type=OpDesc
434eventq_index=0
435opClass=SimdSqrt
436opLat=9
437pipelined=true
438
439[system.cpu.fuPool.FUList4.opList11]
440type=OpDesc
441eventq_index=0
442opClass=SimdFloatAdd
443opLat=5
444pipelined=true
445
446[system.cpu.fuPool.FUList4.opList12]
447type=OpDesc
448eventq_index=0
449opClass=SimdFloatAlu
450opLat=5
451pipelined=true
452
453[system.cpu.fuPool.FUList4.opList13]
454type=OpDesc
455eventq_index=0
456opClass=SimdFloatCmp
457opLat=3
458pipelined=true
459
460[system.cpu.fuPool.FUList4.opList14]
461type=OpDesc
462eventq_index=0
463opClass=SimdFloatCvt
464opLat=3
465pipelined=true
466
467[system.cpu.fuPool.FUList4.opList15]
468type=OpDesc
469eventq_index=0
470opClass=SimdFloatDiv
471opLat=3
472pipelined=true
473
474[system.cpu.fuPool.FUList4.opList16]
475type=OpDesc
476eventq_index=0
477opClass=SimdFloatMisc
478opLat=3
479pipelined=true
480
481[system.cpu.fuPool.FUList4.opList17]
482type=OpDesc
483eventq_index=0
484opClass=SimdFloatMult
485opLat=3
486pipelined=true
487
488[system.cpu.fuPool.FUList4.opList18]
489type=OpDesc
490eventq_index=0
491opClass=SimdFloatMultAcc
492opLat=1
493pipelined=true
494
495[system.cpu.fuPool.FUList4.opList19]
496type=OpDesc
497eventq_index=0
498opClass=SimdFloatSqrt
499opLat=9
500pipelined=true
501
502[system.cpu.fuPool.FUList4.opList20]
503type=OpDesc
504eventq_index=0
505opClass=FloatAdd
506opLat=5
507pipelined=true
508
509[system.cpu.fuPool.FUList4.opList21]
510type=OpDesc
511eventq_index=0
512opClass=FloatCmp
513opLat=5
514pipelined=true
515
516[system.cpu.fuPool.FUList4.opList22]
517type=OpDesc
518eventq_index=0
519opClass=FloatCvt
520opLat=5
521pipelined=true
522
523[system.cpu.fuPool.FUList4.opList23]
524type=OpDesc
525eventq_index=0
526opClass=FloatDiv
527opLat=9
528pipelined=false
529
530[system.cpu.fuPool.FUList4.opList24]
531type=OpDesc
532eventq_index=0
533opClass=FloatSqrt
534opLat=33
535pipelined=false
536
537[system.cpu.fuPool.FUList4.opList25]
538type=OpDesc
539eventq_index=0
540opClass=FloatMult
541opLat=4
542pipelined=true
543
544[system.cpu.icache]
545type=BaseCache
546children=tags
547addr_ranges=0:18446744073709551615
548assoc=1
549clk_domain=system.cpu_clk_domain
550demand_mshr_reserve=1
551eventq_index=0
552forward_snoops=true
553hit_latency=2
554is_read_only=true
555max_miss_count=0
556mshrs=4
557prefetch_on_access=false
558prefetcher=Null
559response_latency=2
560sequential_access=false
561size=32768
562system=system
563tags=system.cpu.icache.tags
564tgts_per_mshr=20
565write_buffers=8
566cpu_side=system.cpu.icache_port
567mem_side=system.cpu.toL2Bus.slave[0]
568
569[system.cpu.icache.tags]
570type=LRU
571assoc=1
572block_size=64

--- 83 unchanged lines hidden (view full) ---

656children=tags
657addr_ranges=0:18446744073709551615
658assoc=8
659clk_domain=system.cpu_clk_domain
660demand_mshr_reserve=1
661eventq_index=0
662forward_snoops=true
663hit_latency=20
664is_read_only=false
665max_miss_count=0
666mshrs=20
667prefetch_on_access=false
668prefetcher=Null
669response_latency=20
670sequential_access=false
671size=4194304
672system=system
673tags=system.cpu.l2cache.tags
674tgts_per_mshr=12
675write_buffers=8
676cpu_side=system.cpu.toL2Bus.master[0]
677mem_side=system.membus.slave[2]
678
679[system.cpu.l2cache.tags]
680type=LRU
681assoc=8
682block_size=64

--- 61 unchanged lines hidden (view full) ---

744children=tags
745addr_ranges=2147483648:2415919103
746assoc=8
747clk_domain=system.clk_domain
748demand_mshr_reserve=1
749eventq_index=0
750forward_snoops=false
751hit_latency=50
752is_read_only=false
753max_miss_count=0
754mshrs=20
755prefetch_on_access=false
756prefetcher=Null
757response_latency=50
758sequential_access=false
759size=1024
760system=system
761tags=system.iocache.tags
762tgts_per_mshr=12
763write_buffers=8
764cpu_side=system.iobus.master[27]
765mem_side=system.membus.slave[3]
766
767[system.iocache.tags]
768type=LRU
769assoc=8
770block_size=64

--- 351 unchanged lines hidden (view full) ---

1122config=system.iobus.master[26]
1123dma=system.iobus.slave[4]
1124pio=system.iobus.master[25]
1125
1126[system.realview.generic_timer]
1127type=GenericTimer
1128eventq_index=0
1129gic=system.realview.gic
1130int_phys=29
1131int_virt=27
1132system=system
1133
1134[system.realview.gic]
1135type=Pl390
1136clk_domain=system.clk_domain
1137cpu_addr=738205696
1138cpu_pio_delay=10000
1139dist_addr=738201600

--- 13 unchanged lines hidden (view full) ---

1153eventq_index=0
1154gic=system.realview.gic
1155int_num=117
1156pio_addr=721420288
1157pio_latency=10000
1158pixel_clock=7299
1159system=system
1160vnc=system.vncserver
1161workaround_swap_rb=true
1162dma=system.membus.slave[0]
1163pio=system.iobus.master[5]
1164
1165[system.realview.ide]
1166type=IdeController
1167BAR0=1
1168BAR0LegacyIO=false
1169BAR0Size=8

--- 389 unchanged lines hidden ---