| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 162093 # Simulator instruction rate (inst/s) 8host_op_rate 190619 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8503081814 # Simulator tick rate (ticks/s) 10host_mem_usage 814268 # Number of bytes of host memory used 11host_seconds 5572.60 # Real time elapsed on the host | 7host_inst_rate 151085 # Simulator instruction rate (inst/s) 8host_op_rate 177673 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7925620115 # Simulator tick rate (ticks/s) 10host_mem_usage 773240 # Number of bytes of host memory used 11host_seconds 5978.63 # Real time elapsed on the host |
| 12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory --- 446 unchanged lines hidden (view full) --- 466system.cpu0.dtb.read_hits 99690232 # DTB read hits 467system.cpu0.dtb.read_misses 367422 # DTB read misses 468system.cpu0.dtb.write_hits 83046551 # DTB write hits 469system.cpu0.dtb.write_misses 162916 # DTB write misses 470system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID | 12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory --- 446 unchanged lines hidden (view full) --- 466system.cpu0.dtb.read_hits 99690232 # DTB read hits 467system.cpu0.dtb.read_misses 367422 # DTB read misses 468system.cpu0.dtb.write_hits 83046551 # DTB write hits 469system.cpu0.dtb.write_misses 162916 # DTB write misses 470system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID |
| 474system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB | 474system.cpu0.dtb.flush_entries 35477 # Number of entries that have been flushed from TLB |
| 475system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 480system.cpu0.dtb.write_accesses 83209467 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 182736783 # DTB hits --- 94 unchanged lines hidden (view full) --- 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID | 475system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 480system.cpu0.dtb.write_accesses 83209467 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 182736783 # DTB hits --- 94 unchanged lines hidden (view full) --- 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID |
| 585system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB | 585system.cpu0.itb.flush_entries 25278 # Number of entries that have been flushed from TLB |
| 586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 593system.cpu0.itb.hits 216521473 # DTB hits --- 1198 unchanged lines hidden (view full) --- 1792system.cpu1.dtb.read_hits 94100008 # DTB read hits 1793system.cpu1.dtb.read_misses 416726 # DTB read misses 1794system.cpu1.dtb.write_hits 75732153 # DTB write hits 1795system.cpu1.dtb.write_misses 163098 # DTB write misses 1796system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1797system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1798system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1799system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID | 586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 593system.cpu0.itb.hits 216521473 # DTB hits --- 1198 unchanged lines hidden (view full) --- 1792system.cpu1.dtb.read_hits 94100008 # DTB read hits 1793system.cpu1.dtb.read_misses 416726 # DTB read misses 1794system.cpu1.dtb.write_hits 75732153 # DTB write hits 1795system.cpu1.dtb.write_misses 163098 # DTB write misses 1796system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1797system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1798system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1799system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID |
| 1800system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB | 1800system.cpu1.dtb.flush_entries 40885 # Number of entries that have been flushed from TLB |
| 1801system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions 1802system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch 1803system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1804system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1805system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1806system.cpu1.dtb.write_accesses 75895251 # DTB write accesses 1807system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1808system.cpu1.dtb.hits 169832161 # DTB hits --- 91 unchanged lines hidden (view full) --- 1900system.cpu1.itb.read_hits 0 # DTB read hits 1901system.cpu1.itb.read_misses 0 # DTB read misses 1902system.cpu1.itb.write_hits 0 # DTB write hits 1903system.cpu1.itb.write_misses 0 # DTB write misses 1904system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1905system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1906system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1907system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID | 1801system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions 1802system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch 1803system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1804system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1805system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1806system.cpu1.dtb.write_accesses 75895251 # DTB write accesses 1807system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1808system.cpu1.dtb.hits 169832161 # DTB hits --- 91 unchanged lines hidden (view full) --- 1900system.cpu1.itb.read_hits 0 # DTB read hits 1901system.cpu1.itb.read_misses 0 # DTB read misses 1902system.cpu1.itb.write_hits 0 # DTB write hits 1903system.cpu1.itb.write_misses 0 # DTB write misses 1904system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1905system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1906system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1907system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID |
| 1908system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB | 1908system.cpu1.itb.flush_entries 29927 # Number of entries that have been flushed from TLB |
| 1909system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1910system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1911system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1912system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions 1913system.cpu1.itb.read_accesses 0 # DTB read accesses 1914system.cpu1.itb.write_accesses 0 # DTB write accesses 1915system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1916system.cpu1.itb.hits 200179962 # DTB hits --- 2073 unchanged lines hidden --- | 1909system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1910system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1911system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1912system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions 1913system.cpu1.itb.read_accesses 0 # DTB read accesses 1914system.cpu1.itb.write_accesses 0 # DTB write accesses 1915system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1916system.cpu1.itb.hits 200179962 # DTB hits --- 2073 unchanged lines hidden --- |