| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 172390 # Simulator instruction rate (inst/s) 8host_op_rate 202727 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9043218476 # Simulator tick rate (ticks/s) 10host_mem_usage 765852 # Number of bytes of host memory used 11host_seconds 5239.76 # Real time elapsed on the host | 7host_inst_rate 162093 # Simulator instruction rate (inst/s) 8host_op_rate 190619 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8503081814 # Simulator tick rate (ticks/s) 10host_mem_usage 814268 # Number of bytes of host memory used 11host_seconds 5572.60 # Real time elapsed on the host |
| 12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory --- 289 unchanged lines hidden (view full) --- 313system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) 314system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) 315system.physmem_1.averagePower 668.602035 # Core power per rank (mW) 316system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states 317system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states 318system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 319system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states 320system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory --- 289 unchanged lines hidden (view full) --- 314system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) 315system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) 316system.physmem_1.averagePower 668.602035 # Core power per rank (mW) 317system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states 318system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states 319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 320system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states 321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 322system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 321system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 326system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 339system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 343system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) | 323system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 330system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 341system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 347system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 348system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) |
| 349system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 350system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 351system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 350system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 351system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 352system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 353system.cpu0.branchPred.lookups 138091637 # Number of BP lookups 354system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 359system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage 360system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. 361system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. 362system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. 363system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. 364system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. 365system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. 366system.cpu_clk_domain.clock 500 # Clock period in ticks | 352system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 353system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 354system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 355system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 356system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 357system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 358system.cpu0.branchPred.lookups 138091637 # Number of BP lookups 359system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 364system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage 365system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. 366system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. 367system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. 368system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. 369system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. 370system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. 371system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 372system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 388system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 389system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 391system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 392system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 393system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 394system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 395system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 394system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 402system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 396system.cpu0.dtb.walker.walks 530338 # Table walker walks requested 397system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors 398system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate 399system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate 400system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting 401system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency 402system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency 403system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency --- 66 unchanged lines hidden (view full) --- 470system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 471system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 472system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 473system.cpu0.dtb.write_accesses 83209467 # DTB write accesses 474system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 475system.cpu0.dtb.hits 182736783 # DTB hits 476system.cpu0.dtb.misses 530338 # DTB misses 477system.cpu0.dtb.accesses 183267121 # DTB accesses | 403system.cpu0.dtb.walker.walks 530338 # Table walker walks requested 404system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors 405system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate 406system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate 407system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting 408system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency --- 66 unchanged lines hidden (view full) --- 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 480system.cpu0.dtb.write_accesses 83209467 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 182736783 # DTB hits 483system.cpu0.dtb.misses 530338 # DTB misses 484system.cpu0.dtb.accesses 183267121 # DTB accesses |
| 485system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 478system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 499system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 500system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 501system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 502system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 503system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 504system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 505system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 506system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 486system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 507system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 508system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 509system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 510system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 511system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 512system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 513system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 514system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 515system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 507system.cpu0.itb.walker.walks 81834 # Table walker walks requested 508system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors 509system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate 510system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate 511system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting 512system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency 513system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency 514system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency --- 64 unchanged lines hidden (view full) --- 579system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 580system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions 581system.cpu0.itb.read_accesses 0 # DTB read accesses 582system.cpu0.itb.write_accesses 0 # DTB write accesses 583system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 584system.cpu0.itb.hits 216521473 # DTB hits 585system.cpu0.itb.misses 81834 # DTB misses 586system.cpu0.itb.accesses 216603307 # DTB accesses | 516system.cpu0.itb.walker.walks 81834 # Table walker walks requested 517system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors 518system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate 519system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate 520system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting 521system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency --- 64 unchanged lines hidden (view full) --- 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 593system.cpu0.itb.hits 216521473 # DTB hits 594system.cpu0.itb.misses 81834 # DTB misses 595system.cpu0.itb.accesses 216603307 # DTB accesses |
| 596system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions 597system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state 613system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state 614system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states 615system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states |
|
| 587system.cpu0.numCycles 746014900 # number of cpu cycles simulated 588system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 589system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 590system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss 591system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed 592system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered 593system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken 594system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked --- 279 unchanged lines hidden (view full) --- 874system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads 875system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes 876system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads 877system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes 878system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads 879system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes 880system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads 881system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes | 616system.cpu0.numCycles 746014900 # number of cpu cycles simulated 617system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 618system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 619system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss 620system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed 621system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered 622system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken 623system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked --- 279 unchanged lines hidden (view full) --- 903system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads 904system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes 905system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads 906system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes 907system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads 908system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes 909system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads 910system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes |
| 911system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 882system.cpu0.dcache.tags.replacements 5793916 # number of replacements 883system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use 884system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. 885system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. 886system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. 887system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. 888system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor 889system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy 890system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy 891system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 892system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 893system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 894system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 895system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 896system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses 897system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses | 912system.cpu0.dcache.tags.replacements 5793916 # number of replacements 913system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use 914system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. 915system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. 916system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. 917system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. 918system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor 919system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy 920system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy 921system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 922system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 923system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 924system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 925system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 926system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses 927system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses |
| 928system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 898system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits 899system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits 900system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits 901system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits 902system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits 903system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits 904system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits 905system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits --- 182 unchanged lines hidden (view full) --- 1088system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency 1089system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency 1090system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency 1091system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency 1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency 1093system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency 1094system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency 1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency | 929system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits 930system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits 931system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits 932system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits 933system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits 934system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits 935system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits 936system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits --- 182 unchanged lines hidden (view full) --- 1119system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency 1120system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency 1121system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency 1122system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency 1123system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency 1124system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency 1125system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency 1126system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency |
| 1127system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1096system.cpu0.icache.tags.replacements 6136519 # number of replacements 1097system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use 1098system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. 1099system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. 1100system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. 1101system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. 1102system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor 1103system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy 1104system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy 1105system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1106system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1107system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 1108system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 1109system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1110system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses 1111system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses | 1128system.cpu0.icache.tags.replacements 6136519 # number of replacements 1129system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use 1130system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. 1131system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. 1132system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. 1133system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. 1134system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor 1135system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy 1136system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy 1137system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1138system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1139system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 1140system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 1141system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1142system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses 1143system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses |
| 1144system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1112system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits 1113system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits 1114system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits 1115system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits 1116system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits 1117system.cpu0.icache.overall_hits::total 209807209 # number of overall hits 1118system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses 1119system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 1190system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1191system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1192system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1193system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1194system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency 1195system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency 1196system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency 1197system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency | 1145system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits 1146system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits 1147system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits 1148system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits 1149system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits 1150system.cpu0.icache.overall_hits::total 209807209 # number of overall hits 1151system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses 1152system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 1223system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1224system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1225system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1226system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1227system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency 1228system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency 1229system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency 1230system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency |
| 1231system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1198system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued 1199system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified 1200system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue 1201system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1202system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1203system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing | 1232system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued 1233system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified 1234system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue 1235system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1236system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1237system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing |
| 1238system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1204system.cpu0.l2cache.tags.replacements 2565485 # number of replacements 1205system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use 1206system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. 1207system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. 1208system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. 1209system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. 1210system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor 1211system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor --- 21 unchanged lines hidden (view full) --- 1233system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id 1237system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 1238system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id 1239system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses 1240system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses | 1239system.cpu0.l2cache.tags.replacements 2565485 # number of replacements 1240system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use 1241system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. 1242system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. 1243system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. 1244system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. 1245system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor 1246system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor --- 21 unchanged lines hidden (view full) --- 1268system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id 1272system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 1273system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id 1274system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses 1275system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses |
| 1276system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1241system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits 1242system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits 1243system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits 1244system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits 1245system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits 1246system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits 1247system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits 1248system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits --- 342 unchanged lines hidden (view full) --- 1591system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency 1592system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency 1593system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. 1594system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1595system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1596system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. 1597system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1598system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1277system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits 1278system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits 1279system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits 1280system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits 1281system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits 1282system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits 1283system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits 1284system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits --- 342 unchanged lines hidden (view full) --- 1627system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency 1628system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency 1629system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. 1630system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1631system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1632system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. 1633system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1634system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1635system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1599system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution 1600system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution 1601system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution 1602system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution 1603system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution 1604system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution 1605system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution 1606system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution --- 51 unchanged lines hidden (view full) --- 1658system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1659system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage 1660system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. 1661system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. 1662system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. 1663system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. 1664system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. 1665system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. | 1636system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution --- 51 unchanged lines hidden (view full) --- 1695system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1696system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage 1697system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. 1698system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. 1699system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. 1700system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. 1701system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. 1702system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. |
| 1703system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1666system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1667system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1668system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1669system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1670system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1687system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1688system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1689system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1690system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1691system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1692system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1693system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1694system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1706system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1707system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1725system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1726system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1727system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1728system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1729system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1730system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1731system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1732system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1733system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1695system.cpu1.dtb.walker.walks 579824 # Table walker walks requested 1696system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors 1697system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate 1698system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate 1699system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting 1700system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency 1701system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency 1702system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency --- 61 unchanged lines hidden (view full) --- 1764system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1765system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1766system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1767system.cpu1.dtb.write_accesses 75895251 # DTB write accesses 1768system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1769system.cpu1.dtb.hits 169832161 # DTB hits 1770system.cpu1.dtb.misses 579824 # DTB misses 1771system.cpu1.dtb.accesses 170411985 # DTB accesses | 1734system.cpu1.dtb.walker.walks 579824 # Table walker walks requested 1735system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors 1736system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate 1737system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate 1738system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting 1739system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency 1741system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency --- 61 unchanged lines hidden (view full) --- 1803system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1804system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1805system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1806system.cpu1.dtb.write_accesses 75895251 # DTB write accesses 1807system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1808system.cpu1.dtb.hits 169832161 # DTB hits 1809system.cpu1.dtb.misses 579824 # DTB misses 1810system.cpu1.dtb.accesses 170411985 # DTB accesses |
| 1811system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1772system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1773system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1774system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1775system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1776system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1777system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1778system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1779system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1793system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1794system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1795system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1796system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1797system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1798system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1799system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1800system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1812system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1813system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1814system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1833system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1834system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1835system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1836system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1837system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1838system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1839system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1840system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1841system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 1801system.cpu1.itb.walker.walks 86146 # Table walker walks requested 1802system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors 1803system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate 1804system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate 1805system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting 1806system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency 1807system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency 1808system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency --- 61 unchanged lines hidden (view full) --- 1870system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1871system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions 1872system.cpu1.itb.read_accesses 0 # DTB read accesses 1873system.cpu1.itb.write_accesses 0 # DTB write accesses 1874system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1875system.cpu1.itb.hits 200179962 # DTB hits 1876system.cpu1.itb.misses 86146 # DTB misses 1877system.cpu1.itb.accesses 200266108 # DTB accesses | 1842system.cpu1.itb.walker.walks 86146 # Table walker walks requested 1843system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors 1844system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate 1845system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate 1846system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting 1847system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency 1848system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency --- 61 unchanged lines hidden (view full) --- 1911system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1912system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions 1913system.cpu1.itb.read_accesses 0 # DTB read accesses 1914system.cpu1.itb.write_accesses 0 # DTB write accesses 1915system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1916system.cpu1.itb.hits 200179962 # DTB hits 1917system.cpu1.itb.misses 86146 # DTB misses 1918system.cpu1.itb.accesses 200266108 # DTB accesses |
| 1919system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions 1920system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state 1921system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state 1922system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state 1923system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state 1924system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state 1925system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state 1926system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 1927system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 1928system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state 1929system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 1930system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 1931system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state 1932system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1933system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state 1934system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state 1935system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states 1936system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states |
|
| 1878system.cpu1.numCycles 683375860 # number of cpu cycles simulated 1879system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1880system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1881system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss 1882system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed 1883system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered 1884system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken 1885system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked --- 279 unchanged lines hidden (view full) --- 2165system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads 2166system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes 2167system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads 2168system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes 2169system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads 2170system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes 2171system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads 2172system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes | 1937system.cpu1.numCycles 683375860 # number of cpu cycles simulated 1938system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1939system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1940system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss 1941system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed 1942system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered 1943system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken 1944system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked --- 279 unchanged lines hidden (view full) --- 2224system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads 2225system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes 2226system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads 2227system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes 2228system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads 2229system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes 2230system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads 2231system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes |
| 2232system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2173system.cpu1.dcache.tags.replacements 5420466 # number of replacements 2174system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use 2175system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. 2176system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. 2177system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. 2178system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. 2179system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor 2180system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy 2181system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy 2182system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2183system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id 2184system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 2185system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 2186system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2187system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses 2188system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses | 2233system.cpu1.dcache.tags.replacements 5420466 # number of replacements 2234system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use 2235system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. 2236system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. 2237system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. 2238system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. 2239system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor 2240system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy 2241system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy 2242system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2243system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id 2244system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 2245system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 2246system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2247system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses 2248system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses |
| 2249system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2189system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits 2190system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits 2191system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits 2192system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits 2193system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits 2194system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits 2195system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits 2196system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits --- 182 unchanged lines hidden (view full) --- 2379system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency 2380system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency 2381system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency 2382system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency 2383system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency 2384system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency 2385system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency 2386system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency | 2250system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits 2251system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits 2252system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits 2253system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits 2254system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits 2255system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits 2256system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits 2257system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits --- 182 unchanged lines hidden (view full) --- 2440system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency 2441system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency 2442system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency 2443system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency 2444system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency 2445system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency 2446system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency 2447system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency |
| 2448system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2387system.cpu1.icache.tags.replacements 5742782 # number of replacements 2388system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use 2389system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. 2390system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. 2391system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. 2392system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. 2393system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor 2394system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy 2395system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy 2396system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2397system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 2398system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id 2399system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 2400system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2401system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses 2402system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses | 2449system.cpu1.icache.tags.replacements 5742782 # number of replacements 2450system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use 2451system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. 2452system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. 2453system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. 2454system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. 2455system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor 2456system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy 2457system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy 2458system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2459system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 2460system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id 2461system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 2462system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2463system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses 2464system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses |
| 2465system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2403system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits 2404system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits 2405system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits 2406system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits 2407system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits 2408system.cpu1.icache.overall_hits::total 193871102 # number of overall hits 2409system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses 2410system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 2481system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2482system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2483system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2484system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2485system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency 2486system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency 2487system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency 2488system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency | 2466system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits 2467system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits 2468system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits 2469system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits 2470system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits 2471system.cpu1.icache.overall_hits::total 193871102 # number of overall hits 2472system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses 2473system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 2544system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2545system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2546system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2547system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2548system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency 2549system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency 2550system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency 2551system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency |
| 2552system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2489system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued 2490system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified 2491system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue 2492system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2493system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2494system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing | 2553system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued 2554system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified 2555system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue 2556system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2557system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2558system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing |
| 2559system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2495system.cpu1.l2cache.tags.replacements 2216875 # number of replacements 2496system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use 2497system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. 2498system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. 2499system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. 2500system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. 2501system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor 2502system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor --- 21 unchanged lines hidden (view full) --- 2524system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id 2525system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id 2526system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id 2527system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id 2528system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 2529system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id 2530system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses 2531system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses | 2560system.cpu1.l2cache.tags.replacements 2216875 # number of replacements 2561system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use 2562system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. 2563system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. 2564system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. 2565system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. 2566system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor 2567system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor --- 21 unchanged lines hidden (view full) --- 2589system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id 2590system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id 2591system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id 2592system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id 2593system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 2594system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id 2595system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses 2596system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses |
| 2597system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2532system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits 2533system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits 2534system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits 2535system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits 2536system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits 2537system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits 2538system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits 2539system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits --- 338 unchanged lines hidden (view full) --- 2878system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency 2879system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency 2880system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. 2881system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2882system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2883system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. 2884system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2885system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2598system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits 2599system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits 2600system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits 2601system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits 2602system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits 2603system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits 2604system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits 2605system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits --- 338 unchanged lines hidden (view full) --- 2944system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency 2945system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency 2946system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. 2947system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2948system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2949system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. 2950system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2951system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2952system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2886system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution 2887system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution 2888system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2889system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution 2890system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution 2891system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution 2892system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution 2893system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution --- 39 unchanged lines hidden (view full) --- 2933system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) 2934system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2935system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) 2936system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2937system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) 2938system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2939system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) 2940system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2953system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution 2954system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution 2955system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2956system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution 2957system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution 2958system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution 2959system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution --- 39 unchanged lines hidden (view full) --- 3000system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) 3001system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3002system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) 3003system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3004system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) 3005system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3006system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) 3007system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3008system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 2941system.iobus.trans_dist::ReadReq 40341 # Transaction distribution 2942system.iobus.trans_dist::ReadResp 40341 # Transaction distribution 2943system.iobus.trans_dist::WriteReq 136646 # Transaction distribution 2944system.iobus.trans_dist::WriteResp 136646 # Transaction distribution 2945system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) 2946system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2947system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2948system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 3009system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) 3010system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3011system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) 3012system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3013system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) 3014system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3015system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3016system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 3009system.iobus.trans_dist::ReadReq 40341 # Transaction distribution 3010system.iobus.trans_dist::ReadResp 40341 # Transaction distribution 3011system.iobus.trans_dist::WriteReq 136646 # Transaction distribution 3012system.iobus.trans_dist::WriteResp 136646 # Transaction distribution 3013system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) 3014system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3015system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3016system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 3077system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) 3078system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3079system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) 3080system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3081system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) 3082system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3083system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3084system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 3085system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3017system.iocache.tags.replacements 115592 # number of replacements 3018system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use 3019system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3020system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. 3021system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3022system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. 3023system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor 3024system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor 3025system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy 3026system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy 3027system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy 3028system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3029system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3030system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3031system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 3032system.iocache.tags.data_accesses 1040856 # Number of data accesses | 3086system.iocache.tags.replacements 115592 # number of replacements 3087system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use 3088system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3089system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. 3090system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3091system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. 3092system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor 3093system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor 3094system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy 3095system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy 3096system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy 3097system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3098system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3099system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3100system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 3101system.iocache.tags.data_accesses 1040856 # Number of data accesses |
| 3102system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3033system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3034system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 3035system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses 3036system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3037system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3038system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3039system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3040system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 3150system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency 3151system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency 3152system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3153system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3154system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3155system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3156system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3157system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency | 3103system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3104system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 3105system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses 3106system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3107system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3108system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3109system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3110system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 3220system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency 3221system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency 3222system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3223system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3224system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3225system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3226system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3227system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency |
| 3228system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3158system.l2c.tags.replacements 1423185 # number of replacements 3159system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use 3160system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. 3161system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. 3162system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. 3163system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. 3164system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor 3165system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor --- 33 unchanged lines hidden (view full) --- 3199system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id 3200system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id 3201system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id 3202system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id 3203system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id 3204system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 3205system.l2c.tags.tag_accesses 76659871 # Number of tag accesses 3206system.l2c.tags.data_accesses 76659871 # Number of data accesses | 3229system.l2c.tags.replacements 1423185 # number of replacements 3230system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use 3231system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. 3232system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. 3233system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. 3234system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. 3235system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor 3236system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor --- 33 unchanged lines hidden (view full) --- 3270system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id 3271system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id 3272system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id 3273system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id 3274system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id 3275system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 3276system.l2c.tags.tag_accesses 76659871 # Number of tag accesses 3277system.l2c.tags.data_accesses 76659871 # Number of data accesses |
| 3278system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3207system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits 3208system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits 3209system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits 3210system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits 3211system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits 3212system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits 3213system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits 3214system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits --- 504 unchanged lines hidden (view full) --- 3719system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency 3720system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency 3721system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. 3722system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3723system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3724system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3725system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3726system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3279system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits 3280system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits 3281system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits 3282system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits 3283system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits 3284system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits 3285system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits 3286system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits --- 504 unchanged lines hidden (view full) --- 3791system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency 3792system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency 3793system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. 3794system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3795system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3796system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3797system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3798system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3799system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3727system.membus.trans_dist::ReadReq 60003 # Transaction distribution 3728system.membus.trans_dist::ReadResp 904829 # Transaction distribution 3729system.membus.trans_dist::WriteReq 38534 # Transaction distribution 3730system.membus.trans_dist::WriteResp 38534 # Transaction distribution 3731system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution 3732system.membus.trans_dist::CleanEvict 238236 # Transaction distribution 3733system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution 3734system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3773system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) 3774system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3775system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) 3776system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3777system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) 3778system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3779system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) 3780system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3800system.membus.trans_dist::ReadReq 60003 # Transaction distribution 3801system.membus.trans_dist::ReadResp 904829 # Transaction distribution 3802system.membus.trans_dist::WriteReq 38534 # Transaction distribution 3803system.membus.trans_dist::WriteResp 38534 # Transaction distribution 3804system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution 3805system.membus.trans_dist::CleanEvict 238236 # Transaction distribution 3806system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution 3807system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3846system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) 3847system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3848system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) 3849system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3850system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) 3851system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3852system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) 3853system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3854system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3855system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3856system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3857system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3858system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3859system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3860system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3781system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3782system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3783system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3784system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3785system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3786system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3861system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3862system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3863system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3864system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3865system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3866system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3867system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3868system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3787system.realview.ethernet.txBytes 966 # Bytes Transmitted 3788system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3789system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3790system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3791system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3792system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3793system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3794system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3821system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3822system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3823system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3824system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3825system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3826system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3827system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3828system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3869system.realview.ethernet.txBytes 966 # Bytes Transmitted 3870system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3871system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3872system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3873system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3874system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3875system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3876system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3903system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3904system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3905system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3906system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3907system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3908system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3909system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3910system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3911system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3912system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3913system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3914system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3915system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3916system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3917system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
|
| 3829system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3830system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3831system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3832system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3918system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3919system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3920system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3921system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3922system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3923system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3924system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3925system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3926system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3927system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3928system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3929system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3930system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3931system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3932system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3933system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
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| 3833system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. 3834system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3835system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3836system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. 3837system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3838system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3934system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. 3935system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3936system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3937system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. 3938system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3939system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3940system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states |
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| 3839system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution 3840system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution 3841system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution 3842system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution 3843system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution 3844system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 3845system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution 3846system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution --- 41 unchanged lines hidden --- | 3941system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution 3942system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution 3943system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution 3944system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution 3945system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution 3946system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 3947system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution 3948system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution --- 41 unchanged lines hidden --- |